METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

Abstract

Procedure comprising: Producing a photoresist (24) over a target layer (20); Performing a plasma-assisted deposition process (28), wherein in the plasma-assisted deposition process sidewalls of the photoresist (24) are etched while a spacer layer (26) is deposited on the sidewalls of the photoresist; Structuring the spacer layer (26) to produce spacers (30) on the sidewalls of the photoresist (24); and Etching the target layer (20) using the spacers (30) and the photoresist (24) as a combined etch mask (34); wherein the plasma-assisted deposition process comprises performing an atomic layer deposition cycle, hereinafter referred to as ALD cycle, several times, and wherein the ALD cycle comprises: - treating the photoresist (24) with a first precursor in a first cycle of the ALD cycle, - treating the photoresist (24) with a second precursor in a second cycle of the ALD cycle, wherein the second precursor is brought into reaction with the first precursor to deposit the spacer layer (26), and - generating a plasma from the second precursor during the second clock of the ALD cycle, wherein the plasma etches the sidewalls of the photoresist (24).

Description

BACKGROUND

[0001] Semiconductor devices are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric material layers, conductive material layers, and semiconductor material layers over a semiconductor substrate. The various material layers are patterned by lithography to create circuit components and elements on the substrate.

[0002] The semiconductor industry is continually improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, allowing more components to be integrated into a given area. However, reducing the minimum feature size creates additional problems that need to be addressed.

[0003] US 2019 / 0 259 612 A1 describes a patterning method in semiconductor manufacturing, wherein a photoresist structure is provided whose structures have a target width. The photoresist structures are trimmed such that a width of each trimmed photoresist structure is smaller than the target width. An oxide film is deposited, and subsequently, an unwanted portion of the oxide film is etched without removing the trimmed photoresist structures. This forms vertical spacers, wherein the spacers substantially maintain the target width and are formed by the trimmed photoresist structures and vertical portions of the oxide film covering the sidewalls of the trimmed photoresist structures. Subsequently, a layer underlying the spacers is etched to transfer a pattern formed by the spacers to the underlying layer.

[0004] US 2015 / 0 243 520 A1 describes a method for fabricating a pattern of a semiconductor device, wherein a hard mask layer is formed on a substrate. A photoresist layer is applied to the hard mask layer. The photoresist layer is exposed and developed to form a first photoresist pattern. The first photoresist pattern is smoothed to produce a second photoresist pattern having a lower roughness than the first photoresist pattern. In the smoothing process, a surface of the first photoresist pattern is treated with an organic solvent. An ALD layer is formed on a surface of the second photoresist pattern. The ALD layer is anisotropically etched to form an ALD layer pattern on a sidewall of the second photoresist pattern. The hard mask layer is etched using the second photoresist pattern and the ALD layer pattern as an etching mask to form a hard mask pattern. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of the present disclosure can best be understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Rather, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration. The Fig. 1 to 4 illustrate a process for patterning features in a substrate according to some embodiments. Fig. 5 shows an example of a nanostructure field effect transistor (nano-FET) in a three-dimensional representation according to some embodiments. The Fig. 6 to 20B are illustrations of intermediate steps in fabricating nano-FETs according to some embodiments. The Fig. 21A and Fig. 21B are illustrations of fin field effect transistors (FinFETs) according to some embodiments. The Fig. 22 to 25 illustrate a process for patterning structural elements in a multilayer stack according to some embodiments. The Fig. 26 to 29 illustrate a process for patterning features in a dummy gate layer according to some embodiments. DETAILED DESCRIPTION

[0006] Embodiments of the present invention relate to the fabrication of a semiconductor device, and more particularly, to patterning a target layer, where the target layer may be a semiconductor substrate or a conductive layer. The following description provides many different embodiments or examples for implementing various features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples.For example, in the description below, the fabrication of a first element over or on top of a second element may include embodiments in which the first and second elements are fabricated in direct contact, and may also include embodiments in which additional elements may be fabricated between the first and second elements such that the first and second elements are not in direct contact. Furthermore, reference numerals may be repeated throughout the various examples of the present disclosure. This repetition is for simplicity and clarity and does not necessarily dictate any relationship between the various embodiments and / or configurations discussed.

[0007] In addition, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to conveniently describe the relationship of one element or structure to one or more other elements or structures illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative descriptors used herein may be interpreted accordingly.

[0008] In various embodiments, a photoresist and a spacer layer are fabricated and used to pattern underlying features. The photoresist is patterned, and the spacer layer is deposited on sidewalls of the patterned photoresist. The spacer layer is deposited using a plasma-assisted deposition process that has both etching and deposition aspects. In particular, the plasma-assisted deposition process etches the sidewalls of the photoresist to reduce their roughness, and the material for the spacer layer is also deposited on the etched sidewalls. In this way, an etch mask with smooth sidewalls can be fabricated, thereby reducing the linewidth roughness of underlying features patterned using the etch mask.

[0009] The Fig. 1 to 4 illustrate a process for patterning features in a substrate according to some embodiments. The patterning process may be used to pattern any type of feature in a substrate. For example, the patterning process may be used to pattern fins, nanostructures, gate structures, interconnects, and the like. The patterning process includes patterning a photoresist 24 (see Fig. 1) over a substrate 20 and then forming a spacer layer 26 (see Fig. 2) on sidewalls of the photoresist 24. The material for the spacer layer 26 is deposited using a plasma-assisted deposition process 28 (see Fig. 2) which has etching and deposition aspects. In particular, the plasma-assisted deposition process 28 etches the sidewalls of the photoresist 24 to reduce their roughness, while the material for the spacer layer 26 is deposited on the etched sidewalls. The spacer layer 26 can be patterned to form spacers 30 (see Fig. 3) are formed, and the substrate 20 is then etched using the spacers 30 and the photoresist 24 as a combined etching mask 34 to form patterned features 36 (see Fig. 4). By reducing the roughness of the sidewalls of the photoresist 24 and depositing a spacer layer 26 on these etched sidewalls, an etch mask 34 with smooth sidewalls is created, thereby reducing the linewidth roughness of the patterned features 36. This can improve the production yield.

[0010] In Fig. 1, one or more masking layers 22 are formed on a substrate 20, and a photoresist 24 is formed on the one or more masking layers 22. As will be explained in more detail later, the substrate 20 may be any type of target layer, such as a semiconductor substrate, a conductive layer, a dielectric layer, or the like. The one or more masking layers 22 are optional, and their use may help reduce the size of underlying features patterned using the photoresist 24.

[0011] In the illustrated embodiment, the one or more masking layers 22 form a multi-layer structure including a lower masking layer 22A and an upper masking layer 22B. The lower masking layer 22A is made of a material that has a high etch selectivity to the etching of the substrate 20. The lower masking layer 22A may, for example, be made of a material comprising a metal (e.g., titanium nitride, titanium, tantalum nitride, tantalum), a metal-doped carbide (e.g., tungsten carbide), or the like, and / or a semimetal (e.g., silicon nitride, boron nitride, silicon carbide, or the like), which may be deposited using a deposition method such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like. The upper masking layer 22B is made of a material that has a high etch selectivity to the etching of the lower masking layer 22A.The upper masking layer 22B may be formed, for example, from silicon oxide, such as undoped TEOS oxide (TEOS: tetraethylorthosilicate) or a BPTEOS oxide (BPTEOS: borophosphorus tetraethylorthosilicate), which may be deposited using a deposition method such as CVD, ALD, or the like. However, other suitable materials deposited using a suitable method may also be used. In some embodiments, a single masking layer 22 is used.

[0012] The photoresist 24 may be any suitable photoresist comprising a photosensitive material, such as a single-layer photoresist, a two-layer photoresist, a three-layer photoresist, or the like. In some embodiments, the photoresist 24 is a three-layer photoresist having a bottom layer, e.g., a BARC (bottom anti-reflective coating) layer, a middle layer (e.g., a nitride, an oxide, an oxide-nitride, or the like), and a top layer (e.g., a photosensitive material). The type of photoresist used may depend on the photolithography process used to pattern the photoresist 24. The one or more layers of the photoresist 24 may be formed using spin coating, a deposition process such as CVD, combinations thereof, or the like.

[0013] The photoresist 24 is patterned using suitable photolithography techniques to create openings therein. The photoresist 24 may be patterned by exposing the photosensitive material of the photoresist 24 to a patterned energy source (e.g., a patterned light source) having the pattern of the openings to initiate a chemical reaction, thereby causing a physical change in the portions of the photoresist 24 exposed to the patterned energy source. In embodiments where the photoresist 24 has multiple layers (e.g., where the photoresist 24 is a two-layer photoresist, a three-layer photoresist, or the like), the top layer (e.g., the photosensitive material) of the photoresist 24 is exposed to the patterned energy source.The photoresist 24 can then be developed by applying a developer to the exposed photoresist to utilize the physical changes and selectively remove either the exposed portion or the unexposed portion of the photoresist 24, depending on the desired structure.

[0014] In some embodiments, the photoresist 24 is patterned using next-generation lithography techniques, such as extreme ultraviolet (EUV) lithography, deep ultraviolet (DUV) lithography, X-ray lithography, soft X-ray (SX) lithography, ion beam projection lithography, electron beam projection lithography, or the like. By using next-generation lithography techniques, the underlying features can be patterned using a single-pattern photolithography technique, eliminating the use of multi-pattern photolithography techniques and reducing manufacturing complexity and cost.

[0015] By using next-generation lithography techniques, the photoresist 24 can be patterned into features having small dimensions. For example, after patterning the photoresist 24 with a single-patterning photolithography technique, the features of the photoresist 24 can have an average width W 1 from 5 nm to 100 nm. This can improve the feature density. However, when the photoresist 24 is patterned using a single-patterning photolithography process, polymer aggregation in the photosensitive material of the photoresist 24 can cause the sidewalls of the photoresist 24 to be rough. After patterning the photoresist 24 using a single-patterning photolithography process, the sidewalls of the photoresist 24 can have, for example, a linewidth roughness R 1from 3 nm to 8 nm. As explained in more detail later, the photoresist 24 is etched to reduce the roughness of its sidewalls. In this context, the "sidewalls" of the photoresist 24 are the surfaces of the photoresist 24 that are perpendicular to a major surface of the substrate 20.

[0016] In Fig. 2, a spacer layer 26 is formed on the top surfaces and sidewalls of the patterned features of the photoresist 24. In embodiments where the photoresist 24 comprises multiple layers (e.g., when the photoresist 24 is a two-layer photoresist, a three-layer photoresist, or the like), the spacer layer 26 is formed on top surfaces and sidewalls of the upper layer (e.g., the photosensitive material) of the photoresist 24. The spacer layer 26 may be formed, for example, from an oxide such as silicon oxide, TEOS oxide, or the like, which may be deposited using a conformal deposition process such as ALD, plasma-enhanced atomic layer deposition (PEALD), CVD, plasma-enhanced CVD (PECVD), or the like.

[0017] In some embodiments, the spacer layer 26 is an oxide layer formed using a plasma-assisted deposition process 28, such as PEALD. The spacer layer 26 may be formed, for example, from silicon oxide. The plasma-assisted deposition process 28 for forming the spacer layer 26 has etching and deposition aspects. In particular, the plasma-assisted deposition process 28 etches the sidewalls of the photoresist 24 while depositing the material for the spacer layer 26.

[0018] The etching aspects of the plasma-assisted deposition process 28 reduce the roughness of the sidewalls of the photoresist 24. After etching the photoresist 24 with the plasma-assisted deposition process 28, the sidewalls of the photoresist 24 may, for example, have a linewidth roughness R 2 from 1.5 nm to 4 nm. The linewidth roughness R 2is smaller than the linewidth roughness R 1 . The linewidth roughness R 2 can, for example, be 30% to 80% of the linewidth roughness R 1 The etching aspects of the plasma-assisted deposition process 28 also reduce the dimensions of the photoresist 24. After etching the photoresist 24 with the plasma-assisted deposition process 28, the structural elements of the photoresist 24 can have an average width W 2 from 15 nm to 80 nm. The width W 2 is smaller than the width W 1 For example, the width W 2 30% to 80% of the width W 1 be.

[0019] Due to the deposition aspects of the plasma-assisted deposition process 28, the material for the spacer layer 26 is deposited on the top surfaces and sidewalls of the photoresist 24. The spacer layer 26 is deposited with a sufficient thickness that (in combination with the etching of the sidewalls of the photoresist 24) enables smooth sidewalls of the spacer layer 26. For example, the spacer layer 26 may be deposited with a thickness T 1 from 0.5 nm to 8 nm, and the sidewalls of the spacer layer 26 may have a linewidth roughness R 3 from 1.5 nm to 2.8 nm. The linewidth roughness R 3 is lower than the linewidth roughness R 2 . The linewidth roughness R 3 can be, for example, 30% to 90% lower than the linewidth roughness R 2As will be explained in more detail later, the spacer layer 26 and the photoresist 24 are used as a combined etching mask for patterning deeper features, and by forming a spacer layer 26 with smooth sidewalls, the sidewalls of the combined etching mask can also be smooth. This can improve production yield. Furthermore, by forming the spacer layer 26 with a sufficient thickness, losses caused by the etching of the photoresist 24 can be compensated. The features of the combined etching mask used for patterning deeper features can thus have sufficient dimensions.

[0020] The plasma-assisted etching process 28 is performed by first placing the substrate 20 in a deposition chamber and then cyclically introducing different source precursors into the deposition chamber. A plasma is generated during at least a portion of each ALD cycle. The source precursors include a first and a second precursor. The first and second precursors are any suitable precursors capable of reacting to deposit the material of the spacer layer 26, and the second precursor is also a precursor capable of acting as an ion source to generate a plasma. For example, if the spacer layer 26 is made of silicon oxide, the first precursor may be a silicon-containing precursor, and the second precursor may be an oxygen-containing precursor.Silicon-containing precursors suitable for depositing silicon oxide are binary silicon-hydrogen compound silanes, such as silane (SiH. 4 ), Disilane (Si 2 H 6 ) and the like. Oxygen-containing precursors suitable for depositing silicon oxide and generating a plasma are oxygen gas (O 2 ), ozone (O 3 ) and the like. However, other suitable precursors may also be used.

[0021] A first cycle of an ALD cycle is performed by introducing the first precursor (e.g., a silicon-containing precursor) into the deposition chamber such that the photoresist 24 is exposed to the first precursor. The first cycle is performed at a low temperature. In some embodiments, the first cycle is performed at a temperature of less than 120°C, such as at a temperature of room temperature (e.g., about 20°C) to 120°C, e.g., by maintaining the deposition chamber at this temperature. The first cycle may be performed at a pressure of 133 Pa to 667 Pa, e.g., by maintaining the deposition chamber at this pressure. The first cycle may be performed for a duration of 1 min to 5 min, e.g., by maintaining the first precursor in the deposition chamber for this duration.The first precursor is then removed from the deposition chamber, such as by a suitable exhaust process and / or by introducing an inert gas into the deposition chamber.

[0022] A second cycle of an ALD cycle is performed by introducing the second precursor (e.g., an oxygen-containing precursor) into the deposition chamber such that the photoresist 24 is exposed to the second precursor. The second cycle is performed at a low temperature. In some embodiments, the second cycle is performed at a temperature of less than 120°C, such as at a temperature of room temperature (e.g., about 20°C) to 120°C, e.g., by maintaining the deposition chamber at this temperature. The second cycle may be performed at a pressure of 133 Pa to 667 Pa, e.g., by maintaining the deposition chamber at this pressure. The second cycle may be performed for a duration of 1 min to 5 min, e.g., by maintaining the second precursor in the deposition chamber for this duration.The second precursor is then removed from the deposition chamber, such as by a suitable exhaust process and / or by introducing an inert gas into the deposition chamber.

[0023] During the second cycle of the ALD cycle, a plasma is generated in the deposition chamber. Generating the plasma increases the reactivity of the second precursor, allowing the second cycle to be performed at a low temperature (specified above). By processing at a low temperature, damage to the photoresist 24 can be avoided. Generating the plasma also etches the material of the photoresist 24. In particular, the second precursor is a gas that, during plasma generation, performs an etch that is selective for the photoresist 24 (e.g., selectively etches the material of the photoresist 24 at a higher rate than the one or more materials of underlying layers, such as the masking layers 22).

[0024] The plasma can be generated during the second cycle of the ALD cycle by introducing a gas source into the deposition chamber and using a plasma generator to excite the gas source into a plasma state. The gas source contains the second precursor and may also contain a carrier gas (such as hydrogen, helium, neon, argon, krypton, xenon, radon, or the like). The gas source can be introduced into the deposition chamber at a flow rate of 0 l / min to 6 l / min. The plasma generator can be a capacitively coupled plasma generator (CCP generator), an inductively coupled plasma generator (ICP generator), a remote plasma generator, or the like. The plasma generator generates RF (radio frequency) power to excite the gas source into a plasma state. The power of the plasma generator is delivered in pulses between low power and high power during the second cycle of the ALD cycle.The plasma generation power can have a clock frequency of 40 kHz to 60 MHz. The plasma generation power can be high, from 15 W to 800 W. If the plasma generation is performed at less than 15 W (using the other deposition parameters mentioned here), the gas source may not be sufficiently activated into a plasma. Conversely, if the plasma generation is performed at more than 800 W (using the other deposition parameters mentioned here), the photoresist 24 may be damaged.

[0025] Each ALD cycle results in the deposition of one atomic layer (sometimes referred to as a monolayer) of the spacer layer 26 material. If the spacer layer 26 is made of silicon oxide, each monolayer may have a thickness of 0.1 nm. The ALD cycles are repeated several times until the spacer layer 26 material has been deposited to a desired thickness (specified above). For example, the ALD cycles may be repeated 1 to 500 times.

[0026] In Fig. 3, the spacer layer 26 is patterned to produce spacers 30. Horizontal portions of the spacer layer 26 are removed using a suitable etching process. During the etching process, the horizontal portions of the spacer layer 26 are selectively etched at a higher speed than the photoresist 24 and vertical portions of the spacer layer 26. For example, if the spacer layer 26 is made of silicon oxide, the etching process may be an anisotropic dry etching process performed with a halogen-based etchant containing fluorine (F), chlorine (Cl), bromine (Br), or the like. After the etching process, the spacers 30 comprise the remaining vertical portions of the spacer layer 26. The photoresist 24 remains after the spacers 30 have been formed.

[0027] The spacers 30 and the photoresist 24 together form a combined etch mask 34. Since the sidewalls of the spacer layer 26 are smooth, the outer sidewalls of the spacers 30 are also smooth. The outer sidewalls of the spacers 30 are also the outer sidewalls of the combined etch mask 34. Therefore, the outer sidewalls of the combined etch mask 34 are also smooth and can have the same linewidth roughness as the spacer layer 26. The deeper features patterned using the combined etch mask 34 can thus have smooth sidewalls.

[0028] As explained above, the spacer layer 26 is formed with a thickness that can compensate for losses caused by the etching of the photoresist 24. The structural elements of the combined etch mask 34 can have an average width W 3 from 15 nm to 80 nm. The width W3 is larger than the width W 2 For example, the width W 3 30% to 80% larger than the width W 2 be.

[0029] In Fig. 4, the substrate 20 is etched using the spacers 30 and the photoresist 24 as a combined etch mask 34 to produce patterned features 36. The etching, which can be performed using any suitable method, transfers the pattern of the combined etch mask 34 (e.g., the spacers 30 and the photoresist 24) to the substrate 20. The etching process can be anisotropic. The spacers 30 and the photoresist 24 can be removed during the etching of the substrate 20, or they can be removed later using a suitable cleaning process. Since the outer sidewalls of the combined etch mask 34 are smooth, the patterned features 36 also have smooth sidewalls.

[0030] In embodiments where the one or more masking layers 22 are formed, etching the substrate 20 comprises transferring the pattern of the combined etch mask 34 to the one or more masking layers 22 to form a mask 32; and then transferring the pattern of the mask 32 to the substrate 20. The etching process may comprise one or more etching steps that are selective to the one or more masking layers 22 (e.g., that etch the materials of the one or more masking layers 22 at a higher rate than the materials of the substrate 20). For example, if the one or more masking layers 22 are a multi-layer structure, a first etching step may be performed to pattern the upper masking layer 22B and a second etching step may be performed to pattern the lower masking layer 22A.In embodiments where the one or more masking layers 22 are formed from a metal or a nitride, the mask 32 may be referred to as a hard mask. The substrate 20 is patterned using the mask 32 as an etch mask.

[0031] The Fig. 3 and Fig. 4 show discrete etching processes, but these may be steps of the same etching process. For example, after forming the spacer layer 26 (see Fig. 2) a single continuous etching step is carried out to pattern the substrate 20. During this continuous etching step, the spacers 30 (see Fig. 3) is temporarily produced, and the continuous etching step is carried out until the structured structural elements 36 (see Fig. 4). For example, if the continuous etching step is anisotropic, the horizontal portions of the spacer layer 26 may be etched at a higher speed than its vertical portions, thus temporarily forming the spacers 30.

[0032] In some embodiments, variations of the structuring process described with reference to the Fig. 1 to 4. For example, the one or more masking layers 22 may be omitted, so that the combined etch mask 34 is used to directly pattern the substrate 20. If necessary, fewer or additional spacers and / or mask layers may be used.

[0033] As explained above, the decision taken with reference to the Fig. 1 to 4 may be used to pattern any type of feature in a substrate. In some embodiments, the patterning process is used to pattern features for transistors. Embodiments are described below in a specific context, namely for a die comprising nano-FETs. However, various embodiments may be used for dies comprising other types of transistors (e.g., finFETs, planar transistors, or the like) instead of or in combination with the nano-FETs.

[0034] Fig. 5 shows an example of nano-FETs (e.g., nanowire FETs, nanolayer FETs, or the like) according to some embodiments. Fig. Figure 5 is a three-dimensional diagram in which some structural elements of the nano-FETs are omitted for clarity. The nano-FETs can be nanolayer field-effect transistors (NSFETs), nanowire field-effect transistors (NWFETs), gate-all-around field-effect transistors (GAA-FETs), or the like.

[0035] The nano-FETs include nanostructures 66 (e.g., nanosheets, nanowires, or the like) over fins 62 on a substrate 50 (e.g., a semiconductor substrate), where the nanostructures 66 function as channel regions for the nano-FETs. The nanostructures 66 may be p-type nanostructures, n-type nanostructures, or a combination thereof. Isolation regions 70, such as shallow trench isolation (STI) regions, are disposed between adjacent fins 62, which may extend over and between adjacent isolation regions 70. While the isolation regions 70 are described or illustrated herein as isolation regions separate from the substrate 50, the term "substrate" as used herein may be used to refer to only the semiconductor substrate or a combination of the semiconductor substrate and the isolation regions.And although a lower portion of the fins 62 is illustrated as a single, continuous material with the substrate 50, the lower portion of the fins 62 and / or the substrate 50 may comprise only one material or a plurality of materials. In this context, the fins 62 refer to portions that extend above and out of spaces between adjacent isolation regions 70.

[0036] Gate dielectrics 122 are disposed over top surfaces of the fins 62 and along top surfaces, sidewalls, and bottom surfaces of the nanostructures 66. Gate electrodes 124 are disposed over the gate dielectrics 122. Source / drain epitaxial regions 98 are disposed on the fins 62 on opposite sides of the gate dielectrics 122 and the gate electrodes 124. An interlayer dielectric (ILD) 104 is formed over the source / drain epitaxial regions 98. A contact etch stop layer (CESL) 102 is optionally formed between the ILD 104 and the source / drain epitaxial regions 98. Source / drain contacts (described later) to the source / drain epitaxial regions 98 are formed through the CESL 102 and the ILD 104. The source / drain epitaxial regions 98 can be shared by various nanostructures 66 and fins 62.For example, adjacent source / drain epitaxial regions 98 may be electrically connected, such as by fusing the source / drain epitaxial regions 98 by epitaxial growth or by connecting the source / drain epitaxial regions 98 to the same source / drain contact.

[0037] Fig. 5 also shows reference cross-sections used in later figures. A cross-section A-A' runs along a longitudinal axis of a gate electrode 124 and in a direction that is, for example, perpendicular to a direction of current flow between the source / drain epitaxial regions 98 of a nano-FET. A cross-section B-B' runs along a longitudinal axis of a fin 62 and in a direction, for example, of current flow between the source / drain epitaxial regions 98 of the nano-FET. A cross-section C-C' is parallel to the cross-section A-A' and runs through the source / drain epitaxial regions 98 of the nano-FET. Later figures refer to these reference cross-sections for clarity.

[0038] Some embodiments are discussed herein in the context of nano-FETs fabricated using a gate-last process. In other embodiments, a gate-first process may be used. Additionally, some embodiments contemplate aspects used in planar devices, such as planar FETs, or FinFETs. For example, FinFETs may include fins on a substrate, with the fins acting as channel regions for the FinFETs. Similarly, planar FETs may include a substrate, with portions of the substrate acting as channel regions for the planar FETs.

[0039] The Fig. 6 to 20B are illustrations of intermediate stages in the fabrication of nano-FETs according to some embodiments. Fig. 6 to 10 are three-dimensional representations corresponding to the three-dimensional representation of Fig. 5 are similar. The Fig. 11A, Fig. 12A, Fig. 13A, Fig. 14A, Fig. 15A, Fig. 16A, Fig. 17A, Fig. 18A, Fig. 19A and Fig. 20A show the reference cross section A - A' of Fig. 5. The Fig. 11B, Fig. 12B, Fig. 13B, Fig. 14B, Fig. 15B, Fig. 16B, Fig. 17B, Fig. 18B, Fig. 19B and Fig. 20B show the reference cross section B - B' of Fig. 5. The Fig. 13C and Fig. 13D show the reference cross section C - C' of Fig. 5.

[0040] In Fig. 6, a substrate 50 for fabricating nano-FETs is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Generally, an SOI substrate comprises a layer of a semiconductor material fabricated on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is fabricated on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used.In some embodiments, the semiconductor material of substrate 50 may include: silicon; germanium; a compound semiconductor such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenophosphide; combinations thereof; or the like.

[0041] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to fabricate n-type devices, such as NMOS transistors, e.g., n-nano-FETs, and the p-type region 50P can be used to fabricate p-type devices, such as PMOS transistors, e.g., p-nano-FETs. The n-type region 50N can be physically separated from the p-type region 50P (not individually shown), and numerous device elements (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between the n-type region 50N and the p-type region 50P. While only one n-type region 50N and one p-type region 50P are shown, numerous n-type regions 50N and p-type regions 50P can be provided.

[0042] The substrate 50 may be lightly doped with a p-type or n-type dopant. An anti-punch-through (APT) implantation may be performed on an upper portion of the substrate 50 to create an APT region. During the APT implantation, dopants may be implanted into the substrate 50. The dopants may have a conductivity type opposite to a conductivity type of source / drain regions that are later created in each n-type region 50N and p-type region 50P. The APT region may extend beneath the source / drain regions in the nano-FETs. The APT region may be used to reduce leakage from the source / drain regions to the substrate 50. In some embodiments, the doping concentration in the APT region may be 10 18 cm -3 up to 10 19 cm -3 be.

[0043] A multilayer stack 52 is fabricated over the substrate 50. The multilayer stack 52 includes alternating first semiconductor layers 54 and second semiconductor layers 56. The first semiconductor layers 54 are made of a first semiconductor material, and the second semiconductor layers 56 are made of a second semiconductor material. The semiconductor materials can each be selected from the semiconductor materials that are suitable for the substrate 50. In the illustrated embodiment, the multilayer stack 52 includes three first semiconductor layers 54 and three second semiconductor layers 56. It should be understood that the multilayer stack 52 may include countless first semiconductor layers 54 and second semiconductor layers 56.

[0044] In the illustrated embodiment, and as will be explained in more detail later, the first semiconductor layers 54 are removed, and the second semiconductor layers 56 are patterned to create channel regions for the nano-FETs in the n-type region 50N and the p-type region 50P. The first semiconductor layers 54 are sacrificial layers (or dummy layers) that are removed during later processing to expose bottom and top surfaces of the second semiconductor layers 56. The first semiconductor material of the first semiconductor layers 54 is a material that has high etch selectivity to the etch of the second semiconductor layers 56, such as silicon germanium. The second semiconductor material of the second semiconductor layers 56 is a material suitable for n- and p-type devices, such as silicon.

[0045] In another embodiment (not individually shown), the first semiconductor layers 54 are patterned to create channel regions for nano-FETs in one region (e.g., the p-type region 50P), and the second semiconductor layers 56 are patterned to create channel regions for nano-FETs in another region (e.g., the n-type region 50N). The first semiconductor material for the first semiconductor layers 54 may be a material suitable for p-type devices, such as silicon germanium (e.g., Si x Ge 1-x, where x can be 0 to 1), pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. The second semiconductor material for the second semiconductor layers 56 can be a material suitable for n-type devices, such as silicon, silicon carbide, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. The first and second semiconductor materials can have high etch selectivity to the etching of each other's semiconductor material, so that the first semiconductor layers 54 can be removed without removing the second semiconductor layers 56 in the n-type region 50N, and the second semiconductor layers 56 can be removed without removing the first semiconductor layers 54 in the p-type region 50P.

[0046] The layers of the multilayer stack 52 may each be grown using a process such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), or they may be deposited using a process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), or the like. The layers may each have a small thickness, such as a thickness of 5 nm to 30 nm. In some embodiments, some layers (e.g., the second semiconductor layers 56) are fabricated to be thinner than other layers (e.g., the first semiconductor layers 54).For example, in embodiments where the first semiconductor layers 54 are sacrificial layers (or dummy layers) and the second semiconductor layers 56 are patterned to create channel regions for the nano-FETs in the n-type region 50N and the p-type region 50P, the first semiconductor layers 54 may have a first thickness, and the second semiconductor layers 56 may have a second thickness, where the second thickness is 30% to 60% smaller than the first thickness. By forming the second semiconductor layers 56 with a smaller thickness, the channel regions can be created with a higher density.

[0047] In Fig. 7, trenches are patterned in the substrate 50 and the multilayer stack 52 to produce fins 62, first nanostructures 64, and second nanostructures 66. The fins 62 are semiconductor stripes patterned in the substrate 50. The first nanostructures 64 and the second nanostructures 66 are the remaining portions of the first semiconductor layers 54 and the second semiconductor layers 56, respectively. The trenches may be patterned using any suitable etching technique, such as a reactive ion etch (RIE), a neutral beam etch (NBE), or the like, or a combination thereof. The etch may be anisotropic.

[0048] The fins 62 and the nanostructures 64 and 66 may be patterned using any suitable method. For example, the fins 62 and the nanostructures 64 and 66 may be patterned using one or more photolithography processes, such as double-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithographic and self-aligned processes that can create structures that have, for example, pitches smaller than those otherwise achievable with a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate, which is then patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-aligned process.The sacrificial layer is then removed, and the remaining spacers can then be used as masks for patterning the fins 62 and the nanostructures 64 and 66. In some embodiments, the mask (or other layer) may remain on the nanostructures 64 and 66.

[0049] The structuring process, which is carried out with reference to the Fig. 1 to 4 can also be used to pattern the trenches in the substrate 50 and the multilayer stack 52. As described in the Fig. 22 to 25, for example, the one or more masking layers 22 and / or the photoresist 24 (see Fig. 22) on the multilayer stack 52. The spacer layer 26 (see Fig. 23) can be deposited on the top surfaces and side walls of the structured structural elements of the photoresist 24 using a plasma-assisted deposition process 28 (see Fig. 23), which also smoothes the side walls of the photoresist 24. The spacers 30 (see Fig. 24) can be fabricated by patterning the spacer layer 26 on the photoresist 24. The substrate 50 and the multilayer stack 52 can then be formed using the spacers 30 and the photoresist 24 as a combined etch mask 34 (see Fig. 25) to produce the fins 62 and the nanostructures 64 and 66, respectively. This can reduce the linewidth roughness of the fins 62 and the nanostructures 64 and 66.

[0050] The fins 62 and the nanostructures 64 and 66 may each have a width of 8 nm to 40 nm. In the illustrated embodiment, the fins 62 and the nanostructures 64 and 66 have substantially equal widths in the n-type region 50N and the p-type region 50P. In another embodiment, the fins 62 and the nanostructures 64 and 66 are wider or narrower in one region (e.g., the n-type region 50N) than the fins 62 and the nanostructures 64 and 66 in another region (e.g., the p-type region 50P).

[0051] In Fig. 8, STI regions 70 are created above the substrate 50 and between adjacent fins 62. The STI regions 70 are arranged around at least a portion of the fins 62 such that at least a portion of the nanostructures 64 and 66 protrude between adjacent STI regions 70. In the illustrated embodiment, top surfaces of the STI regions 70 are coplanar (within process variations) with the top surfaces of the fins 62. In some embodiments, the top surfaces of the STI regions 70 are located above or below the top surfaces of the fins 62. The STI regions 70 separate the features of adjacent devices from one another.

[0052] The STI regions 70 may be created using any suitable method. For example, an insulating material may be deposited over the substrate 50 and the nanostructures 64 and 66 and between adjacent fins 62. The insulating material may be an oxide, such as silicon oxide, a nitride, such as silicon nitride, or the like, or a combination thereof, deposited using a CVD process, such as high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD), or the like, or a combination thereof. Other insulating materials deposited using a suitable method may also be used. In some embodiments, the insulating material is silicon oxide deposited using an FCVD process. After the insulating material is deposited, an annealing process may be performed.In one embodiment, the insulating material is deposited such that excess insulating material covers the nanostructures 64 and 66. While the STI regions 70 are each illustrated as only one layer, in some embodiments, multiple layers may be used. For example, in some embodiments, a coating (not individually illustrated) may first be formed along the surfaces of the substrate 50, the fins 62, and the nanostructures 64 and 66. A fill material, such as that mentioned above, may then be deposited over the coating.

[0053] A removal process is then performed on the insulating material to remove excess insulating material over the nanostructures 64 and 66. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, or the like, may be used. In embodiments where a mask remains on the nanostructures 64 and 66, the planarization process may expose or remove the mask. After the planarization process, top surfaces of the insulating material and the mask (if present) or the nanostructures 64 and 66 are coplanar (within process variations). Accordingly, the top surfaces of the mask (if present) or the nanostructures 64 and 66 are not covered with the insulating material. In the illustrated embodiment, the mask does not remain on the nanostructures 64 and 66.The insulating material is then recessed to create the STI regions 70. The insulating material is recessed such that at least a portion of the nanostructures 64 and 66 protrude between adjacent portions of the insulating material. Furthermore, the top surfaces of the STI regions 70 may have a flat surface as shown, a convex surface, a concave surface (such as dishing), or a combination thereof. The top surfaces of the STI regions 70 may be created flat, convex, and / or concave by a suitable etch. The insulating material may be recessed using a suitable etching process, such as one that is selective for the insulating material (e.g., that selectively etches the insulating material of the STI regions 70 at a higher rate than the materials of the fins 62 and the nanostructures 64 and 66). For example, oxide removal may be performed using dilute hydrofluoric acid (dHF acid).

[0054] The process described above is only one example of how the fins 62 and the nanostructures 64 and 66 may be formed. In some embodiments, the fins 62 and / or the nanostructures 64 and 66 may be formed using a mask and an epitaxial growth process. For example, a dielectric layer may be formed over a top surface of the substrate 50, and trenches may be etched through the dielectric layer to expose the underlying substrate 50. The process described with reference to FIG. Fig. The patterning process described in Figures 1 to 4 can also be used to pattern the trenches in the dielectric layer. Epitaxial structures can be epitaxially grown in the trenches, and the dielectric layer can be recessed such that the epitaxial structures protrude from the dielectric layer and form the fins 62 and / or the nanostructures 64 and 66. The epitaxial structures can include the alternating semiconductor materials already described, such as the first and second semiconductor materials. In some embodiments where epitaxial structures are epitaxially grown, the epitaxially grown materials can be doped in situ during growth, thereby eliminating the need for prior and / or subsequent implantations, but in situ and implantation doping can also be used together.

[0055] Additionally, corresponding wells (not individually shown) may be formed in the nanostructures 64 and 66, the fins 62, and / or the substrate 50. The wells may have a conductivity type opposite that of source / drain regions later formed in the n-type region 50N and the p-type region 50P. In some embodiments, a p-type well is formed in the n-type region 50N, and an n-type well is formed in the p-type region 50P. In some embodiments, a p-type well or an n-type well is formed in the n-type region 50N and the p-type region 50P.

[0056] In embodiments with different well types, different implantation steps for the n-type region 50N and the p-type region 50P may be realized using a mask (not individually shown), such as a photoresist. For example, a photoresist may be formed over the fins 62, the nanostructures 64 and 66, and the STI regions 70 in the n-type region 50N. The photoresist is patterned to expose the p-type region 50P. The photoresist may be formed using a spin-on process and may be patterned using suitable photolithography techniques. After the photoresist has been patterned, an implantation with an n-type dopant is performed in the p-type region 50P, where the photoresist may act as a mask to largely prevent n-type dopants from being implanted into the n-type region 50N.The n-dopants can be phosphorus, arsenic, antimony or the like, which fall into the range with a concentration of 10. 13 cm -3 up to 10 14 cm -3 implanted. After implantation, the photoresist can be removed, for example, using a suitable stripping process.

[0057] After or before implanting the p-type region 50P, a mask (not individually shown), such as a photoresist, is formed over the fins 62, the nanostructures 64 and 66, and the STI regions 70 in the p-type region 50P. The photoresist is patterned to expose the n-type region 50N. The photoresist may be formed using a spin-on process and may be patterned using suitable photolithography techniques. After the photoresist has been patterned, an implantation with a p-type dopant may be performed in the n-type region 50N, wherein the photoresist may act as a mask to substantially prevent p-type dopants from being implanted into the p-type region 50P. The p-type dopants may be boron, boron fluoride, indium, or the like, which may be introduced into the region at a concentration of 10 13 cm -3 up to 10 14 cm -3implanted. After implantation, the photoresist can be removed, for example, using a suitable stripping process.

[0058] Following the implantation of the n-type region 50N and the p-type region 50P, an annealing process may be performed to repair implantation damage and activate the implanted p- and / or n-type dopants. In some embodiments where epitaxial structures for the fins 62 and / or the nanostructures 64 and 66 are grown epitaxially, the grown materials may be doped in situ during growth, thereby eliminating the need for implantation, but in situ and implantation doping may also be used together.

[0059] In Fig. 9, a dummy dielectric layer 72 is formed on the fins 62 and the nanostructures 64 and 66. The dummy dielectric layer 72 may be formed from a dielectric material, such as silicon oxide, silicon nitride, a combination thereof, or the like, which may be deposited or thermally grown using suitable techniques. A dummy gate layer 74 is formed over the dummy dielectric layer 72, and a mask layer 76 is formed over the dummy gate layer 74. The dummy gate layer 74 may be deposited over the dummy dielectric layer 72 and subsequently planarized, for example, using a CMP. The mask layer 76 may be deposited over the dummy gate layer 74.The dummy gate layer 74 may be formed from a conductive or non-conductive material, such as amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), a metal, a metal nitride, a metal silicide, a metal oxide, or the like, which may be deposited by physical vapor deposition (PVD), CVD, or the like. The dummy gate layer 74 may be formed from one or more materials that have high etch selectivity toward the etching of insulating materials, e.g., the STI regions 70 and / or the dummy dielectric layer 72. The mask layer 76 may be formed from a dielectric material, such as silicon nitride, silicon oxynitride, or the like. In this example, only one dummy gate layer 74 and only one mask layer 76 are formed across the n-type region 50N and the p-type region 50P.In the illustrated embodiment, the dummy dielectric layer 72 covers the fins 62, the nanostructures 64 and 66, and the STI regions 70, such that the dummy dielectric layer 72 extends over the STI regions 70 and between the dummy gate layer 74 and the STI regions 70. In another embodiment, the dummy dielectric layer 72 covers only the fins 62 and the nanostructures 64 and 66.

[0060] In Fig. 10, the mask layer 76 is patterned using suitable photolithography and etching processes to produce masks 86. The pattern of the masks 86 is then transferred to the dummy gate layer 74 using a suitable etching process to produce dummy gates 84. Optionally, the pattern of the masks 86 can also be transferred to the dummy dielectric layer 72 using a suitable etching process to produce dummy dielectrics 82. The dummy gates 84 cover portions of the nanostructures 64 and 66 that will be exposed during later processing to form channel regions. In particular, the dummy gates 84 extend along the portions of the nanostructures 66 that will be patterned to create channel regions 68. The pattern of the masks 86 can be used to physically separate adjacent dummy gates 84.The dummy gates 84 may also have longitudinal directions that are (within process variations) substantially perpendicular to the longitudinal directions of the fins 62. The masks 86 may optionally be removed after patterning, for example, using a suitable etching process.

[0061] The structuring process, which is carried out with reference to the Fig. 1 to 4 can also be used to pattern the dummy dielectric layer 72 and / or the dummy gate layer 74. As described in the Fig. 26 to 29, for example, the one or more masking layers 22 and / or the photoresist 24 (see Fig. 26) on the dummy gate layer 74. The one or more masking layers 22 may function as the mask layer 76. The spacer layer 26 (see Fig. 27) can be deposited on the top surfaces and side walls of the patterned structural elements of the photoresist 24 using a plasma-assisted deposition process 28 (see Fig. 27), which also smoothes the side walls of the photoresist 24. The spacers 30 (see Fig. 28) can be fabricated by patterning the spacer layer 26 on the sidewalls of the photoresist 24. Then, the dummy dielectric layer 72 and / or the dummy gate layer 74 can be formed using the spacers 30 and the photoresist 24 as a combined etch mask 34 (see Fig. 29) to produce the dummy dielectrics 82 and the dummy gates 84, respectively. This can reduce the linewidth roughness of the dummy dielectrics 82 and the dummy gates 84.

[0062] The Fig. 11A to 20B show various further steps in the manufacture of exemplary devices. Fig. Figures 11A to 20B show structural elements in the n-type region 50N and the p-type region 50P. For example, the structures shown can be used for both the n-type region 50N and the p-type region 50P. Differences (if any) between the structures of the n-type region 50N and the p-type region 50P are described in the text accompanying each figure.

[0063] In the Fig. 11A and Fig. 11B, gate spacers 90 are formed over the nanostructures 64 and 66, on exposed sidewalls of the masks 86 (if present), the dummy gates 84, and the dummy dielectrics 82. The gate spacers 90 may be formed by conformally depositing one or more dielectric materials and subsequently etching the dielectric materials. Suitable dielectric materials may be silicon oxide, silicon nitride, silicon oxynitride, silicon oxide carbonitride, or the like, which may be deposited using a conformal deposition process such as CVD, plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), or the like. Other insulating materials deposited using a suitable process may also be used. In the illustrated embodiment, the gate spacers 90 each comprise multiple layers, e.g.,a first spacer layer 90A and a second spacer layer 90B. In some embodiments, the first spacer layer 90A and the second spacer layer 90B are formed of silicon oxide carbonitride (e.g., SiO. x N y C 1-x-y, where x and y are 0 to 1), wherein the first spacer layer 90A is made of silicon oxide carbonitride having a similar composition to, or a different composition than, the second spacer layer 90B. To pattern the one or more dielectric materials, a suitable etching process, such as a dry etch, a wet etch, or the like, or a combination thereof, may be performed. The etch may be anisotropic. The one or more dielectric materials, after etching, have portions remaining on the sidewalls of the dummy gates 84 (thus forming the gate spacers 90). As will be explained in more detail later, the one or more dielectric materials, after etching, may also have portions remaining on the sidewalls of the fins 62 and / or the nanostructures 64 and 66 (thus forming the fin spacers 92; see Fig. 13C and Fig. 13D). After etching, the fin spacers 92 and / or the gate spacers 90 may have straight sidewalls (as shown) or curved sidewalls (not individually shown).

[0064] Additionally, implantations may be performed to create lightly doped source / drain regions (LDD regions; not individually shown). In the embodiments with different device types, similar to the implantations for the wells described above, a mask (not individually shown), such as a photoresist, may be formed over the n-type region 50N while leaving the p-type region 50P uncovered, and appropriate dopants (e.g., p-type dopants) may be implanted into the fins 62 and / or the nanostructures 64 and 66 exposed in the p-type region 50P. Subsequently, the mask may be removed. Then, a mask (not individually shown), such as a photoresist, may be formed over the p-type region 50P while leaving the n-type region 50N uncovered, and appropriate dopants (e.g.,N-type dopants may be implanted into the fins 62 and / or the nanostructures 64 and 66 exposed in the n-type region 50N. The mask may then be removed. The n-type dopants may be some of the aforementioned n-type dopants, and the p-type dopants may be some of the aforementioned p-type dopants. During the implantation, the channel regions 68 remain covered by the dummy gates 84, such that the channel regions 68 remain substantially free of the dopants implanted to create the LDD regions. The LDD regions may have a dopant concentration of 10%. 15 cm -3 up to 10 19 cm -3 An annealing process can be performed to repair implantation damage and activate the implanted dopants.

[0065] It should be noted that the above disclosure generally describes a method for fabricating spacers and LDD regions. Other processes and process flows may also be used. For example, fewer or more spacers may be used, a different sequence of steps may be used, additional spacers may be fabricated and removed, and / or the like. Furthermore, n- and p-type devices may be fabricated using different structures and steps.

[0066] In the Fig. 12A and Fig. 12B, source / drain recesses 94 are created in the nanostructures 64 and 66. In the illustrated embodiment, the source / drain recesses 94 extend through the nanostructures 64 and 66 and into the fins 62. The source / drain recesses 94 may also extend into the substrate 50. In various embodiments, the source / drain recesses 94 may extend to a top surface of the substrate 50 without etching the substrate 50; the fins 62 may be etched such that bottom surfaces of the source / drain recesses 94 are below the top surfaces of the STI regions 70; or the like. The source / drain recesses 94 may be created by etching the nanostructures 64 and 66 with anisotropic etch processes, such as an RIE, an NBE, or the like.The gate spacers 90 and the dummy gates 84 collectively mask portions of the fins 62 and / or the nanostructures 64 and 66 during the etching processes used to create the source / drain recesses 94. Only one etching process may be used to etch each of the nanostructures 64 and 66, or multiple etching processes may be used. Timed etching processes may be used to terminate the etching of the source / drain recesses 94 after reaching a desired depth.

[0067] Optionally, internal spacers 96 may be formed on the sidewalls of the remaining portions of the first nanostructures 64, e.g., the sidewalls exposed by the source / drain recesses 94. As will be explained in more detail later, source / drain regions are subsequently formed in the source / drain recesses 94, and the first nanostructures 64 are then replaced by corresponding gate structures. The internal spacers 96 act as insulation elements between the subsequently formed source / drain regions and the subsequently formed gate structures. Furthermore, the internal spacers 96 may be used to largely prevent damage to the subsequently formed source / drain regions by subsequent etching processes, such as etching processes used to later remove the first nanostructures 64.

[0068] As an example for fabricating the internal spacers 96, the source / drain recesses 94 may be laterally expanded. In particular, portions of the sidewalls of the first nanostructures 64 that have been exposed by the source / drain recesses 94 may be recessed. While the sidewalls of the first nanostructures 64 are shown to be straight, the sidewalls may also be concave or convex. The sidewalls may be recessed using a suitable etching process, such as an etching process that is selective for the material of the first nanostructures 64 (e.g., that etches the material of the first nanostructures 64 at a higher rate than the material of the second nanostructures 66). The etching may be isotropic.For example, if the second nanostructures 66 are made of silicon and the first nanostructures 64 are made of silicon germanium, the etching process may be a wet etch using tetramethylammonium hydroxide (TMAH), ammonium hydrate (NH 4OH) or the like. In another embodiment, the etching process may be a dry etch using a fluorine-based gas, such as hydrogen fluoride (HF) gas. In some embodiments, the same etching process may be performed continuously to create the source / drain recesses 94 and recess the sidewalls of the first nanostructures 64. The internal spacers 96 may then be formed by conformally depositing an insulating material and subsequently etching the insulating material. The insulating material may be silicon nitride or silicon oxynitride, but any suitable materials may be used, such as low-k dielectric materials (e.g., dielectric materials with a k value of less than about 3.5). The insulating material may be deposited using a conformal deposition method such as ALD, CVD, or the like. The etching of the insulating material may be anisotropic.The etching process may be, for example, a dry etch such as RIE, NBE, or the like. While outer sidewalls of the inner spacers 96 are illustrated as being flush with the sidewalls of the gate spacers 90, the outer sidewalls of the inner spacers 96 may extend beyond or be recessed from the sidewalls of the gate spacers 90. In other words, the inner spacers 96 may partially or completely fill or overfill the sidewall recesses. Furthermore, while the sidewalls of the inner spacers 96 are illustrated as straight sidewalls, they may also be concave or convex.

[0069] In the Fig. 13A and Fig. 13B, source / drain epitaxial regions 98 are formed in the source / drain recesses 94. The source / drain epitaxial regions 98 are formed in the source / drain recesses 94 such that each dummy gate 84 (and corresponding channel regions 68) are disposed between respective adjacent pairs of source / drain epitaxial regions 98. In some embodiments, the gate spacers 90 and the inner spacers 96 are used to separate the source / drain epitaxial regions 98 from the dummy gates 84 and the first nanostructures 64, respectively, by an appropriate lateral spacing such that the source / drain epitaxial regions 98 do not short-circuit later-fabricated gates of the resulting nano-FETs. The material for the source / drain epitaxial regions 98 can be selected to introduce mechanical stress into the respective channel regions 68, thereby improving performance.

[0070] The source / drain epitaxial regions 98 in the n-type region 50N may be created by masking the p-type region 50P. The source / drain epitaxial regions 98 in the n-type region 50N are then epitaxially grown in the source / drain recesses 94 in the n-type region 50N. The source / drain epitaxial regions 98 may comprise a material suitable for n-type devices. For example, the source / drain epitaxial regions 98 in the n-type region 50N may comprise materials that inject tensile stress into the channel regions 68, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like. The source / drain epitaxial regions 98 in the n-type region 50N may also be referred to as "n-source / drain regions." The source / drain epitaxial regions 98 in the n-region 50N may have surfaces that are raised from respective surfaces of the fins 62 and the nanostructures 64 and 66, and they may have chamfers.

[0071] The source / drain epitaxial regions 98 in the p-type region 50P may be created by masking the n-type region 50N. The source / drain epitaxial regions 98 in the p-type region 50P are then epitaxially grown in the source / drain recesses 94 in the p-type region 50P. The source / drain epitaxial regions 98 may comprise a material suitable for p-type devices. For example, the source / drain epitaxial regions 98 in the p-type region 50P may comprise materials that inject compressive stress into the channel regions 68, such as silicon germanium, boron-doped silicon germanium, germanium, germanium-tin, or the like. The source / drain epitaxial regions 98 in the p-type region 50P may also be referred to as "p-source / drain regions." The source / drain epitaxial regions 98 in the p-type region 50P may have surfaces that are raised from respective surfaces of the fins 62 and the nanostructures 64 and 66, and they may have chamfers.

[0072] The source / drain epitaxial regions 98, the nanostructures 64 and 66, and / or the fins 62 may be implanted with dopants to create source / drain regions, similar to the process described above for creating LDD regions, and then an annealing process may be performed. The source / drain regions may have a doping concentration of 10 19 cm -3 up to 10 21 cm -3 The n- and / or p-type dopants for the source / drain regions may be some of the aforementioned dopants. In some embodiments, the source / drain epitaxial regions 98 may be doped in situ during growth.

[0073] Due to the epitaxial processes used to create the source / drain epitaxial regions 98, top surfaces of the source / drain epitaxial regions 98 have chamfers that extend laterally outward beyond the sidewalls of the fins 62 and the nanostructures 64 and 66. In some embodiments, these chamfers cause adjacent source / drain epitaxial regions 98 to merge together, as shown in Fig. 13C. In some embodiments, adjacent source / drain epitaxial regions 98 remain separated after completion of the epitaxial process, as shown in Fig. 13D. In the illustrated embodiments, the spacer etch used to form the gate spacers 90 is adjusted to also form fin spacers 92 on the sidewalls of the fins 62 and / or the nanostructures 64 and 66. The fin spacers 92 are formed to cover a portion of the sidewalls of the fins 62 and / or the nanostructures 64 and 66 that extend above the STI regions 70, thereby blocking epitaxial growth. In another embodiment, the spacer etch used to form the gate spacers 90 is adjusted to not form fin spacers to allow the source / drain epitaxial regions 98 to extend to the surface of the STI regions 70.

[0074] The source / drain epitaxial regions 98 may include one or more semiconductor material layers. For example, the source / drain epitaxial regions 98 may each include a cap layer 98A, a main layer 98B, and a cap layer 98C (or more generally, a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer). Any number of semiconductor material layers may be used for the source / drain epitaxial regions 98. The cap layer 98A, the main layer 98B, and the cap layer 98C may each be made of different semiconductor materials and may be doped with different doping concentrations.In some embodiments, the cap layer 98A may have a lower doping concentration than the main layer 98B, and the cap layer 98C may have a higher doping concentration than the cap layer 98A and a lower doping concentration than the main layer 98B. In embodiments where the source / drain epitaxial regions 98 include three semiconductor material layers, the cap layer 98A may be grown in the source / drain recesses 94, the main layer 98B may be grown on the cap layer 98A, and the cap layer 98C may be grown on the main layer 98B.

[0075] In the Fig. 14A and Fig. 14B, a first ILD 104 is deposited over the source / drain epitaxial regions 98, the gate spacers 90, the masks 86 (if present), or the dummy gates 84. The first ILD 104 may be formed from a dielectric material deposited using a suitable process such as CVD, PECVD, FCVD, or the like. Suitable dielectric materials may be phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials deposited using a suitable process may also be used.

[0076] In some embodiments, a CESL 102 is formed between the first ILD 104, on the one hand, and the source / drain epitaxial regions 98, the gate spacers 90, and the masks 86 (if present) or the dummy gates 84, on the other hand. The CESL 102 may be formed from a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, that has a high etch selectivity to the etch of the first ILD 104. The CESL 102 may be formed using a suitable process, such as CVD, ALD, or the like.

[0077] In the Fig. 15A and Fig. 15B, a removal process is performed to bring a top surface of the first ILD 104 level with the top surfaces of the masks 86 (if present) or the dummy gates 84. In some embodiments, a planarization process, such as a CMP process, an etch-back process, a combination thereof, or the like, may be used. The planarization process may also remove the masks 86 on the dummy gates 84, as well as portions of the gate spacers 90 along the sidewalls of the masks 86. After the planarization process, the top surfaces of the gate spacers 90, the first ILD 104, the CESL 102, and the masks 86 (if present) or the dummy gates 84 (within process variations) are coplanar. Accordingly, the top surfaces of the masks 86 (if present) or the dummy gates 84 are not covered by the first ILD 104.In the illustrated embodiment, the masks 86 remain in place, and the planarization process brings the top surfaces of the first ILD 104 to the same height as the top surfaces of the masks 86.

[0078] In the Fig. 16A and Fig. 16B, the masks 86 (if present) and the dummy gates 84 are removed in an etch process to form recesses 106. Portions of the dummy gate dielectrics 82 in the recesses 106 are also removed. In some embodiments, the dummy gates 84 are removed using an anisotropic dry etch process. For example, the etch process may be a dry etch process using one or more reactant gases that etch the dummy gates 84 at a higher rate than the first ILD 104 or the gate spacers 90. During removal, the dummy gate dielectrics 82 may be used as etch stop layers when the dummy gates 84 are etched. Then, the dummy gate dielectrics 82 are removed. Each recess 106 exposes and / or covers portions of the channel regions 68. Portions of the second nanostructures 66, which function as the channel regions 68, are arranged between adjacent pairs of source / drain epitaxial regions 98.

[0079] Then, the remaining parts of the first nanostructures 64 are removed to widen the recesses 106, so that openings 108 are created in regions 501 between the second nanostructures 66. The remaining parts of the first nanostructures 64 can be removed using a suitable etching process in which the material of the first nanostructures 64 is etched at a higher speed than the material of the second nanostructures 66. The etching can be isotropic. For example, if the first nanostructures 64 are made of silicon germanium and the second nanostructures 66 are made of silicon, the etching process can be a wet etch using tetramethylammonium hydroxide (TMAH), ammonium hydrate (NH 4 OH) or the like. In some embodiments, a trimming process (not individually shown) is performed to reduce thicknesses of the exposed portions of the second nanostructures 66.

[0080] In the Fig. 17A and Fig. 17B, ​​a gate dielectric layer 112 is formed in the recesses 106. A gate electrode layer 114 is formed on the gate dielectric layer 112. The gate dielectric layer 112 and the gate electrode layer 114 are layers for replacement gates, and they each enclose all (e.g., four) sides of the second nanostructures 66. In this way, the gate dielectric layer 112 and the gate electrode layer 114 are formed in the openings 108 between the second nanostructures 66.

[0081] The gate dielectric layer 112 is disposed on the sidewalls and / or top surfaces of the fins 62, on the top surfaces, sidewalls, and bottom surfaces of the second nanostructures 66, and on the sidewalls of the gate spacers 90. The gate dielectric layer 112 may also be formed on the top surfaces of the first ILD 104 and the gate spacers 90. The gate dielectric layer 112 may comprise an oxide, such as silicon oxide, or a metal oxide, a silicate, such as a metal silicate, combinations thereof, multilayers thereof, or the like. The gate dielectric layer 112 may comprise a high-k dielectric material (e.g., a dielectric material having a k value greater than about 7.0), such as a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Fig. 17A and Fig. 17B illustrates a single-layer gate dielectric layer 112, but the gate dielectric layer 112 may include any number of interface layers and any number of main layers.

[0082] The gate electrode layer 114 may comprise a metal-containing material such as titanium nitride, titanium oxide, tungsten, cobalt, ruthenium, aluminum, combinations thereof, multilayers thereof, or the like. Fig. 17A and Fig. 17B, ​​a single-layer gate electrode layer 114 is shown, but the gate electrode layer 114 may include any number of work function adjustment layers, any number of barrier layers, any number of adhesive layers, and a filler material.

[0083] The formation of the gate dielectric layers 112 may occur simultaneously in the n-type region 50N and the p-type region 50P, such that the gate dielectric layers 112 are formed from the same materials in each region, and the formation of the gate electrode layers 114 may also occur simultaneously, such that they are formed from the same materials in each region. In some embodiments, the gate dielectric layers 112 in each region may be formed using different processes, such that they may be different materials and / or each have a different number of layers, and / or the gate electrode layers 114 in each region may be formed using different processes, such that they may be different materials and / or each have a different number of layers.Different masking steps can be used to mask or leave corresponding areas uncovered when different processes are used.

[0084] In the Fig. 18A and Fig. 18B, a removal process is performed to remove excess portions of the materials of the gate dielectric layer 112 and the gate electrode layer 114 located above the top surfaces of the first ILD 104 and the gate spacers 90, thereby forming gate dielectrics 122 and gate electrodes 124. In some embodiments, a planarization process, such as a CMP process, an etch-back process, a combination thereof, or the like, may be used. After planarization, portions of the gate dielectric layer 112 remain in the recesses 106 (thus forming the gate dielectrics 122). After planarization, portions of the gate electrode layer 114 remain in the recesses 106 (thus forming the gate electrodes 124). The top surfaces of the gate spacers 90, the CESL 102, the first ILD 104, the gate dielectrics 122 and the gate electrodes 124 are coplanar (within process variations).The gate dielectrics 122 and the gate electrodes 124 form replacement gates (sometimes referred to as "metal gates") of the resulting nano-FETs. Each respective pair of a gate dielectric 122 and a gate electrode 124 may be collectively referred to as a "gate structure." The gate structures extend along top surfaces, sidewalls, and bottom surfaces, respectively, of a channel region 68 of the second nanostructures 66.

[0085] In the Fig. 19A and Fig. 19B, a second ILD 134 is deposited over the gate spacers 90, the CESL 102, the first ILD 104, the gate dielectrics 122, and the gate electrodes 124. In some embodiments, the second ILD 134 is a flowable layer formed using a flowable CVD process. In some embodiments, the second ILD 134 is formed from a dielectric material such as PSG, BSG, BPSG, USG, or the like, which may be deposited using a suitable process such as CVD, PECVD, or the like.

[0086] In some embodiments, an etch stop layer (ESL) 132 is formed between the second ILD 134, on the one hand, and the gate spacers 90, the CESL 102, the first ILD 104, the gate dielectrics 122, and the gate electrodes 124, on the other hand. The ESL 132 may comprise a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, that has a high etch selectivity to the etch of the second ILD 134.

[0087] In the Fig. 20A and Fig. 20B, gate contacts 142 and source / drain contacts 144 are fabricated for contacting the gate electrodes 124 and the source / drain epitaxial regions 98, respectively. The gate contacts 142 are physically and electrically connected to the gate electrodes 124. The source / drain contacts 144 are physically and electrically connected to the source / drain epitaxial regions 98.

[0088] As an example for forming the gate contacts 142 and the source / drain contacts 144, openings for the gate contacts 142 are created by the second ILD 134 and the ESL 132, and openings for the source / drain contacts 144 are created by the second ILD 134, the ESL 132, the first ILD 104, and the CESL 102. The openings may be created using suitable photolithography and etching techniques. A coating (not individually shown), such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are deposited in the openings. The coating may comprise titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as CMP, may be performed to remove excess material from a surface of the second ILD 134.The remaining coating and conductive material form the gate contacts 142 and the source / drain contacts 144 in the openings. The gate contacts 142 and the source / drain contacts 144 can be formed using different processes or the same process. While the gate contacts 142 and the source / drain contacts 144 are shown as having the same cross-sections, it should be understood that they can each be formed using different cross-sections to avoid shorting the contacts.

[0089] Optionally, metal-semiconductor alloy regions 146 may be formed at the interfaces between the source / drain epitaxial regions 98 and the source / drain contacts 144. The metal-semiconductor alloy regions 146 may include: silicide regions made of a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.); germanide regions made of a metal germanide (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.); silicon germanide regions made of a metal silicide and a metal germanide; or the like. The metal-semiconductor alloy regions 146 may be formed prior to the deposition of the source / drain contact materials 144 by depositing a metal in the openings for the source / drain contacts 144 and then performing a thermal annealing process. The metal can be a metal that is compatible with the semiconductor materials (e.g. silicon, silicon germanium, germanium, etc.) of the source / drain epitaxial regions 98 to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, another precious metal, another refractory metal, a rare earth metal, or an alloy thereof. The metal may be deposited using a deposition process such as ALD, CVD, PVD, or the like. After the thermal annealing process, a cleaning process, such as wet cleaning, may be performed to remove residual metal from the openings for the source / drain contacts 144, such as from surfaces of the metal-semiconductor alloy regions 146. The one or more materials for the source / drain contacts 144 may then be deposited on the metal-semiconductor alloy regions 146.

[0090] As stated above, some embodiments contemplate aspects used in planar devices, such as planar FETs, or FinFETs. Fig. 21A and Fig. 21B are illustrations of FinFETs according to some embodiments. The Fig. 21A and Fig. 21B show a similar representation as the Fig. 20A and Fig. 20B, except that FinFETs are used instead of Nano-FETs. In this embodiment, the fins 62 have channel regions 68, and the gate structures extend along the sidewalls and top surfaces of the fins 62. The fins 62 may be fabricated in the substrate 50, similarly to that described with reference to Fig. 7 (e.g. with the structuring process described with reference to the Fig. 1 to 4).

[0091] Embodiments may achieve advantages. By depositing the spacer layer 26 on the sidewalls of the photoresist 24 using the plasma-assisted deposition process 28, the roughness of the sidewalls of the photoresist 24 may be reduced. Furthermore, by depositing the spacer layer 26 with a sufficient thickness, losses incurred by etching the photoresist 24 may be compensated. An etch mask with smooth sidewalls may be produced, thereby reducing the linewidth roughness of deeper features patterned using the etch mask.

[0092] The invention is defined by the main claim and the subordinate claims. The subclaims describe further embodiments of the invention.

Claims

[1] Procedure comprising: Producing a photoresist (24) over a target layer (20); Performing a plasma-assisted deposition process (28), wherein in the plasma-assisted deposition process sidewalls of the photoresist (24) are etched while a spacer layer (26) is deposited on the sidewalls of the photoresist; Structuring the spacer layer (26) to produce spacers (30) on the sidewalls of the photoresist (24); and Etching the target layer (20) using the spacers (30) and the photoresist (24) as a combined etch mask (34); wherein the plasma-assisted deposition process comprises performing an atomic layer deposition cycle, hereinafter referred to as ALD cycle, several times, and wherein the ALD cycle comprises: - treating the photoresist (24) with a first precursor in a first cycle of the ALD cycle, - treating the photoresist (24) with a second precursor in a second cycle of the ALD cycle, wherein the second precursor is reacted with the first precursor to deposit the spacer layer (26), and - generating a plasma from the second precursor during the second clock of the ALD cycle, wherein the plasma etches the sidewalls of the photoresist (24). [2] The method of claim 1, wherein the target layer (20) is a semiconductor substrate (50) and etching the target layer forms a channel region (68) for a transistor. [3] The method of claim 1, wherein the target layer (20) is a conductive layer (74) and etching the target layer forms a gate structure for a transistor. [4] The method of any preceding claim, wherein the sidewalls of the photoresist (24) have a first roughness before the plasma-assisted deposition process (28) and have a second roughness after the plasma-assisted deposition process, the second roughness being lower than the first roughness. [5] The method of claim 4, wherein sidewalls of the combined etch mask (34) have a third roughness, the third roughness being lower than the second roughness. [6] The method of any preceding claim, wherein the photoresist (24) has a first width before the plasma-assisted deposition process (28) and a second width after the plasma-assisted deposition process, the second width being smaller than the first width. [7] The method of claim 6, wherein the combined etch mask (34) has a third width, the third width being greater than the second width. [8] A method according to any one of the preceding claims, wherein the first precursor contains silicon; the second precursor contains oxygen; and the spacer layer (26) contains silicon oxide. [9] Procedure comprising: Forming a photoresist (24) over a semiconductor substrate (50); Reducing a roughness of sidewalls of the photoresist (24) by etching the sidewalls of the photoresist; Depositing an oxide layer (26) on the sidewalls of the photoresist (24) while they are etched; Etching the oxide layer (26) to produce spacers (30) on the sidewalls of the photoresist (24); and Creating a channel region (68) by etching trenches in the semiconductor substrate (50) using the spacers (30) and the photoresist (24) as a combined etching mask (34); wherein the etching of the side walls of the photoresist (24) and the deposition of the oxide layer (26) are carried out by repeatedly performing an atomic layer deposition cycle, hereinafter referred to as ALD cycle, and wherein the ALD cycle comprises: - treating the photoresist (24) with a first precursor in a first cycle of the ALD cycle, - treating the photoresist (24) with an oxygen-containing second precursor in a second cycle of the ALD cycle, wherein the oxygen-containing second precursor is brought into reaction with the first precursor to deposit the oxide layer (26), and - generating a plasma from the oxygen-containing second precursor during the second cycle of the ALD cycle, wherein the plasma etches the sidewalls of the photoresist (24). [10] The method of claim 9, wherein etching the trenches in the semiconductor substrate (50) forms a nanostructure (66) having the channel region (68). [11] The method of claim 9, wherein etching the trenches in the semiconductor substrate (50) forms a fin (62) having the channel region (68). [12] The method of any one of claims 9 to 11, wherein etching the sidewalls of the photoresist (24) reduces a width of the photoresist. [13] Method comprising: Forming a photoresist (24) over a substrate (20); Carrying out an atomic layer deposition cycle, hereinafter referred to as ALD cycle, comprising: - treating the photoresist (24) with a silicon-containing precursor in a first step of the ALD cycle, - treating the photoresist (24) with an oxygen-containing precursor in a second cycle of the ALD cycle, wherein the oxygen-containing precursor is reacted with the silicon-containing precursor to deposit a spacer material (26) on sidewalls of the photoresist, and - generating a plasma from the oxygen-containing precursor during the second cycle of the ALD cycle, the plasma etching the sidewalls of the photoresist (24); and Repeating the ALD cycle several times. [14] The method of claim 13, wherein the second cycle of the ALD cycle is performed at a temperature of room temperature to 120 °C, at a pressure of 133 Pa to 667 Pa and for a duration of 1 min to 5 min, wherein a plasma generation power is a high power of 15 W to 800 W and has a cycle frequency of 40 kHz to 60 MHz. [15] The method of claim 13 or 14, wherein the spacer material (26) is an oxide, the silicon-containing precursor is silane, and the oxygen-containing precursor is oxygen gas. [16] The method of claim 13 or 14, wherein the spacer material (26) is an oxide, the silicon-containing precursor is silane, and the oxygen-containing precursor is ozone. [17] The method of claim 13 or 14, wherein the spacer material (26) is silicon oxide and the method further comprises: Patterning the spacer material (26) to form spacers (30) on the sidewalls of the photoresist (24) by performing an anisotropic dry etch with a halogen-based etchant. [18] A method according to any one of claims 13 to 16, further comprising: Patterning the spacer material (26) to form spacers (30) on the sidewalls of the photoresist (24); Etching the substrate (20) using the spacers (30) and the photoresist (24) as a combined etch mask (34) to form a fin (62); and Forming a gate structure on a channel region (68) of the fin (62). [19] A method according to any one of claims 13 to 16, further comprising: Patterning the spacer material (26) to form spacers (30) on the sidewalls of the photoresist (24); Etching the substrate (20) using the spacers (30) and the photoresist (24) as a combined etch mask (34) to form a nanostructure (66); and Forming a gate structure on a channel region (68) of the nanostructure (66). [20] A method according to any one of claims 13 to 16, further comprising: Patterning the spacer material (26) to form spacers (30) on the sidewalls of the photoresist (24); Etching the substrate (20) using the spacers (30) and the photoresist (24) as a combined etch mask (34) to produce a dummy gate on a channel region (68); and Replacing the dummy gate (84) with a metal gate (124).

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