Semiconductor device

Abstract

Semiconductor device comprising: a semiconductor substrate; a transistor region (10) in which a transistor is formed, the transistor having a base layer (15) of a first conductivity type arranged in a surface layer of the semiconductor substrate, a source layer (13) of a second conductivity type selectively arranged in a surface layer of the base layer (15), and a trench gate (11) extending such that it intersects the source layer (13) in plan view; a diode area (20) which is arranged adjacent to the transistor area (10) and in which a diode is formed; a gate (51) of a boundary trench, which is arranged in a boundary subregion between the transistor area (10) and the diode area (20); and a carrier control region (50) which is arranged as the surface layer of the semiconductor substrate at a position closer to the gate (51) of a boundary trench than the source layer (13) located between the gate (51) of a boundary trench and the trench gate (11), wherein a concentration of defects of a first conductivity type contained in the carrier control region (50) is higher than a concentration of defects of a first conductivity type contained in the source layer (13), or a concentration of defects of a second conductivity type contained in the carrier control region (50) is lower than a concentration of defects of a second conductivity type contained in the source layer (13); the transistor region (10) has a collector layer (16) of a first conductivity type, which is arranged in a surface layer on one side of a lower surface of the semiconductor substrate; the transistor area (10) has a contact layer (14) of a first conductivity type, which is formed in the surface layer of the base layer (15), a concentration of defects of a first conductivity type contained in the contact layer (14) is higher than a concentration of defects of a first conductivity type contained in the base layer (15), wherein the collector layer (16) is arranged such that it projects into the diode region (20); and wherein the carrier control area (50) has the base layer (15) arranged between the source layer (13) and the gate (51) of a boundary trench and the contact layer (14) is not arranged in the carrier control area (50).

Description

Background of the invention; Field of the invention

[0001] The present disclosure relates to a semiconductor device. Description of the background technology

[0002] Reverse-conducting insulated-gate bipolar transistors (RC-IGBTs) were developed to improve the performance of semiconductor devices and reduce their cost. An RC-IGBT incorporates an IGBT and a diode embedded in the same semiconductor substrate. That is, the RC-IGBT is a semiconductor device that integrates the functions of both the IGBT and the diode onto a single chip. A transistor region containing an IGBT cell structure and a diode region containing a diode cell structure are arranged within the same plane of the semiconductor substrate forming the RC-IGBT. The structure of an interface region between the transistor region and the diode region influences the electrical characteristics of the RC-IGBT.

[0003] See, for example, JP 6 319 057 B2.

[0004] Since a contact layer from p + Since a p-type anode in the transistor region has a lower resistance than a p-type anode in the diode region, holes (carriers) flow easily from the diode region to the transistor region when the diode's operation is switched from on to off. Therefore, holes become concentrated at the interface between the diode and transistor regions, and a large current is more likely to flow near the interface than elsewhere. This current concentration can cause diode failure.

[0005] JP 2017-98359A discloses a semiconductor device in which a semiconductor layer is divided from the center of an IGBT region to the boundary between the IGBT region and a diode region by one-third of a distance from the center to the boundary. In this device, a first region comprising all the side faces where a trench gate, contained in a division region on the boundary side, projects into a drift region is larger than a second region, comprising all the side faces where the trench gate, contained in a division region, projects into a drift region on the central side. A third region, comprising all the side faces if a trench gate is contained in a separation region between the separation region on the boundary side and the separation region on the central side and projects into the drift region, is equal to or larger than the second region but equal to or smaller than the first region.

[0006] DE 11 2012 003 111 T5 discloses a technology capable of reducing a loss at the time of switching in a diode.A diode disclosed in the present specification comprises a cathode electrode, a cathode region consisting of a semiconductor of a first conductivity type, a drift region consisting of a semiconductor of the first conductivity type with a low concentration, an anode region consisting of a semiconductor of a second conductivity type, an anode electrode made of metal, a barrier region formed between the drift region and the anode region and consisting of a semiconductor of the first conductivity type with a higher concentration than that of the drift region, and a pillar region configured to connect the barrier region to the anode electrode and consisting of a semiconductor of the first conductivity type with a higher concentration than that of the boundary region. The pillar region and the anode are connected via a Schottky junction.

[0007] LUTZ, J. [et al.]: Semiconductor Power Devices. Heidelberg : Springer, 2011. pp. 331f. - ISBN 978-3-642-11124-2 reveals power semiconductors and operating principles of power diodes, thyristors, MOSFETs and IGBTs.

[0008] Another semiconductor device is known from US 2014 / 0 084 337 A1. Summary

[0009] To solve the above problems, the present disclosure provides a semiconductor device that reduces element destruction caused by a current concentrated at an interface region between a transistor region and a diode region.

[0010] This problem is solved by the features of the independent claim. The dependent claims contain advantageous embodiments of the invention.

[0011] The semiconductor device according to one aspect of the present disclosure comprises a semiconductor substrate, a transistor region, a diode region, a gate of a boundary trench, and a carrier control region. A transistor is formed in the transistor region. The transistor has a base layer of a first conductivity type, a source layer of a second conductivity type, and a trench gate. The base layer of the first conductivity type is arranged in a surface layer of the semiconductor substrate. The source layer of the second conductivity type is selectively arranged in a surface layer of the base layer. The trench gate extends such that, in plan view, it intersects the source layer. A diode is formed in the diode region. The diode region is arranged adjacent to the transistor region.The gate of a boundary trench is located in a boundary subregion between the transistor and diode regions. The carrier control region is the surface layer of the semiconductor substrate located closer to the gate of the boundary trench than the source layer situated between the gate of the boundary trench and the trench gate. The concentration of first-conductivity-type defects in the carrier control region is higher than the concentration of first-conductivity-type defects in the source layer, or the concentration of second-conductivity-type defects in the carrier control region is lower than the concentration of second-conductivity-type defects in the source layer.

[0012] The semiconductor device of the present disclosure reduces element destruction caused by a current concentrated at an interface region between a transistor region and a diode region.

[0013] These and other tasks, features, aspects and advantages of the present disclosure will become more apparent from the following detailed description of the present disclosure when it is taken in conjunction with the accompanying drawings. Brief description of the drawings Fig. 1 is a top view illustrating an example of a configuration of a semiconductor device according to a first preferred embodiment; Fig. 2 is a top view illustrating an example of a configuration of the semiconductor device according to the first preferred embodiment; Fig. Figure 3 is a partially enlarged top view illustrating a configuration of an IGBT area of ​​the semiconductor device according to the first preferred embodiment; Fig. Figure 4 is a cross-sectional view illustrating a configuration of the IGBT area of ​​the semiconductor device according to the first preferred embodiment; Fig. Figure 5 is a cross-sectional view illustrating a configuration of the IGBT area of ​​the semiconductor device according to the first preferred embodiment; Fig. Figure 6 is a partially enlarged top view illustrating a configuration of a diode area of ​​the semiconductor device according to the first preferred embodiment; Fig. Figure 7 is a cross-sectional view illustrating a configuration of the diode area of ​​the semiconductor device according to the first preferred embodiment; Fig. Figure 8 is a cross-sectional view illustrating a configuration of the diode area of ​​the semiconductor device according to the first preferred embodiment; Fig. Figure 9 is a top view illustrating a configuration of a boundary sub-region between the IGBT region and the diode region; Fig. Figure 10 is a cross-sectional view illustrating a configuration of the boundary sub-area between the IGBT area and the diode area; Fig. Figure 11 is a cross-sectional view illustrating a configuration of a boundary sub-area between the IGBT area and a terminal or termination area; Fig. Figure 12 is a cross-sectional view illustrating a configuration of the boundary sub-area between the diode area and the termination area; Fig. Figure 13 is a diagram illustrating one step in the preparation of a semiconductor substrate; Fig. Figure 14 is a diagram illustrating a step in forming an n-type storage carrier layer, a p-type base layer, and a p-type anode layer; Fig. 15 is a diagram that shows a step towards forming a source layer from n + -type, a contact layer from p + -type and a contact layer from p + -Type illustrated; Fig. Figure 16 is a diagram illustrating one step in the construction of trenches; Fig. Figure 17 is a diagram illustrating one step in the formation of an oxide film; Fig. Figure 18 is a diagram illustrating a step in forming a gate trench electrode, a dummy trench electrode, a diode trench electrode, and a boundary trench electrode; Fig. Figure 19 is a diagram illustrating one step in forming an intermediate layer insulating film; Fig. Figure 20 is a diagram illustrating one step in forming a barrier metal and an emitter electrode; Fig. Figure 21 is a diagram illustrating one step in thinning the semiconductor substrate; Fig. Figure 22 is a diagram illustrating a step in forming an n-type buffer layer and a p-type collector layer; Fig. Figure 23 is a diagram showing a step towards the formation of a cathode layer from n + -Type illustrated; Fig. Figure 24 is a diagram illustrating one step in forming a collector electrode; Fig. Figure 25 is a top view illustrating a configuration of a boundary sub-region between an IGBT region and a diode region in the second preferred embodiment; Fig. Figure 26 is a top view illustrating a configuration of a boundary sub-region between an IGBT region and a diode region in a comparative example; Fig. Figure 27 is a cross-sectional view illustrating a configuration of a boundary sub-region between an IGBT region and a diode region in the third preferred embodiment. Description of preferred embodiments<Erste bevorzugte Ausführungsform>

[0014] A semiconductor device and a method for fabricating the semiconductor device according to the first preferred embodiment are described below. In the following description, n and p denote conductivity types of a semiconductor. - Indicates that the impurity concentration is lower than n. n + indicates that the impurity concentration is higher than n. Similarly, p indicates - indicates that the impurity concentration is lower than p. p+ Indicates that an impurity concentration is higher than p. The p-type and n-type of each layer described below can be interchanged. (Overall structure of a semiconductor device)

[0015] Fig. Figure 1 is a top view illustrating an example of a configuration of a semiconductor device 100 according to the first preferred embodiment. The semiconductor device 100 comprises a region 10 of an insulated-gate bipolar transistor (IGBT) and a diode region 20 in a semiconductor substrate. The diode region 20 is adjacent to the IGBT region 10. A plurality of IGBT cell structures (IGBT cells) are formed in the IGBT region 10, and a plurality of freewheeling diode cell structures (diode cells) are formed in the diode region 20. A cell structure is a structure corresponding to a smallest unit of an element. A region comprising the IGBT region 10 and the diode region 20 is referred to as a cell region. The semiconductor device 100 according to the first preferred embodiment is a reverse-conducting IGBT (RC-IGBT).The semiconductor device is made from, for example, a semiconductor such as Si or a so-called wide bandgap semiconductor such as SiC or GaN.

[0016] The IGBT region 10 and the diode region 20 have a striped planar shape. The IGBT region 10 and the diode region 20 extend in one direction within a plane of the semiconductor substrate. The IGBT region 10 and the diode region 20 are arranged alternately next to each other in a direction orthogonal to the direction in which the IGBT region 10 and the diode region 20 extend. Such a semiconductor device 100 is referred to as a "striped type".

[0017] Fig. Figure 2 is a top view illustrating an example of a configuration of a semiconductor device 101 according to the first preferred embodiment. Similar to the semiconductor device 100, the semiconductor device 101 is also an RC-IGBT with an IGBT region 10 and a diode region 20 in a semiconductor substrate.

[0018] The diode region 20 has an island-shaped planar form. In this example, a plurality of diode regions 20 are arranged side by side in a longitudinal and a lateral direction within a plane of the semiconductor substrate. The IGBT region 10 surrounds each of the plurality of diode regions 20. Such a semiconductor device 101 is referred to as an "island type".

[0019] Each of the semiconductor devices 100 and 101 has, in addition to the IGBT area 10 and the diode area 20, a pad area 40 and a terminal or termination area 30.

[0020] Pad area 40 is located outside the cell area, that is, outside the IGBT area 10 and the diode area 20. In this example, pad area 40 is located adjacent to the IGBT area 10. Pad area 40 is an area in which control pads 41 for controlling the semiconductor device are located. The control pads 41 include, for example, a current sensing pad 41a, a Kelvin emitter pad 41b, a gate pad 41c, pads 41d and 41e for a temperature sensing diode, and the like.

[0021] The current sensing pad 41a is a control pad used to detect a current flowing through the cell area. The current sensing pad 41a is electrically connected to one or some of the IGBT cells or diode cells in the cell area in such a way that a current flows which is many times, or even tens of thousands of times, smaller than the current flowing through the entire cell area.

[0022] The Kelvin emitter pad 41b and the gate pad 41c are control pads to which a voltage is applied for gate control, enabling on / off switching of the semiconductor device. The Kelvin emitter pad 41b has a p-type base layer and an n-type source layer. + The p-type IGBT cell is electrically connected (not illustrated). The Kelvin emitter pad 41b and the p-type base layer can be connected to the p-type IGBT via a contact layer (not illustrated). + -Type electrically connected. The gate pad 41c is electrically connected to an electrode (not illustrated) of a gate trench of the IGBT cell.

[0023] Pads 41d and 41e for a temperature sensing diode are control pads electrically connected to the anode and cathode of a (not illustrated) temperature sensing diode located in the cell region. Pads 41d and 41e measure a voltage between the anode and cathode of the temperature sensing diode to measure the temperature of the semiconductor device.

[0024] The termination region 30 is designed to surround a region combining the cell region and the pad region 40. The termination region 30 has a structure to withstand a stress of the semiconductor device. Any suitable structure is selected to serve as a stress-retaining structure. For example, the stress-retaining structure is a field-limiting ring (FLR), a variation of lateral doping (VLD), or the like, formed in a surface layer on one side of a first primary surface (one side of an upper surface) of the semiconductor device. The FLR has a p-type termination well layer (not illustrated) arranged to surround the cell region.The VLD features a (not illustrated) p-type well layer arranged to surround the cell area and exhibits a concentration gradient in one direction in the plane of the semiconductor device. The number of annular p-type end well layers 31 forming the FLR and the concentration distribution of the p-type well layers forming the VLD are selected appropriately depending on the design of the semiconductor device's withstand voltage. Furthermore, a p-type end well layer can be arranged over nearly the entire pad area 40. Alternatively, an IGBT cell or a diode cell can be arranged in the pad area 40.

[0025] In Fig. Figure 1 illustrates three IGBT regions 10 and two diode regions 20. However, the number of IGBT regions 10 and the number of diode regions 20 are not limited to those shown in Fig. Figure 1 illustrates this. The number of IGBT regions (10) can be four or more, or two or fewer. The number of diode regions (20) can be three or more, or one. Each in Fig. Figure 1 illustrates a diode region 20 sandwiched between two IGBT regions 10. However, the arrangement of the IGBT regions 10 and the diode regions 20 is not limited to this. The semiconductor device 100 can be configured such that the positions of the IGBT regions 10 and the diode regions 20 differ from those shown in Figure 1. Fig. As illustrated in Figure 1, the IGBT regions 10 and diode regions 20 are arranged in a sandwich-like manner. Alternatively, an equal number of IGBT regions 10 and diode regions 20 can be arranged such that the IGBT region 10 and the diode region 20 alternate.

[0026] In Fig. 2 represents a plurality of diode regions 20 arranged in a matrix in four columns in the left-right direction and two rows in the up-down direction. However, the number and arrangement of the diode regions 20 are not limited to this. The semiconductor device 101 can be configured such that at least one diode region 20 is distributed within the IGBT region 10. The diode region 20 can be arranged in any way as long as it is surrounded by the IGBT region 10. (Structure of an IGBT area)

[0027] Fig. Figure 3 is a partially enlarged top view illustrating a configuration of the IGBT area 10 of the semiconductor device according to the first preferred embodiment. Fig. Figure 3 is an enlarged view of area 82 in the Fig. 1 illustrated semiconductor device 100 or the one in Fig. 2 illustrated semiconductor device 101.

[0028] The semiconductor device 100 and the semiconductor device 101 each have a gate 11 of an active trench and a gate 12 of a dummy trench, which are arranged in the IGBT area 10.

[0029] In the semiconductor device 100, the gate 11 of an active trench and the gate 12 of a dummy trench extend in the longitudinal direction of the IGBT region 10. In other words, the gate 11 of an active trench and the gate 12 of a dummy trench in the semiconductor device 100 have longer sides in the direction in which the IGBT region 10 extends. The longitudinal direction of the IGBT region 10 corresponds to the left-right direction in Fig. 3.

[0030] In the semiconductor device 101, the gate 11 of an active trench and the gate 12 of a dummy trench extend in one direction in the IGBT region 10. For example, the gate 11 of an active trench and the gate 12 of a dummy trench extend in either the up-down direction or the left-right direction. Fig. 2.

[0031] The gate 11 of an active trench comprises an insulating film 11b of a gate trench and an electrode 11a of a gate trench. Although details of a cross-sectional structure of the gate 11 of an active trench are described later, the insulating film 11b of a gate trench is formed along an inner wall of a trench extending in the depth direction from the first main surface (the top surface) of the semiconductor substrate. The electrode 11a of a gate trench is formed within the trench with the insulating film 11b of a gate trench positioned between them. The electrode 11a of a gate trench is electrically connected to the (not illustrated) gate pad 41c.

[0032] The gate 12 of a dummy trench comprises an insulating film 12b of a dummy trench and an electrode 12a of a dummy trench. Although details of a cross-sectional structure of the gate 12 of a dummy trench are described later, the insulating film 12b of a dummy trench is formed along an inner wall of a trench extending in the depth direction from the first main surface of the semiconductor substrate. The electrode 12a of a dummy trench is formed within the trench with the insulating film 12b of a dummy trench positioned between them. The electrode 12a of a dummy trench is connected to an emitter electrode 6 (see Fig. 4) electrically connected, which is arranged above the first main surface of the semiconductor device 100 or the semiconductor device 101.

[0033] A source layer 13 of n + -type and a contact layer 14 from p +-Type are selectively arranged in a surface layer on the side of the first main surface of the semiconductor substrate on which the gate 11 of an active trench is located. In the first preferred embodiment, the source layer 13 is separated from the n + -type and the contact layer 14 from p + -Type arranged alternately along the direction (the longitudinal direction) in which the gate 11 of an active trench extends. The gate 11 of an active trench is arranged such that it separates the source layer 13 from the n + -type and the contact layer 14 from p + -Type crosses. On both sides of gate 11 of an active trench (in a direction orthogonal to the direction of travel of gate 11 of an active trench), the source layer 13 is from n + -Type in contact with the insulating film 11b of a gate trench. Details of the source layer 13 of n + -type and the contact layer 14 from p + -Types will be described later.

[0034] A contact layer 14 from p + The -type is arranged in a surface layer on the side of the first main surface of the semiconductor substrate on which the gate 12 of a dummy trench is located. The contact layer 14 of the p + -Type is arranged between two adjacent Gates 12 of dummy trenches.

[0035] In Fig. In the 3rd case, three Gates 12 of dummy trenches are arranged adjacent to three Gates 11 of active trenches. Furthermore, three more Gates 11 of active trenches are arranged adjacent to those three Gates 12 of dummy trenches. That is, a group of Gates 11 of active trenches consisting of three Gates 11 of active trenches and a group of Gates 12 of dummy trenches consisting of three Gates 12 of dummy trenches are arranged alternately. The number of Gates 11 of active trenches contained in a group of Gates 11 of active trenches is not limited to three and can be one or more. Furthermore, the number of Gates 12 of dummy trenches contained in a group of Gates 12 of dummy trenches is not limited to three and can be one or more. However, in Semiconductor Device 100 and Semiconductor Device 101, the Gate 12 of a dummy trench is not always necessary. This means that all trench gates arranged in IGBT area 10 can be gate 11 of an active trench.

[0036] Fig. Figure 4 is a cross-sectional view illustrating a configuration of the IGBT area 10 of the semiconductor device according to the first preferred embodiment. Fig. 4 illustrates one along a in Fig. 3 shown line AA, cross-section taken.

[0037] The semiconductor device 100 and the semiconductor device 101 contain a drift layer 1 in the IGBT area 10 of the n - -type, a carrier storage layer 2 of n-type, a base layer 15 of p-type, the source layer 13 of n + -Type, the contact layer 14 from p + -type, an n-type buffer layer 3, a p-type collector layer 16, an intermediate insulating film 4, a barrier metal 5, an emitter electrode 6, and a collector electrode 7. The IGBT cell corresponds, for example, to an area subdivided for each gate 11 of an active trench. Therefore, an IGBT cell has the drift layer 1 of n --type, the carrier storage layer 2 of n-type, the base layer 15 of p-type, the source layer 13 of n + -type, the buffer layer 3 of n-type, the collector layer 16 of p-type, the intermediate insulating film 4, the barrier metal 5, the emitter electrode 6 and the collector electrode 7.

[0038] The drift layer 1 from n - The -type is formed as an inner layer of the semiconductor substrate. The drift layer 1 of the n - The -type is located between the first major surface and a second major surface of the semiconductor substrate. The first major surface is the upper surface of the semiconductor substrate. The second major surface is a lower surface of the semiconductor substrate, opposite the first major surface. The first major surface in the IGBT region 10 corresponds to surfaces of the source layer 13 of n + -type and the contact layer 14 from p +-Type. That is, the first main surface in the IGBT region 10 corresponds to the upper surfaces of the source layer 13 of n. + -type and the contact layer 14 from p + -Type in Fig. 4. The second main surface in IGBT region 10 corresponds to a surface of the p-type collector layer 16. That is, the second main surface in IGBT region 10 corresponds to a lower surface of the p-type collector layer 16 in Fig. 4. In the Fig. In the illustrated cross-section 4, the semiconductor substrate corresponds to an area from the source layer 13 to n + -type and the contact layer 14 from p + -type up to collector layer 16 of the p-type. The drift layer 1 of the n -The drift layer type is derived from the structure of a substrate that is prepared before the semiconductor device structures are formed on the first major surface and the second major surface of the semiconductor substrate. For example, drift layer 1 corresponds to n - -Type of semiconductor layer formed by thinning the substrate. The drift layer 1 of n - The -type semiconductor layer contains n-type impurities, such as arsenic (As) or phosphorus (P). The concentration of n-type impurities is preferably 1.0 E + 12 / cm². 3 or more and 1.0E + 15 / cm 3 or less.

[0039] The n-type storage layer 2 is located on the side of the first main surface of the semiconductor substrate with respect to the drift layer 1 of the n -The n-type storage layer 2 is a semiconductor layer containing n-type defects such as arsenic or phosphorus. The n-type storage layer 2 has a higher concentration of n-type defects than the n-type drift layer 1. - -Type. The concentration of n-type defects is preferably 1.0E + 13 / cm². 3 or more and 1.0E + 17 / cm 3 or less. The n-type carrier storage layer 2 reduces current loss when current flows through the IGBT area 10. The n-type carrier storage layer 2 and the n-type drift layer 1 - The -type can be defined together as a drift layer of n-type. The second carrier storage layer of n-type is not always necessary. The first drift layer of n-type - -Type can be located at the position of the n-type carrier storage layer 2.

[0040] The p-type base layer 15 is located on the side of the first main surface of the semiconductor substrate with respect to the n-type storage layer 2. The p-type base layer 15 is a semiconductor layer containing, for example, boron (B) or aluminum (Al) as p-type impurities. The concentration of p-type impurities is preferably 1.0 E + 12 / cm². 3 or more and 1.0E + 19 / cm 3 or less. The p-type base layer 15 is in contact with the insulating film 11b of a gate trench of the gate 11 of an active trench. When a voltage is applied to the electrode 11a of a gate trench for gate control, a channel is formed in the p-type base layer 15.

[0041] Source layer 13 of n + The -type layer is located on the side of the first main surface of the semiconductor substrate with respect to the p-type base layer 15. The n-type source layer 13 +The -type is selectively arranged on a surface layer of the p-type base layer 15. The surface of the n-type source layer 13 + The -type forms the first main surface of the semiconductor substrate in the IGBT region 10. The source layer 13 of the n + The -type is a semiconductor layer containing n-type impurities, such as arsenic or phosphorus. The concentration of n-type impurities is preferably 1.0 E + 17 / cm². 3 or more and 1.0E + 20 / cm 3 or less. On source layer 13 of n + -Type can be used as an emitter layer from n + -type referenced.

[0042] The contact layer 14 from p + The -type is located on the side of the first main surface of the semiconductor substrate with respect to the p-type base layer 15. The contact layer 14 of the p + -Type is located in a region of the semiconductor layer of the base layer 15 of the p-type, in which the source layer 13 of the n +-Type not provided. The surface of contact layer 14 from p + The -type forms the first main surface of the semiconductor substrate in the IGBT region 10. The contact layer 14 from p + -type is a semiconductor layer containing p-type defects such as boron or aluminum. A concentration of p-type defects in the contact layer 14 of the p + The concentration of p-type defects is higher than the concentration of p-type defects in the base layer. The concentration of p-type defects is preferably 1.0 E + 15 / cm². 3 or more and 1.0E + 20 / cm 3 or less. The contact layer 14 from p + The -type and the base layer 15 of p-type can be defined together as a base layer of p-type.

[0043] The n-type buffer layer 3 is located on the side of the second main surface of the semiconductor substrate with respect to the drift layer 1 of the n --type arranged. The n-type buffer layer 3 is a semiconductor layer containing n-type defects, for example phosphorus or protons (H). + The buffer layer 3 of n-type has a higher concentration of n-type defects than the drift layer 1 of n-type. - -Type. The concentration of n-type defects is preferably 1.0E + 12 / cm². 3 or more and 1.0E + 18 / cm 3 or less. The n-type buffer layer 3 reduces the occurrence of punch-through because a depletion layer extends from the p-type base layer 15 to the side of the second main surface when the semiconductor device 100 is in an off state. The n-type buffer layer 3 and the n-type drift layer 1 - The -type can be defined together as a drift layer of n-type. Furthermore, the carrier storage layer 2 can be of n-type, the buffer layer 3 of n-type, and the drift layer 1 of n-type. -The -type buffers together are defined as a drift layer of type n. Buffer layer 3 of type n is not always necessary. A drift layer 1 of type n can be placed at the position of buffer layer 3 of type n. - -type be arranged.

[0044] The p-type collector layer 16 is arranged on the side of the second primary surface of the semiconductor substrate with respect to the n-type buffer layer 3. One surface of the p-type collector layer 16 forms the second primary surface of the semiconductor substrate. The p-type collector layer 16 is a semiconductor layer containing, for example, boron or aluminum as p-type impurities. The concentration of p-type impurities is preferably 1.0 E + 16 / cm². 3 or more and 1.0E + 20 / cm 3 or less.

[0045] The gate 11 of an active trench penetrates the source layer 13 from the first main surface of the semiconductor substrate. +-type, the base layer 15 of p-type and the carrier storage layer 2 of n-type and reaches the drift layer 1 of n - -Type. The insulating film 11b of a gate trench is formed along an inner wall of a trench extending in the depth direction from the first main surface of the semiconductor substrate. The electrode 11a of a gate trench is formed inside the trench with the insulating film 11b of a gate trench positioned between them. A bottom of the electrode 11a of a gate trench lies against the drift layer 1 of the n - -Type with the insulating film 11b of a gate trench arranged between them. The insulating film 11b of a gate trench is connected to the source layer 13 of the n +-type and the p-type base layer 15 in contact. When a voltage is applied to the electrode 11a of a gate trench for gate control, a channel is formed in the p-type base layer 15, which is in contact with the insulating film 11b of a gate trench.

[0046] The gate 12 of a dummy trench penetrates the contact layer 14 from the first main surface of the semiconductor substrate at p + -type, the base layer 15 of p-type and the carrier storage layer 2 of n-type and reaches the drift layer 1 of n - -Type. The insulating film 12b of a dummy trench is formed along an inner wall of a trench extending in the depth direction from the first main surface of the semiconductor substrate. The electrode 12a of a dummy trench is formed within the trench with the insulating film 12b of a dummy trench arranged between them. A bottom of the electrode 12a of a dummy trench lies against the drift layer 1 of the n- -Type with the insulating film 12b of a dummy trench arranged between them. The insulating film 12b of a dummy trench is connected to the source layer 13 of the n + -Type not in contact.

[0047] The interlayer insulating film 4 is arranged on the electrode 11a of a gate trench of gate 11 of an active trench.

[0048] The barrier metal 5 is formed on the interlayer insulating film 4 and on a region of the first main surface of the semiconductor substrate where the interlayer insulating film 4 is not located. The barrier metal 5 is formed, for example, from a titanium (Ti)-containing conductor. The titanium-containing conductor is, for example, titanium nitride, TiSi, or the like. TiSi is an alloy of titanium and silicon (Si). The barrier metal 5 is in ohmic contact with the source layer 13 of the n + -Type, of contact layer 14 from p +-type and electrode 12a of a dummy trench. The barrier metal 5 is connected to the source layer 13 of the n + -Type, of contact layer 14 from p + -Type and the electrode 12a of a dummy trench are electrically connected.

[0049] The emitter electrode 6 is arranged on the barrier metal 5. The emitter electrode 6 is made of, for example, an aluminum alloy (Al-Si-based alloy) containing aluminum and silicon. The emitter electrode 6 is connected to the source layer 13 via the barrier metal 5. + -Type, of contact layer 14 from p + -Type and the electrode 12 of a dummy trench are electrically connected.

[0050] The emitter electrode 6 can be formed from a variety of metal films, comprising an aluminum alloy film and another metal film. For example, the emitter electrode 6 can contain an aluminum alloy film and a plating film formed on the aluminum alloy film by electroless plating or electrolytic plating. The plating film is, for example, a nickel (Ni) plating film. In a thin layer, such as between adjacent interlayer insulating films 4, a tungsten film can be formed. The emitter electrode 6 is designed to cover the tungsten film. Since a tungsten film has better embedding properties than a plating film, a good emitter electrode 6 is formed.

[0051] Although an example in which the emitter electrode 6 is arranged on the first main surface of the semiconductor substrate with the barrier metal 5 arranged between it, in Fig. As illustrated in Figure 4, the barrier metal 5 is not always necessary. If the barrier metal 5 is not provided, the emitter electrode 6 on the source layer 13 is isolated from the n + -Type, of contact layer 14 from p + -type and the electrode 12a of a dummy trench and establishes an ohmic contact with them. Alternatively, the barrier metal 5 can only be placed on an n-type semiconductor layer such as the source layer 13 of the n +-type. The barrier metal 5 and the emitter electrode 6 can be defined together as one emitter electrode. Furthermore, the interlayer insulating film 4 can be arranged on a portion of the electrode 12a of a dummy trench. In this case, it is only necessary that the emitter electrode 6 is electrically connected to the electrode 12a of a dummy trench in some region on the electrode 12a of a dummy trench.

[0052] The collector electrode 7 is arranged on the p-type collector layer 16. Similar to the emitter electrode 6, the collector electrode 7 can be made of an aluminum alloy or of an aluminum alloy and a plating film. Alternatively, the collector electrode 7 can have a different configuration than the emitter electrode 6. The collector electrode 7 is in ohmic contact with the p-type collector layer 16 and is electrically connected to it.

[0053] Fig. Figure 5 is a cross-sectional view illustrating a configuration of the IGBT area 10 of the semiconductor device according to the first preferred embodiment. Fig. 5 illustrates one along a in Fig. 3 illustrated line BB is the cross-section taken.

[0054] The one taken along line BB, in Fig. The illustrated cross-section 5 differs from the one taken along line AA, in Fig. 4 illustrated cross-section by the fact that the source layer 13 from n + -Type is not arranged as a surface layer on the side of the first main surface of the semiconductor substrate. That is, as in Fig. As illustrated in 3, the source layer 13 is from n. + -Type selectively arranged on the surface layer of the base layer 15 of the p-type. (Structure of a diode region)

[0055] Fig. Figure 6 is a partially enlarged top view illustrating a configuration of the diode area 20 of the semiconductor device according to the first preferred embodiment. Fig. Figure 6 is an enlarged view of area 83 in the Fig. 1 illustrated semiconductor device 100 or the one in Fig. 2 illustrated semiconductor device 101.

[0056] The semiconductor device 100 and the semiconductor device 101 each contain a gate 21 of a diode trench arranged in the diode area 20.

[0057] The gate 21 of a diode trench extends in one direction in the diode region 20. In the first preferred embodiment, the gate 21 of a diode trench extends in the same direction as the gate 11 of an active trench and the gate 12 of a dummy trench.

[0058] The gate 21 of a diode trench comprises an insulating film 21b and an electrode 21a. Although details of a cross-sectional structure of the gate 21 of the diode trench will be described later, the insulating film 21b is formed along an inner wall of a trench extending in the depth direction from the first main surface of the semiconductor substrate. The electrode 21a is located within the trench, with the insulating film 21b positioned between it and the diode trench.

[0059] A contact layer 24 from p + A p-type anode layer and a p-type anode layer 25 are selectively arranged on a surface layer on the side of the first main surface of the semiconductor substrate, on which the gate 21 of a diode trench is arranged. In the first preferred embodiment, the contact layer 24 is of the p-type +The p-type and p-type anode layer 25 are arranged alternately along the direction (the longitudinal direction) in which the gate 21 of a diode trench extends. The gate 21 of a diode trench is arranged such that it separates the p-type contact layer 24 from the p-type anode layer 25. + -type and the anode layer 25 of the p-type crosses. The contact layer 24 of the p + The p-type anode layer 25 is arranged between two adjacent gates 21 of a diode trench. Details of the p-type contact layer 24 + The -type and the p-type anode layer 25 will be described later.

[0060] Fig. Figure 7 is a cross-sectional view illustrating a configuration of the diode area 20 of the semiconductor device according to the first preferred embodiment. Fig. 7 illustrates one along a in Fig. 6 illustrated line CC taken cross-section.

[0061] The semiconductor device 100 and the semiconductor device 101 each have a drift layer 1 in the diode region 20 from n - -type, a carrier storage layer 2 of n-type, the anode layer 25 of p-type, the contact layer 24 of p-type + -type, a buffer layer 3 of n-type, a cathode layer 26 of n + -type, a barrier metal 5, an emitter electrode 6 and a collector electrode 7. The diode cell corresponds, for example, to an area subdivided for each gate 21 of a diode trench. Therefore, a diode cell contains the drift layer 1 of the n - -type, the carrier storage layer 2 of n-type, the anode layer 25 of p-type, the contact layer 24 of p-type + -type, the buffer layer 3 of n-type, the cathode layer 26 of n + -type, the barrier metal 5, the emitter electrode 6 and the collector electrode 7.

[0062] The drift layer 1 from n -The -type is formed as an inner layer of the semiconductor substrate. The drift layer 1 of the n - -Type in the diode region 20 is similar to drift layer 1 of n - -Type in the IGBT region 10 is arranged between the first main surface and the second main surface of the semiconductor substrate. The first main surface in the diode region 20 corresponds to a surface of the contact layer 24 from p + -Type. That is, the first main surface in the diode region 20 corresponds to an upper surface of the contact layer 24 from p + -Type in Fig. 7. The first main surface in the diode region 20 extends continuously from the first main surface in the IGBT region 10. The second main surface in the diode region 20 corresponds to a surface of the cathode layer 26 of n + -Type. That is, the second main surface in the diode region 20 corresponds to a lower surface of the cathode layer 26 of n + -Type in Fig. 7. The second main surface in the diode region 20 is continuous from the second main surface in the IGBT region 10. In the Fig. In the illustrated cross-section 7, the semiconductor substrate corresponds to an area from the contact layer 24 to the p. + -Type up to the cathode layer 26 from n + -Type. The drift layer 1 from n - -Type in the diode region 20 is similar to drift layer 1 of n - -Type in the IGBT region 10 derived from a structure of a substrate that is prepared before the structures are formed on the side of the first main surface and the side of the second main surface of the semiconductor substrate. That is, the drift layers 1 from n - The -type in the diode region 20 and the IGBT region 10 are formed continuously and integrally together. In other words, the drift layers 1 of n --Type in the diode area 20 and the IGBT area 10 on the same semiconductor substrate.

[0063] The n-type storage layer 2 is located, as in the IGBT area 10, on the side of the first main surface of the semiconductor substrate with respect to the drift layer 1 of the n - -type arranged. The n-type carrier storage layer 2 arranged in diode region 20 has the same configuration as the n-type carrier storage layer 2 arranged in IGBT region 10. The n-type carrier storage layer 2 and the n-type drift layer 1 - The -type components can be defined together as a drift layer of n-type. The n-type carrier storage layer 2 in the diode region 20 is not always necessary. The n-type drift layer 1 -The -type can be provided at the position of the n-type carrier storage layer 2. Even in a case where the n-type carrier storage layer 2 is located in the IGBT area 10, it is not necessary, for example, to provide the n-type carrier storage layer 2 in the diode area 20.

[0064] The p-type anode layer 25 is arranged on the side of the first main surface of the semiconductor substrate with respect to the n-type storage layer 2. The p-type anode layer 25 is a semiconductor layer containing, for example, boron or aluminum as p-type impurities. The concentration of p-type impurities is preferably 1.0 E + 12 / cm². 3 or more and 1.0E + 19 / cm 3or less. For example, the concentration of p-type impurities in the p-type anode layer 25 is the same as the concentration of p-type impurities in the p-type base layer 15 in IGBT region 10. If the p-type impurity concentrations are the same, the p-type anode layer 25 will form at the same time as the p-type base layer 15. Alternatively, the concentration of p-type impurities in the p-type anode layer 25 may be lower than the concentration of p-type impurities in the p-type base layer 15 in IGBT region 10. If the concentration of p-type impurities in the p-type anode layer 25 is lower, the number of holes injected into diode region 20 during diode operation decreases. Accordingly, recovery loss during diode operation is reduced.

[0065] The contact layer 24 from p +The -type is arranged on the side of the first main surface of the semiconductor substrate with respect to the p-type anode layer 25. The contact layer 24 of the p + The -type is arranged on a surface layer of the p-type anode layer 25. A surface of the p-type contact layer 24 + The -type forms the first main surface of the semiconductor substrate in the diode region 20. The contact layer 24 from p + -type is a semiconductor layer containing p-type defects such as boron or aluminum. A concentration of p-type defects in the contact layer 24 of the p + The concentration of p-type defects is higher than the concentration of p-type defects in the p-type anode layer 25. The concentration of p-type defects is preferably 1.0 E + 15 / cm². 3 or more and 1.0E + 20 / cm 3 or less. The contact layer 24 from p +The p-type anode layer 25 and the p-type anode layer can together be defined as a p-type anode layer. The concentration of p-type impurities in the p-type contact layer 24 + -Type can be the same as the concentration of defects of the p-type of contact layer 14 from the p + -Type in the IGBT range 10 or different from this.

[0066] The n-type buffer layer 3 is located on the side of the second main surface of the semiconductor substrate with respect to the drift layer 1 of the n - -type arranged. The n-type buffer layer 3 arranged in diode region 20 has the same configuration as the n-type buffer layer 3 arranged in IGBT region 10. The n-type buffer layer 3 and the n-type drift layer 1 - The -type can be defined together as a drift layer of n-type. Furthermore, the carrier storage layer 2 can be of n-type, the buffer layer 3 of n-type, and the drift layer 1 of n-type. -The -type buffers together are defined as a drift layer of type n. Buffer layer 3 of type n is not always necessary. A drift layer 1 of type n can be placed at the position of buffer layer 3 of type n. - -type will be arranged.

[0067] The cathode layer 26 from n + The -type is located on the side of the second main surface of the semiconductor substrate with respect to the n-type buffer layer 3. One surface of the cathode layer 26 of the n + The -type forms the second main surface of the semiconductor substrate. The cathode layer 26 of the n + The -type semiconductor layer contains n-type impurities, such as arsenic or phosphorus. The concentration of n-type impurities is preferably 1.0 E + 16 / cm². 3 or more and 1.0E + 21 / cm 3 or less.

[0068] The cathode layer 26 from n +The -type can be arranged in the entire diode region 20 or can be arranged in a part of the diode region 20. The semiconductor device 100 and the semiconductor device 101 can each have a semiconductor layer in which the cathode layer 26 is separated from the n + -type and a cathode layer of p + -type as a semiconductor layer forming the second main surface of the semiconductor substrate in the diode region 20, are arranged alternately, although their illustration is omitted. Such a structure is formed, for example, by a step of selectively injecting p-type impurities into a portion of a region where the cathode layer 26 is separated from the n + -type. A diode containing a semiconductor layer in which the cathode layer 26 is formed by n + -type and a cathode layer p +-Type alternating, is called a diode with relaxed field of cathode (RFC) (engl. Relaxed Field of Cathode).

[0069] The gate 21 of a diode trench penetrates the contact layer 24 from the first main surface of the semiconductor substrate at p + -type, the anode layer 25 of the p-type and the storage layer 2 of the n-type, and reaches the drift layer 1 of the n - -Type. The insulating film 21b of a diode trench is formed along an inner wall of a trench extending in the depth direction from the first main surface of the semiconductor substrate. The electrode 21a of a diode trench is formed within the trench with the insulating film 21b of a diode trench positioned between them. A bottom of the electrode 21a of a diode trench lies at the drift layer 1 of the n - -Type with the insulating film 21b arranged between it and a diode trench opposite.

[0070] On the electrode 21a of a diode trench and on the contact layer 24 of the p + The barrier metal 5 is arranged in the -type. The barrier metal 5 can have the same configuration as the barrier metal 5 in the IGBT area 10. For example, the barrier metal 5 is formed from a titanium-containing conductor. The barrier metal 5 is in ohmic contact with the electrode 21a of a diode trench and the contact layer 24 of the p + -Type. The barrier metal 5 is connected to the electrode 21a of a diode trench and the contact layer 24 of the p + -Type electrically connected.

[0071] The emitter electrode 6 is arranged on the barrier metal 5. The emitter electrode 6 located in the diode region 20 is continuous with the emitter electrode 6 located in the IGBT region 10. The emitter electrode 6 is connected via the barrier metal 5 to the electrode 21a of a diode trench and the contact layer 24 from p +-Type electrically connected.

[0072] As in the configuration in the IGBT area 10, the barrier metal 5 is not always necessary. If the barrier metal 5 is not provided, the emitter electrode 6 is on the electrode 21a of a diode trench and on the contact layer 24 of the p + -type arranged and establishes an ohmic contact with them. Although an example in which the interlayer insulating film 4 is not arranged on the electrode 21a of a diode trench, in Fig. As illustrated in Figure 7, the intermediate insulating film 4 can be provided on a portion of the electrode 21a of a diode trench. In this case, it is only necessary that the emitter electrode 6 is electrically connected to the electrode 21a of the diode trench in some region.

[0073] The collector electrode 7 is on the cathode layer 26 from n +-type arranged. The collector electrode 7 in the diode region 20 is fully connected to the collector electrode 7 arranged in the IGBT region 10. The collector electrode 7 is in ohmic contact with the cathode layer 26 of the n + -type and is connected to the cathode layer 26 of n + -Type electrically connected.

[0074] Fig. Figure 8 is a cross-sectional view illustrating a configuration of the diode area 20 of the semiconductor device according to the first preferred embodiment. Fig. Figure 8 illustrates one along a path in Fig. 6 illustrated line DD taken cross-section.

[0075] The in Fig. The cross-section shown in Figure 8, taken along a line DD, differs from the one in Fig. Figure 7 illustrated the cross-section taken along a line CC by showing that the contact layer 24 is separated from the p +-Type is not arranged on the side of the first main surface of the semiconductor substrate. That is, in Fig. 6 is the contact layer 24 of the p + -Type selectively arranged on a surface layer of the p-type anode layer 25. In a portion of the diode region 20 where the contact layer 24 is of the p-type + If the -type is not arranged, a surface of the anode layer 25 of the p-type corresponds to the first main surface of the semiconductor substrate. (Structure of a boundary subregion between an IGBT region and a diode region)

[0076] Fig. Figure 9 is a top view illustrating a configuration of a boundary sub-area between the IGBT area 10 and the diode area 20. Fig. Figure 10 is a cross-sectional view illustrating the configuration of the boundary section between the IGBT area 10 and the diode area 20. Fig. 10 illustrates one along a in Fig. 1, Fig. 2 and Fig. The cross-section illustrated by line EE in section 9 is shown. However, in Fig. 9 an illustration of a gate 11 of an active trench and an adjacent gate 12 of a dummy trench, which are on the far left of the page Fig. Figures 10 are omitted. Similarly, in Fig. 9 an illustration of one on the far right of the page Fig. Gates 10 illustrated a diode trench, but omitted the 21.

[0077] The semiconductor device 100 and the semiconductor device 100 each have a gate 51 of a boundary trench and a carrier control area 50.

[0078] Gate 51 of a boundary trench is located in the boundary section between IGBT area 10 and diode area 20. Gate 51 of a boundary trench is adjacent to a gate of an active trench that is closest to diode area 20 among the gates 11 of active trenches located in IGBT area 10. Furthermore, Gate 51 of a boundary trench is located on the side of diode area 20 with respect to the gate of an active trench closest to diode area 20.

[0079] In an area between Gate 51 of a border trench and Gate 11 of an active trench that is closest to Gate 51 of a border trench, the source layer 13 is from n + -Type selectively arranged on a surface layer of the p-type base layer 15. The contact layer 14 of the p + -Type is not located in this area. Surfaces of source layer 13 from n +The -type and the p-type base layer 15 form the first main surface of the semiconductor substrate. The n-type source layer 13 + -type and the base layer 15 of the p-type are arranged alternately along a direction (the longitudinal direction) in which the gate 11 of an active trench and the gate 51 of a boundary trench extend.

[0080] The carrier control area 50 is closer to gate 51 of a border trench than the source layer 13 is to n + The carrier control region 50 is arranged between gate 51 of a boundary trench and gate 11 of an active trench, which is the nearest gate 51 of a boundary trench. The carrier control region 50 is arranged as a surface layer on the side of the first main surface of the semiconductor substrate. The concentration of n-type defects in the carrier control region 50 is lower than the concentration of n-type defects in the source layer 13. +-Type containing defects of the n-type.

[0081] The carrier control area 50 in the first preferred embodiment is that between the source layer 13 and the n + -type and the base layer 15 of p-type located at Gate 51 of a border trench. As in Fig. As illustrated in Figure 10, the base layer 15 of p-type surrounds an end of the source layer 13 of n-type. + -Type of below source layer 13 of n + -type and is exposed on the first main surface of the semiconductor substrate. That is, the p-type base layer 15 forms a surface layer of the semiconductor substrate between the n-type source layer 13. +-type and the gate 51 of a boundary trench. The p-type base layer 15, as the carrier control region 50, is in contact with the gate 51 of the boundary trench. Although details of the process for fabricating the semiconductor device 100 and the semiconductor device 101 will be described later, the source layer 13 is connected to the n + -type is formed by injecting n-type defects into the surface layer of the p-type base layer 15. Accordingly, a concentration of defects in the p-type base layer 15 between the n-type source layer 13 is + -type and Gate 51 of a border trench are contained, lower than the concentration of in source layer 13 from n + -Type containing defects of the n-type.

[0082] Source layer 13 of n +The IGBT type between Gate 51 of a boundary trench and Gate 11 of an active trench is in contact with Gate 11 of an active trench, but is not in contact with Gate 51 of a boundary trench. Gate 51 of a boundary trench does not form an IGBT cell and is different from Gate 11 of an active trench.

[0083] The gate 51 of a boundary trench penetrates from the first main surface of the semiconductor substrate the base layer 15 of the p-type and the storage layer 2 of the n-type and reaches the drift layer 1 of the n-type. --Type. The gate 51 of a boundary trench has an insulating film 51b of a boundary trench and an electrode 51a of a boundary trench. The insulating film 51b of a boundary trench is formed along an inner wall of a trench that extends in the depth direction from the first main surface of the semiconductor substrate. The electrode 51a of a boundary trench is formed within the trench with the insulating film 51b of a boundary trench positioned between them. The bottom of the electrode 51a of a boundary trench lies from the drift layer 1 of the n - -Type with the insulating film 51b arranged between them opposite a boundary ditch.

[0084] The barrier metal 5 extends from the IGBT area 10 and the diode area 20 and is also located on the electrode 51a of a boundary trench. The barrier metal 5 is in ohmic contact with the electrode 51a of the boundary trench. The barrier metal 5 is electrically connected to the electrode 51a of the boundary trench. The emitter electrode 6 is electrically connected to the electrode 51a of the boundary trench via the barrier metal 5.

[0085] The p-type collector layer 16, located on the side of the second main surface of the IGBT region 10, is arranged such that it projects into the diode region 20 by a distance U1 from the boundary between the IGBT region 10 and the diode region 20. A distance between the cathode layer 26 and the n +The current flow between the p-type collector layer 16 and the gate 11 of an active trench is greater than in a structure where the p-type collector layer 16 does not extend into the diode region 20. Such a structure reduces the current flowing from a channel adjacent to the gate 11 of an active trench to the cathode layer 26. + -Type current flows even when a gate-driven voltage is applied to electrode 11a of a gate trench during operation of the freewheeling diode. The distance U1 is, for example, 100 µm. However, depending on the application of semiconductor device 100 or semiconductor device 101, the distance U1 can be 0 µm or less than 100 µm. The gate 51 of a boundary trench is not, for example, defined by the arrangement of the p-type collector layer 16 located on the side of the second main surface of the semiconductor substrate. (Structure of a closing section)

[0086] Fig. Figure 11 is a cross-sectional view illustrating a configuration of a boundary sub-area between the IGBT area 10 and the termination area 30. Fig. 11 illustrates one along a in Fig. 1 or Fig. 2 illustrated line FF cross-section taken. Fig. Figure 12 is a cross-sectional view illustrating a configuration of the boundary sub-area between the diode area 20 and the termination area 30. Fig. 12 illustrates one along a in Fig. 1 illustrated line GG cross-section taken.

[0087] The semiconductor device 100 and the semiconductor device 101 each contain a drift layer 1 of n in the termination region 30. - -type, a finishing trough layer 31 of p-type, a channel stop layer 32 of n +-type, a buffer layer 3 of n-type, a terminal collector layer 16a of p-type, an intermediate insulating film 4, a barrier metal 5, an emitter electrode 6, a terminal or termination electrode 6a, a semi-insulating film 33, a termination protective film 34 and a collector electrode 7.

[0088] The drift layer 1 from n - -Type in the termination area 30 is similar to the drift layers 1 from n - -Type in the IGBT region 10 and the diode region 20 between the first main surface and the second main surface of the semiconductor substrate. However, part of the drift layer 1 is located away from the n - -Type in termination region 30 on the first main surface as a surface layer of the semiconductor substrate. The first main surface in termination region 30 corresponds to surfaces of drift layer 1 of n - -type, the final trough layer 31 of the p-type and the channel stop layer 32 of the n +-Type. That is, the first main surface in the termination area 30 corresponds to the upper surfaces of the drift layer 1 of n - -type, the final trough layer 31 of the p-type and the channel stop layer 32 of the n + -Type in Fig. 11. The first main surface in the termination region 30 extends continuously from the first main surface in the IGBT region 10 or the diode region 20. The second main surface in the termination region 30 corresponds to a surface of the p-type termination collector layer 16a. That is, the second main surface in the termination region 30 corresponds to a lower surface of the p-type termination collector layer 16a. Fig. 11. The second main surface in the termination region 30 is continuous from the second main surface in the IGBT region 10 or the diode region 20. The drift layer 1 from n - -Type in the termination area 30 is similar to drift layer 1 from n --Type in the IGBT region 10 and the diode region 20 derived from a substrate structure that is prepared before the structures are formed on the side of the first main surface or the side of the second main surface of the semiconductor substrate. That is, the drift layers 1 from n - The -type in the termination area 30, the IGBT area 10, and the diode area 20 are continuous and integrally formed. In other words, the drift layers 1 of n - -Type formed in the termination area 30, the IGBT area 10 and the diode area 20 on the same substrate.

[0089] The p-type termination well layer 31 is located on the side of the first main surface of the semiconductor substrate with respect to the drift layer 1 of the n -The p-type termination layer 31 is arranged such that it surrounds a cell region in plan view. In the first preferred embodiment, three p-type termination layers 31 form a triple ring in plan view and surround the cell region. The three p-type termination layers 31 form a field-loaded refractory layer (FLR). The number of p-type termination layers 31 is not limited to three. The number of p-type termination layers 31 is selected appropriately depending on the design of the withstand voltage of the semiconductor device 100 or the semiconductor device 101. The p-type termination layer 31 is a semiconductor layer that contains, for example, boron or aluminum as p-type impurities. The concentration of p-type impurities is 1.0 E + 14 / cm². 3 or more and 1.0E + 19 / cm 3 or less.

[0090] The channel stop layer 32 from n +-Type is on the side of the first main surface of the semiconductor substrate with respect to drift layer 1 of n - -type arranged. The channel stop layer 32 of n + The -type is arranged in plan view on an outside of the p-type end trough layer 31. The channel stop layer 32 of the n + The -type is arranged in such a way that it surrounds the p-type final trough layer 31.

[0091] The n-type buffer layer 3 is located on the side of the second main surface of the semiconductor substrate with respect to the drift layer 1 of the n --type. The n-type buffer layer 3 arranged in the termination region 30 has a configuration similar to the n-type buffer layer 3 arranged in the IGBT region 10 or the diode region 20. The n-type buffer layer 3 arranged in the termination region 30 is continuous and integral with the n-type buffer layer 3 arranged in the IGBT region 10 or the diode region 20. The n-type buffer layer 3 and the n-type drift layer 1 - The -type can be defined together as a drift layer of type n. The buffer layer 3 of type n is not always necessary. A drift layer 1 of type n - -Type can be placed at the position of buffer layer 3 of n-type.

[0092] The p-type termination collector layer 16a is located on the side of the second main surface of the semiconductor substrate with respect to the n-type buffer layer 3. The p-type termination collector layer 16a has a configuration similar to that of the p-type collector layer 16 located in IGBT region 10. The p-type termination collector layer 16a is continuous and integral with the p-type collector layer 16 located in IGBT region 10. The p-type termination collector layer 16a in termination region 30 and the p-type collector layer 16 in IGBT region 10 can together be defined as a single p-type collector layer.

[0093] As in Fig. As illustrated in Figure 12, the p-type termination collector layer 16a is arranged such that it projects into the diode region 20 by a distance U2 from the boundary between the diode region 20 and the termination region 30. A distance between the cathode layer 26 and the termination region 30 is also present. +The area of ​​the p-type termination layer 31 is larger than in a structure where the p-type termination collector layer 16a does not protrude into the diode region 20. Such a structure prevents the p-type termination layer 31 from acting as the anode of the freewheeling diode. The distance U2 is, for example, 100 µm.

[0094] The interlayer insulating film 4 is arranged on the first main surface of the semiconductor substrate. The interlayer insulating film 4 has contact holes. The contact holes are of the p-type type corresponding to the positions of the termination well layer 31 and the channel stop layer 32. + -type arranged. Surfaces of the finishing trough layer 31 of p-type and the channel stop layer 32 of n-type. + -Type are exposed by the contact holes.

[0095] The barrier metal 5 is of the p-type on the final trough layer 31 and of the n-type on the channel stop layer 32. + -Type arranged.

[0096] The emitter electrode 6 is arranged such that it is electrically connected via the barrier metal 5 to the p-type termination well layer 31 near the IGBT region 10 or the diode region 20. The emitter electrode 6 in the termination region 30 is continuous and integral with the emitter electrode 6 in the IGBT region 10 or the diode region 20.

[0097] The termination electrode 6a is separated from the emitter electrode 6 and is located on an outer surface of the emitter electrode 6. The termination electrode 6a is connected via the barrier metal 5 in the contact hole to the p-type termination trough layer 31 and the n-type channel stop layer 32. + -Type electrically connected.

[0098] The semi-insulating film 33 is arranged to electrically connect the emitter electrode 6 and the termination electrode 6a. The semi-insulating film 33 is, for example, a semi-insulating silicon nitride (SiN₂).

[0099] The protective end film 34 covers the emitter electrode 6, the termination electrode 61 and the semi-insulating film 33. The protective end film 34 is made of polyimide, for example.

[0100] The collector electrode 7 is arranged on the p-type termination collector layer 16a, that is, on the second main surface of the semiconductor substrate. The collector electrode 7 in the termination region 30 is fully and integrally connected to the collector electrodes 7 in the IGBT region 10 and the diode region 20. (Method for manufacturing a semiconductor device)

[0101] Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. 20, Fig. 21, Fig. 22, Fig. 23 to Fig. Figure 24 are diagrams illustrating a method for manufacturing a semiconductor device according to the first preferred embodiment. Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19 to Fig. Figure 20 illustrates the steps for forming structures on the side of the first main surface of the semiconductor device. Fig. 21, Fig. 22, Fig. 23 to Fig. Figure 24 illustrates steps for forming structures on the side of the second main surface of the semiconductor device. Each drawing illustrates a cross-section of the interface region between the IGBT region 10 and the diode region 20, that is, one along a Fig. 1 or Fig. 2 illustrated line EE cross-section taken.

[0102] Fig. Figure 13 is a diagram illustrating a step in the preparation of a semiconductor substrate. In the first preferred embodiment, an n-type wafer containing defects is prepared as the semiconductor substrate. In this step, the entire semiconductor substrate corresponds to drift layer 1 of the n - -type. A concentration of n-type defects is selected appropriately according to the specifications of the withstand voltage of semiconductor device 100 or semiconductor device 101. For example, if the specification of the withstand voltage of the semiconductor device is 1200 V, the concentration of n-type defects is adjusted so that a specific resistance of drift layer 1 is n - -Type lies in a range of approximately 40 Ω·cm to 120 Ω·cm. Although Fig. Figure 13 illustrates a step in preparing an n-type wafer as a semiconductor substrate, which is entirely directed to drift layer 1 from the n -The step for preparing the semiconductor substrate is not limited to this type. For example, the drift layer 1 can be separated from the n - A semiconductor substrate containing n-type defects is prepared by a step in which ion implantation of n-type defects is performed from the first or second primary surface of the semiconductor substrate, and a step in which the n-type defects are diffused by thermal treatment. The semiconductor substrate can be a so-called FZ wafer produced by a floating zone (FZ) process, or an MCZ wafer produced by a Czochralski process with an applied magnetic field (MCZ). Alternatively, the semiconductor substrate can be a wafer produced by a sublimation process or chemical vapor deposition (CVD).

[0103] In the semiconductor substrate, the IGBT area 10, in which IGBT cells are to be arranged, and the diode area 20, in which diode cells are to be arranged, are determined beforehand according to the configuration of the semiconductor device 100 or the semiconductor device 101. The (in Fig. The termination area 30 (not illustrated) in which the structure capable of withstanding a voltage is to be formed is defined beforehand around the IGBT area 10 and the diode area 20. The following primarily describes a method for fabricating the structures in the IGBT area 10 and the diode area 20.

[0104] Fig. Figure 14 is a diagram illustrating a step in the formation of the n-type storage layer 2, the p-type base layer 15, and the p-type anode layer 25. From the first main surface of the semiconductor substrate, n-type impurity ion implantation occurs to form the n-type storage layer 2 into a surface layer of the n-type drift layer 1. -The n-type impurities are, for example, phosphorus. Ion implantation of p-type impurities to form the p-type base layer 15 and the p-type anode layer 25 is performed into the first main surface of the semiconductor substrate. The p-type impurities are, for example, boron. After ion implantation, a heat treatment is performed. This heat treatment causes the n-type and p-type impurities to diffuse, forming the n-type storage layer 2, the p-type base layer 15, and the p-type anode layer 25.

[0105] At the time of ion implantation, a mask with an opening in a predetermined region is formed on the first primary surface of the semiconductor substrate. The n-type and p-type defects are injected into this region according to the opening of the mask. The mask is formed in two steps: first, by depositing a resist onto the first primary surface of the semiconductor substrate, and second, by creating an opening in a predetermined region of the resist using photolithography. This masking process is referred to as the masking process. The n-type and p-type defects are injected into the predetermined region through this masking process.As a result, the n-type storage layer 2, the p-type base layer 15 and the p-type anode layer 25 are selectively formed within a plane of the first main surface of the semiconductor substrate.

[0106] If the p-type base layer 15 and the p-type anode layer 25 have the same configuration, that is, if the p-type base layer 15 and the p-type anode layer 25 have the same depth and concentration of p-type defects, ion implantation of the p-type defects is performed simultaneously. If, on the other hand, the p-type base layer 15 and the p-type anode layer 25 have different configurations, that is, if the p-type base layer 15 and the p-type anode layer 25 have different depths or different concentrations of p-type defects, ion implantation of the p-type defects for the p-type base layer 15 and the p-type defects for the p-type anode layer 25 is performed separately using the masking process.For example, ion implantation of p-type defects for the p-type base layer 15 is carried out through an opening provided in the IGBT region 10. Ion implantation of p-type defects for the p-type anode layer 25 is carried out through an opening provided in the diode region 20.

[0107] A step to form an FLR, which has a p-type termination well layer 31 as the withstand-stress structure in the (not illustrated) termination region 30, can be performed before processing the IGBT region 10 and the diode region 20, or it can be performed simultaneously with the ion implantation of p-type defects into the IGBT region 10 or the diode region 20. For example, if the p-type termination well layer 31 in the termination region 30 has the same configuration as the p-type anode layer 25, ion implantation of the p-type defects into the p-type termination well layer 31 is performed at the same time as ion implantation of the p-type defects into the p-type anode layer 25. As a result, the p-type terminal trough layer 31 and the p-type anode layer 25 are formed with the same depth and concentration of p-type defects.If the p-type terminal layer 31 and the p-type anode layer 25 have different depths or concentrations of p-type defects, ion implantation of the p-type defects for the p-type terminal layer 31 and the p-type defects for the p-type anode layer 25 is performed separately using the masking process. Even if the p-type terminal layer 31 and the p-type anode layer 25 have different configurations, ion implantation of the p-type defects for the p-type terminal layer 31 can be performed simultaneously with ion implantation of the p-type defects for the p-type anode layer 25. However, a lattice shape is formed in an opening of the mask in the area where the p-type final trough layer 31 is to be formed and / or the area where the p-type anode layer 25 is to be formed.Since the lattice shape reduces the aperture ratio, the number of p-type impurities injected into the semiconductor substrate is controlled. Although a formation relationship between the p-type termination layer 31 and the p-type anode layer 25 has been described, the same applies to a formation relationship between the p-type termination layer 31 and the p-type base layer 15. Furthermore, ion implantation of the p-type impurities can be performed simultaneously to form the p-type termination layer 31, the p-type base layer 15, and the p-type anode layer 25. The n-type storage layer 2 and the p-type base layer 15 are formed in the IGBT region 10 and are connected to the p-type termination layer 31 in the termination region 30.The n-type carrier storage layer 2 and the p-type anode layer 25 are formed in the diode region 20 and are connected to the p-type termination basin layer 31 in the termination region 30.

[0108] Fig. 15 is a diagram that shows a step towards forming the source layer 13 from n + -Type, of contact layer 14 from p + -type and the contact layer 24 from p + -type illustrated. The ion implantation of the defects of the n-type to form the source layer 13 of the n + The injection of n-type defects into a surface layer of the p-type base layer 15 is carried out from the side of the first main surface of the semiconductor substrate. The n-type defects are, for example, arsenic or phosphorus. In this step, a mask is positioned such that the n-type defects are injected only into a predetermined area within the IGBT region 10. This masking process removes the n-type defects from the source layer 13. +-type defects are selectively formed in a surface layer of the p-type base layer 15 in the IGBT region 10. In particular, in the first preferred embodiment, a mask is arranged such that the n-type defects are not injected into a portion of the IGBT region 10 adjacent to the diode region 20. As a result, the p-type base layer 15 remains as the carrier control layer 50 at the end of the IGBT region 10.

[0109] Similarly, ion implantation of the p-type defects is used to form the contact layer 14 of the p + -type and the contact layer 24 from p +The p-type defects are introduced from the side of the first main surface of the semiconductor substrate. The p-type defects are, for example, boron or aluminum. In this step, a mask is arranged such that the p-type defects are injected only into a predetermined area in the IGBT region 10 and a predetermined area in the diode region 20. This masking process protects the contact layer 14 from the p-type defects. + -type and the contact layer 24 from p + -Type in the surface layer of the base layer 15 of the p-type selectively formed in the IGBT area 10 or the diode area 20.

[0110] Fig. Figure 16 is a diagram illustrating a process for forming trenches 8. The trenches 8 are formed by a step to deposit a material for a hard mask onto the first main surface of a semiconductor substrate, a step to form a hard mask containing openings in the trenches 8 corresponding to the sub-regions by means of photolithography, and a step to etch the semiconductor substrate through the hard mask. The hard mask is, for example, a thin film such as SiO2. Among the multitude of trenches 8, a trench 8a is formed in the interface sub-region between the IGBT sub-region 10 and the diode sub-region 20. Trench 8a is formed such that there is no contact with the source layer 13 from the n + -type is created. In other words, the trench 8a in the boundary region between the IGBT region 10 and the diode region 20 is separated from the end of the source layer 13 formed in the IGBT region 10 by a predetermined distance from the n+ -Type remotely trained.

[0111] The trenches 8 in the IGBT area 10 penetrate from the first main surface of the semiconductor substrate the base layer 15 of the p-type and the storage layer 2 of the n-type and reach the drift layer 1 of the n - -Type. Some of the trenches 8 formed in IGBT area 10 also penetrate the source layer 13 from n + -Type. The trenches 8 in the diode region 20 penetrate from the first main surface of the semiconductor substrate the anode layer 25 of p-type and the storage layer 2 of n-type and reach the drift layer 1 of n - -Type.

[0112] In Fig. 16 is a center-to-center distance, or a pitch of the trenches 8 in the IGBT region 10, which is the same as the pitch of the trenches 8 in the diode region 20. However, the pitch of the trenches 8 in the IGBT region can differ from the pitch of the trenches 8 in the diode region 20. The pitch of the trenches 8 is appropriately modified during the masking process, depending on the mask structure.

[0113] Fig. Figure 17 is a diagram illustrating a step in the formation of an oxide film 9. The semiconductor substrate is heated in an oxygen-containing atmosphere. The oxide film 9 forms on the inner walls of the trenches 8 and the first main surface of the semiconductor substrate. Of the oxide film 9 formed on the inner walls of the trenches 8, the oxide film 9 formed in the trenches 8 of the IGBT area 10 corresponds to the insulating film 11b of a gate trench of gate 11 of an active trench or the insulating film 12b of a dummy trench of gate 12 of a dummy trench. The oxide film 9 that forms on the inner walls of the source layer 13 of the n +The oxide film 9 formed in the penetrating trenches 8 of the type is the insulating film 11b of a gate trench. The oxide film 9 formed in the trenches 8 of the diode region 20 corresponds to the insulating film 21b of a diode trench of gate 21 of a diode trench. The oxide film 9 formed in the trench 8a located in the interface region between the IGBT region 10 and the diode region 20 corresponds to the insulating film 51b of a boundary trench of gate 51 of a boundary trench. The oxide film 9 formed on the first main surface of the semiconductor substrate is removed in a later step.

[0114] Fig. Figure 18 is a diagram illustrating a step in the formation of the electrode 11a of a gate trench, the electrode 12a of a dummy trench, the electrode 21a of a diode trench, and the electrode 51a of a boundary trench. Polysilicon doped with n-type or p-type defects is deposited within the trenches 8 using a process such as chemical vapor deposition (CVD). As a result, the electrode 11a of a gate trench is formed inside the trenches 8 with the insulating film 11b of a gate trench positioned between it. The electrode 12a of a dummy trench is formed inside the trenches 8 with the insulating film 12b of a dummy trench positioned between it. The electrode 21a of a diode trench is formed inside the trenches 8 with the insulating film 21b of a diode trench arranged between them. The electrode 51a of a boundary trench is formed inside the trench 8a with the insulating film 51b of a boundary trench arranged between them.

[0115] Fig. Figure 19 is a diagram illustrating a step in the formation of the interlayer insulating film 4. The interlayer insulating film 4 is formed on the electrode 11a of a gate trench in the IGBT area 10. The interlayer insulating film 4 contains, for example, SiO2. Contact holes are then formed in the interlayer insulating film 4 by a masking process. The contact holes are formed such that the source layer 13 is shielded from the n + -Type, the contact layer 14 from p + -Type, the contact layer 24 from p + -Type, electrode 12a of a dummy trench, electrode 21a of a diode trench, and electrode 51a of a boundary trench are exposed. Furthermore, in these steps, the oxide film 9 formed on the first main surface of the semiconductor substrate is removed.

[0116] Fig. Figure 20 is a diagram illustrating one step in the formation of the barrier metal 5 and the emitter electrode 6. The barrier metal 5 is formed on the first main surface of the semiconductor substrate and the interlayer insulating film 4. The barrier metal 5 contains, for example, titanium nitride. The barrier metal 5 is formed by physical vapor deposition (PVD) or CVD.

[0117] Furthermore, the emitter electrode 6 is formed on the barrier metal 5. The emitter electrode 6 contains, for example, an aluminum-silicon alloy (Al-Si-based alloy). The emitter electrode 6 is formed by PVD, such as sputtering or vapor deposition. A nickel alloy (Ni alloy) can be formed as the emitter electrode 6 by electroless or electrolytic plating on the aluminum-silicon alloy. The plating process makes it possible to easily form a thick metal film. If the emitter electrode 6 becomes thicker, its heat capacity increases, and consequently, the heat resistance of the emitter electrode 6 improves. If a nickel alloy is formed on the aluminum-silicon alloy by a plating process, the plating process can be carried out after processing on the side of the second main surface of the semiconductor substrate.

[0118] Fig. Figure 21 is a diagram illustrating a step in thinning the semiconductor substrate. The second main surface of the semiconductor substrate is ground to thin it to a predetermined thickness according to the design of the semiconductor device. For example, the thickness of the semiconductor substrate after grinding is 80 µm or more and 200 µm or less.

[0119] Fig. Figure 22 is a diagram illustrating a step in the formation of the n-type buffer layer 3 and the p-type collector layer 16. Ion implantation of the n-type defects to form the n-type buffer layer 3 is carried out from the side of the second main surface of the semiconductor substrate into a surface layer of the drift layer 1 of the n-type substrate. --type. For example, phosphorus or protons can be injected as n-type defects. Alternatively, both phosphorus and protons can be injected.

[0120] Protons are injected from the second main surface of the semiconductor substrate into a deep position with a relatively low acceleration energy. The depth to which protons are injected is controlled relatively easily by changing the acceleration voltage. If proton ion implantation is performed a large number of times while changing the acceleration energy, a buffer layer 3 of n-type is formed with a greater width in the thickness direction of the semiconductor substrate than a phosphorus-containing buffer layer 3 of n-type.

[0121] Phosphorus, as an n-type impurity, has a higher activation rate than protons. Even in a thinned semiconductor substrate, the phosphorus-containing n-type buffer layer 3 more reliably reduces the occurrence of punch-through due to depletion layer expansion. To further thin the semiconductor substrate, it is preferred to form an n-type buffer layer 3 containing both protons and phosphorus. In this case, protons are injected from the second main surface of the semiconductor substrate into a deeper position than phosphorus.

[0122] Furthermore, ion implantation of p-type defects to form the p-type collector layer 16 is performed from the second primary surface of the semiconductor substrate. For example, boron is injected as the p-type defect. After ion implantation, the second primary surface of the semiconductor substrate is irradiated with a laser. The laser annealing activates the injected boron, thereby forming the p-type collector layer 16.

[0123] During this laser annealing process, phosphorus in the n-type buffer layer 3, injected from the second main surface of the semiconductor substrate into a relatively shallow position, is also activated. On the other hand, protons are activated at a relatively low annealing temperature of approximately 380°C to 420°C. Therefore, after proton injection, it is preferable that the semiconductor substrate, except for the proton activation step, is not heated to a temperature higher than 380°C to 420°C. Laser annealing only heats the area surrounding the second main surface of the semiconductor substrate to a high temperature. Therefore, laser annealing is effective for activating n-type or p-type defects after proton injection.

[0124] The n-type buffer layer 3 can be formed in IGBT region 10, diode region 20, and termination region 30, or it can be formed only in IGBT region 10 or diode region 20. The p-type collector layer 16 can also be formed in termination region 30. The p-type collector layer 16 in termination region 30 corresponds to the p-type termination collector layer 16a.

[0125] Fig. Figure 23 is a diagram showing a step towards the formation of the cathode layer 26 from n + -Type illustrated. Ion implantation of the defects of the n-type to form the cathode layer 26 of the n +The injection of n-type defects into the second main surface of the semiconductor substrate in the diode region 20 is carried out. Phosphorus is injected as the n-type defects. The n-type defects are selectively injected by means of a masking process such that a boundary is created between the p-type collector layer 16 and the n-type cathode layer 26. + -Type at a distance U1 from the boundary between the IGBT area 10 and the diode area 20 in the direction of the diode area 20.

[0126] An injection quantity of the n-type defects to form the cathode layer 26 of n + The -type is greater than the injection quantity of p-type defects contained in the p-type collector layer 16. The n-type defects for the cathode layer 26 of the n +-type impurities are injected into an area where the collector layer 16 is of p-type. That is, it is necessary to convert the p-type semiconductor into an n-type semiconductor by injecting the n-type impurities. Therefore, the n-type impurities are injected in such a way that the concentration of n-type impurities in all areas where the cathode layer 26 of n-type is to be formed is higher than the concentration of p-type impurities.

[0127] Although an example in which the depth of the collector layer 16 is of the p-type and the depth of the cathode layer 26 is of the n-type + -type from the second main surface are the same, in Fig. Figure 23 illustrates a depth relationship between the p-type collector layer 16 and the n-type cathode layer 26. + -Type not limited to these. The depth of the cathode layer 26 of n +-Type is equal to the depth of the collector layer 16 of p-type or greater.

[0128] Fig. Figure 24 is a diagram illustrating one step in the formation of the collector electrode 7. The collector electrode 7 is formed on the second main surface in the IGBT region 10, the diode region 20, and the termination region 30. The collector electrode 7 can be formed over the entire second main surface of the semiconductor substrate.

[0129] The collector electrode 7 contains an aluminum-silicon alloy, titanium, and the like. The collector electrode 7 is formed by PVD processes such as sputtering or vapor deposition. The collector electrode 7 can have a configuration in which multiple metal layers, created from a metal such as an aluminum-silicon alloy, titanium, nickel, or gold, are laminated. Furthermore, another metal film can be formed as the collector electrode 7 by electroless plating or electroplating onto a metal film formed by PVD.

[0130] In the first preferred embodiment, a plurality of semiconductor devices 100 or a plurality of semiconductor devices 101 are fabricated in a matrix on a single wafer by the above manufacturing steps. The plurality of semiconductor devices is separated into individual semiconductor devices by laser cutting or cutting with a knife. As a result, the semiconductor device 100 or the semiconductor device 101 is completed. (Effects)

[0131] In summary, the semiconductor device according to the first preferred embodiment comprises the semiconductor substrate, the IGBT region 10, the diode region 20, the gate 51 of a boundary trench, and the carrier control region 50. A transistor is formed in the IGBT region 10. The transistor has a p-type base layer 15 (the base layer of a first conductivity type) and an n-type source layer 13. +-type (the source layer of a second conductivity type) and the gate 11 of an active trench. The p-type base layer 15 is formed in the surface layer of the semiconductor substrate. The n-type source layer 13 + The -type is selectively arranged in the surface layer of the base layer 15 of the p-type. The gate 11 of an active trench extends such that, in plan view, it borders the source layer 13 of the n + -Type crosses. A diode is formed in diode region 20. Diode region 20 is arranged adjacent to IGBT region 10. Gate 51 of a boundary trench is located in the boundary subregion between IGBT region 10 and diode region 20. Carrier control region 50 is arranged as a surface layer of the semiconductor substrate at a position closer to gate 51 of a boundary trench than the source layer 13 located between gate 51 of a boundary trench and gate 11 of an active trench. +-type. The concentration of n-type defects (the concentration of defects of a second conductivity type contained in the carrier control region 50) is lower than the concentration of n-type defects in the source layer 13. + -type contained defects of n-type. The carrier control region 50 in the first preferred embodiment is that between the source layer 13 of the n + -type and the Gate 51 of a border trench arranged base layer 15 of p-type.

[0132] The source layer 13 located between Gate 51 of a border trench and Gate 11 of an active trench from n + -Type is in contact with Gate 11 of an active trench and is not in contact with Gate 51 of a border trench.

[0133] The semiconductor device 100 and the semiconductor device 101, configured as above, reduce element destruction caused by a current concentrated in the boundary region between the IGBT area 10 and the diode area 20.

[0134] When the IGBT or the freewheeling diode switches from on to off, a Hall current flows from diode region 20 to IGBT region 10. Therefore, holes are concentrated on the side of IGBT region 10 adjacent to the gate 51 of a boundary trench. In particular, a region along the gate 51 of a boundary trench corresponds to the shortest path for the movement of the holes. Therefore, a large current is more likely to flow in the region along the gate 51 of a boundary trench than at other locations. The Hall current flowing in IGBT region 10 passes through contact layer 14 from p + -type, which exhibits low resistance. In a conventional structure, where the source layer 13 is separated from the n +When the type is in contact with gate 51 of a boundary trench, the Hall current reaches the contact layer 14 of the p + -type, while directly below source layer 13 from n + -type passes through. As the current increases, a latch-up of a signal from source layer 13 of the n occurs. + -type and the basal layer 15 formed by the p-type parasitic pn transition, causing element destruction.

[0135] The semiconductor device 100 and the semiconductor device 101 according to the first preferred embodiment have between the source layer 13 of the n + -Type and the gate 51 of a boundary trench open the carrier control area 50 described above. The Hall current flowing into the IGBT area 10 reaches the contact layer 14 from p via the carrier control area 50. + -Type. Therefore, the Hall current hardly flows below source layer 13 from the n +-Type. Therefore, a latch-up of the parasitic pn junction is unlikely to occur, thus preventing element destruction.

[0136] Furthermore, source layer 13 is from n + -Type in contact with the gate 11 of an active trench of the IGBT area 10, which is adjacent to the gate 51 of a boundary trench. Such a configuration increases the current-carrying capability of the semiconductor device 100 and the semiconductor device 101. The semiconductor device 100 and the semiconductor device 101, configured as above, are useful for power semiconductor devices that control a large amount of electrical power.

[0137] In the first preferred embodiment, the first conductivity type corresponds to the p-type and the second conductivity type corresponds to the n-type. However, the first conductivity type can correspond to the n-type and the second conductivity type can correspond to the p-type. That is, the p-type and n-type layers of the semiconductor device 100 or the semiconductor device 101 can be interchanged. (Modification 1 of the first preferred embodiment)

[0138] The carrier control area 50 is not on the base layer 15 of p-type between the source layer 13 of n. + -type and the gate 51 of a boundary trench. The carrier control area 50 can, for example, be any one of a semiconductor layer from n - -type, a semiconductor layer of p - -type and a semiconductor layer of p +-type, which is arranged as a surface layer of the semiconductor substrate at a position closer to the gate 51 of a boundary trench than the source layer 13 of the n + -type. An interface between source layer 13 and n + The type of defect and the carrier control region 50 need not be clearly defined. That is, it is only necessary that the concentration of n-type defects contained in the carrier control region 50 is lower than the concentration of n-type defects in the source layer 13. + -type contained defects of n-type. For example, the carrier control region 50 can be a semiconductor layer of n-type. - -type, a semiconductor layer of p - -type or a semiconductor layer of p + -type, whose concentration of n-type defects from source layer 13 from n + -Type gradually decreases in the direction of Gate 51 of a border trench. (Modification 2 of the first preferred embodiment)

[0139] Gate 51 of a border trench is connected to source layer 13 from n + The IGBT type is not in contact between Gate 51 of a boundary trench and Gate 11 of an active trench. Therefore, Gate 51 of a boundary trench does not form an IGBT cell.

[0140] Gate 51 of a boundary trench can be a gate of a diode trench that is closest to the IGBT area 10 among the gates 21 of diode trenches arranged in diode area 20. In this case, the boundary sub-area where gate 51 of a boundary trench is located corresponds to an end of the diode area 20 that is adjacent to the IGBT area 10. <Zweite bevorzugte Ausführungsform>

[0141] A semiconductor device according to the second preferred embodiment is described below. The second preferred embodiment is a subordinate concept of the first preferred embodiment. In the second preferred embodiment, components similar to those in the first preferred embodiment are given identical reference numerals, and their detailed description is omitted.

[0142] Fig. Figure 25 is a top view illustrating a configuration of a boundary sub-region between an IGBT region 10 and a diode region 20 in the second preferred embodiment.

[0143] The semiconductor device according to the second preferred embodiment has a source layer 13 of the n + -type and a contact layer 14 from p + -Type between Gate 51 of a border trench and Gate 11 of an active trench. The source layer 13 of n +-type and the contact layer 14 from p + -type are formed in a surface layer of the base layer 15 of p-type. In an area between gate 51 of a boundary trench and gate 11 of an active trench, the source layer 13 of n + -type and the contact layer 14 from p + -Type arranged alternately in one direction of the direction of gate 11 of an active trench. That is, the contact layer 14 from p + -Type is on both sides of source layer 13 of n + -Type arranged.

[0144] A carrier control area 50 is, as in the first preferred embodiment, a p-type base layer 15. The p-type base layer 15 is closer to the gate 51 of a boundary trench than the n-type source layer 13. + -Type arranged.

[0145] This configuration reduces the resistance of a path through which a Hall current flows. Consequently, the occurrence of a latch-up is further prevented. <Comparison example>

[0146] A semiconductor device according to a comparative example is described below. The comparative example is a subordinate concept of the first preferred embodiment. In the comparative example, components similar to those in the first or second preferred embodiment are given identical reference numerals, and their detailed description is omitted.

[0147] Fig. Figure 26 is a top view illustrating a configuration of a boundary sub-area between an IGBT area 10 and a diode area 20 in the comparison example.

[0148] As in the second preferred embodiment, a source layer 13 of n is located in a region between the gate 51 of a boundary trench and a gate 11 of an active trench. + -type and a contact layer 14 from p + -Type arranged alternately in a direction in which Gate 11 of an active trench extends.

[0149] A carrier control area 50 in the comparison example has a connection between the source layer 13 and n. + -Type and the contact layer 14 located at Gate 51 of a border trench from p + -Type on. The contact layer 14 from p + The -type is formed in a surface layer of a base layer 15 of p-type. In the area between gate 51 of a boundary trench and gate 11 of an active trench, surfaces of the source layer 13 of n + -type and the contact layer 14 from p + -Type the first main surface of the semiconductor substrate.

[0150] The source layer 13 located between Gate 51 of a border trench and Gate 11 of an active trench from n + The -type is formed by injecting n-type defects into the surface layer of the p-type base layer 15. Furthermore, the contact layer 14 is formed by the p + -type as the carrier control area 50 is formed by injecting p-type defects into the surface layer of the p-type base layer 15. Accordingly, a concentration of n-type defects is formed in the contact layer 14 of the p + -type as contained in the carrier control area 50, lower than a concentration of n-type defects contained in the source layer 13 of the n + -type are included. In addition, there is a concentration of p-type defects in contact layer 14 of the p + -type are present, higher than a concentration of p-type defects found in source layer 13 of n +-type are included.

[0151] With such a configuration, a resistance between source layer 13 and n decreases. + -type and Gate 51 of a border trench. That is, contact layer 14 from p + -Type reduces the resistance of a current path and suppresses one below source layer 13 from n + -Type of diode range 20 flowing Hall current. (Modification of the comparative example)

[0152] In a modification of the comparison example, the contact layer 14 is from p + -Type as the carrier control area 50 to a deeper position than the source layer 13 of n + -type formed. In this case, contact layer 14 is formed by p + -Type designed such that it forms an end of a lower part of source layer 13 from n + -type covered. Therefore, a resistance of a current path between the source layer 13 of the n +-Type and Gate 51 of a border trench further on. <Dritte bevorzugte Ausführungsform>

[0153] A semiconductor device according to the third preferred embodiment is described below. The third preferred embodiment is a subordinate concept of the first preferred embodiment. In the third embodiment, components similar to those in any one of the first to second preferred embodiments or the comparative example are given identical reference numerals, and their detailed description is omitted.

[0154] Fig. Figure 27 is a cross-sectional view illustrating a configuration of a boundary sub-region between an IGBT region 10 and a diode region 20 in the third preferred embodiment.

[0155] A cathode layer 26 arranged on one side of the second main surface of the diode region 20 from n +The -type is arranged such that it projects into the IGBT region 10 by a distance U2 from a boundary between the IGBT region 10 and the diode region 20. Compared to a structure in which the cathode layer 26 is not located at the boundary between the IGBT region 10 and the diode region 20, the following applies: + -Type does not protrude into the IGBT area 10, are drifted into a drift layer 1 by n during operation of the IGBT. - The injected hole carrier type is reduced. A Hall current flowing into one end of the IGBT region 10 adjacent to a gate 51 of a boundary trench when the IGBT switches from on to off is also reduced. Therefore, destruction of the semiconductor device is prevented.

[0156] The embodiments and the comparative example of the present disclosure can be combined.

Claims

[1] Semiconductor device comprising: a semiconductor substrate; a transistor region (10) in which a transistor is formed, the transistor having a base layer (15) of a first conductivity type arranged in a surface layer of the semiconductor substrate, a source layer (13) of a second conductivity type selectively arranged in a surface layer of the base layer (15), and a trench gate (11) extending such that it intersects the source layer (13) in plan view; a diode area (20) which is arranged adjacent to the transistor area (10) and in which a diode is formed; a gate (51) of a boundary trench, which is arranged in a boundary subregion between the transistor area (10) and the diode area (20); and a carrier control region (50) which is arranged as the surface layer of the semiconductor substrate at a position closer to the gate (51) of a boundary trench than the source layer (13) located between the gate (51) of a boundary trench and the trench gate (11), wherein a concentration of defects of a first conductivity type contained in the carrier control region (50) is higher than a concentration of defects of a first conductivity type contained in the source layer (13), or a concentration of defects of a second conductivity type contained in the carrier control region (50) is lower than a concentration of defects of a second conductivity type contained in the source layer (13); the transistor region (10) has a collector layer (16) of a first conductivity type, which is arranged in a surface layer on one side of a lower surface of the semiconductor substrate; the transistor area (10) has a contact layer (14) of a first conductivity type, which is formed in the surface layer of the base layer (15), a concentration of defects of a first conductivity type contained in the contact layer (14) is higher than a concentration of defects of a first conductivity type contained in the base layer (15), wherein the collector layer (16) is arranged such that it projects into the diode region (20); and wherein the carrier control area (50) has the base layer (15) arranged between the source layer (13) and the gate (51) of a boundary trench and the contact layer (14) is not arranged in the carrier control area (50). [2] Semiconductor device according to claim 1, wherein the source layer (13) located between the gate (51) of a boundary trench and the trench gate (11) is in contact with the trench gate (11) and is not in contact with the gate (51) of a boundary trench. [3] Semiconductor device according to claim 1 or 2, wherein the transistor area (10) the contact layer (14) of a first conductivity type, which is formed in the surface layer of the base layer (15), as the surface layer of the semiconductor substrate between the gate (51) of a boundary trench and the trench gate (11), and the source layer (13) and the contact layer (14), which are arranged between the gate (51) of a boundary ditch and the ditch gate (11), are arranged alternately in a direction of travel of the ditch gate (11). [4] Semiconductor device according to any one of claims 1 to 3, wherein the diode region (20) comprises: an anode layer (25) of a first conductivity type, which is arranged in the surface layer on one side of an upper surface of the semiconductor substrate; and a cathode layer (26) of a second conductivity type, which is arranged in a surface layer on one side of a lower surface of the semiconductor substrate. [5] Semiconductor device according to any one of claims 1 to 4, wherein the transistor area (10) comprises: the base layer (15) and the source layer (13), which are arranged in the surface layer on one side of an upper surface of the semiconductor substrate; and a drift layer (1) of a second conductivity type between the base layer (15) and the collector layer (16), the trench gate (11) penetrates the source layer (13) and the base layer (15) from the upper surface of the semiconductor substrate and reaches the drift layer (1), the transistor is an insulated-gate bipolar transistor (IGBT) having the source layer (13), base layer (15), drift layer (1), trench gate (11) and collector layer (16), the diode area (20) exhibits: an anode layer (25) of a first conductivity type, which is arranged in the surface layer on the side of the upper surface of the semiconductor substrate; a cathode layer (26) of a second conductivity type, which is arranged in the surface layer on the side of the lower surface of the semiconductor substrate; and the drift layer (1) between the anode layer (25) and the cathode layer (26), the diode is a freewheeling diode comprising the anode layer (25), the cathode layer (26) and the drift layer (1), and The insulated gate bipolar transistor and the freewheeling diode, arranged on the semiconductor substrate, form a backward-conducting IGBT.

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