PACKAGE STRUCTURE, SEMICONDUCTOR DEVICE AND METHOD FOR THEM TO BE MADE

Abstract

Package structure with: a solder element (130, 218A-C); a front-side redistribution layer structure (122) on the solder element (130, 218A-C), wherein the front-side redistribution layer structure (122) has one or more dielectric layers (213-216) filled with a thermally conductive dielectric material, wherein the front-side redistribution layer structure (122) has an upper metal layer (Mz) adjacent to the solder element (130, 218A-C), and an intermediate metal layer (My) is electrically connected to the upper metal layer (Mz), wherein a thickness of the upper metal layer (Mz) is greater than a thickness of the intermediate metal layer (My); a die (150, 160, 211) which is mounted on the front-side redistribution layer structure (122) and electrically connected to it; and a rear-side redistribution layer structure (128, 204) which is electrically connected to the die (150, 160, 211) and the front-side redistribution layer structure (122).

Description

background

[0001] A three-dimensional integrated circuit (3DIC) consists of a semiconductor device with two or more layers of active electronic components stacked vertically and interconnected to form an integrated circuit. Heat dissipation is a concern with 3DICs, as 3DIC systems with increased chip density can exhibit high heat density and poor heat dissipation performance.

[0002] The heat generated in the inner dies of a 3DIC can become trapped in an inner region of a lower stack die, causing a high local temperature peak, sometimes referred to as a hot spot. Hot spots, caused by heat generated by devices, can impair the electrical performance of other devices higher up in the stack dies and often lead to electromigration and reliability issues for 3DIC packages. Therefore, it is necessary to address these shortcomings and problems.

[0003] Package structures and semiconductor devices, as well as methods for their fabrication, are also known, for example, from JP 2020 - 113 748 A, US 2017 / 0 345 714 A1, US 2015 / 0 206 799 A1, WO 2020 / 078 939 A1, US 2015 / 0 145 142 A1, US 2019 / 0 304 959 A1 and US 2011 / 0 068 484 A1. Short description of the drawings

[0004] Aspects of the present invention are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. Rather, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 is a sectional view of a PoP device (PoP: Package on Package) according to exemplary embodiments of the present invention. The Fig. Figures 2 to 16 are sectional views of an integrated fan-out package (InFO package) at various stages of an IC-BEOL manufacturing process (BEOL: Back End of Line) according to exemplary embodiments of the present invention. Fig. Figure 17 is a sectional view of an information package according to exemplary embodiments of the present invention. Detailed description

[0005] The following description provides many different exemplary embodiments or examples for implementing various features of the provided subject matter. Specific simplified examples of components and arrangements are described below to illustrate the present invention. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, such that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present invention.This repetition is for simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0006] The terms used in this patent description generally have their usual meanings in the field and in the specific context in which each term is used. The use of examples in this description, such as examples of terms discussed herein, is for illustrative purposes only and in no way limits the scope and meaning of the invention or any exemplary term. Likewise, the present invention is not limited to various embodiments described in this patent description.

[0007] While the terms "first," "second," etc., can be used here to describe different elements, these elements should not be limited by these terms. These terms merely serve to distinguish one element from another. For example, a first element could be called a second element, and likewise a second element could be called a first element, without altering the scope of the embodiments. The term "and / or" used here encompasses all combinations of one or more of the listed associated elements.

[0008] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to conveniently describe the relationship of one element or structure to one or more other elements or structures illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative descriptors used herein may be interpreted accordingly.

[0009] In this document, the term "coupled" can also mean "electrically coupled," and the term "connected" can also mean "electrically connected." The terms "coupled" and "connected" can also be used to indicate that two or more elements work together or interact with each other.

[0010] Various embodiments of the present invention are described in a specific context, namely with a three-dimensional (3D) information point-of-promotion (PoP) device. However, the principles of the present invention can also apply to other semiconductor structures or circuits.

[0011] Fig. Figure 1 is a sectional view of a PoP device 100 according to some embodiments of the present invention. As shown in Fig. As shown in Figure 1, the PoP device 100 has an upper package 110, which is electrically connected to a lower package 120 by means of one or more redistribution layers, which are manufactured in a later described InFO PoP device. In some implementations, the upper package 110 and the lower package 120 may have various other components, layers, circuits and structures, which are omitted here for the sake of clarity.

[0012] As also in Fig. As shown in Figure 1, the upper package 110 is arranged above the lower package 120. The upper package 110 can include one or more device dies 112 and 114. In some embodiments, the device dies 112 and 114 are vertically separated memory components. For example, the device dies 112 and 114 can be memory components such as dynamic random-access memory (DRAM) or other suitable types of memory devices. Fig. Figure 1 shows two device dies 112 and 114, but the present invention is not limited to these. In various embodiments, the upper package 110 can have any number of device dies 112 and 114.

[0013] In some embodiments, the device dies 112 and 114 in the upper package 120 are electrically connected to the lower package 120 by one or more wire bonds, vias, and contact pads in an upper package substrate 118. The upper package 110 can comprise a molding material 116 or another suitable encapsulation material to cover the device dies 112 and 114 and protect the wire bonds.

[0014] The lower package 120 has a lower package substrate on its front face. In some embodiments, the lower package substrate is polybenzoxazole (PBO) or another suitable substrate material. As shown in Fig. As shown in Figure 1, one or more solder elements 130 are mounted on the lower package substrate to function as electrical connectors. In some embodiments, the solder elements 130 are manufactured from solder balls made from a ball grid array (BGA). As shown, the solder elements 130 can be used to mount the lower package 120 to, for example, a printed circuit board (PCB) 140 located below it or to other components and to connect them electrically. In some embodiments, one or more integrated passive devices (IPDs) 190 can be mounted below the lower package 120 and can be positioned between the lower package 120 and the printed circuit board 140 located below it.

[0015] As also in Fig. As shown in Figure 1, the lower package 120 has a front-facing RDL (Redistribution Layer) structure 122 in the lower package substrate. The front-facing RDL structure 122 electrically connects a device die 150 in the lower package 120 to, for example, the solder elements 130 and the printed circuit board 140. In some embodiments, device dies 150 and 160 in the lower package 120 are logic devices or logic components, such as integrated logic circuits, analog circuits, etc. The device dies 150 and 160 can be encapsulated with a molding material 126 or another suitable encapsulation material to cover the device dies 150 and 160. As shown in Figure 1, the lower package 120 has a front-facing RDL structure 122 that electrically connects a device die 150 in the lower package 120 to, for example, the solder elements 130 and the printed circuit board 140. Fig. As shown in Figure 1, two device dies 150 and 160 are stacked vertically on top of each other and connected to each other by conductive structural elements, but in other embodiments the lower package 120 can have any number of device dies that are integrated and encapsulated with the molding material 126.

[0016] In some embodiments, the device dies 150 and 160 can be mounted below or onto a passivation layer by means of a die attachment layer (DAF). In some embodiments, the passivation layer comprises polybenzoxazole (PBO), an Ajinomoto build-up layer (ABF), or another suitable material. A buffer layer, also comprising PBO, ABF, or another suitable material, can be arranged above the passivation layer. Optionally, a multilayer tape can be arranged above the buffer layer. The multilayer tape can be a solder release layer (SR layer), an ABF, or a back-side multilayer coating tape (LC tape) containing a thermosetting polymer or another suitable material. In some embodiments, an underfill material can be used to encapsulate portions of the upper package 110 and the lower package 120.The underfill material can extend from a top surface of the printed circuit board 140, along sides of the lower package 120, and along a portion of the sides of the upper package 110. In some embodiments, the underfill material can be positioned between the upper package substrate 118 and the multilayer tape or buffer layer.

[0017] Let us stay with Fig. 1. The lower package 120 also features package vias (TPVs) 124 that penetrate the mold material 126 and extend between the front and back sides of the lower package 120. The package vias 124, which may also be referred to here as InFO vias (TIVs) or metal vias, are embedded in and pass through the mold material 126. In some embodiments, the package vias 124 contain copper (Cu), nickel (Ni), a copper alloy (e.g., copper / titanium), solder, and / or a solder alloy such as tin-silver (SnAg), tin-bismuth (SnBi), tin-copper (SnCu), tin-silver-copper (SnAgCu), or tin-silver-copper-nickel (SnAgCuNi), or combinations thereof, or another suitable metal. Fig. Although four package vias 124 are shown in Figure 1, in other embodiments more or fewer package vias 124 can be used in the lower package 120.

[0018] In some embodiments, the lower package 120 also has a rear-facing RDL structure 128. In some embodiments, part of the rear-facing RDL structure 128 can extend over a top surface of the device die 160. This electrically connects the device die 160, for example, to the device dies 112 and 114 in the upper package 110 and to the package vias 124. Furthermore, another part of the rear-facing RDL structure 128 can extend over the package vias 124. In particular, redistribution layer bond pads 1282 of the rear-facing RDL structure 128 are arranged on top surfaces of the package vias 124 and cap the top surface of the package vias 124. Fig. 1 or cover them in some other way. Accordingly, the rear-facing RDL structure 128 can be electrically connected to the device die 160 and the front-facing RDL structure 122 via the package vias 124. In some embodiments, the redistribution layer bond pads 1282 and the package vias 124 are made of the same material (e.g., copper). Therefore, the redistribution layer bond pads 1282 and the package vias 124 appear to be a single unit structure.

[0019] Solder elements 170 are fabricated or mounted on the redistribution layer bond pads 1282 and the package vias 124, and are electrically connected to them. The solder elements 170 electrically connect the upper package 110 to the lower package 120. In some embodiments, the solder elements 170 are made of solder paste, organic solderability preservative (OSP), or another suitable conductive material, or a combination thereof. In some embodiments, an intermetallic compound (IMC) is arranged between the solder elements 170 and the underlying redistribution layer bond pads 1282, capping the package vias 124. The intermetallic compound is formed by a melting process, which is used to electrically connect the solder elements 170 to the package vias 124.

[0020] In some other embodiments, three-dimensional integrated chips can also be implemented in other ways, since the device 100 of Fig. 1 is merely an example and is not intended to limit the present invention. For example, a 3D SoIC (System on an Integrated Chip) structure can be implemented in some semiconductor devices. This structure is a non-monolithic vertical structure comprising two to eight stacked two-dimensional (2D) flip chips with different functionalities, such as logic chips, memory chips, radio frequency (RF) chips, and the like. By way of example, and not limiting, the logic chips can be main processors (CPUs), and the memory chips can be SRAM (static random-access memory), DRAM (dynamic random-access memory), MRAM (magnetic random-access memory), or other memory arrangements. In the 3D SoIC structure, the 2D chips can be interconnected by microbumps, bond pads, silicon vias (TSVs), or other interconnect structures.

[0021] Poor heat dissipation in an IC package can lead to electromigration and reliability issues, resulting in poor IC performance. Different types of IC chips can have varying thermal tolerances. For example, memory chips, such as SRAM arrays, may have lower thermal tolerances than logic chips. In some modern devices, the chip speed may need to be reduced (e.g., by about 5% to 10%) to meet temperature requirements.

[0022] The current density of a 3DIC structure can be higher than that of a single die chip due to the stacking of dies in a modern node. These 3DIC structures have increased chip density and higher current / heat density per unit area, and they present challenges for heat dissipation. For example, electromigration can increase the resistance of interconnects and TSVs, reducing chip performance and shortening the lifetime of the 3DIC structures. Reliability issues can also arise from the materials used in 3DIC structures, which may have different coefficients of thermal expansion (CTEs). Materials with differing CTEs can lead to thermomechanical stresses between IC chips.

[0023] As in Fig. As shown in Figure 1, the heat generated in the inner dies can be trapped in an inner region 180 of the lower stacked device dies 150 and 160 and can cause a hot spot. In some embodiments, local hot spots can occur on any chip layer and are not limited to chip layers containing logic chips. To provide a heat dissipation path that removes and distributes heat generated by the device dies 150 and 160, in some embodiments of the present invention, the front-facing RDL structure 122 can have one or more dielectric layers filled with a thermally conductive dielectric material, such as a material having a thermal conductivity substantially equal to or greater than about 2 W / (m·K).

[0024] By fabricating one or more dielectric layers using a thermally conductive but electrically insulating material in the front-facing RDL structure 122, heat can be efficiently dissipated and eliminated. By way of example, and not as a limitation, the thermally conductive dielectric material for the one or more dielectric layers can be aluminum nitride (AlN) and / or boron nitride (BN), such as hexagonal boron nitride (h-BN), or a combination thereof. Under certain temperature conditions (e.g., 300 K), aluminum nitride offers high thermal conductivity up to a range of about 285 W / (m·K) to about 321 W / (m·K), and it is an electrical insulator with a static dielectric constant of about 8.5.Hexagonal boron nitride also offers high thermal conductivity of up to about 400 W / (m · K) in a plane and about 6 W / (m · K) out of the plane, and it is an electrical insulator with a static dielectric constant of about 6.9 in the plane and about 3.5 out of the plane.

[0025] In some embodiments of the present invention, the front-facing RDL structure 122 can have one or more electrically conductive layers, wherein at least one of the electrically conductive layers has a thickness substantially greater than 4 µm. In some embodiments, the thickness of the electrically conductive layer can be approximately 4 µm to approximately 10 µm. The thick electrically conductive layers, such as metal layers, in the front-facing RDL structure 122 can also improve the thermal conductivity of the front-facing RDL structure 122 and the heat dissipation between different layers in the lower package 120. Accordingly, one or more thermally conductive horizontal layers can be produced adjacent to the electrical interconnects in the lower package 120 to dissipate heat from local hot spots.

[0026] A manufacturing process for the lower package 120 is described by way of example with reference to the Fig. 2 to 16 described. The Fig. Figures 2 to 16 are sectional views of an InFO package 200 at various stages of an IC-BEOL manufacturing process according to some embodiments of the present invention.

[0027] Although the manufacturing process is presented and described here as a series of steps or events, it should be understood that the sequence of these steps or events shown should not be interpreted as restrictive. For example, some steps may be performed in different sequences, and / or they may occur simultaneously with other steps or events than those presented and / or described here. Furthermore, not all of the steps presented here need to implement one or more aspects or embodiments of the description, and one or more of the steps presented here may be performed in one or more separate steps and / or phases.

[0028] In Fig. 2. A carrier 201, an adhesive layer 202, and a polymer-based layer 203 are provided. In some embodiments, the carrier 201 comprises glass, ceramic, or another suitable material to provide structural support during the fabrication of various structural elements in a device package. In some embodiments, the adhesive layer 202, which is, for example, an adhesive layer, an LTHC coating (LTHC: light-to-heat conversion), an ultraviolet (UV) layer, or the like, is arranged over the carrier 201. The polymer-based layer 203 is applied to the carrier 201 by means of the adhesive layer 202. In some embodiments, the polymer-based layer 203 is polybenzoxazole (PBO), an Ajinomoto build-up layer (ABF), a polyimide, benzocyclobutene (BCB), a solder release layer (SR layer), a die attachment layer (DAF) or the like, but the present invention is not limited thereto.

[0029] Now let's move on to... Fig. 3, where a rear-side redistribution layer (RDL) 204 is subsequently fabricated. In some embodiments, the rear-side RDL 204 has one or more redistribution lines as conductive structural elements, such as electrically conductive lines and / or vias fabricated between one or more dielectric layers. In some embodiments, the dielectric layers are fabricated from aluminum nitride, boron nitride, or a combination thereof. In some embodiments, the dielectric layers are fabricated from another suitable material, such as PI, PBO, BCB, epoxy, silicone, acrylates, nanofilled phenolic resin, siloxane, a fluorinated polymer, a polynorbornene, or the like, using a suitable process such as spin coating, sputtering, and the like.

[0030] In some embodiments, conductive structural elements / layers are fabricated between the dielectric layers. The fabrication of these conductive structural elements comprises the following: structuring the dielectric layers, for example, using a combination of photolithography and etching processes; and fabricating conductive structural elements within the structured dielectric layers, for example, by depositing a seed layer and using a mask layer to define the shape of the conductive structural elements. The conductive structural elements are designed to form functional circuits and input / output elements for subsequently attached device dies.

[0031] Now let's move on to... Fig. 4. A structured photoresist 205 is produced over the backside RDL 204 and the polymer-based layer 203. In some embodiments, the photoresist 205 is deposited, for example, as a protective layer over the backside RDL 204. Then, portions of the photoresist 205 are exposed using a photomask (not shown). Subsequently, exposed or unexposed portions of the photoresist 205 are removed, depending on whether a negative or a positive resist is used. The resulting structured photoresist 205 has openings 206 arranged in peripheral regions of the support 201. In some embodiments, the openings 206 also expose conductive structural elements in the backside RDL 204.

[0032] Now let's move on to... Fig. 5. A seed layer 207 is deposited over the structured photoresist 205. Then, in Fig. 6. The openings 206 are filled with a conductive material 208, such as copper, silver, gold, and the like, to create conductive vias. In some embodiments, the openings 206 are plated with the conductive material 208 during a plating process, which may be, for example, electrochemical plating, electroless plating, or the like. In some embodiments, the conductive material 208 overfills the openings 206.

[0033] Now let's move on to... Fig. 7, where a grinding and a CMP process (CMP: chemical-mechanical polishing) are carried out to remove excess parts of the conductive material 208 above the photoresist 205.

[0034] Now let's move on to... Fig. 8, where the photoresist 205 is removed. In some embodiments, a plasma removal or wet stripping process is used to remove the photoresist 205. In some embodiments, the plasma removal process is followed by wet immersion in a sulfuric acid solution (H₂SO₄) to clean the package 200 and remove the remaining photoresist material.

[0035] In this way, conductive vias 209 are created above the rear-side RDL 204. Alternatively, in some embodiments, the conductive vias 209 are replaced by conductive pins or conductive wires, such as copper, gold, or silver wires. In some embodiments, the conductive vias 209 are spaced apart from each other by openings 210, with at least one opening 210 between adjacent conductive vias 209 being large enough to accommodate one or more semiconductor device dies.

[0036] Now let's move on to... Fig. 9, where a device die 211 is mounted and attached to the package 200. In some embodiments, an adhesive layer is used to attach the device die 211 to the rear RDL 204. In Fig. Figure 1 shows only one device die 211, but in some other embodiments, two or more device dies 211, such as a driver die and a receiver die, can be mounted and attached to the package 200. In some embodiments, a stack of one or more device dies (e.g., device dies 150 and 160 of Figure 1) can be mounted on the package 200. Fig. 1) be mounted and attached to the Package 200.

[0037] Now let's move on to... Fig. 10, where a molding compound 212 is produced in the package 200 after the one or more device dies 211 have been mounted on the rear RDL 204 and / or the polymer-based layer 203 in the opening 210. The molding compound 212 is distributed such that it fills gaps between the one or more device dies 211 and the conductive vias 209, gaps between adjacent conductive vias 209, and / or gaps between any two of the device dies 211. In some embodiments, the molding compound 212 contains a suitable material, such as an epoxy resin, a mold filler, or the like. In some embodiments, compression molding, injection molding, and molding of a liquid encapsulation material are suitable methods for producing the molding compound 212, but the present invention is not limited to these methods.For example, the molding compound 212 can be distributed in a liquid form between the one or more device dies 211 and the conductive vias 209. In some embodiments, the molding compound 212 can flood the one or more device dies 211 and the conductive vias 209, so that the molding compound 212 covers the top surfaces of the one or more device dies 211 and the conductive vias 209.

[0038] Now let's move on to... Fig. 11, where a grinding and a CMP process are performed to remove excess material from the molding compound 212, and the molding compound 212 is reground to reduce its overall thickness, thus exposing the conductive vias 209. Because the resulting structure has conductive vias 209 extending through the molding compound 212, the conductive vias 209 are also referred to as mold vias, interconnect vias (TIVs), and the like. The conductive vias 209 establish electrical connections with the rear-side RDL 204 in the package 200. In some embodiments, the conductive vias 209 can be used with a 3D silicon interposer.

[0039] Now let's move on to... Fig. 12, where a structured dielectric layer 213, having openings, is produced over the molding compound 212. In some embodiments, the dielectric layer 213 comprises aluminum nitride, boron nitride, or a combination thereof. In some embodiments, the dielectric layer 213 comprises PI, PBO, BCB, epoxy, silicone, acrylates, nanofilled phenolic resin, siloxane, a fluorinated polymer, a polynorbornene, or the like. In some embodiments, the dielectric layer 213 is selectively treated with an etchant containing, for example, CF4, CHF3, C4F8, HF, and the like, configured to etch the dielectric layer 213 to create the openings. As shown by way of example, the openings expose conductive pillars and the conductive vias 209. In some embodiments, the openings comprise one or more via openings and a metal wire trench above them.The via openings extend vertically from a bottom of the dielectric layer 213 to a bottom of the metal wire grooves, which extend to a top of the dielectric layer 213.

[0040] Now let's move on to... Fig. 13, where in some embodiments the openings are filled with an electrically conductive material to produce an electrically conductive layer Mx having one or more conductive structural elements (e.g., redistribution lines). By way of example, a seed layer (not shown) is produced in the openings, and the conductive material in the openings is plated, for example, by an electrochemical plating process, a currentless plating process, or the like. Resulting vias Vx in the dielectric layer 213 are electrically connected to the conductive pillars or the conductive vias 209, as shown by way of example.In some embodiments, the conductive material, which contains, for example, copper or aluminum, is deposited using a deposition process, and subsequently a plating process and a CMP process are carried out as described above, and for the sake of brevity the associated detailed description is omitted here.

[0041] Now let's move on to... Fig. 14, wherein in some embodiments a dielectric layer 214, comprising conductive structural elements, is produced above the dielectric layer 213. In particular, an electrically conductive layer My, comprising one or more conductive structural elements (e.g., redistribution lines), and vias Vy between the dielectric layer 214 and a dielectric layer 215 are produced. In some embodiments, the redistribution lines are conductive structural elements arranged between different dielectric layers. In some embodiments, the dielectric layer 215 is structured to create openings, and a metallic material is deposited in the openings to produce the redistribution lines.

[0042] Now let's move on to... Fig. 15, wherein in some embodiments a further dielectric layer 216, comprising conductive structural elements, is produced above the dielectric layer 215. In particular, an electrically conductive layer Mz, comprising one or more conductive structural elements (e.g., redistribution lines), and vias Vz between the dielectric layers 215 and 216 are produced. In some embodiments, the width of the conductive structural elements in one or more of the electrically conductive layers Mx, My, and Mz can be equal to or substantially greater than 0.8 µm. In some embodiments, the spacing between adjacent conductive structural elements in one or more of the electrically conductive layers Mx, My, and Mz can be equal to or substantially greater than 0.8 µm. In some embodiments, the height of the vias Vx, Vy, or Vz can be approximately 1.5 µm.

[0043] As illustrated by way of example, in some embodiments the device die 211 is electrically connected to the conductive structural elements of the redistribution lines. In some embodiments, the redistribution lines produced between the dielectric layers are essentially similar in composition and manufacturing process to those of the rear-facing RDL 204, and for the sake of brevity the associated detailed descriptions are omitted here.

[0044] Now let's move on to... Fig. 16, where metallizations are fabricated under the contact bumps (UBMs) 217 ​​for electrical connection to the electrically conductive layer Mz on the dielectric layer 216. Then, external interconnects 218A, 218B, and 218C, configured as input / output pads (I / O pads) and, for example, solder balls, are fabricated on the UBMs 217. In some embodiments, the interconnects 218A, 218B, and 218C are BGA spheres (BGA: Ball Grid Array), C4 contact bumps (C4: Controlled Collapse Chip Interconnect), and the like, arranged on the UBMs 217 and fabricated over the redistribution lines. In some embodiments, the connecting elements 218A, 218B and 218C are used to electrically connect the package 200 to other package components, such as other dies, interposers, package substrates, printed circuit boards, a motherboard and the like.

[0045] In some embodiments, an inspection is carried out at this stage to ensure that the package 200 has been manufactured properly. The package 200 is then detached from the carrier part and turned over. For example, the carrier 201 and, optionally, the adhesive layer 202 can be removed from the package 200. Fig. Figure 17 is a sectional view of the InFO package 200 according to some embodiments of the present invention. As shown in Fig. As shown in Figure 17, in some embodiments the polymer-based layer 203 remains in the resulting package 200 as an insulating and protective layer, but the present invention is not limited thereto. In some embodiments, a ribbon layer is deposited after the removal of the adhesive layer 202. In some embodiments, a laser drilling process is performed to create a recess and expose the redistribution layer bond pads from the rearward RDL 204.

[0046] In various implementations, other packaging technologies can also be used to manufacture the upper package 110 and / or the lower package 120. Possible packaging technologies include, for example, Chip on Wafer on Substrate (CoWoS), Die first Face Down InFO, Die first Face Up InFO, Die last Face Down InFO, and the like. The manufacturing process described in the Fig. Figures 2 to 16, which are shown and described with reference to them, are a simplified example and are not intended to limit the present invention.

[0047] As in Fig. As shown in Figure 17, the RDL structure in package 200 comprises: one or more dielectric layers filled with a thermally conductive dielectric material, such as aluminum nitride, boron nitride, or a combination thereof; and one or more electrically conductive layers. In particular, the electrically conductive layers in the RDL structure can be metal layers (e.g., layers Mx, My, and Mz). In some embodiments, the metal layers contain aluminum, copper, or a combination thereof, but the present invention is not limited thereto. In some embodiments, at least one of the metal layers (e.g., layers Mx, My, and Mz) has a thickness substantially greater than 4 µm (and is, for example, about 4 µm to about 10 µm).

[0048] An upper metal layer (e.g., layer Mz) is adjacent to solder elements (e.g., connecting elements 218A, 218B, and 218C), and an inner metal layer (e.g., layer Mx) is adjacent to the device die 211. An intermediate metal layer (e.g., layer My) is electrically connected to the upper metal layer and the inner metal layer by corresponding vias.

[0049] In some embodiments, the thickness of the upper metal layer is substantially greater than the thickness of the intermediate metal layer, and the thickness of the intermediate metal layer is substantially greater than the thickness of the inner metal layer. For example, in some embodiments, the thickness of the inner metal layer and the one or more redistribution lines in the inner metal layer may be about 2 µm, the thickness of the intermediate metal layer and the one or more redistribution lines in the intermediate metal layer may be about 3 µm, and the thickness of the upper metal layer and the one or more redistribution lines in the upper metal layer may be substantially greater than 4 µm (and, for example, about 6 µm), but the present invention is not limited thereto.

[0050] By providing a relatively thicker and wider upper metal layer for current distribution, the RDL structure can achieve the desired electrical performance as well as heat dissipation. Furthermore, by arranging the thick upper metal layer adjacent to the connecting elements 218A, 218B, and 218C, the effect of ohmic voltage drop, which often causes an increase in delay, can also be reduced.

[0051] Let's return to Fig. 1. After the upper package 110 and the lower package 120 have been manufactured, the upper package 110 can be mounted onto the lower package 120. In some embodiments, a die-bonding process is performed to melt the solder elements 170. By melting the solder elements 170, the upper package 110 and the lower package 120 are electrically connected to each other. As in Fig.As shown in Figure 1, an underfill (or a sealing material, an encapsulation material, or the like) can optionally be inserted or manufactured between the upper package 110 and the lower package 120. The PoP structure can then be mounted onto the printed circuit board 140.

[0052] In some embodiments, one or more thick metal layers (e.g., substantially thicker than or equal to 6 µm) with one or more dielectric layers filled with a thermally conductive dielectric material, such as AlN or h-BN, can also be applied to form the rear RDL structure 128 of the lower package 120 to further improve heat dissipation, but the present invention is not limited thereto. For example, the rear RDL structure 128 can comprise: one or more electrically conductive layers over the mold material, electrically connected to the one or more device dies; and one or more dielectric layers, each arranged on the corresponding one or more electrically conductive layers.As a result, the device dies 112 and 114, which are encapsulated in the mold material 116, are electrically connected to the redistribution layer bond pads 1282 and one or more electrically conductive layers in the rear RDL structure 128 via wire bonds, the RDL structure, vias, contact pads in the upper package substrate 118 and the solder elements 170.

[0053] When the thermally conductive horizontal layer (which may comprise one or more thermally conductive dielectric layers and / or one or more thick metal layers) is used adjacent to the electrical interconnects as the heat dissipation structure, 3DICs conforming to the embodiments described herein can improve the heat dissipation properties of the IC packages by efficiently dissipating the heat generated by the stacked device dies that are trapped in an inner region of a package and eliminating the heat via the electrical interconnects. Accordingly, 3DICs conforming to the embodiments described herein are capable of maintaining the operating temperature of memory dies or chips within a desired range (e.g., from about 80 °C to about 100 °C).The optimized heat dissipation performance not only improves the speed and performance of the chips, but also prevents potential electromigration and reliability problems for the 3DIC packages.

[0054] In some embodiments, a package structure is disclosed comprising: a solder element; a first redistribution layer structure on the solder element, wherein the first redistribution layer structure comprises one or more dielectric layers filled with a thermally conductive dielectric material; and a die mounted on the first redistribution layer structure and electrically connected to it.

[0055] In some embodiments, a semiconductor device is also disclosed comprising: one or more electrical interconnects; a stack of one or more dies; and one or more redistribution layer structures electrically connecting the one or more dies to the one or more electrical interconnects, wherein at least one of the one or more redistribution layer structures has a thermally conductive horizontal layer adjacent to the one or more electrical interconnects.

[0056] In some embodiments, a method is disclosed comprising the following steps: securing a first die in a package; applying a first molding material such that it encloses the first die; producing one or more first electrically conductive layers beneath the first molding material and in electrical connection with the first die; and producing one or more first dielectric layers comprising aluminum nitride, boron nitride, or a combination thereof, wherein one or more of the first dielectric layers is arranged on a corresponding first electrically conductive layer.

Claims

[1] Package structure with: a solder element (130, 218A-C); a front-side redistribution layer structure (122) on the solder element (130, 218A-C), the front-side redistribution layer structure (122) comprising one or more dielectric layers (213-216) filled with a thermally conductive dielectric material, the front-side redistribution layer structure (122) comprising an upper metal layer (Mz) adjacent to the solder element (130, 218A-C), and an intermediate metal layer (My) electrically connected to the upper metal layer (Mz), a thickness of the upper metal layer (Mz) being greater than a thickness of the intermediate metal layer (My); a die (150, 160, 211) mounted on and electrically connected to the front-side redistribution layer structure (122); and a backside redistribution layer structure (128, 204) electrically connected to the die (150, 160, 211) and the frontside redistribution layer structure (122). [2] The package structure of claim 1, wherein the front-side redistribution layer structure (122) comprises one or more electrically conductive layers (Mx, My, Mz), wherein at least one of the one or more electrically conductive layers (Mx, My, Mz) has a thickness greater than 4 µm. [3] The package structure of claim 1 or 2, wherein the front-side redistribution layer structure (122) comprises one or more dielectric layers (213-216) filled with aluminum nitride, boron nitride, or a combination thereof. [4] The package structure of claim 1, wherein the front-side redistribution layer structure (122) further comprises an inner metal layer (Mx) electrically connected to the intermediate metal layer (My) and disposed adjacent to the die (211), the thickness of the intermediate metal layer (My) being greater than a thickness of the inner metal layer (Mx). [5] Package structure according to claim 1 or 4, wherein the upper metal layer (Mz) comprises aluminum, copper or a combination thereof. [6] The package structure according to claim 1, 4 or 5, wherein a thickness of the upper metal layer (Mz) is greater than or equal to 6 µm. [7] The package structure of claim 1, wherein the backside redistribution layer structure (128, 204) comprises one or more dielectric layers filled with the thermally conductive dielectric material. [8] A package structure according to any one of the preceding claims, wherein the thermally conductive dielectric material has a thermal conductivity greater than or equal to 2 W / (m K). [9] Semiconductor device comprising: one or more electrical connecting elements (130, 218A-C); a stack of one or more dies (150, 160, 211); one or more redistribution layer structures (122, 128, 204) electrically connecting the one or more dies (150, 160, 211) to the one or more electrical connection elements (130, 218A-C), wherein at least one of the one or more redistribution layer structures (122, 128, 204) comprises a first thermally conductive horizontal layer with a first redistribution line (Mz) adjacent to the one or more electrical connection elements (130, 218A-C); and a second thermally conductive horizontal layer having a second redistribution line (My) electrically connected to the first redistribution line (Mz), wherein a thickness of the first redistribution line (Mz) is greater than a thickness of the second redistribution line (My), wherein at least one of the thermally conductive horizontal layers further comprises a dielectric layer (213-216) filled with a thermally conductive dielectric material containing aluminum nitride, boron nitride, or a combination thereof. [10] The semiconductor device of claim 9, wherein at least one of the thermally conductive horizontal layers comprises a redistribution line having a thickness greater than 4 µm. [11] The semiconductor device according to any one of claims 9 to 10, wherein the one or more redistribution layer structures (122, 128, 204) comprise a backside redistribution layer structure (128, 204) or a frontside redistribution layer structure (122). [12] Procedure with the following steps: Mounting a first die (150, 160, 211) in a package (100, 200); Applying a first mold material (126, 212) so as to enclose the first die (150, 160, 211); Producing one or more electrical connecting elements (130, 218A-C); Forming a plurality of front-side electrically conductive layers (Mx, My, Mz) under the first mold material (126, 212) and in electrical connection with the first die (150, 160, 211), wherein forming the plurality of front-side electrically conductive layers comprises: Producing a first of the plurality of front-side electrically conductive layers having a first thickness adjacent to the one or more electrical connection elements, and Forming a second of the plurality of front-side electrically conductive layers having a second thickness that is electrically connected to the first of the plurality of front-side electrically conductive layers, the first thickness being greater than the second thickness; Producing one or more first dielectric layers (213-216) containing aluminum nitride, boron nitride, or a combination thereof, wherein one of the one or more first dielectric layers (213-216) is arranged on a corresponding front-side electrically conductive layer (Mz, My, Mx); and Producing one or more backside electrically conductive layers over the first mold material (126, 212) and in electrical connection with the first die (150, 160, 211). [13] The method of claim 12, further comprising: Producing one or more second dielectric layers, wherein one of the one or more second dielectric layers (213-216) is arranged on a corresponding rear electrically conductive layer. [14] The method of claim 12 or 13, wherein forming the plurality of front-side electrically conductive layers comprises: Producing at least one of the plurality of front-side electrically conductive layers with a thickness greater than 4 µm. [15] The method of any one of claims 12 to 14, wherein forming the one or more first dielectric layers (213-216) comprises: Producing at least one of the one or more first dielectric layers (213-216) to be filled with a thermally conductive dielectric material having a thermal conductivity greater than or equal to 2 W / (m K). [16] A method according to any one of claims 12 to 15, further comprising: Producing the one or more electrical connection elements (130, 218A-C) such that they are electrically connected to one or more of the front-side electrically conductive layers.

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