SEMICONDUCTOR PACKAGE AND METHOD FOR ITS MANUFACTURE

Abstract

Semiconductor package with: a first die structure (10) comprising: an interposer (S IP ) comprising a semiconductor substrate (102) and vias (104) penetrating the semiconductor substrate (102), and a first integrated circuit die (105) disposed in the semiconductor substrate (102) of the interposer (S IP ), wherein the first integrated circuit die (105) comprises: an integrated circuit device (1051); an interconnect structure (1052) connected to the integrated circuit device (1051); a dielectric layer (1054) over the integrated circuit device (1051); and Bond pads (1056) arranged in the dielectric layer (1054); a first redistribution structure (13) arranged on the first die structure (10) in physical contact with a top surface (102a) of the semiconductor substrate (102), wherein the bond pads (1056) are electrically connected to the interconnect structure (1052) and the first redistribution structure (13); a second die structure (20) arranged on the first redistribution structure (13), the second die structure (20) comprising: a second integrated circuit die (205, 206) encapsulated in an encapsulation material (208), and conductive pillars (204) penetrating the encapsulation material (208); and a second redistribution structure (23) arranged on the second die structure (20), wherein the first integrated circuit die (105) is electrically connected to the second integrated circuit die (205, 206) via the first redistribution structure (13), the conductive pillars (204) and the second redistribution structure (23).

Description

Background of the inventionField of the invention

[0001] The present invention relates to a semiconductor package and a method for manufacturing the same, and more particularly to a semiconductor package with three-dimensionally stacked integrated circuit dies and a method for manufacturing the same.

[0002] US 10 333 623 B1 describes an optical transceiver. US 2015 / 0 303 174 A1 describes a fan-out semiconductor package. DE 10 2019 109 592 A1 describes a die stack. US 2020 / 0 091 123 A1 describes a semiconductor package. Description of the state of the art

[0003] To ensure miniaturization and multifunctionality of electronic products and communication devices, semiconductor packages are designed with integrated circuit dies with a small size to support high operating speeds and high functionality. The demand for increasing numbers of input / output (I / O) pins and high-performance integrated circuit (IC) dies has led to the development of semiconductor packages. In the manufacture of two-dimensional (2D) ICs, the integrated components are essentially arranged on the surface of a semiconductor wafer. Although drastic improvements in lithography have led to considerable improvements in the fabrication of two-dimensional ICs, there are physical limits to the integration density that can be achieved in two dimensions.

[0004] To further increase integration density, an interposer with vias, such as a silicon interposer with silicon vias (TSVs), has been used in a stacked structure. In a manufacturing process for 2.5D semiconductor packages, several IC dies are first attached side by side to the silicon interposer with TSVs. The IC dies are attached to the silicon interposer using microbumps. The silicon interposer is then attached to a package substrate, and a dicing process is performed. The resulting stacked structure can be mounted on a printed circuit board.

[0005] While existing semiconductor packages are suitable for their intended purposes, they are not yet satisfactory in all respects. For example, die-to-die interconnection in the 2.5D semiconductor package using microbumps does not allow for a sufficient number of I / O ports and / or interconnects. Furthermore, the operating efficiency of 2.5D semiconductor packages must be increased to meet package performance requirements as the demands for manufacturing semiconductor packages with high integration density continue to increase. Therefore, several problems with semiconductor packages in the field of IC semiconductor technology still remain to be overcome. Brief description of the invention

[0006] In some embodiments of the present invention, semiconductor packages are provided. An exemplary embodiment of a semiconductor package includes: a first die structure; a first redistribution structure disposed on the first die structure; a second die structure disposed on the first redistribution structure; and a second redistribution structure disposed on the second die structure. In some embodiments, the first die structure includes an interposer having a semiconductor substrate and vias penetrating the semiconductor substrate. In some embodiments, the first integrated circuit die is disposed within the semiconductor substrate of the interposer.In some embodiments, the second die structure includes a second integrated circuit die encapsulated in an encapsulation material and a plurality of conductive pillars penetrating the encapsulation material. In some embodiments, the first integrated circuit die is electrically connected to the second integrated circuit die via the first redistribution structure, the conductive pillars, and the second redistribution structure.

[0007] In some embodiments of the present invention, a semiconductor package is provided. An exemplary embodiment of a semiconductor package includes: a first die structure; a first redistribution structure disposed on the first die structure; a second die structure disposed on the first redistribution structure; and a second redistribution structure disposed on the second die structure. In some embodiments, the first die structure includes a first integrated circuit die disposed in a semiconductor substrate of an interposer. The interposer has vias penetrating the semiconductor substrate. In some embodiments, the second die structure includes a second integrated circuit die encapsulated in an encapsulation material and a plurality of conductive pillars penetrating the encapsulation material.In some embodiments, top surfaces of bond pads of the first integrated circuit die are in physical contact with the first redistribution structure, and top surfaces of bond pads of the second integrated circuit die are in physical contact with the second redistribution structure.

[0008] In some embodiments of the present invention, a method of manufacturing a semiconductor package is provided. First, a first die structure is provided comprising a first integrated circuit die disposed in a semiconductor substrate of an interposer. The interposer has vias penetrating the semiconductor substrate. The method of manufacturing a semiconductor package further comprises forming a first redistribution structure on the first die structure; and forming a second die structure on the first redistribution structure. In some embodiments, the second die structure comprises a second integrated circuit die encapsulated in an encapsulation material and conductive pillars penetrating the encapsulation material.The method of fabricating a semiconductor package further comprises forming a second redistribution structure on the second die structure. In some embodiments, the first integrated circuit die is electrically connected to the second integrated circuit die via the first redistribution structure, the conductive pillars, and the second redistribution structure.

[0009] Hereinafter, the present invention will be described in more detail using the following embodiments with reference to the accompanying drawings. Short description of the drawings

[0010] The present invention can be better understood by reading the following detailed description and examples with reference to the accompanying drawings. The Fig. 1A to 1F are cross-sectional views of intermediate stages of a method of manufacturing a semiconductor package according to some embodiments of the present invention. Fig. 2 is a cross-sectional view of a semiconductor package according to some embodiments of the present invention. Fig. 3 is a cross-sectional view of a semiconductor package according to some embodiments of the present invention. Detailed description

[0011] The following description is of the best mode contemplated for carrying out the invention. This description is intended to explain the general principles of the invention and is not to be taken in a limiting sense.

[0012] The inventive concept will now be fully described with reference to the accompanying drawings, which show exemplary embodiments of the inventive concept. The advantages and features of the inventive concept and methods for achieving them will become apparent from the following exemplary embodiments, which are described in more detail with reference to the accompanying drawings. It should be noted, however, that the inventive concept is not limited to the following exemplary embodiments, but may be implemented in various forms. Accordingly, the exemplary embodiments are provided only to disclose the inventive concept and enable those skilled in the art to recognize the scope of the inventive concept. Furthermore, the drawings are only schematic and not restrictive. In the drawings, some elements may be enlarged for illustrative purposes and not drawn to scale.The dimensions and relative dimensions do not correspond to the actual dimensions when using the invention.

[0013] The terms used herein are for the purpose of describing particular embodiments only and are not intended to be limiting of the invention. The singular forms "a" and "the" are intended to include the plural forms unless the context clearly indicates otherwise. The term "and / or" as used herein includes all combinations of one or more of the listed associated elements. It is understood that when an element is referred to as being "connected" to or "contacting" another element, the element may be directly connected to or contacting the other element, or intervening elements may be present.

[0014] Likewise, it should be understood that when an element, such as a layer, region, or substrate, is referred to as being disposed "on" another element, the element may be disposed directly on the other element, or there may be intervening elements. In contrast, the term "directly" means that there are no intervening elements. It should be understood that the terms "comprising," "including," and / or "having" as used herein specify the presence of stated structural elements, integers, steps, operations, elements, and / or components, but do not preclude the presence or additional use of one or more other structural elements, integers, steps, operations, elements, components, and / or groups thereof.

[0015] In addition, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to simply describe the relationship of one element or structure to one or more other elements or structures illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation illustrated in the figures. It should be understood that while the terms "first," "second," "third," etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used merely to distinguish one element from another.Thus, a first element in some embodiments could be referred to as a second element in other embodiments without departing from the principles of the present invention. Exemplary embodiments of aspects of the present inventive concept explained and illustrated herein include their complementary counterparts. Throughout the specification, the same or similar reference numbers and letters refer to the same or similar elements.

[0016] Some embodiments of the invention are described below. It should be noted that additional steps may be provided before, during, and / or after the steps described in these embodiments. Some of the described steps may be replaced or omitted in other embodiments. Other elements may be used for the semiconductor package. Some of the elements described below may be replaced or omitted in other embodiments. While some embodiments are discussed with steps performed in a particular order, these steps may also be performed in a different logical order.

[0017] A semiconductor package and a method for manufacturing the same are described below according to some embodiments of the present invention. In some embodiments, a bottom die structure of the semiconductor package includes an interposer, and a first integrated circuit die is disposed in a semiconductor substrate of the interposer. The interposer includes a plurality of vias, e.g., silicon vias (TSVs). An interposer including at least one integrated circuit die may also be referred to as an active TSV interposer. In some embodiments, the active TSV interposer implements a 3D IC (three-dimensional integrated circuit) stack structure in a package instead of a 2.5 ID IC structure using a non-active TSV interposer. The active TSV interposer may include multi-dies.Furthermore, one or more integrated circuit dies in the lower die structure can be electrically connected to one or more integrated circuit dies in an upper die structure through redistribution layers (abbreviated as "RDLs") and conductive pillars penetrating an encapsulation material, without the use of contact bumps. Thus, in some embodiments, a 3D IC stack structure using an active TSV interposer is more flexible than a conventional chip-to-chip or wafer-to-wafer interconnect (e.g., Cu-Cu bonding). Furthermore, in some embodiments of the present invention, the active TSV interposer enables greater flexibility for RDL routing design. A conductive line width and line pitch (L / S) can be reduced to approximately 2.0 µm / 2.0 µm or less, eliminating a bottleneck for package design.Furthermore, in some embodiments, the active TSV interposer and redistribution layers (RDLs) minimize the signal path to increase processing speed, and they also offer the benefits of low power consumption and short latency. Furthermore, in some embodiments, the thermal conductivity of the active TSV interposer, which is made of silicon, is higher than the thermal conductivity of the encapsulation material (e.g., made of a molding compound). The one or more integrated circuit dies arranged in the active silicon TSV interposer have better thermal properties. Therefore, a chip stack connected by the active silicon TSV interposer in the embodiments may be the solution to thermal problems due to the integrated circuit die in the interposer having a silicon fan-out (i.e., the bottom layer of the interposer).

[0018] One of the methods for manufacturing a semiconductor package according to some embodiments of the present invention is described below. It should be noted that the present invention is not limited to the exemplary package structures and their manufacturing methods disclosed herein. The structures and steps described below are intended merely to provide examples for configuring and manufacturing a semiconductor package.

[0019] The Fig. 1A to 1F are cross-sectional views of intermediate stages of a method for manufacturing a semiconductor package according to some embodiments of the present invention. To simplify the illustration, only the structure in a single die region is shown in the drawings. The die region corresponds to a portion of a wafer after dicing the wafer along scribe trenches (e.g., scribe trenches L S in Fig. 1E) in a later process.

[0020] In Fig. 1A, a first die structure 10 is provided. In some embodiments, the first die structure 10 comprises an interposer S IP and a first integrated circuit die 105, which is in the interposer S IP The interposer S IP comprises a semiconductor substrate 102 and a plurality of vias 104 penetrating the semiconductor substrate 102. In some embodiments, the semiconductor substrate 102 is a silicon substrate or a substrate comprising another suitable material.

[0021] In some embodiments, the first integrated circuit die 105 is in the semiconductor substrate 102 of the interposer S IP In some embodiments, which are shown in Fig. 1A, the first integrated circuit die 105 includes an integrated circuit device 1051 and an interconnect structure 1052 on the integrated circuit device 1051, and is connected to the integrated circuit device 1051. The first integrated circuit die 105 further includes a dielectric layer 1054 over the integrated circuit device 1051, for example, arranged on the interconnect structure 1052. The first integrated circuit die 105 further includes a plurality of bond pads 1056 arranged in the dielectric layer 1054 and contacting the interconnect structure 1052. The bond pads 1056 are electrically connected to the integrated circuit device 1051 via the interconnect structure 1052.

[0022] In some embodiments, a top surface 105a of the first integrated circuit die 105 is coplanar with a top surface of the interposer S IP . As in Fig. 1A, a top surface 1056a of the bond pads 1056 and a top surface 1054a of the dielectric layer 1054 are coplanar with a top surface 102a of the semiconductor substrate 102 and top surfaces 104a of the vias 104.

[0023] Additionally, in some embodiments, a backside 105b of the first integrated circuit die 105 is coplanar with a bottom side of the interposer S IP . As in Fig. 1A, a backside 105b of the first integrated circuit die 105 is coplanar with a bottom side 102b of the semiconductor substrate 102 and bottom sides 104b of the vias 104. In the embodiments described above, a top side 13a and a bottom side 13b of a first redistribution structure 13 are planar surfaces.

[0024] In Fig. 1B, the first redistribution structure 13 is formed on the first die structure 10. In one example, the first redistribution structure 13 is provided over the integrated circuit device 1051 of the first integrated circuit die 105. The first redistribution structure 13 may include a plurality of dielectric layers 132 and conductive traces in the dielectric layers 132. The conductive traces may include metal lines 130M and conductive vias 130V connected to the metal lines 130M. Furthermore, in this embodiment, the interconnect structure 1052 and the bond pads 1056 may be collectively referred to as an active portion, providing an active surface of the first integrated circuit die 105 facing the first redistribution structure 13. A fan-out of the first integrated circuit die 105 in the semiconductor substrate 102 can be achieved by the first redistribution structure 13 on the top side of the interposer S IP, the vias 104 in the interposer S IP and the underside of the interposer S IP can be achieved.

[0025] In some embodiments described in Fig. 1B, the metal lines 130M have narrow widths and narrow pitches. In some embodiments, the width of the metal line 130M is about 0.4 µm to about 2 µm, and the pitch of the metal lines 130M is also about 0.4 µm to about 2 µm. Additionally, a conductive material of the metal lines 130M may be a metal such as copper, titanium, tungsten, aluminum, or another suitable material. The dielectric layers 132 may be formed from a photosensitive material such as polybenzoxazole (PBO), a polyimide, benzocyclobutene (BCB), or another suitable material. The dielectric layers 132 may be formed by spin coating, lamination, chemical vapor deposition (CVD), another suitable method, or a combination thereof.

[0026] In some embodiments, the first redistribution structure 13 is in physical contact with the top surface 102a of the semiconductor substrate 102 and the top surfaces 104a of the vias 104 of the interposer S IP . The top surface 102a and the bottom surface 102b are located on opposite sides of the semiconductor substrate 102, and the top surfaces 104a and the bottom surfaces 104b are located on opposite sides of the vias 104.

[0027] In some embodiments, the first redistribution structure 13 completely covers the first die structure 10. As in Fig. 1B, in particular, the entire bottom side 13b of the first redistribution structure 13 is in physical contact with the entire top side 105a of the first integrated circuit die 105 and the entire top side (which is, for example, level with the top sides 102a and 104a) of the interposer S IP the first die structure 10.

[0028] In some embodiments, the first integrated circuit die 105 is electrically connected to the first redistribution structure 13. In particular, the bond pads 1056 of the first integrated circuit die 105 are electrically connected to the conductive lines (such as the metal lines 130M and the conductive vias 130V) of the first redistribution structure 13. As shown in Fig. 1B, the top surfaces 1056a of the bond pads 1056 of the first integrated circuit die 105 are in physical contact with the first redistribution structure 13.

[0029] Then, in some embodiments, a second die structure 20 is fabricated on the first redistribution structure 13, and subsequently a second redistribution structure 23 is fabricated on the second die structure 20. The Fig. 1C and Fig. 1D illustrate one of the exemplary methods for fabricating the second die structure 20 and the second redistribution structure 23 according to some embodiments of the present invention.

[0030] In Fig. 1C, a plurality of conductive pillars 204 are formed on the top surface 13a of the first redistribution structure 13 such that they extend away from the top surface 13a of the first redistribution structure 13. In particular, the conductive pillars 204 are electrically connected to the conductive traces (such as the metal lines 130M and the conductive vias 130V) of the first redistribution structure 13.

[0031] In one example for fabricating the conductive pillars 204, a seed layer is formed on the first redistribution structure 13. The seed layer is a metal layer, which may be a single layer or a composite layer comprising a plurality of sublayers made of different materials. In a specific embodiment, the seed layer comprises a titanium layer and a copper layer over the titanium layer. The seed layer may be formed by physical vapor deposition (PVD) or another suitable method. A photoresist is formed on the seed layer, which is subsequently patterned. The photoresist may be formed by spin coating or another suitable method and may be exposed for patterning. The pattern of the photoresist corresponds to the conductive pillars 204. Patterning creates openings through the photoresist to expose the seed layer.A conductive material is deposited in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be deposited by plating, such as electroplating or electroless plating, or by another suitable method. The conductive material may be a metal such as copper, titanium, tungsten, aluminum, or another suitable material. The photoresist and the portions of the seed layer on which the conductive material has not been deposited are removed. The photoresist may be removed using a suitable stripping process, such as using an oxygen plasma or the like. After the photoresist has been removed, the exposed portions of the seed layer are removed, for example, using a suitable etching process such as wet or dry etching. The remaining portions of the seed layer and the conductive material form the conductive pillars 204.In this embodiment, the conductive pillars 204 are made of copper and may therefore also be referred to as copper pillars.

[0032] Additionally, in some embodiments, each of the conductive pillars 204 has a critical dimension that is larger than that of each of the vias 104 of the interposer S IP As in Fig. 1D, each of the vias 104 of the interposer S IPa first dimension D1 (as its critical dimension), and each of the conductive pillars 204 of the second die structure 20 has a second dimension D2 (as its critical dimension), wherein the second dimension D2 is greater than the first dimension D1. The first dimension D1 and the second dimension D2 may be a diameter of the via 104 and the conductive pillar 204, respectively. In some embodiments, the first dimension D1 is about 10 µm to about 20 µm, and the second dimension D2 is about 100 µm to about 200 µm. The number of input / output terminals (I / O terminals) of the bottom of the interposer S IP is significantly increased by manufacturing the via 104 with a smaller first dimension D1. In addition, the increased number of I / O terminals also contributes to a fan-out of the first integrated circuit die 105 in the interposer S IP at.

[0033] The second die structure 20 may include one or more second integrated circuit dies. In this exemplary embodiment, two second integrated circuit dies 205 and 206 are fabricated for illustrative purposes. However, the number of second integrated circuit dies is not limited here.

[0034] In Fig. 1C, in this exemplary embodiment, the second integrated circuit die 205 includes an integrated circuit device 2051 and an interconnect structure 2052 on the integrated circuit device 2051. The interconnect structure 2052 is connected to the integrated circuit device 2051. The second integrated circuit die 205 further includes a dielectric layer 2054 over the integrated circuit device 2051, for example, on the interconnect structure 2052. The second integrated circuit die 205 further includes a plurality of bond pads 2056 disposed in the dielectric layer 2054 and contacting the interconnect structure 2052. The bond pads 2056 are electrically connected to the integrated circuit device 2051 via the interconnect structure 2052.Similarly, the second integrated circuit die 206 includes an integrated circuit device 2061 and an interconnect structure 2062 on the integrated circuit device 2061. The interconnect structure 2062 is connected to the integrated circuit device 2061. The second integrated circuit die 206 further includes a dielectric layer 2064 over the integrated circuit device 2061, for example, on the interconnect structure 2062. The second integrated circuit die 206 further includes a plurality of bond pads 2066 disposed in the dielectric layer 2064 and contacting the interconnect structure 2062. The bond pads 2066 are electrically connected to the integrated circuit device 2061 via the interconnect structure 2062. The integrated circuit dies 205 and 206 may have the same function or different functions.

[0035] In the Fig. 1C, in this exemplary embodiment, the second integrated circuit dies 205 and 206 are attached to the first redistribution structure 13 by an adhesion layer 145 and 146, respectively. The adhesion layer 145 may have edges flush with edges of the second integrated circuit die 205, and the adhesion layer 146 may have edges flush with edges of the second integrated circuit die 206.

[0036] Then in Fig. 1D, the conductive pillars 204 and the second integrated circuit dies 205 and 206 are encapsulated in an encapsulation material 208. The encapsulation material 208 may be a molding compound that may include a base material and filler particles in the base material. The base material may be a polymer, a resin, an epoxy, or the like. The base material may be a carbon-based polymer. The filler particles may be particles of one or more dielectric materials such as SiO2, Al2O3, silicon dioxide, a compound of iron (Fe), a compound of sodium (Na), or the like, and they may be spherical. The encapsulation material 208 may be applied by compression molding, transfer molding, or another suitable molding technique.In some embodiments, an encapsulation material may be formed over the first redistribution structure 13 such that the conductive pillars 204 and the second integrated circuit dies 205 and 206 are covered or buried. A planarization process, such as a chemical mechanical polishing (CMP) process or a mechanical grinding process, is then performed to planarize the top surfaces of the second integrated circuit dies 205 and 206 and the encapsulation material until the second integrated circuit dies 205 and 206 are exposed. After the planarization process, the encapsulation material 208 has a planar top surface 208a. The top surface 208a of the encapsulation material 208 is coplanar with a top surface 205a of the second integrated circuit die 205 and a top surface 206a of the second integrated circuit die 206.

[0037] In the exemplary embodiment of the present invention, the second integrated circuit dies 205 and 206 and the encapsulation material 208 may be collectively referred to as the second die structure 20.

[0038] In Fig. 1D, a second redistribution structure 23 is also formed on the second die structure 20. The second redistribution structure 23 may include a plurality of dielectric layers 232 and conductive traces (such as a plurality of metal lines 230M and a plurality of conductive vias 230V connected to the metal lines 230M) in the dielectric layers 232. In some embodiments, the second integrated circuit dies 205 and 206 are electrically connected to the conductive traces of the second redistribution structure 23. As shown in Fig. 1D, top surfaces 2056a of the bond pads 2056 of the second integrated circuit die 205 are in physical contact with the second redistribution structure 23. Top surfaces 2066a of the bond pads 2066 of the second integrated circuit die 206 are in physical contact with the second redistribution structure 23. Furthermore, in some embodiments, the top surface 23a and the bottom surface 23b of the second redistribution structure 23 are planar surfaces.

[0039] In this embodiment, the interconnect structure 2052 and the bond pads 2056 of the second integrated circuit die 205 may be collectively referred to as an active portion, providing an active surface of the second integrated circuit die 205. Similarly, the interconnect structure 2062 and the bond pads 2066 of the second integrated circuit die 206 may be collectively referred to as an active portion, providing an active surface of the second integrated circuit die 206. The active surfaces of the second integrated circuit dies 205 and 206 face the second redistribution structure 23 in some embodiments of the present invention.

[0040] Materials and methods for manufacturing the components (such as the dielectric layer 232, the metal lines 230M and the conductive vias 230V) of the second redistribution structure 23 of Fig. 1D may be the same as for similar components (such as the dielectric layer 132, the metal lines 130M and the conductive vias 130V) of the first redistribution structure 13 of Fig. 1B, and they are not repeated here.

[0041] In some embodiments of the present invention, the conductive pillars 204 (such as Cu pillars) of the second die structure 20 are in physical contact with the first redistribution structure 13 and the second redistribution structure 23 to electrically connect the first redistribution structure 13 and the second redistribution structure 23. In some embodiments, the second die structure 20 may be electrically connected to the first die structure 10 via the second redistribution structure 23, the conductive pillars 204, and the first redistribution structure 13. Accordingly, the second integrated circuit dies 205 and 206 may be electrically connected to the first integrated circuit die 105 via the second redistribution structure 23, the conductive pillars 204, and the first redistribution structure 13 without using bumps.

[0042] As in Fig. 1D, in some embodiments, the second redistribution structure 23 is in physical contact with a top surface 20a of the second die structure 20. The first redistribution structure 13 physically contacts a bottom surface 20b of the second die structure 20. The top surface 20a and the bottom surface 20b are located on opposite sides of the second die structure 20. In particular, the second redistribution structure 23 is in physical contact with the top surface 205a of the second integrated circuit die 205, the top surface 206a of the second integrated circuit die 206, the top surface 208a of the encapsulation material 208, and the top surfaces 204a of the conductive pillars 204. As shown in Fig. 1D, in some embodiments, the top surfaces 204a and the bottom surfaces 204b of the conductive pillars 204 are in physical contact with the first redistribution structure 13 and the second redistribution structure 23, respectively.

[0043] In some embodiments, the second redistribution structure 23 completely covers the second integrated circuit die 205. As in Fig. 1D, the entire bottom surface 23b of the second redistribution structure 23 is in physical contact with the entire top surface 205a of the second integrated circuit die 205, with the entire top surface 206a of the second integrated circuit die 206, with the entire top surface 208a of the encapsulation material 208, and with the entire top surfaces 204a of the conductive pillars 204.

[0044] Furthermore, the first integrated circuit die 205 and the second integrated circuit die 206 may have the same function or different functions. The first integrated circuit die 105 and the second interconnect layer circuit dies 205 and 206 may each be: a logic die, e.g., a CPU die (CPU: main processing unit), a GPU die (GPU: graphics processing unit), a SoC die (SoC: system-on-a-chip), an application processor die (AP die), a microcontroller die, etc.; a memory die, e.g., a DRAM die (DRAM: dynamic random access memory), an SRAM die (SRAM: static random access memory), etc.; a power management die, e.g., a power management integrated circuit (PMIC), a radio frequency (RF) die, a sensor die; a MEMS die (MEMS: microelectromechanical system), a signal processing die, e.g., a DSP die (DSP: digital signal processing), a front-end die, e.g., an analog front-end die (AFE die), or the like.

[0045] In some embodiments, the semiconductor substrate 102 of the interposer S IP The first die structure 10 has a first thermal conductivity, and the encapsulation material 208 of the second die structure 20 has a second thermal conductivity, wherein the first thermal conductivity is higher than the second thermal conductivity. Thus, the first integrated circuit die 105 may be a die that generates large amounts of heat during operation because the interposer S IP has better thermal properties than the encapsulation material 208. For example, the first integrated circuit die 105, which is embedded in the semiconductor substrate 102 of the interposer S IP may be a logic die, which generates considerable heat during operation, and the second integrated circuit dies 205 and 206 may each be a memory die, which generates less heat during operation.

[0046] In Fig. 1E, in some embodiments, a conductive interconnect arrangement 40 is fabricated on the underside of the first die structure 10. The conductive interconnect arrangement 40 includes a plurality of conductive interconnect elements 401 formed on the underside of the interposer S IP The conductive connecting elements 401 of the conductive connecting element arrangement 40 are connected to the vias 104 of the interposer S IP the first die structure 10 electrically connected.

[0047] The conductive interconnects may be solder balls, metal pillars, C4 (controlled collapse die interconnect), microbumps, ENEPIG (electroless nickel electroless palladium immersion gold) bumps, or the like. The conductive interconnects 401 may comprise a conductive material such as copper, aluminum, gold, nickel, silver, palladium, tin, solder, or another suitable material, or a combination thereof. In some embodiments, the conductive interconnects 401 are formed by first forming a layer of solder by evaporation, electroplating, printing, solder transfer, ball placement, or another suitable method. After the layer of solder is formed on the structure, a reflow process may be performed to form the material into the desired bump shapes.In another embodiment, the conductive interconnect elements 401 are metal pillars (such as copper pillars) formed by sputtering, printing, electroplating, electroless plating, CVD, or another suitable method. The metal pillars may be solderless and have substantially vertical sidewalls. In some embodiments, a metal capping layer is formed on the metal pillars. The metal capping layer may comprise nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, or another suitable material, or a combination thereof, and may be formed using a plating process. In this embodiment, the conductive interconnect elements 401 are C4 bumps.

[0048] After fabricating the conductive interconnect elements 401, the resulting structure is separated into individual integrated circuit packages. Fig. Figure 1E shows a single integrated circuit package after performing the dicing process. The dicing process is performed by sawing along the scribe trenches L S In the singulation process, an integrated circuit package is separated from adjacent integrated circuit packages. In some embodiments, the singulation process may be performed by dicing, laser ablation, etching, a combination thereof, or another suitable method. The resulting singulated integrated circuit package may then be mounted on a substrate using the conductive interconnect elements 401.

[0049] In Fig. 1F, in some embodiments, a substrate 50 is provided with conductive traces 502, and the resulting structure of Fig. 1E is mounted on the substrate 50 by means of the conductive connecting elements 401. That is, the conductive connecting elements 401 are arranged between the substrate 50 and the first die structure 10. Accordingly, the vias 104 of the interposer S IP the first die structure 10 is electrically connected to the conductor tracks 502 of the substrate 50 by means of the conductive connecting elements 401 of the conductive connecting element arrangement 40.

[0050] Additionally, an underfill layer 42 is formed between the first die structure 10 and the substrate 50. In some embodiments, an underfill material may be distributed into the remaining gaps between the conductive interconnects 401, wherein the underfill material fills the gaps between the first die structure 10 and the substrate 50. The underfill material is then cured using a curing process to form the underfill layer 42. In some further embodiments, the underfill layer 42 may be formed using a capillary flow process or another suitable method after the conductive interconnects 401 have been bonded to the substrate 50.

[0051] As in Fig. 1F, in some embodiments, the first integrated circuit die 105 of the first die structure 10 may be connected via the first redistribution structure 13, the vias 104 of the interposer S IP and the conductive connecting elements 401 of the conductive connecting element arrangement 40 are electrically connected to the substrate 50. The second integrated circuit dies 205 and 206 of the second die structure 20 can be electrically connected via the second redistribution structure 23, the conductive pillars 204, the first redistribution structure 13, the vias 104 of the interposer S IPand the conductive interconnects 401 of the conductive interconnect array 40 are electrically connected to the substrate 50. In some embodiments, the second integrated circuit dies 205 and 206 may be electrically connected to the first integrated circuit die 105 through the second redistribution structure 23, the conductive pillars 204, and the first redistribution structure 13.

[0052] In some embodiments described above, a semiconductor package and a method of manufacturing the same achieve several advantages. In some embodiments, the lower die structure in the semiconductor package includes an interposer S IP and a first integrated circuit die disposed in the semiconductor substrate 102 of the interposer S IP with several vias 104 (TSVs 104). The interposer S IPAn integrated circuit package comprising at least one integrated circuit die may also be referred to as an active TSV interposer. Unlike the conventional 2.5D IC package using a non-active TSV interposer, in some embodiments the active TSV interposer in a package implements a 3D IC stacking package. The active TSV interposer may comprise multiple dies. In some embodiments, heterogeneous integration with multifunctional devices, passive components, or memory may be achieved through a fan-out process of the upper die structure.

[0053] Furthermore, one or more integrated circuit dies in a lower die structure may be electrically connected to one or more integrated circuit dies in an upper die structure through redistribution layers (RDLs) (such as the second redistribution structure 23 and the first redistribution structure 13) and the conductive pillars 204 penetrating the encapsulation material 208, without the use of bumps. Thus, a 3D IC stack structure using an active TSV interposer is more flexible than a conventional chip-on-chip or wafer-on-wafer stack structure (e.g., Cu-Cu bonding). In some embodiments, chip arrangement / layout flexibility may be achieved with a fan-out of the upper die structure or a silicon fan-out of the lower die structure (such as the active TSV interposer).

[0054] Furthermore, in some embodiments of the present invention, the active TSV interposer enables greater flexibility for RDL routing design, and the conductive line width and line pitch (L / S) of the RDLs can be greatly reduced, thereby eliminating a bottleneck for package design. For example, the conductive line width and line pitch (L / S) of the second redistribution structure 23 on the encapsulation material 208 can be reduced to about 2.0 µm / 2.0 µm or less than 2.0 µm / 2.0 µm. In one example, the conductive line width and line pitch (L / S) of the first redistribution structure 13 on a silicon interposer S IP(e.g., semiconductor substrate 102, which is made of silicon) can be reduced to approximately 0.4 µm / 0.4 µm. Furthermore, the die-to-die stack containing the RDL interconnect and the active TSV interposer has a larger number of I / O pins than microbumps in a conventional 2.5D semiconductor package. Accordingly, in some embodiments, the package with the stacked structure containing, for example, the active TSV interposer and the redistribution layers (RDLs) minimizes the signal path to increase processing speed and also offers the benefits of low power consumption and short latency.

[0055] Furthermore, in some embodiments, the TSV interposer, which is made of silicon, has a higher thermal conductivity than the encapsulation material 208 (which is made of a molding compound). Accordingly, one or more integrated circuit dies that generate a lot of heat during operation can be placed in the silicon TSV interposer to achieve better thermal properties.

[0056] In the Fig. Although only one first integrated circuit die 105 is illustrated in FIGS. 1A to 1F, the first die structure 10 may include multiple first integrated circuit dies (e.g., two, three, four, etc.). Fig. Figure 2 is a cross-sectional view of a semiconductor package according to some embodiments of the present invention. The same or similar reference numbers or letters indicate the same or similar elements (such as components or layers) in the Fig. 1A to 1F and 2. For brevity, the materials of the same or similar components / layers and the processes for manufacturing these components / layers are not repeated here.

[0057] In Fig. 2, the first die structure 10, which includes first integrated circuit dies 105 and 106, serves as an example according to an embodiment of the present invention. The components / layers and the processes for manufacturing these components / layers of the first integrated circuit die 105 have been described above and will not be repeated here. The first integrated circuit die 106 may have similar components / layers as the first integrated circuit die 105. It should be noted that the configuration and number of the first integrated circuit dies used in Fig. 2 are for illustrative purposes only and the present invention is not limited thereto.

[0058] In some embodiments, the first integrated circuit die 106 is in the semiconductor substrate 102 of the interposer S IP The first integrated circuit dies 105 and 106 can be inserted through the semiconductor substrate 102 of the interposer S IPbe physically separated from each other. In some embodiments, the first integrated circuit die 106 includes an integrated circuit device 1061 and an interconnect structure 1062 on the integrated circuit device 1061, and is connected to the integrated circuit device 1061. The first integrated circuit die 106 further includes a dielectric layer 1064 over the integrated circuit device 1061, for example, disposed on the interconnect structure 1062. The first integrated circuit die 106 further includes a plurality of bond pads 1066 disposed in the dielectric layer 1064 and contacting the interconnect structure 1062. The bond pads 1066 are electrically connected to the integrated circuit device 1061 via the interconnect structure 1062.Furthermore, in an exemplary embodiment, the interconnect structure 1062 and the bond pads 1066 may be collectively referred to as an active portion that provides an active surface of the first integrated circuit die 106. The active surfaces of the first integrated circuit dies 105 and 106 face the first redistribution structure 13.

[0059] In some embodiments, a top side 106a and a back side 106b of the first integrated circuit die 106 are coplanar with the top and bottom sides of the interposer S IP . As in Fig. 2, the first redistribution structure 13 is formed on the first integrated circuit dies 105 and 106 such that it completely covers them. In particular, the entire bottom surface 13b of the first redistribution structure 13 is in physical contact with the entire top surface 105a of the first integrated circuit die 105, the entire top surface 106a of the first integrated circuit die 106, and the entire top surface of the interposer S IP the first die structure 10.

[0060] In some embodiments, the first integrated circuit die 106 is electrically connected to the first redistribution structure 13. In particular, the bond pads 1066 of the first integrated circuit die 106 are electrically connected to the conductive lines (such as the metal lines 130M and the conductive vias 130V) of the first redistribution structure 13. In the exemplary embodiment shown in Fig. 2, the first integrated circuit die 106 can be connected via the first redistribution structure 13, the vias 104 of the interposer S IP and the conductive connecting elements 401 of the conductive connecting element arrangement 40 are electrically connected to the substrate 50.

[0061] The first integrated circuit dies 105 and 106 may have the same function or different functions. The first integrated circuit dies 105 and 106 and the second integrated circuit dies 205 and 206 may have the same function or different functions. The first integrated circuit die 106 may be: a logic die, e.g., a CPU die (CPU: main processing unit), a GPU die (GPU: graphics processing unit), a SoC die (SoC: system-on-a-chip), an application processor die (AP die), a microcontroller die, etc.; a memory die, e.g., a DRAM die (DRAM: dynamic random access memory), an SRAM die (SRAM: static random access memory), etc.; a power management die, e.g., a power management integrated circuit (PMIC), a radio frequency (RF) die, a sensor die; a MEMS die (MEMS: microelectromechanical system), a signal processing die, e.g., a DSP die (DSP: digital signal processing), a front-end die, e.g.,an analog front-end die (AFE die), or the like.

[0062] In some embodiments, the semiconductor substrate 102 of the interposer S IP of the first die structure 10 has a first thermal conductivity, and the encapsulation material 208 of the second die structure 20 has a second thermal conductivity. The first thermal conductivity is higher than the second thermal conductivity. Thus, the first integrated circuit die 106 may be a die that generates large amounts of heat during operation because the interposer S IP has better thermal properties than the encapsulation material 208.

[0063] Although in the Fig. 1A to 1F and 2, the second die structure 20 is arranged vertically above the first die structure 10 (ie, a TSV interposer having one or more first integrated circuit dies and may also be considered an active TSV interposer), in some embodiments of the present invention, the semiconductor package may include one or more further die structures above the second die structure 20.

[0064] Fig. 3 is a cross-sectional view of a semiconductor package according to some embodiments of the present invention. The same or similar reference numbers or letters indicate the same or similar elements (such as components or layers) in the Fig. 1A to 1F and 3. For brevity, the materials and arrangements of the same or similar components / layers and the processes for fabricating these similar components / layers of the first die structure 10, the first redistribution structure 13, the second die structure 20, and the second redistribution structure 23 are not repeated here.

[0065] In Fig. 3, in some embodiments, a semiconductor package may further include a third die structure 30 over the second die structure 20, for example, arranged on the second redistribution structure 23. The third die structure 30 may include one or more third integrated circuit dies.

[0066] In this exemplary embodiment, which is shown in Fig. 3, the encapsulation material 208 of the second die structure 20 may be referred to as a first encapsulation material 208. The third die structure 30 includes third integrated circuit dies 305 and 306 encapsulated in a second encapsulation material 308.

[0067] The third integrated circuit die 305 may include: an integrated circuit device 3051; an interconnect structure 3052 connected to the integrated circuit device 3051; a dielectric layer 3054 over the integrated circuit device 3051; and a plurality of bond pads 3056 disposed on the dielectric layer 3054. The bond pads 3056 are electrically connected to the integrated circuit device 3051 via the interconnect structure 3052. The third integrated circuit die 306 may include: an integrated circuit device 3061; an interconnect structure 3062 connected to the integrated circuit device 3061; a dielectric layer 3064 over the integrated circuit device 3061; and a plurality of bond pads 3066 disposed on the dielectric layer 3064.The bond pads 3066 are electrically connected to the integrated circuit device 3061 via the interconnect structure 3062. The third integrated circuit dies 305 and 306 may have the same function or different functions.

[0068] In this exemplary embodiment, which is shown in Fig. 3, the conductive pillars 204 of the second die structure 20 may be referred to as first conductive pillars 204. The third die structure 30 further includes second conductive pillars (such as Cu pillars) 304 that penetrate the second encapsulation material 308. Two ends (i.e., the top surfaces 304a and the bottom surfaces 304b) of the second conductive pillars 304 contact the second redistribution structure 23 and a third redistribution structure 33 (described below) above the third die structure 30, respectively. The materials and processes for forming the second conductive pillars 304 of the third die structure 30 may be the same as or similar to the materials and processes for forming the first conductive pillars 204 of the second die structure 20. These details will not be repeated here.

[0069] Additionally, in some embodiments, the semiconductor package further includes a third redistribution structure 33 disposed on the third die structure 30. The third redistribution structure 33 may have a planar top surface 33a and a planar bottom surface 33b. In some embodiments, the third redistribution structure 33 is in physical contact with a top surface 30a of the third die structure 30, and the second redistribution structure 33 is in physical contact with a bottom surface 30b of the third die structure 30.

[0070] In some embodiments, the third redistribution structure 33 includes a plurality of dielectric layers 332 and conductive traces in the dielectric layers 332. The conductive traces may include a plurality of metal lines 330M and a plurality of conductive vias 330V connected to the metal lines 330M, thereby providing an electrical connection function of the third redistribution structure 33.

[0071] In this exemplary embodiment, which is shown in Fig. 3, the third integrated circuit dies 305 and 306 are connected via the third redistribution structure 33, the second conductive pillars 304, the second redistribution structure 23, the first conductive pillars 204, the first redistribution structure 13, the vias 104 of the interposer S IPand the conductive interconnects 401 of the conductive interconnect array 40 are connected to the substrate 50. In some embodiments, the third integrated circuit dies 305 and 306 are electrically connected to the second integrated circuit dies 205 and 206 through the third redistribution structure 33, the second conductive pillars 304, and the second redistribution structure 23 without using bumps. In some embodiments, the third integrated circuit dies 305 and 306 are electrically connected to the first integrated circuit dies 105 and 106 through the third redistribution structure 33, the second conductive pillars 304, the second redistribution structure 23, the conductive pillars 204, and the first redistribution structure 13 without using bumps.

[0072] In some embodiments described above, the semiconductor packages and methods of fabricating them achieve several advantages. In some embodiments, the bottom die structure of the semiconductor package includes an interposer S IP and one or more first integrated circuit dies disposed in a semiconductor substrate 102 of the interposer S IP with multiple vias (TSVs) 104. The interposer S IP, which includes at least one integrated circuit die, may also be referred to as an active TSV interposer. In contrast to the conventional 2.5D IC package that uses a non-active TSV interposer, in some embodiments, the active TSV interposer in one package realizes a 3D IC stack package. The active TSV interposer may include multiple dies. In some embodiments, heterogeneous integration with multifunctional devices, passive components, or memory may be achieved through a fan-out process of the upper die structure.

[0073] Furthermore, one or more integrated circuit dies in a lower die structure can be electrically connected to one or more integrated circuit dies in an upper die structure through the redistribution layers (RDLs) (such as the first redistribution structure 13, the second redistribution structure 23, and the third redistribution structure 33) and the conductive pillars 204 penetrating the encapsulation material 208 (and the conductive pillars 304 penetrating the encapsulation material 308) without the use of contact bumps. Thus, a 3D IC stack structure using an active TSV interposer is more flexible than a conventional chip-on-chip or wafer-on-wafer stack structure (e.g., Cu-Cu bonding). In some embodiments, chip arrangement / layout flexibility may be achieved with a fan-out of the upper die structure or a silicon fan-out of the lower die structure (such as the active TSV interposer).Furthermore, in some embodiments, the active TSV interposer made of silicon has a higher thermal conductivity than the encapsulation material 208 / 308 (made of a molding compound), so that the integrated circuit die disposed in the silicon TSV interposer has better thermal properties.

[0074] Furthermore, in some embodiments of the present invention, the active TSV interposer enables greater flexibility for RDL routing design, and the conductive line width and the line pitch (L / S) of the RDLs can be greatly reduced, thereby eliminating a bottleneck for package design. For example, the conductive line width and the line pitch (L / S) of the RDLs can be reduced to about 2.0 µm / 2.0 µm or less when the RDL is disposed on the encapsulation material 208 / 308, and they can be reduced to about 0.4 µm / 0.4 µm when the RDL is disposed on the interposer S. IPis arranged. Furthermore, the die-to-die stack with the RDL interconnect and the active TSV interposer has a larger number of I / O pins than microbumps in a conventional 2.5D semiconductor package. As described above, in some embodiments, a package with the stack structure including, for example, the active TSV interposer and the RDLs minimizes the signal path to increase processing speed and also offers the benefits of low power consumption and short latency.

[0075] It should be noted that the details of the structures and manufacture of the embodiments are for illustrative purposes only, and the described details of the embodiments are not intended to limit the present invention. It should also be noted that not all embodiments of the invention are illustrated. Modifications and variations may be made without departing from the spirit of the invention in order to meet the requirements of practical application. Thus, there may be other embodiments of the present invention that are not individually illustrated. In addition, the accompanying drawings have been simplified in order to clearly illustrate the embodiments. Sizes and proportions in the drawings may not directly correspond to actual products. Therefore, the specification and drawings are to be regarded as illustrative and not restrictive.

[0076] While the invention has been described by way of examples and preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments. Rather, it is intended to cover various modifications and similar arrangements (which will be apparent to those skilled in the art).

Claims

[1] Semiconductor package with: a first die structure (10) comprising: an interposer (S IP ) comprising a semiconductor substrate (102) and vias (104) penetrating the semiconductor substrate (102), and a first integrated circuit die (105) disposed in the semiconductor substrate (102) of the interposer (S IP ), wherein the first integrated circuit die (105) comprises: an integrated circuit device (1051); an interconnect structure (1052) connected to the integrated circuit device (1051); a dielectric layer (1054) over the integrated circuit device (1051); and Bond pads (1056) arranged in the dielectric layer (1054); a first redistribution structure (13) arranged on the first die structure (10) in physical contact with a top surface (102a) of the semiconductor substrate (102), wherein the bond pads (1056) are electrically connected to the interconnect structure (1052) and the first redistribution structure (13); a second die structure (20) arranged on the first redistribution structure (13), the second die structure (20) comprising: a second integrated circuit die (205, 206) encapsulated in an encapsulation material (208), and conductive pillars (204) penetrating the encapsulation material (208); and a second redistribution structure (23) arranged on the second die structure (20), wherein the first integrated circuit die (105) is electrically connected to the second integrated circuit die (205, 206) via the first redistribution structure (13), the conductive pillars (204) and the second redistribution structure (23). [2] The semiconductor package of claim 1, wherein an active surface of the first integrated circuit die (105) faces the first redistribution structure (13) and an active surface of the second integrated circuit die (205, 206) faces the second redistribution structure (23). [3] Semiconductor package according to claim 1 or 2, wherein a backside (105b) of the first integrated circuit die (105) coplanar with a bottom side (102b) of the semiconductor substrate (102) of the interposer (S IP ), and / or a backside of the second integrated circuit die (205, 206) is arranged on the first redistribution structure (13), and / or the conductive pillars (204) of the second die structure (20) are in physical contact with the first redistribution structure (13) and the second redistribution structure (23), and / or the vias (104) of the first die structure (10) physically contact the first redistribution structure (13). [4] A semiconductor package according to any one of the preceding claims, wherein the second integrated circuit die (205, 206) comprises: an integrated circuit device (2051, 2061); an interconnect structure (2052, 2062) connected to the integrated circuit device (2051, 2061); a dielectric layer (2054, 2064) over the integrated circuit device (2051, 2061); and Bond pads (2056, 2066) arranged in the dielectric layer (2054, 2064), wherein the bond pads (2056, 2066) are electrically connected to the interconnect structure (2052, 2062) and the first redistribution structure (13). [5] Semiconductor package according to claim 4, wherein Top sides (1056a, 2056a, 2066a) of the bond pads (1056, 2056, 2066) are coplanar with a top side (1054a, 2054a, 2064a) of the dielectric layer (1054, 2054, 2064), and / or Top sides (1056) of the bond pads (1056) of the first integrated circuit die (105) physically contact the first redistribution structure (13), and / or Top sides (2056a, 2066a) of the bond pads (2056, 2066) of the second integrated circuit die (205, 206) physically contact the second redistribution structure (23). [6] A semiconductor package according to any one of the preceding claims, further comprising: conductive connecting elements (401) which are arranged on a bottom side of the interposer (S IP ) are arranged; and an underfill layer (42) disposed between the interposer (S IP ) and a substrate (50) with conductor tracks (502), wherein the conductive connecting elements (401) are arranged between the substrate (50) and the first die structure (10). [7] Semiconductor package according to claim 6, wherein the vias (104) of the interposer (S IP ) of the first die structure (10) are electrically connected to the conductor tracks (502) by the conductive connecting elements (401). [8] A semiconductor package according to any one of the preceding claims, wherein a backside of the second integrated circuit die (205, 206) is coplanar with a bottom side of the encapsulation material (208) and the bottom side of the encapsulation material (208) physically contacts a top side of the first redistribution structure (13). [9] Semiconductor package according to one of the preceding claims, wherein the semiconductor substrate (102) of the interposer (S IP ) of the first die structure (10) has a first thermal conductivity and the encapsulation material (208) of the second die structure (20) has a second thermal conductivity, wherein the first thermal conductivity is higher than the second thermal conductivity. [10] Semiconductor package according to one of the preceding claims, wherein the first die structure (10) further comprises a third integrated circuit die (106) disposed in the semiconductor substrate (102) of the interposer (S IP ), wherein the first redistribution structure (13) is arranged on the third integrated circuit die (106) and is electrically connected thereto, and the second die structure (20) further comprises a fourth integrated circuit die (205, 206) encapsulated in the encapsulation material (208), wherein the second redistribution structure (23) is disposed on and electrically connected to the fourth integrated circuit die (205, 206). [11] A semiconductor package according to any one of the preceding claims, further comprising: A third die structure (305, 306) arranged on the second redistribution structure (23); and a third redistribution structure (33) arranged on the third die structure (305, 306). [12] Semiconductor package according to claim 11, wherein the encapsulation material (208) of the second die structure (20) is referred to as a first encapsulation material (208) and the conductive pillars (204) of the second die structure (20) are referred to as first conductive pillars (204), and the third die structure (305, 306) has the following: a third integrated circuit die (3051, 3061) encapsulated in a second encapsulation material (308); and second conductive pillars (304) penetrating the second encapsulation material (308), wherein the third integrated circuit die (305, 306) is electrically connected to the first conductive pillars (204) via the third redistribution structure (33), the second conductive pillars (304) and the second redistribution structure (23). [13] Semiconductor package according to one of the preceding claims, wherein each of the vias (104) of the interposer (S IP ) has a first dimension and each of the conductive pillars (204) of the second die structure (20) has a second dimension, the second dimension being greater than the first dimension. [14] Semiconductor package with: a first die structure (10) comprising a first integrated circuit die (105) disposed in a semiconductor substrate (102) of an interposer (S IP ), wherein the interposer (S IP ) vias (104) penetrating the semiconductor substrate (102), wherein the first integrated circuit die (105) comprises: an integrated circuit device (1051); an interconnect structure (1052) connected to the integrated circuit device (1051); a dielectric layer (1054) over the integrated circuit device (1051); and Bond pads (1056) arranged in the dielectric layer (1054); a first redistribution structure (13) arranged on the first die structure (10) in physical contact with a top surface (102a) of the semiconductor substrate (102), wherein the bond pads (1056) are electrically connected to the interconnect structure (1052) and the first redistribution structure (13); a second die structure (20) disposed on the first redistribution structure (13), the second die structure (20) comprising a second integrated circuit die (205, 206) encapsulated in an encapsulation material (208) and conductive pillars (204) penetrating the encapsulation material (208); and a second redistribution structure (23) arranged on the second die structure (20), wherein top surfaces of bond pads (1056) of the first integrated circuit die (105) physically contact the first redistribution structure (13) and top surfaces of bond pads (1056) of the second integrated circuit die (205, 206) physically contact the second redistribution structure (23). [15] The semiconductor package of claim 14, wherein the second integrated circuit die (205, 206) is electrically connected to the first integrated circuit die (105) via the second redistribution structure (23), the conductive pillars (204) and the first redistribution structure (13). [16] Semiconductor package according to claim 14 or 15, wherein a backside of the second integrated circuit die (205, 206) physically contacts the first redistribution structure (13), and / or a backside of the second integrated circuit die (205, 206) is coplanar with a bottom side of the encapsulation material (208), and / or a bottom side of the first redistribution structure (13) comprises the first integrated circuit die (105) and the interposer (S IP ) of the first die structure (10) is completely covered and physically contacted, and / or a backside (105b) of the first integrated circuit die (105) coplanar with a bottom side (102b) of the semiconductor substrate (102) of the interposer (S IP ), and / or the second redistribution structure (23) completely covers and physically contacts the second integrated circuit die (205, 206) and the encapsulation material (208) of the second die structure (20). [17] A method for manufacturing a semiconductor package comprising the following steps: Providing a first die structure (10) comprising a first integrated circuit die (105) disposed in a semiconductor substrate (102) of an interposer (S IP ), wherein the interposer (S IP ) vias (104) penetrating the semiconductor substrate (102), and wherein the first integrated circuit die (105) comprises: an integrated circuit device (1051); an interconnect structure (1052) connected to the integrated circuit device (1051); a dielectric layer (1054) over the integrated circuit device (1051); and Bond pads (1056) arranged in the dielectric layer (1054), the bond pads (1056) being electrically connected to the interconnect structure (1052); Producing a first redistribution structure (13) on the first die structure (10) in physical contact with a top surface (102a) of the semiconductor substrate (102) such that the bond pads (1056) are electrically connected to the first redistribution structure (13); Producing a second die structure (20) on the first redistribution structure (13), the second die structure (20) comprising a second integrated circuit die (205, 206) encapsulated in an encapsulation material (208) and conductive pillars (204) penetrating the encapsulation material (208); and Producing a second redistribution structure (23) on the second die structure (20), wherein the first integrated circuit die (105) is electrically connected to the second integrated circuit die (205, 206) via the first redistribution structure (13), the conductive pillars (204) and the second redistribution structure (23). [18] The method of manufacturing a semiconductor package of claim 17, wherein top surfaces of the bond pads (1056) of the first integrated circuit die (105) physically contact the first redistribution structure (13) and top surfaces of bond pads (1056) of the second integrated circuit die (205, 206) physically contact the second redistribution structure (23). [19] A method of manufacturing a semiconductor package according to claim 17 or 18, wherein manufacturing the second die structure (20) comprises: Attaching the second integrated circuit die (205, 206) to a top surface (13a) of the first redistribution structure (13); Producing conductive pillars (204) on the top side (13a) of the first redistribution structure (13); and Encapsulating the conductive pillars (204) and the second integrated circuit die (205, 206) using the encapsulation material (208). [20] A method of manufacturing a semiconductor package according to claim 19, wherein a top surface (208a) of the encapsulation material (208) is coplanar with top surfaces (204a) of the conductive pillars (204) and a top surface (205a, 205b) of the second integrated circuit die (205, 206). [21] A method of manufacturing a semiconductor package according to any one of claims 17 to 20, further comprising: Producing conductive connecting elements (401) on a bottom side of the interposer (S IP ), thereby obtaining a resulting structure; and Performing dicing on the resulting structure to produce individual integrated circuit packages. [22] A method of manufacturing a semiconductor package according to claim 21, wherein the method, after performing the singulation, further comprises: Providing a substrate (50) with conductive tracks (502); Bonding the conductive connecting elements (401) to the substrate (50), wherein the conductive connecting elements (401) are connected to the conductor tracks (502) of the substrate (50) and the vias (104) of the interposer (S IP ) are electrically connected; and Producing an underfill layer (42) between the interposer (S IP ) and the substrate (50), wherein the conductive connecting elements (401) are encapsulated in the underfill layer (42). [23] A method of manufacturing a semiconductor package according to claim 22, wherein the conductive interconnect elements (401) are bonded to a top surface of the substrate (50) and ball grid array interconnect elements are bonded to a bottom surface of the substrate (50).

Images