Hybrid power converter

Abstract

A power converter configured to receive an input voltage (VIN) at an input node of the power converter and to generate an output voltage (VOUT) at an output node of the power converter, wherein the power converter comprises: - an inductor (L) coupled between an inductor node (VLX) and the output node, - a first flying capacitor (CFLY1) coupled between a first capacitor node (VCX1) and a second capacitor node (VCY), - a second flying capacitor (CFLY2) coupled between a third capacitor node (VCX2) and the inductor node (VLX), - a first switching element (S1) coupled between the input node and the first capacitor node (VCX1), - a second switching element (S2) coupled between the first capacitor node (VCX1) and a reference potential (PGND), - a third switching element (S3),that is coupled between the second capacitor node (VCY) and a reference potential (PGND), a fourth switching element (S4) that is coupled between the second capacitor node (VCY) and the third capacitor node (VCX2), a fifth switching element (Fig. 11: S5) that is coupled between the first capacitor node (VCX1) and the third capacitor node (VCX2), and a sixth switching element (Fig. 11: S6) that is coupled between the inductor node (VLX) and the second capacitor node (VCY), wherein the power converter is configured to charge the second flying capacitor (CFLY2) by establishing a current path from the input node via the first switching element (S1), via the fifth switching element (Fig. 12: S5), via the second flying capacitor (CFLY2), via the sixth switching element (S6) and via the third switching element (S3) to a reference potential (PGND), and wherein the power converter is configured toto discharge the first flying capacitor (CFLY1) and the second flying capacitor (CFLY2) by switching off the fifth switching element (Fig. 14: S5) and by establishing a current path from a reference potential (PGND) via the second switching element (S2), via the first flying capacitor (CFLY1), via the fourth switching element (S4), via the second flying capacitor (CFLY2) and via the inductor (L) to the output node of the power converter.

Description

Technical FieldThe present document relates to power converters. More particularly, the present document relates to improved hybrid buck-boost power converters for generating negative output voltages that may be implemented using transistors with low rated voltages (i.e., low maximum drain-source voltages).BackgroundThere is an increased need for highly efficient regulated power converters in a number of market segments, such as solid-state drives (SSDs), computing devices, charging devices, wearable power management integrated circuits (PMICs), and display power supply integrated circuits. In particular, it is highly desirable to develop power converters with higher efficiency and smaller area.The present document relates to "hybrid" buck-boost power converters, i.e., power converters having both flying capacitors and inductors. Buck-boost power converters typically include a plurality of switching elements for controlling current paths within the power converter. Depending on the application scenario, the regulated output voltage may be higher, lower, or equal to the input voltage of the power converter. To this end, the switching behavior of the switching elements is adjusted such that the power converter operates in a buck mode, a boost mode, or a buck-boost mode.Each switching element is characterized by a rated voltage, i.e., a maximum voltage that the switching element can withstand without being damaged. When field effect transistors (FETs) are used as switching elements, the rated voltage may correspond to the maximum voltage that may be applied across the non-conductive drain-source channel of an FET. In other words, when the FET is off, the rated voltage may be considered the maximum voltage that may be applied across the drain-source channel of the transistor that does not result in current flow across the drain-source channel or current flow that is below a predefined threshold current. The use of FETs with reduced rated voltage enables to reduce the area of the switching elements for a given target resistance Ron, since FETs with lower rated voltage typically have a smaller specific resistance and a smaller gate capacitance. It is therefore desirable to develop a new hybrid power converter that enables the use of low rated voltage FETs.The present document addresses the technical problems mentioned above. In particular, the present document addresses the technical problem of providing novel hybrid buck-boost power converters that can be implemented with FETs with a reduced rated voltage and / or size.U.S. Pat. No. 10,027,223 B1 describes charging switched capacitors in power converter circuits. US 2005 / 0 047 180 A1 describes a voltage step-up circuit and a corresponding method. DE 693 19 512 T2 describes a voltage converter circuit of the charge pump type.SummaryIn one aspect, a power converter is provided. The power converter may be configured to receive an input voltage at an input node of the power converter and generate an output voltage at an output node of the power converter. In particular, the power converter may be configured to generate a negative output voltage at the output node. In other words, the power converter may be configured to generate an output voltage having opposite polarity with respect to the input voltage. The power converter may include an inductor coupled between an inductor node and the output node. The power converter may include a first flying capacitor coupled between a first capacitor node and a second capacitor node. The power converter may include a second flying capacitor coupled between a third capacitor node and the inductor node. The power converter may include a first switching element coupled between the input node and the first capacitor node. The power converter may include a fifth switching element coupled between the first capacitor node and the third capacitor node.Instead of coupling the fifth switching element between the input node and the third capacitor node, the fifth switching element may be indirectly coupled to the input node via the first switching element. In other words, the fifth switching element may be coupled in series with the first switching element between the input node and the third capacitor node. In other words, the fifth switching element may be coupled in parallel to the first flying capacitor. On the one hand, when the fifth switching element is turned on, an input current can be provided to the fifth switching element via the first switching element. On the other hand, when the fifth switching element is off, the maximum voltage across the fifth switching element may be reduced because the fifth switching element is not pulled to the input voltage, but only to the voltage at the first capacitor node. The voltage at the first capacitor node may in turn be drawn to the reference potential when the fifth switching element is off, thereby reducing the required nominal voltage for the fifth switching element.The flying capacitors may be passive electronic components that can store electrical energy in an electric field. Each flying capacitor may have a first terminal and a second terminal. The flying capacitors are referred to as "flying" because, in various modes of operation of the described power converter, one of the terminals may be a fixed terminal driven to a defined voltage level and the voltage at the other terminal may "fly" to a voltage that depends on the voltage at the fixed terminal and the voltage at the flying capacitor. The voltage across the flying capacitor may in turn depend on the stored charge quantity and on the capacitance of the flying capacitor. The terminals of the flying capacitors need not be permanently connected to the input voltage or a reference potential (such as ground).In this document, the term "reference potential" is intended to be understood in the broadest sense. In particular, the reference potential is not limited to ground, i.e. a reference potential with a direct physical connection to ground or a voltage of 0 V. Rather, the term "reference potential" may refer to any reference point to and from which electrical currents may flow or from which voltages may be measured. Moreover, it should be noted that the reference potentials mentioned in this document need not necessarily relate to the same physical contact. Instead, the reference potentials mentioned in this document may refer to different physical contacts, although reference is made to "the" reference potential for simplicity of illustration.The switching elements described in this document may be implemented with suitable devices, such as metal-oxide-semiconductor field effect transistors (MOSFETs), insulated-gate bipolar transistors (IGBTs), MOS gate thyristors, or other suitable power devices.The switching elements may be implemented using identical transistors or different transistors. For example, some switching elements may be p-type MOSFETs and other switching elements may be implemented using n-type MOSFETs. Each switching element may have a control terminal (e.g., a gate) to which a corresponding control signal or drive voltage may be applied to turn on (i.e., close) the switching element or turn off (i.e., open) the switching element.Generally, the power converter may be configured to operate in one of at least three different modes of operation: a buck mode of operation, a boost mode of operation, or a buck-boost mode of operation. Depending on the selected operating mode, the power converter may be configured to switch between a first, a second, and a third operating phase, as described in more detail below. As already mentioned, the output voltage of the power converter may be negative. In the buck operating mode, the absolute value of the regulated output voltage may be lower than the absolute value of the input voltage and the output current may be higher than the input current. In the boost mode of operation, the absolute value of the regulated output voltage may be higher than the absolute value of the input voltage and the output current may be lower than the input current. Finally, in the buck-boost mode of operation, the absolute value of the regulated output voltage may be higher or lower than the absolute value of the input voltage. The absolute value of the regulated output voltage may also be equal to the absolute value of the input voltage.The power converter may be configured to charge the second flying capacitor by establishing a current path from the input node to a reference potential via the first switching element, the fifth switching element, and the second flying capacitor. Thus, the power converter may be configured to turn on the fifth switching element to charge the second flying capacitor.The power converter may be configured to discharge the first flying capacitor and the second flying capacitor by turning off the fifth switching element and by establishing a current path from a reference potential to the output node of the power converter via the first flying capacitor, the second flying capacitor, and the inductor.The power converter may further include a second switching element coupled between the first capacitor node and a reference potential. The power converter may further include a third switching element coupled between the second capacitor node and a reference potential. The power converter may further include a fourth switching element coupled between the second capacitor node and the third capacitor node. The power converter may further include a sixth switching element coupled between the inductor node and a reference potential. Alternatively, the power converter may further include a sixth switching element coupled between the inductor node and the second capacitor node.The power converter may be configured to establish a first current path from the input node to a reference potential via the first switching element and via the first flying capacitor during a first operating phase. In other words, during the first operating phase, the power converter may be configured to charge the first flying capacitor to the input voltage. The power converter may be configured to establish a second current path from the input node to the reference potential via the first switching element, the fifth switching element, and the second flying capacitor during the first operating phase. In other words, during the first phase of operation, the power converter may be configured to charge the second flying capacitor to the input voltage. The power converter may be configured to establish a third current path from the reference potential via the inductor to the output node of the power converter during the first operating phase.The power converter may be configured to establish a first current path from the input node to a reference potential via the first switching element and via the first flying capacitor during a second operating phase. The power converter may be configured to establish a second current path from the reference potential via the second flying capacitor and via the inductor to the output node of the power converter during the second operating phase.Finally, the power converter may be configured to establish a current path from a reference potential via the first flying capacitor, via the second flying capacitor, and via the inductor to the output node of the power converter during a third operating phase.In another aspect, another power converter is provided. The power converter may be configured to receive an input voltage at an input node of the power converter and generate an output voltage at an output node of the power converter. The power converter may include an inductor coupled between an inductor node and the output node. The power converter may include a first flying capacitor coupled between a first capacitor node and a second capacitor node. The power converter may include a second flying capacitor coupled between a third capacitor node and the inductor node. The power converter may include a first switching element coupled between the input node and the first capacitor node. The power converter may include a sixth switching element coupled between the second capacitor node and the inductor node.Instead of coupling the sixth switching element between a reference potential and the inductor node, the sixth switching element may be indirectly coupled to the reference potential via the second capacitor node. In other words, the sixth switching element may be coupled in parallel to the second flying capacitor, limiting the voltage across the sixth switching element. On the one hand, when the sixth switching element is turned on, a current may flow through the sixth switching element to charge the second flying capacitor. On the other hand, when the sixth switching element is off, the maximum voltage across the sixth switching element may be reduced because the sixth switching element is not drawn to the reference potential, but only to the voltage at the second capacitor node. The voltage at the second capacitor node may be drawn to a negative input voltage when the sixth switching element is off, wherein the voltage at the inductor node may be as low as twice the negative input voltage. In this way, the required rated voltage for the sixth switching element can be reduced.The power converter may be configured to charge the second flying capacitor by establishing a current path from the input node to a reference potential via the second flying capacitor and via the sixth switching element. Thus, the power converter may be configured to turn on the sixth switching element to charge the second flying capacitor.The power converter may be configured to discharge the first flying capacitor and the second flying capacitor by turning off the sixth switching element and establishing a current path from a reference potential to the output node of the power converter via the first flying capacitor, the second flying capacitor, and the inductor.The power converter may further include a second switching element coupled between the first capacitor node and a reference potential. The power converter may further include a third switching element coupled between the second capacitor node and a reference potential. The power converter may further include a fourth switching element coupled between the second capacitor node and the third capacitor node. The power converter may further include a fifth switching element coupled between the third capacitor node and the input node of the power converter. Alternatively, the power converter may further include a fifth switching element coupled between the third capacitor node and the first capacitor node.The power converter may be configured to establish a first current path from the input node to a reference potential via the first switching element and via the first flying capacitor during a first operating phase. In other words, during the first phase of operation, the power converter may be configured to charge the first flying capacitor to the input voltage. The power converter may be configured to establish a second current path from the input node to the reference potential via the second flying capacitor and via the sixth switching element during the first operating phase. In other words, during the first phase of operation, the power converter may be configured to charge the second flying capacitor to the input voltage. The power converter may be configured to establish a third current path from the reference potential via the sixth switching element and via the inductor to the output node of the power converter during the first operating phase.The power converter may be configured to establish a first current path from the input node to a reference potential via the first flying capacitor during a second operating phase. The power converter may be configured to establish a second current path from the reference potential via the second flying capacitor and via the inductor to the output node of the power converter during the second operating phase.The power converter may be configured to establish a current path from a reference potential to the output node of the power converter via the first flying capacitor, the second flying capacitor, and the inductor during a third operating phase.According to another aspect, a method of operating a power converter is presented. The method may include steps corresponding to the functional features of a power converter described herein. In particular, the power converter may include an inductor coupled between an inductor node and an output node of the power converter, a first flying capacitor coupled between a first capacitor node and a second capacitor node, and a second flying capacitor coupled between a third capacitor and the inductor node. The method may include charging the second flying capacitor by establishing a charging current via a switching element, the switching element coupled between the first capacitor node and the third capacitor node. The method may include discharging the second flying capacitor by generating a discharge current when the switching element is turned off. The step of establishing the charging current may further comprise establishing the charging current from the input node to the reference potential via another switching element, via the switching element, and via the second flying capacitor. Further, the step of establishing the discharge current may further comprise establishing the discharge current from a reference potential to the output node of the power converter via the first flying capacitor, via the second flying capacitor, and via the inductor.According to another aspect, a further method of operating a power converter is presented. Again, the power converter may include an inductor coupled between an inductor node and an output node of the power converter, a first flying capacitor coupled between a first capacitor node and a second capacitor node, and a second flying capacitor coupled between a third capacitor node and the inductor node. The method may include charging the second flying capacitor by establishing a charging current via a switching element, the switching element coupled between the second capacitor node and the inductor node. The method may include discharging the second flying capacitor by generating a discharge current when the switching element is turned off. The step of establishing the charging current may further comprise establishing the charging current from the input node to the reference potential via the second flying capacitor, via the switching element, and via another switching element. The step of establishing the discharge current may further comprise establishing the discharge current from a reference potential to the output node of the power converter via the first flying capacitor, the second flying capacitor, and the inductor.It should be noted that the methods and systems, including their preferred embodiments, as set forth herein may be used alone or in combination with the other methods and systems disclosed herein. In addition, the features set forth in the context of a system are also applicable to a corresponding method. Moreover, all aspects of the methods and systems set forth in the present document may be combined in any combination. In particular, the features of the claims can be combined with one another as desired.In the present document, the term "couple" or "coupled" refers to elements that are in electrical communication with each other, either directly connected, e.g., via wires, or in some other manner.Brief Description of the FiguresThe present invention is illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like reference numerals refer to similar or identical elements, and in which FIG. 1 shows an example inverting buck converter; FIG. 2 shows a buck magnetization phase for the inverting buck converter of FIG. 1 ; FIG. 3 shows a buck-demagnetization phase for the inverting buck converter of FIG. 1 ; FIG. 4 shows rated voltages for the FET devices for the inverting buck converter of FIG. 1 ; FIG. 5 shows an exemplary two-stage converter based on the converter in FIG. 1, which enables V OUT= -2 V IN( ideally); FIG. 6 shows rated voltages of the FET devices of the converter of FIG. 5 ; FIG. 7 shows a buck magnetization phase for the transducer of FIG. 5 ; FIG. 8 shows a buck-demagnetization phase / boost magnetization phase / buck-boost bypass phase for the converter of FIG. 5 ; FIG. 9 shows a step-up demagnetization phase / step-down step-up demagnetization phase for the converter of FIG. 5 ; FIG. 10 shows a timing diagram of the converter of FIG. 5 operating in the boost mode; FIG. 11 shows an example hybrid buck-boost inverting topology; FIG. 12 shows a buck magnetization phase of the converter of FIG. 11 ; FIG. 13 shows a buck-demagnetization phase / boost magnetization phase / buck-boost bypass phase for the converter of FIG. 11 ; FIG. 14 shows a step-up demagnetization phase / step-down step-up demagnetization phase for the converter of FIG. 11 ; FIG. 15 shows an example low rated inverting hybrid buck-boost variant for switch S 5; FIG. 16 shows an example low rated inverting hybrid buck-boost variant for switch S 6; FIG. 17 shows a buck magnetization phase of the converter of FIG. 15 ; FIG. 18 shows a buck-demagnetization phase / boost magnetization phase / buck-boost bypass phase for the converter of FIG. 15 ; FIG. 19 shows a step-up demagnetization phase / step-down step-up demagnetization phase for the converter of FIG. 15 ; FIG. 20 shows a buck magnetization phase of the converter of FIG. 16 ; FIG. 21 shows a buck-demagnetization phase / boost magnetization phase / buck-boost bypass phase for the converter of FIG. 16 ; FIG. 22 shows a step-up demagnetization phase / step-down step-up demagnetization phase for the converter of FIG. 16 ; and FIG. 23 shows rated voltages of the FET devices of the hybrid converter of FIG. 11 and its variants of FIGS. 15 and 16.Detailed DescriptionThe inverting buck topology shown in FIG. 1 is used to generate a negative output voltage V OUT down to -V IN( theoretical). In mobile applications, the input voltage V IN is typically generated by a single-cell Li-Ion battery.FIGS. 2 and 3 show example switching phases of the converter of FIG. 1 The converter passes through the phases of FIGS. 2 and 3 It is equivalent to a conventional buck DC-DC converter: the voltage swing at the LX node is filtered by a second-order low pass filter (inductor L and output capacitor C OUT) and the output voltage V OUT is taken from the non-grounded terminal of the output capacitor C OUT.The operation of the inverting buck converter is:• Magnetization phase shown in Fig. 2. The switches S1 and S3 are closed, thus the voltage of the nodes VCX and VLX goes to V IN and VLX, respectively. PGND. The flying capacitor C FLY is charged to V IN( theoretical), while the inductor is magnetized with a current sharing V OUT / L. The switch S2 is open and thus experiences a drain-source voltage V DS= VIN.• Demagnetization phase shown in Fig. 3. The only switch involved is S2: once this FET is turned on, the voltage of node VLX goes below PGND (i.e. to -V IN). The flying capacitor C FLY is discharged to the output node while the inductor is de-magnetized with -(V IN+ V OUT) / L current sharing. The switches S 1, S 3 are open, thus experience a drain-source voltage V DS= V IN in absolute value.The relationship between V IN and V OUT is expressed by V OUT / V IN= -(1- D), where D denotes a duty cycle with D ∈ [0,1]. The rated voltage (i.e., the maximum V DS- voltage V DS_max) for the FET devices is summarized in the table in FIG. 4.The converter cell shown in FIG. 1 may be replicated to achieve a lower output voltage V OUT. FIG. 5 shows how a theoretical V OUT= - 2 V IN can be achieved by connecting two of the basic cells forming the transducer shown in FIG. 1 in series.The converter shown in FIG. 5 passes through the phases of FIGS. 7, 8 and 9 It is equivalent to a conventional buck DC-DC converter: the voltage swing at the LX node (PGND, - VIN or -2VIN) is filtered by a second-order low-pass filter (inductor L and output capacitor COUT). The output voltage VOUTis taken from the non-grounded terminal of the output capacitor COUT, as for the converter in FIG. 1.The converter of FIG. 5 operates in the following switching phases:• The step-down operation passes through the magnetization phase shown in Fig. 7 and the step-down demagnetization phase in Fig. 8.During the magnetization phase, both flying capacitors are charged again to V IN via switches S 1, S 3 and S 5, S 6. Switch S6 connects the VLX node to PGND. The inductor is magnetized with a current sharing V OUT / L. During the demagnetization phase, the flying capacitor C FLY1 is "parked", i.e. connected between the input voltage V IN and PGND, via the switches S1 and S3. When parked, the capacitor voltage may be held constant at V IN. The second flying capacitor C FLY2 is connected between PGND using switches S3 and S4 and the VLX node. In this configuration, the voltage at the VLX node becomes negative. The inductor is demagnetized with (-V IN- V OUT) / L current sharing.• A first possible step-up operation passes through the magnetization phase shown in Figure 8 and the demagnetization phase in Figure 9. During the magnetization phase, the flying capacitor C is parked FLY1 i.e. connected between V IN and PGND via the switches S1 and S3. The second flying capacitor C FLY2 is connected between PGND using switches S3 and S4 and the VLX node. In this configuration, the voltage at the VLX node becomes negative. The inductor is magnetized with (-V IN- V OUT) / L current sharing. During the up-demagnetization phase, C FLY1 and C FLY2 are connected in series via the switch S 4. Node VCX1 is connected to PGND via switch S2, therefore node VLX goes to -2V IN.It should be noted that the switches S 5, S 6 both experience the voltage V DS= 2 V IN in this phase. The inductor is demagnetized with (-2V IN- V OUT) / L current sharing.The relationship between V IN and V OUT for this up mode is expressed by V OUT / V IN= -(2- D) with D ∈ [0,1]. It should also be noted that the first possible step-up operation described above cannot be maintained indefinitely, since the flying capacitor C FLY2( must be recharged by a step-down magnetization phase).Time-independent boost operation goes through the phases of FIG. 7 - recharging the flying capacitors - and FIG. 9 - VLX nodes at -2V IN. This configuration increases the voltage ripple across the coil with respect to the boost mode described above.The relationship between V IN and V OUT for the time-independent up mode is expressed by: V OUT / V IN= -2(1- D) with D ∈ [0,1].• The down-up operation goes through the phases of Figures 7, 8 and 9.The rated voltage (maximum V DS- voltage V DS_max) for the FET devices of the converter in FIG. 5 is summarized in the table in FIG. 6. A higher rated voltage results in a higher R SP for the device and, in turn, a larger silicon area for a given target on-resistance R ON of an FET device.The converter of Figure 5 has a basic limitation of the output voltage V OUT during its boost operation - assuming the time-independent boost mode cycling between phase in Figures 7 and 9. The timing diagram of the converter during boost operation is shown in FIG. 10. The limitation is a result of the charge conservation across both flying capacitors C FLY: the charge removed from the capacitors during the up-demagnetization phase (see FIG. 9 ) is added during the up-magnetization phase (see FIG. 7 ). Therefore, the current I FLY, which flows in C FLY1 during the demagnetization phase, can be expressed as (by applying the charge conservation principle): I OUT / I CFLY1= D / (1-D), with D ∈[0,1]. The latter equation indicates that duty cycle D should be limited to 0.5 to keep I CFLY1< I OUT. For values of D>0.5, the current I CFLY experiences a steep rise. Similar considerations apply to the second flying capacitor CFLY 2.Another inverting hybrid converter is shown in FIG. 11. In this topology, switch S 5 connects node VCX 2 (also referred to as third capacitor node) to input node VIN via switch S 1. Here, the switch S 5 is disposed between the node VCX 1 (also referred to as a first capacitor node) and the node VCX 2 (i.e., the third capacitor node). Further, the switch S 6 connects the VLX node (also referred to as inductor node) to PGND via the switch S 3. Here, the switch S 6 is disposed between the node VLX (i.e., the inductor node) and the node VCY (also referred to as a second capacitor node). These connections enable low rated voltage FETs for both S5 and S6 because they are parallel to a flying capacitor when turned off during converter operation. In other words, in FIG. 11, the VLX terminal and the VCY terminal may be short-circuited during a buck magnetization phase, and the VCX1 terminal and the VCX2 terminal may be short-circuited during a buck magnetization phase.FIGS. 12, 13 and 14 show the switching phases of the inverting hybrid converter of FIG. 11 The operation of this topology is similar to the operation of the converter in FIG. 5 ; however, lower rated voltage devices are used for switches S 5 and S 6:• The buck operation goes through phases of Figures 12 and 13, It is equivalent to a conventional inverting buck with only the second flying capacitor CFLY2. The switches S 1, S 5, S 3, S 6 are closed so that both flying capacitors C FLY are connected between VIN and PGND during recharging of the flying capacitor.• An up-mode passes through phases of FIGS. 13 and 14. As described above, this mode cannot be maintained indefinitely because the flying capacitor C FLY2 must be recharged (e.g., by the down-magnetization phase illustrated in FIG. 12 ). A time-independent boost mode operation cycles through phases of FIGS. 12 and 14. During the boost mode of operation, none of the instantiated switches are subject to a drain-source voltage V DS > V IN.• The down-up operation goes through phases of Figs. 12, 13 and 14 and may comprise all switches.Two variants can be derived from the topology of Figure 11: On the one hand, Figure 15 shows a low rated hybrid buck-boost variant for the switch S5. This switch operates in parallel with the first flying capacitor C FLY1, thus enabling a reduced rated voltage. On the other hand, FIG. 16 shows a low rated voltage hybrid buck-boost variant for the switch S 6. This switch operates in parallel with the second flying capacitor C FLY2, thus enabling a reduced rated voltage.The hybrid buck-boost variants described above take advantage of the operating phases described above for the architecture of FIG. 11. FIGS. 17 to 22 show the corresponding switching phases. In particular, FIG. 17 shows a buck magnetization phase (also referred to as a first operating phase) of the converter of FIG. 15. FIG. 18 shows a buck demagnetization phase / boost magnetization phase / buck-boost bypass phase (also referred to as a second operating phase) for the converter of FIG. 15. FIG. 19 shows a boost demagnetization phase / buck-boost demagnetization phase (also referred to as a third operating phase) for the converter of FIG. 15. FIG. 20 shows a buck magnetization phase (also referred to as a first operating phase) of the converter of FIG. 16. FIG. 21 shows a buck demagnetization phase / boost magnetization phase / buck-boost bypass phase (also referred to as a second operating phase) for Figure 22 shows a boost demagnetization phase / buck-boost demagnetization phase (also referred to as third operating phase) for the converter of Figure 16.The rated voltages for the devices of these hybrid converter topologies are given in the table in FIG. 23. In particular, FIG. 23 compares the rated voltage for the topology of FIG. 11 (new hybrid), the topology of FIG. 15 (variant LV S 5) and the topology of FIG. 16 (variant LV S 6). Due to the reduced V DS_max for the switches, lower R SP devices may be used to reduce the silicon area while achieving a higher V OUT for a given I OUT and V IN or a lower V IN for a given V OUT and I OUT.The hybrid buck-boost architectures of FIG. 11 and their variants of FIGS. 15 and 16 have the same trade-off explained for the architecture of FIG. 5 between V OUT_max and I OUT due to charge conservation at both flying capacitors C FLY. However, the use of devices designed for a lower V DS- voltage allows to reduce the IR drop developed at switches S 5 and S 6 while occupying less silicon area. The hybrid topology illustrated and its variant may also be used at either the input or output pins of a DC-DC converter to double the input voltage and the output voltage, respectively.In summary, the topologies of this invention occupy less area for the same target impedance of the power FETs, while achieving a higher V OUT for a given load current. Alternatively, lower V IN- voltages could be achieved for the same V OUT- voltages and load current I OUT.An additional advantage of the proposed invention over conventional inverting buck-boost architectures is fast response and low noise output voltage. The topologies presented require a coil connected between the LX node and the output node, such as a buck converter. It allows current to be supplied to the output during both the magnetization and demagnetization phases of the coil, i.e. no "right half-plane zero (RHPHZ)" affects the frequency response of the architectures presented. Moreover, the LC filter at the output of the converter drastically reduces the high frequency noise that would otherwise be generated by intermittent current supply to the output.It should be noted that the description and drawings merely represent the principles of the proposed methods and systems. Those skilled in the art will be able to implement various arrangements which, although not explicitly described or shown herein, embody the principles of the invention and are incorporated in its spirit and scope. Moreover, all examples and embodiments set forth herein are intended in principle for purposes of illustration only to aid the reader in understanding the principles of the proposed methods and systems. Moreover, all statements herein providing principles, aspects, and embodiments of the invention, as well as specific examples thereof, are intended to encompass equivalents thereof.

Claims

A power converter configured to receive an input voltage (V IN) at an input node of the power converter and generate an output voltage (V OUT) at an output node of the power converter, the power converter comprising: - an inductor (L) coupled between an inductor node (VLX) and the output node, - a first flying capacitor (C FLY1), coupled between a first capacitor node (VCX1) and a second capacitor node (VYC), - a second flying capacitor (C FLY2), coupled between a third capacitor node (VCX2) and the inductor node (VLX), a first switching element (S1) coupled between the input node and the first capacitor node (VCX1), a second switching element (S2) coupled between the first capacitor node (VCX1) and a reference potential (PGND), a third switching element (S3) coupled between the second capacitor node (VCY) and a reference potential (PGND), a fourth switching element (S4) coupled between the second capacitor node (VCY) and the third capacitor node (VCX2), a fifth switching element (FIG. 11 : S 5) coupled between the first capacitor node (VCX1) and the third capacitor node (VCX2), and a sixth switching element (FIG. 11: S 6) coupled between the inductor node (VLX) and the second capacitor node (VCY), wherein the power converter is configured to charge the second flying capacitor (C FLY2) to a reference potential (PGND) by establishing a current path from the input node via the first switching element (S 1), via the fifth switching element (FIG. 12: S 5), via the second flying capacitor (C FLY2), via the sixth switching element (S 6) and via the third switching element (S 3), and wherein the power converter is configured to, the first flying capacitor (C FLY1) and the second flying capacitor (C FLY2) by switching off the fifth switching element (FIG. 14 : S 5), and by establishing a current path from a reference potential (PGND) to the output node of the power converter via the second switching element (S 2), via the first flying capacitor (C FLY1), via the fourth switching element (S 4), via the second flying capacitor (C FLY2) and via the inductor (L).The power converter of claim 1, further comprising a sixth switching element coupled between the inductor node (VLX) and a reference potential (PGND).The power converter according to any of the preceding claims, wherein the power converter is configured to establish a first current path from the input node via the first switching element (S1) and via the first flying capacitor (C FLY1) to a reference potential (PGND) during a first operating phase.The power converter of claim 3, wherein the power converter is configured to establish a second current path from the input node via the first switching element (S1), via the fifth switching element (FIG. 11 : S 5), and via the second flying capacitor (C FLY2) to the reference potential (PGND) during the first operating phase.The power converter of claim 3 or 4, wherein the power converter is configured to establish a third current path from the reference potential (PGND) via the inductor (L) to the output node of the power converter during the first operating phase.The power converter according to any of the preceding claims, wherein the power converter is configured to establish a first current path from the input node via the first switching element (S1) and via the first flying capacitor (C FLY1) to the reference potential (PGND) during a second operating phase.The power converter of claim 6, wherein the power converter is configured to establish a second current path from the reference potential (PGND), via the second flying capacitor (C FLY2) and via the inductor (L), to the output node of the power converter during the second operating phase.The power converter of any preceding claim, wherein the power converter is configured to establish a current path from a reference potential (PGND) via the first flying capacitor (C FLY1), via the second flying capacitor (C FLY2) and via the inductor (L) to the output node of the power converter during a third phase of operation.A power converter configured to receive an input voltage (V IN) at an input node of the power converter and generate an output voltage (V OUT) at an output node of the power converter, the power converter comprising: - an inductor (L) coupled between an inductor node (VLX) and the output node, - a first flying capacitor (C FLY1), coupled between a first capacitor node (VCX1) and a second capacitor node (VYC), - a second flying capacitor (C FLY2), coupled between a third capacitor node (VCX2) and the inductor node (VLX), a first switching element (S1) coupled between the input node and the first capacitor node (VCX1), a second switching element (S2) coupled between the first capacitor node (VCX1) and a reference potential (PGND), a fourth switching element (S4) coupled between the second capacitor node (VYC) and the third capacitor node (VCX2), a fifth switching element coupled between (S5) the third capacitor node (VCX2) and the input node, and a sixth switching element coupled between the second capacitor node (VYC) and the inductor node (VLX), the power converter being configured to, charging the second flying capacitor (C FLY2) to a reference potential (PGND) by establishing a current path from the input node, via the first switching element (FIG. 17:S 1 ), via the fifth switching element (FIG. 17:S 5 ), via the second flying capacitor (C FLY2) and via the sixth switching element (FIG. 17:S 6 ), and wherein the power converter is configured to, the first flying capacitor (C FLY1) and the second flying capacitor (C FLY2) by turning off the sixth switching element (FIG. 19:S 6), and by establishing a current path from a reference potential (PGND) to the output node of the power converter via the first flying capacitor (C FLY1), via the second switching element (FIG. 19:S 2), via the fourth switching element (FIG. 19:S 4), via the second flying capacitor (C FLY2) and via the inductor (L).The power converter of claim 9, wherein the power converter is configured to establish a first current path from the input node via the first switching element (S1) and via the first flying capacitor (C FLY1) to a reference potential (PGND) during a first operating phase.The power converter of claim 10, wherein the power converter is configured to establish a second current path from the input node to the reference potential (PGND) via the second flying capacitor (C FLY2) and the sixth switching element during the first operating phase.The power converter of claim 10 or 11, wherein the power converter is configured to establish a third current path from the reference potential (PGND) via the sixth switching element and via the inductor (L) to the output node of the power converter during the first operating phase.The power converter of any of claims 9 to 12, wherein the power converter is configured to establish a first current path from the input node via the first flying capacitor (C FLY1) to a reference potential (PGND) during a second phase of operation.The power converter of claim 13, wherein the power converter is configured to establish a second current path from the reference potential (PGND), via the second flying capacitor (C FLY2) and via the inductor (L), to the output node of the power converter during the second operating phase.The power converter of any of claims 9 to 14, wherein the power converter is configured to establish a current path from a reference potential (PGND) via the first flying capacitor (C FLY1) via the second flying capacitor (C FLY2) and via the inductor (L) to the output node of the power converter during a third operating phase.A method of operating a power converter, the power converter comprising an inductor (L) coupled between an inductor node (VLX) and an output node of the power converter, a first flying capacitor (C FLY1) coupled between a first capacitor node (VCX1) and a second capacitor node (VYC), and a second flying capacitor (C FLY2), coupled between a third capacitor node (VCX2) and the inductor node (VLX), a first coupled switching element (S1) coupled between an input node and the first capacitor node (VCX1), a second coupled switching element (S2) coupled between the first capacitor node (VCX1) and a reference potential (PGND), a third coupled switching element (S3) between the second capacitor node (VCY) and a reference potential (PGND), a fourth coupled switching element (S4) between the second capacitor node (VCY) and the third capacitor node (VCX2), a fifth coupled switching element (S5) between the first capacitor node (VCX1) and the third capacitor node (VCX2), and a sixth coupled switching element (S6) between the inductor node (VLX) and the second capacitor node (VCY), the method comprising: charging the second flying capacitor (C FLY2) by establishing a charging current from the input node via the first switching element (S1), via the fifth switching element (S5:Fig. 14), via the second flying capacitor (C FLY2), via the sixth switching element (S6) and via the third switching element (S3) to a reference potential (PGND), - discharging the second flying capacitor (C FLY2) by establishing a discharge current when the switching element (Fig. 14:S5) is switched off, and - establishing the discharge current from a reference potential (PGND), via the second switching element (S2), via the first flying capacitor (C FLY1), via the fourth switching element (S4), via the second flying capacitor (C FLY2) and via the inductor (L) to the output node of the power converter.A method of operating a power converter, the power converter comprising an inductor (L) coupled between an inductor node (VLX) and an output node of the power converter, a first flying capacitor (C FLY1) coupled between a first capacitor node (VCX1) and a second capacitor node (VYC), and a second flying capacitor (C FLY2) coupled between a third capacitor node (VCX2) and the inductor node (VLX), a first coupled switching element (S1) coupled between the input node and the first capacitor node (VCX1), a second coupled switching element (S2) coupled between the first capacitor node (VCX1) and a reference potential (PGND), a fourth coupled switching element (S4) between the second capacitor node (VCX) and the third capacitor node (VCX2), a fifth coupled switching element (S5) between the first capacitor node (VCX1) and the third capacitor node (VCX2), and a sixth coupled switching element (S6) between the inductor node (VLX) and the second capacitor node (VCX), the method comprising: - charging the second flying capacitor (C FLY2) by establishing a charging current from the input node via the first switching element (FIG. 17:S 1), via the fifth switching element (FIG. 17:S 5), across the second flying capacitor (C FLY2) and across the sixth switching element (FIG. 17:S 6) to a reference potential (PGND), and / or - discharging the second flying capacitor (C FLY2) by establishing a discharge current when the sixth switching element (FIG. 19:S 6) is switched off, - establishing the discharge current from a reference potential (PGND) via the first flying capacitor (C FLY1), via the second switching element (FIG. 19:S 2), via the fourth switching element (FIG. 19:S 4), via the second flying capacitor (C FLY2) and via the inductor (L) to the output node of the power converter.

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