Novel integrated charge pump driving circuit and power integrated circuit

Abstract

The embodiment of the invention provides a novel integrated charge pump driving circuit and a power integrated circuit, and relates to the technical field of driving circuits, the circuit comprises a front signal processing circuit and a main charge pump and driving circuit; the front signal processing circuit receives a driving logic signal input by the system, preprocesses the driving logic signal and outputs a low-voltage control signal, a first high-voltage control signal and a second high-voltage control signal; and the main charge pump and drive circuit is connected with the output end of the front signal processing circuit, receives the low-voltage control signal, the first high-voltage control signal and the second high-voltage control signal, and processes and outputs a gate drive signal. The circuit provided by the invention can continuously output high-quality gate driving signals, hundred percent duty ratio driving is realized, only dynamic power consumption of the charge pump exists in the whole driving scheme, and the efficiency is higher.

Description

Technical Field

[0001] The present application relates to the technical field of drive circuits, and in particular to a novel integrated charge pump drive circuit and a power integrated circuit. Background Art

[0002] With the trend of electronic circuit integration and miniaturization, the drive circuit, as a key module of power integrated circuits, is constantly pursuing smaller area, more comprehensive functions, and higher performance indicators. Most power integrated circuits use N-type metal oxide semiconductor field effect transistors as power tubes, which have smaller area and stronger current driving capability than P-type power tubes, but correspondingly require high-quality gate drive signals that are higher than the power supply voltage; secondly, for drive applications in small battery-powered scenarios, taking the step-down switching power supply as an example, a 100% duty cycle drive function is usually required to provide faster transient performance and a wider power level output range. At the same time, considering the cost and power density, it is also necessary to achieve low-cost integration of the bootstrap capacitor in the drive circuit.

[0003] Traditional gate drive circuits require the use of level conversion circuits plus multiple drive buffer stages. Since the high power rail of the buffer stage is the bootstrap capacitor voltage, and the drive transistor is a P-type transistor, the size must be large. In order to ensure the quality of the drive signal, not only a very large bootstrap capacitor is required, which makes the cost too high to be integrated, but also increases additional losses, affecting the drive efficiency. In addition, the external bootstrap capacitor has a large loss and requires a minimum off time for the system to charge, so it is impossible to achieve a 100% duty cycle drive function. Summary of the invention

[0004] The embodiments of the present application provide a novel integrated charge pump drive circuit and power integrated circuit to solve the problems of poor drive efficiency, the need for large bootstrap capacitors that are difficult to integrate, and the inability to achieve 100% duty cycle drive function in traditional gate drive circuits.

[0005] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by the practice of the present application.

[0006] According to a first aspect of an embodiment of the present application, a novel integrated charge pump driving circuit is provided, comprising: a front-end signal processing circuit and a main charge pump and driving circuit;

[0007] The pre-signal processing circuit receives the system input drive logic signal for pre-processing and outputs a low voltage control signal, a first high voltage control signal and a second high voltage control signal;

[0008] The main charge pump and driving circuit is connected to the output end of the front signal processing circuit, receives the low voltage control signal, the first high voltage control signal and the second high voltage control signal, and processes and outputs a gate driving signal;

[0009] Wherein, when the system input drive logic signal is at a high level, the low voltage control signal outputs a low level, the first high voltage control signal outputs a low level, the second high voltage control signal outputs a low level, and the gate drive signal outputs a high level;

[0010] When the system input drive logic signal is at a low level, the low voltage control signal outputs a high level, the first high voltage control signal outputs a high level, the second high voltage control signal outputs a high level, and the gate drive signal outputs a low level.

[0011] In some embodiments of the present application, based on the aforementioned scheme, the pre-signal processing circuit includes: a 100% mode trigger circuit, an oscillator, a first logic gate, a second logic gate, a first-stage charge pump, and a level shift circuit based on the charge pump;

[0012] The oscillator is connected to the first input terminal of the first logic gate;

[0013] The 100% mode trigger circuit is connected to the second input terminal of the first logic gate;

[0014] The output terminal of the first logic gate is connected to the second input terminal of the second logic gate;

[0015] The first input terminal of the second logic gate receives the system input drive logic signal;

[0016] The first output terminal of the second logic gate outputs the low voltage control signal;

[0017] The second output end of the second logic gate is connected to the first-stage charge pump, and the first-stage charge pump outputs the first high-voltage control signal;

[0018] The third output terminal of the second logic gate is connected to the charge pump-based level shift circuit, and the charge pump-based level shift circuit outputs the second high-voltage control signal.

[0019] In some embodiments of the present application, based on the above scheme, the main charge pump and driving circuit include: a main charge pump, a second-stage charge pump, a pre-charging circuit, a first high-voltage switch circuit, a second high-voltage switch circuit, a delayed self-locking switch circuit, a first transistor, and a low-side driver;

[0020] The input end of the main charge pump is connected to the pre-signal processing circuit to receive the low voltage control signal, the first high voltage control signal and the second high voltage control signal; the first output end of the main charge pump is connected to the input end of the first high voltage switch circuit, and the second output end is connected to the input end of the second high voltage switch;

[0021] A first output terminal of the first high-voltage switch circuit is connected to the low-side driver, and a second output terminal is connected to the drain of the first transistor;

[0022] The first output terminal of the second high-voltage switch circuit is connected to the first input terminal of the second-stage charge pump, and the second output terminal is connected to the drain of the first transistor;

[0023] The second input end of the second-stage charge pump is connected to the front-end signal processing circuit to receive the low-voltage control signal, the first high-voltage control signal and the second high-voltage control signal, and the output end of the second-stage charge pump is connected to the input end of the delay self-locking switch circuit;

[0024] The output end of the time-delay self-locking switch circuit is connected to the drain of the first transistor;

[0025] The gate of the first transistor receives the low voltage control signal, and the source is grounded;

[0026] The input end of the pre-charging circuit receives the second high-voltage control signal, and the output end is connected to the low-side driver and then grounded;

[0027] The output end of the pre-charging circuit is also connected to the first output end of the first high-voltage switching circuit.

[0028] In some embodiments of the present application, based on the above solution, the first high-voltage switch circuit includes: a second transistor, a third transistor and a first diode;

[0029] The drain of the second transistor is connected to the first output terminal of the main charge pump;

[0030] The gate of the second transistor is connected to the gate of the third transistor, and the source of the second transistor is connected to the source of the third transistor and then connected to the drain of the first transistor;

[0031] The first diode is connected in parallel with the gate and source of the second transistor;

[0032] The gate of the third transistor is connected to the output end of the pre-charging circuit and then connected to the low-side driver.

[0033] In some embodiments of the present application, based on the above solution, the second high-voltage switch circuit includes: a fourth transistor, a second diode and a resistor;

[0034] The drain of the fourth transistor is connected to the second output terminal of the main charge pump, the source is connected to the second diode and the second-stage charge pump respectively, and the gate is connected to the drain of the first transistor;

[0035] The second diode is connected to the resistor and then connected to the gate of the fourth transistor.

[0036] In some embodiments of the present application, based on the aforementioned solution, the time-delay self-locking switch circuit includes: a fifth transistor and a time-delay circuit;

[0037] The drain of the fifth transistor is connected to the drain of the first transistor, and the source is connected to the output end of the second-stage charge pump;

[0038] One end of the delay circuit is connected to the source of the fifth transistor, and the other end is connected to the gate of the fifth transistor.

[0039] According to a second aspect of an embodiment of the present application, a power integrated circuit is provided, comprising the novel integrated charge pump drive circuit as described in the first aspect.

[0040] The beneficial effects of this application are as follows:

[0041] The circuit provided in the present application can continuously output high-quality gate drive signals and achieve 100% duty cycle drive. In the entire drive scheme, only the dynamic power consumption of the charge pump exists, which is more efficient.

[0042] The circuit proposed in this application can continuously output high-quality gate drive signals and achieve 100% duty cycle drive.

[0043] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0045] Figure 1 A schematic structural diagram of a novel integrated charge pump gate drive circuit according to an embodiment of the present application is shown;

[0046] Figure 2 A schematic diagram of the structure of a front-end signal processing circuit according to an embodiment of the present application is shown;

[0047] Figure 3 A schematic structural diagram of a main charge pump and a driving circuit according to an embodiment of the present application is shown;

[0048] Figure 4 A schematic diagram of the timing sequence of key driving signals according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0049] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more comprehensive and complete and fully convey the concept of the example embodiments to those skilled in the art.

[0050] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present application. However, those skilled in the art will appreciate that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, known methods, devices, realizations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0051] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the objects used in this way can be interchanged where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those shown or described.

[0052] In order to make the purpose, technical solution and advantages of the present invention clearer, the technical solution in the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiment of the present invention. Obviously, the described embodiment is only a part of the embodiment of the present invention, not all the embodiments. Based on the embodiment of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0053] Some embodiments of the present application will be described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments may be combined with each other.

[0054] In view of the shortcomings of the traditional gate drive circuit, such as poor driving efficiency, the need for a large bootstrap capacitor that is difficult to integrate, and the inability to achieve a 100% duty cycle driving function, this application proposes a new integrated charge pump gate drive circuit, see Figure 1 , shows a structural schematic diagram of a new integrated charge pump gate drive circuit according to an embodiment of the present application.

[0055] Specifically, the circuit includes: a pre-signal processing circuit and a main charge pump and drive circuit;

[0056] The pre-signal processing circuit receives the system input drive logic signal for pre-processing and outputs a low voltage control signal, a first high voltage control signal and a second high voltage control signal;

[0057] The main charge pump and driving circuit is connected to the output end of the front signal processing circuit, receives the low voltage control signal, the first high voltage control signal and the second high voltage control signal, and processes and outputs a gate driving signal;

[0058] Wherein, when the system input drive logic signal is at a high level, the low voltage control signal outputs a low level, the first high voltage control signal outputs a low level, the second high voltage control signal outputs a low level, and the gate drive signal outputs a high level;

[0059] When the system input drive logic signal is at a low level, the low voltage control signal outputs a high level, the first high voltage control signal outputs a high level, the second high voltage control signal outputs a high level, and the gate drive signal outputs a low level.

[0060] like Figure 1 As shown, the system input drives the logic signal V CTL When it is high level, the main charge pump and drive circuit output high level gate drive signal V Drive ; V CTL If it is low level, the opposite is true.

[0061] For example, when the system input driving logic signal V CTL When it is at a low level, the low voltage domain control signal V1 is output as high, the first high voltage control signal V2 is output as 2VCC (twice VCC), and the second high voltage control signal V3 is output as HVCC.

[0062] When the system input of the pre-signal processing circuit drives the logic signal V CTL When it is at a high level, the low voltage domain control signal V1 is output as low, the first high voltage control signal V2 is output as VCC, and the second high voltage control signal V3 is output as HVCC-5V.

[0063] The high level of the first high-voltage control signal V2 is 2VCC, and the low level is VCC; the high level of the second high-voltage control signal V3 is HVCC, and the low level is HVCC-5V.

[0064] It should be noted that the VCC described in the embodiments of the present application is a low-voltage domain power rail, the HVCC is a high-voltage domain power rail, and the GND is the ground.

[0065] See also Figure 2 , showing a structural schematic diagram of a front-end signal processing circuit.

[0066] like Figure 2 As shown, in some feasible embodiments, based on the above scheme, the front signal processing circuit includes: a 100% mode trigger circuit, an oscillator, a first logic gate, a second logic gate, a first-stage charge pump and a level shift circuit based on the charge pump;

[0067] The oscillator is connected to the first input terminal of the first logic gate;

[0068] The 100% mode trigger circuit is connected to the second input terminal of the first logic gate;

[0069] The output terminal of the first logic gate is connected to the second input terminal of the second logic gate;

[0070] The first input terminal of the second logic gate receives the system input drive logic signal;

[0071] The first output terminal of the second logic gate outputs the low voltage control signal;

[0072] The second output end of the second logic gate is connected to the first-stage charge pump, and the first-stage charge pump outputs the first high-voltage control signal;

[0073] The third output terminal of the second logic gate is connected to the charge pump-based level shift circuit, and the charge pump-based level shift circuit outputs the second high-voltage control signal.

[0074] It should be noted that both the first and second logic gates operate in a low voltage domain, and the power supply voltage is VCC.

[0075] It should be noted that the working principle of the pre-signal processing circuit is as follows:

[0076] When the system input drives the logic signal V CTLWhen the 100% mode trigger circuit outputs a low level, the first logic gate NAND1 outputs a high level, the low-voltage domain control signal V1 is flipped to a low level, the first-stage charge pump outputs the first high-voltage control signal V2 flipped to VCC, and the level shift circuit based on the charge pump outputs the second high-voltage control signal V3 flipped to HVCC-5V; similarly, when the system inputs the driving logic signal V CTL When flipping from a high level to a low level, the low voltage domain control signal V1 outputs a high level, the first high voltage control signal V2 outputs 2VCC, and the second high voltage control signal V3 outputs HVCC.

[0077] When the system enters the 100% duty cycle driving mode and needs to continuously output the on-state driving signal, the system inputs the driving logic signal V CTL Keep high level, 100% mode trigger circuit outputs high level, V1 outputs a low voltage control signal with the same frequency as the oscillator output, V2 outputs a high voltage control signal with the same frequency as the oscillator output, and V3 outputs a high voltage control signal with the same frequency as the oscillator output.

[0078] See also Figure 3 , showing a structural schematic diagram of a main charge pump and a driving circuit.

[0079] like Figure 3 As shown, in some feasible embodiments, based on the above scheme, the main charge pump and driving circuit include: a main charge pump, a second-stage charge pump, a pre-charging circuit, a first high-voltage switch circuit, a second high-voltage switch circuit, a delayed self-locking switch circuit, a first transistor and a low-side driver;

[0080] The input end of the main charge pump is connected to the front signal processing circuit to receive the low voltage control signal, the first high voltage control signal and the second high voltage control signal; the first output end of the main charge pump is connected to the input end of the first high voltage switch circuit, and the second output end is connected to the input end of the second high voltage switch;

[0081] A first output terminal of the first high-voltage switch circuit is connected to the low-side driver, and a second output terminal is connected to the drain of the first transistor;

[0082] The first output terminal of the second high-voltage switch circuit is connected to the first input terminal of the second-stage charge pump, and the second output terminal is connected to the drain of the first transistor;

[0083] The second input end of the second-stage charge pump is connected to the front-end signal processing circuit to receive the low-voltage control signal, the first high-voltage control signal and the second high-voltage control signal, and the output end of the second-stage charge pump is connected to the input end of the delay self-locking switch circuit;

[0084] The output end of the time-delay self-locking switch circuit is connected to the drain of the first transistor;

[0085] The gate of the first transistor receives the low voltage control signal, and the source is grounded;

[0086] The input end of the pre-charging circuit receives the second high-voltage control signal, and the output end is connected to the low-side driver and then grounded;

[0087] The output end of the pre-charging circuit is also connected to the first output end of the first high-voltage switching circuit.

[0088] It should be noted that the second-stage charge pump and pre-charging circuit both have a unidirectional conduction function, that is, when the internal or input-output node is higher than HVCC, it can avoid the formation of a reverse conduction path between the high-voltage node and the HVCC power rail.

[0089] In some feasible embodiments, based on the above solution, the first high-voltage switch circuit includes: a second transistor, a third transistor and a first diode;

[0090] The drain of the second transistor is connected to the first output terminal of the main charge pump;

[0091] The gate of the second transistor is connected to the gate of the third transistor, and the source of the second transistor is connected to the source of the third transistor and then connected to the drain of the first transistor;

[0092] The first diode is connected in parallel with the gate and source of the second transistor;

[0093] The gate of the third transistor is connected to the output end of the pre-charging circuit and then connected to the low-side driver.

[0094] In some feasible embodiments, based on the above solution, the second high-voltage switch circuit includes: a fourth transistor, a second diode and a resistor;

[0095] The drain of the fourth transistor is connected to the second output terminal of the main charge pump, the source is connected to the second diode and the second-stage charge pump respectively, and the gate is connected to the drain of the first transistor;

[0096] The second diode is connected to the resistor and then connected to the gate of the fourth transistor.

[0097] In some feasible embodiments, based on the above solution, the time-delay self-locking switch circuit includes: a fifth transistor and a time-delay circuit;

[0098] The drain of the fifth transistor is connected to the drain of the first transistor, and the source is connected to the output end of the second-stage charge pump;

[0099] One end of the delay circuit is connected to the source of the fifth transistor, and the other end is connected to the gate of the fifth transistor.

[0100] It should be noted that if Figure 3 As shown, the delayed self-locking switch circuit S3 is turned on when the voltage at the source terminal of the transistor MN5 changes suddenly. After a period of delay, the gate voltage of the transistor MN5 is pulled up to the source terminal voltage, and the switch is turned off.

[0101] See also Figure 3 The working principle of the main charge pump and the driving circuit described in the embodiment of the present application is as follows:

[0102] When the system input drives the logic signal V CTL is low level. From the above description, it can be known that the low-voltage domain control signal V1 is high level, the first high-voltage control signal V2 is 2VCC, and the second high-voltage control signal V3 is HVCC; V1, V2, and V3 control the main charge pump output nodes 1 and 2 to be precharged to VCC, and control the second-stage charge pump output node 4 to be precharged to VCC. At this time, node 3 is connected to the lower plate of the second-stage charge pump bootstrap capacitor, and its voltage is GND; V3 controls the precharge circuit to be turned off; transistor MN1 is turned on, and node 5 is pulled down to GND; the first high-voltage switch circuit S1, the second high-voltage switch circuit S2, and the delayed self-locking switch circuit S3 remain turned off; the low-side drive is turned on, node 6 is pulled down to GND, and V Drive Output low level driving signal.

[0103] When the system input drives the logic signal V CTL When the voltage level is high, it can be seen from the above description that the low-voltage domain control signal V1 is low, the first high-voltage control signal V2 is VCC, and the second high-voltage control signal V3 is HVCC-5V; the low-side drive is turned off, and the transistor MN1 is turned off; V3 controls the pre-charge circuit to turn on, slowly pulling up the node 6, V Drive It rises slowly and starts precharging; V1, V2, and V3 control the main charge pump output nodes 1 and 2 to bootstrap to HVCC+VCC, and control the second-stage charge pump output node 4 to bootstrap to HVCC+VCC. At this time, node 3 is connected to the lower plate of the second-stage charge pump bootstrap capacitor, and its voltage is HVCC; the delayed self-locking switch circuit S3 is turned on during the process of node 4 being bootstrapped to HVCC+VCC, and node 5 is synchronously pulled up to HVCC+VCC; the second high-voltage switch circuit S2 is turned on, and node 2 pulls node 3 up to HVV+VCC through charge sharing; node 4 is bootstrapped to HVCC+2VCC again, and is synchronized to node 5 through the delayed self-locking switch circuit S3, so that the first high-voltage switch circuit S1 is turned on, and the second high-voltage switch circuit S2 remains on. Node 1 pulls node 6 to HVCC+VCC through charge sharing, V Drive Output high level driving signal.

[0104] In 100% duty cycle driving mode, the system input driving logic signal V CTL Maintain high level, V1, V2, V3 are all control signals of the oscillator with the same frequency but different voltage domains; during the conduction period of the 100% duty cycle driving mode, the low-side drive is always turned off, and the remaining circuits rely on V1, V2, V3 to repeat the above driving behavior; Among them, during the high level period of V1, the first high-voltage switch circuit S1 is turned off, node 6 is floating, and V Drive The voltage is self-sustaining with the help of the parasitic capacitance of the gate of the driven power tube. It should be noted that the system input drive logic signal V CTL During the high level period, that is, when a high level gate drive signal needs to be output, the low-side drive does not work, regardless of whether it enters the 100% duty cycle drive mode.

[0105] The pre-charging circuit described in the above principle can charge V before the first high-voltage switch circuit S1 is turned on. Drive Precharging can reduce the size of the bootstrap capacitor in the main charge pump to achieve low-cost integration. The synchronous logic signal generated by the second-stage charge pump and the delayed self-locking switch circuit S3 is used as the control signal of the first high-voltage switch circuit S1, which can achieve the main charge pump bootstrap capacitor replenishing charge without affecting the drive output voltage, and realize a 100% duty cycle drive mode. In the entire drive scheme, only the dynamic power consumption of the charge pump exists, which is more efficient.

[0106] See also Figure 4 , shows a schematic diagram of the timing of key driving signals.

[0107] like Figure 4 As shown in the figure, the time t1 is the timing of driving the high-level output switch, and the arrows show the sequence of the switching actions; the time t2 is the timing of driving the low-level output switch; the time t3 is the driving into the 100% duty cycle mode, V CTL Keep the high level, the other key nodes switch at a fixed period, and node 6 outputs V Drive Continuously output high-level driving signal.

[0108] In summary, the embodiments of the present application propose a novel integrated charge pump gate drive circuit, in which the pre-charge circuit can avoid the reliance on large bootstrap capacitors, and at the same time use different types of capacitor stacks to achieve small-area integration, effectively improving the power density and reducing the application cost. The charge pump drive can self-generate high-voltage drive signals, thereby avoiding inefficient drive buffer stage chains. Combined with the advantage of the charge pump being able to periodically replenish charges, the circuit proposed by the present invention can continuously output high-quality gate drive signals and achieve 100% duty cycle drive.

[0109] Based on the same inventive concept, an embodiment of the present application further provides a power integrated circuit, which includes a novel integrated charge pump driving circuit as described in any of the above embodiments.

[0110] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the embodiments disclosed herein. The present application is intended to cover any variations, uses or adaptations of the present application, which follow the general principles of the present application and include common knowledge or customary techniques in the art that are not disclosed in the present application. It should be understood that the present application is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from the scope thereof. The scope of the present application is limited only by the appended claims.

Claims

1. A novel integrated charge pump driving circuit, characterized in that: include: Pre-signal processing circuit and main charge pump and driving circuit; The pre-signal processing circuit receives the system input drive logic signal for pre-processing and outputs a low voltage control signal, a first high voltage control signal and a second high voltage control signal; The main charge pump and driving circuit is connected to the output end of the front signal processing circuit, receives the low voltage control signal, the first high voltage control signal and the second high voltage control signal, and processes and outputs a gate driving signal; Wherein, when the system input drive logic signal is at a high level, the low voltage control signal outputs a low level, the first high voltage control signal outputs a low level, the second high voltage control signal outputs a low level, and the gate drive signal outputs a high level; When the system input drive logic signal is at a low level, the low voltage control signal outputs a high level, the first high voltage control signal outputs a high level, the second high voltage control signal outputs a high level, and the gate drive signal outputs a low level.

2. The circuit according to claim 1, characterized in that The pre-signal processing circuit includes: a 100% mode trigger circuit, an oscillator, a first logic gate, a second logic gate, a first-stage charge pump and a level shift circuit based on the charge pump; The oscillator is connected to the first input terminal of the first logic gate; The 100% mode trigger circuit is connected to the second input terminal of the first logic gate; The output terminal of the first logic gate is connected to the second input terminal of the second logic gate; The first input terminal of the second logic gate receives the system input drive logic signal; The first output terminal of the second logic gate outputs the low voltage control signal; The second output end of the second logic gate is connected to the first-stage charge pump, and the first-stage charge pump outputs the first high-voltage control signal; The third output terminal of the second logic gate is connected to the charge pump-based level shift circuit, and the charge pump-based level shift circuit outputs the second high-voltage control signal.

3. The circuit according to claim 1, characterized in that The main charge pump and driving circuit include: a main charge pump, a second-stage charge pump, a pre-charging circuit, a first high-voltage switch circuit, a second high-voltage switch circuit, a delayed self-locking switch circuit, a first transistor and a low-side drive; The input end of the main charge pump is connected to the pre-signal processing circuit to receive the low voltage control signal, the first high voltage control signal and the second high voltage control signal; the first output end of the main charge pump is connected to the input end of the first high voltage switch circuit, and the second output end is connected to the input end of the second high voltage switch; A first output terminal of the first high-voltage switch circuit is connected to the low-side driver, and a second output terminal is connected to the drain of the first transistor; The first output terminal of the second high-voltage switch circuit is connected to the first input terminal of the second-stage charge pump, and the second output terminal is connected to the drain of the first transistor; The second input end of the second-stage charge pump is connected to the front-end signal processing circuit to receive the low-voltage control signal, the first high-voltage control signal and the second high-voltage control signal, and the output end of the second-stage charge pump is connected to the input end of the delay self-locking switch circuit; The output end of the time-delay self-locking switch circuit is connected to the drain of the first transistor; The gate of the first transistor receives the low voltage control signal, and the source is grounded; The input end of the pre-charging circuit receives the second high-voltage control signal, and the output end is connected to the low-side driver and then grounded; The output end of the pre-charging circuit is also connected to the first output end of the first high-voltage switching circuit.

4. The circuit according to claim 3, characterized in that The first high-voltage switch circuit includes: a second transistor, a third transistor and a first diode; The drain of the second transistor is connected to the first output terminal of the main charge pump; The gate of the second transistor is connected to the gate of the third transistor, and the source of the second transistor is connected to the source of the third transistor and then connected to the drain of the first transistor; The first diode is connected in parallel with the gate and source of the second transistor; The gate of the third transistor is connected to the output end of the pre-charging circuit and then connected to the low-side driver.

5. The circuit according to claim 3, characterized in that The second high-voltage switch circuit includes: a fourth transistor, a second diode and a resistor; The drain of the fourth transistor is connected to the second output terminal of the main charge pump, the source is connected to the second diode and the second-stage charge pump respectively, and the gate is connected to the drain of the first transistor; The second diode is connected to the resistor and then connected to the gate of the fourth transistor.

6. The circuit according to claim 3, characterized in that The time-delay self-locking switch circuit comprises: a fifth transistor and a time-delay circuit; The drain of the fifth transistor is connected to the drain of the first transistor, and the source is connected to the output end of the second-stage charge pump; One end of the delay circuit is connected to the source of the fifth transistor, and the other end is connected to the gate of the fifth transistor.

7. A power integrated circuit, characterized in that: It comprises a novel integrated charge pump driving circuit as claimed in any one of claims 1 to 6.

Images