Thin-layer transmitter with a hydrogen-blocking dielectric barrier layer and method for its manufacture

Abstract

Semiconductor device with: an insulating matrix layer (42) which has an opening (11) and is arranged over a substrate (8); a hydrogen-blocking dielectric barrier layer (44) extending over a horizontal plane containing a bottom side of the insulating matrix layer (42); a gate electrode (15) which is arranged in the opening (11) on the hydrogen-blocking dielectric barrier layer (44); a stack of a gate dielectric (10) and a semiconducting metal oxide plate (20) above a top surface of the gate electrode (15) and above horizontally extending portions of the hydrogen-blocking dielectric barrier layer (44) arranged above the insulating matrix layer (42); and a source electrode (52) and a drain electrode (56) that contact respective parts of a top side of the semiconducting metal oxide plate (20), wherein the hydrogen-blocking dielectric barrier layer (44) has a dielectric metal oxide coating (44B) with a dielectric metal oxide material in contact with a first region of a bottom surface of the gate dielectric (10) below the source electrode (52) and in contact with a second region of the bottom surface of the gate dielectric (10) which is located below the drain electrode (56) and is spaced laterally from the first region of the bottom surface of the gate dielectric (10) by the gate electrode (15), wherein the hydrogen-blocking dielectric barrier layer (44) has a silicon nitride coating (44A) which is in contact with the gate electrode (15) and is spaced apart from the insulating matrix layer (42) by the dielectric metal oxide coating (44B).

Description

background

[0001] Thin-film transistors (TFTs) made from oxide semiconductors are an interesting option for BEOL (Back End of Line) integration because TFTs can be machined at low temperatures and therefore do not damage existing devices. For example, existing FEOL (Front End of Line) and MEOL (Middle End of Line) devices cannot be damaged by the manufacturing conditions and processes.

[0002] Thin-film transistors are known, for example, from US 9 466 615 B2 and US 2019 / 0 103 401 A1. Brief description of the drawings

[0003] Aspects of the present invention are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. Rather, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 is a vertical sectional view showing a first exemplary structure after fabrication of CMOS transistors (CMOS: complementary metal oxide semiconductor), first metallic interconnect structures fabricated in dielectric lower-level material layers, a planar insulating spacer layer and an optional dielectric etch stop layer according to an embodiment of the present invention. Fig. Figure 2A is a top-down view of part of the first exemplary structure after the fabrication of an insulating matrix layer according to a first embodiment of the present invention. Fig. 2B is a vertical sectional view of the first exemplary structure along a vertical plane B - B' of Fig. 2A. Fig. 2C is a vertical sectional view of the first exemplary structure along a vertical plane C - C' of Fig. 2A. Fig. Figure 3A is a top-down view of an area of ​​the first exemplary structure after creating an opening in the insulating matrix layer according to the first embodiment of the present invention. Fig. 3B is a vertical sectional view of the first exemplary structure along a vertical plane B - B' of Fig. 3A. Fig. 3C is a vertical sectional view of the first exemplary structure along a vertical plane C - C' of Fig. 3A. Fig. Figure 4A is a top-down view of an area of ​​the first exemplary structure after fabrication of a hydrogen-blocking dielectric barrier layer according to the first embodiment of the present invention. Fig. 4B is a vertical sectional view of the first exemplary structure along a vertical plane B - B' of Fig. 4A. Fig. 4C is a vertical sectional view of the first exemplary structure along a vertical plane C - C' of Fig. 4A. Fig. Figure 5A is a top-down view of an area of ​​the first exemplary structure after fabrication of a lower gate electrode according to the first embodiment of the present invention. Fig. 5B is a vertical sectional view of the first exemplary structure along a vertical plane B - B' of Fig. 5A. Fig. 5C is a vertical sectional view of the first exemplary structure along a vertical plane C - C' of Fig. 5A. Fig. Figure 6A is a top-down view of an area of ​​the first exemplary structure after fabrication of a lower gate dielectric and a semiconducting metal oxide plate according to the first embodiment of the present invention. Fig. 6B is a vertical sectional view of the first exemplary structure along a vertical plane B - B' of Fig. 6A. Fig. 6C is a vertical sectional view of the first exemplary structure along a vertical plane C - C' of Fig. 6A. Fig. Figure 7A is a top-down view of an area of ​​the first exemplary structure after fabrication of a hydrogen-blocking dielectric capping barrier layer and a dielectric electrode plane material layer according to the first embodiment of the present invention. Fig. 7B is a vertical sectional view of the first exemplary structure along a vertical plane B - B' of Fig. 7A. Fig. 7C is a vertical sectional view of the first exemplary structure along a vertical plane C - C' of Fig. 7A. Fig. Figure 8A is a top-down view of an area of ​​the first exemplary structure after creating a source opening, a drain opening and a lower gate through-contact opening according to the first embodiment of the present invention. Fig. 8B is a vertical sectional view of the first exemplary structure along a vertical plane B - B' of Fig. 8A. Fig. 8C is a vertical sectional view of the first exemplary structure along a vertical plane C - C' of Fig. 8A. Fig. Figure 9A is a top-down view of an area of ​​the first exemplary structure after fabrication of a source electrode, a drain electrode and a backside electrode through-contact structure according to the first embodiment of the present invention. Fig. 9B is a vertical sectional view of the first exemplary structure along a vertical plane B - B' of Fig. 9A. Fig. 9C is a vertical sectional view of the first exemplary structure along a vertical plane C - C' of Fig. 9A. Fig. Figure 10A is a top-down view of an area of ​​a first alternative configuration of the first exemplary structure after fabricating a source electrode, a drain electrode and a backside electrode through-contact structure according to the first embodiment of the present invention. Fig. 10B is a vertical sectional view of the first exemplary structure along a vertical plane B - B' of Fig. 10A. Fig. 10C is a vertical sectional view of the first exemplary structure along a vertical plane C - C' of Fig. 10A. Fig. Figure 11A is a top-down view of an area of ​​a second alternative configuration of the first exemplary structure after fabricating a source electrode, a drain electrode and a backside electrode through-contact structure according to the first embodiment of the present invention. Fig. 11B is a vertical sectional view of the first exemplary structure along a vertical plane B - B' of Fig. 11A. Fig. 11C is a vertical sectional view of the first exemplary structure along a vertical plane C - C' of Fig. 11A. Fig. Figure 12A is a top-down view of an area of ​​a third alternative configuration of the first exemplary structure after fabricating a source electrode, a drain electrode and a backside electrode through-contact structure according to the first embodiment of the present invention. Fig. 12B is a vertical sectional view of the first exemplary structure along a vertical plane B - B' of Fig. 12A. Fig. 12C is a vertical sectional view of the first exemplary structure along a vertical plane C - C' of Fig. 12A. Fig. Figure 13A is a top-down view of an area of ​​a fourth alternative configuration of the first exemplary structure after fabricating a source electrode, a drain electrode and a backside electrode through-contact structure according to the first embodiment of the present invention. Fig. 13B is a vertical sectional view of the first exemplary structure along a vertical plane B - B' of Fig. 13A. Fig. 13C is a vertical sectional view of the first exemplary structure along a vertical plane C - C' of Fig. 13A. Fig. Figure 14A is a top-down view of an area of ​​a fifth alternative configuration of the first exemplary structure after fabrication of a source electrode, a drain electrode and a backside electrode through-contact structure according to the first embodiment of the present invention. Fig. 14B is a vertical sectional view of the first exemplary structure along a vertical plane B - B' of Fig. 14A. Fig. 14C is a vertical sectional view of the first exemplary structure along a vertical plane C - C' of Fig. 14A. Fig. Figure 15A is a top-down view of a region of a second exemplary structure after fabrication of a lower gate dielectric and a semiconducting metal oxide plate according to a second embodiment of the present invention. Fig. 15B is a vertical sectional view of the second exemplary structure along a vertical plane B - B' of Fig. 15A. Fig. 15C is a vertical sectional view of the second exemplary structure along a vertical plane C - C' of Fig. 15A. Fig. Figure 16A is a top-down view of a region of the second exemplary structure after fabrication of an upper gate dielectric according to the second embodiment of the present invention. Fig. 16B is a vertical sectional view of the second exemplary structure along a vertical plane B - B' of Fig. 16A. Fig. 16C is a vertical sectional view of the second exemplary structure along a vertical plane C - C' of Fig. 16A. Fig. Figure 17A is a top-down view of an area of ​​the second exemplary structure after fabrication of a hydrogen-blocking dielectric capping barrier layer and a dielectric electrode plane material layer according to the second embodiment of the present invention. Fig. 17B is a vertical sectional view of the second exemplary structure along a vertical plane B - B' of Fig. 17A. Fig. 17C is a vertical sectional view of the second exemplary structure along a vertical plane C - C' of Fig. 17A. Fig. Figure 18A is a top-down view of an area of ​​the second exemplary structure after creating a source opening, a drain opening and a lower gate through-contact opening according to the second embodiment of the present invention. Fig. 18B is a vertical sectional view of the second exemplary structure along a vertical plane B - B' of Fig. 8A. Fig. 18C is a vertical sectional view of the second exemplary structure along a vertical plane C - C' of Fig. 18A. Fig. Figure 19A is a top-down view of an area of ​​the second exemplary structure after fabrication of a source electrode, a drain electrode and a backside electrode through-contact structure according to the second embodiment of the present invention. Fig. 19B is a vertical sectional view of the second exemplary structure along a vertical plane B - B' of Fig. 19A. Fig. 19C is a vertical sectional view of the second exemplary structure along a vertical plane C - C' of Fig. 19A. Fig. Figure 20A is a top-down view of an area of ​​a first alternative configuration of the second exemplary structure after fabricating a source electrode, a drain electrode and a backside electrode through-contact structure according to the second embodiment of the present invention. Fig. 20B is a vertical sectional view of the second exemplary structure along a vertical plane B - B' of Fig. 20A. Fig. 20C is a vertical sectional view of the second exemplary structure along a vertical plane C - C' of Fig. 20A. Fig. Figure 21A is a top-down view of an area of ​​a second alternative configuration of the second exemplary structure after fabrication of a source electrode, a drain electrode and a backside electrode through-contact structure according to the second embodiment of the present invention. Fig. 21B is a vertical sectional view of the second exemplary structure along a vertical plane B - B' of Fig. 21A. Fig. 21C is a vertical sectional view of the second exemplary structure along a vertical plane C - C' of Fig. 21A. Fig. Figure 22A is a top-down view of an area of ​​a third alternative configuration of the second exemplary structure after fabrication of a source electrode, a drain electrode and a backside electrode through-contact structure according to the second embodiment of the present invention. Fig. 22B is a vertical sectional view of the second exemplary structure along a vertical plane B - B' of Fig. 22A. Fig. 22C is a vertical sectional view of the second exemplary structure along a vertical plane C - C' of Fig. 22A. Fig. Figure 23A is a top-down view of an area of ​​a fourth alternative configuration of the second exemplary structure after fabricating a source electrode, a drain electrode and a backside electrode through-contact structure according to the second embodiment of the present invention. Fig. 23B is a vertical sectional view of the second exemplary structure along a vertical plane B - B' of Fig. 23A. Fig. 23C is a vertical sectional view of the second exemplary structure along a vertical plane C - C' of Fig. 23A. Fig. Figure 24A is a top-down view of an area of ​​a fifth alternative configuration of the second exemplary structure after fabricating a source electrode, a drain electrode and a backside electrode through-contact structure according to the second embodiment of the present invention. Fig. 24B is a vertical sectional view of the second exemplary structure along a vertical plane B - B' of Fig. 24A. Fig. 24C is a vertical sectional view of the second exemplary structure along a vertical plane C - C' of Fig. 24A. Fig. Figure 25A is a top-down view of a region of a third exemplary structure after fabrication of a hydrogen-blocking dielectric barrier layer and a gate electrode layer according to a third embodiment of the present invention. Fig. 25B is a vertical sectional view of the third exemplary structure along a vertical plane B - B' of Fig. 25A. Fig. 25C is a vertical sectional view of the third exemplary structure along a vertical plane C - C' of Fig. 25A. Fig. Figure 26A is a top-down view of an area of ​​the third exemplary structure after fabrication of a source electrode, a drain electrode and a backside electrode through-contact structure according to the third embodiment of the present invention. Fig. 26B is a vertical sectional view of the third exemplary structure along a vertical plane B - B' of Fig. 26A. Fig. 26C is a vertical sectional view of the third exemplary structure along a vertical plane C - C' of Fig. 26A. Fig. Figure 27A is a top-down view of an area of ​​an alternative configuration of the third exemplary structure after fabrication of a source electrode, a drain electrode and a backside electrode through-contact structure according to the third embodiment of the present invention. Fig. 27B is a vertical sectional view of the third exemplary structure along a vertical plane B - B' of Fig. 27A. Fig. 27C is a vertical sectional view of the third exemplary structure along a vertical plane C - C' of Fig. 27A. Fig. Figure 28 is a vertical sectional view of an exemplary structure after the fabrication of memory cells according to an embodiment of the present invention. Fig. Figure 29 is a flowchart showing general processing steps for manufacturing a semiconductor device of the present invention. Detailed description

[0004] The present invention provides semiconductor devices with the features of claim 1 and 9, as well as a method for manufacturing a semiconductor device with the features of claim 12. Exemplary embodiments are given in the dependent claims. The following description provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present invention. These are, of course, merely examples and are not intended to be limiting.For example, the fabrication of a first element over or on a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, so that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present invention. This repetition serves for simplicity and clarity and does not in itself imply any relationship between the various embodiments and / or configurations discussed.

[0005] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, may be used here to simply describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. These spatially relative terms are intended to encompass orientations of the device in use or operation beyond the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative descriptors used here may be interpreted accordingly. Elements with the same reference numbers refer to one and the same element, and it is assumed that they have the same material composition and thickness range unless explicitly stated otherwise.

[0006] In general, the structures and methods of the present invention can be used to fabricate a semiconductor structure with at least one thin-film transistor, such as a plurality of thin-film transistors. The thin-film transistors can be fabricated on a substrate, which may be an insulating substrate, a conductive substrate, or a semiconducting substrate. In embodiments where a conductive or semiconducting substrate is used, at least one insulating layer can be used to provide electrical insulation between the thin-film transistors and the underlying substrate.In embodiments where a semiconductor substrate, such as a single-crystal substrate, is used, field-effect transistors, in which portions of the semiconductor substrate are used as semiconductor channels, can be fabricated on the semiconductor substrate. Metallic interconnect structures can then be fabricated over the field-effect transistors and embedded in dielectric interconnect-level layers. The thin-film transistors can be fabricated over the field-effect transistors with single-crystal semiconductor channels and over the metallic interconnect structures, which are referred to here as metallic lower-level interconnect structures.

[0007] According to one aspect of the present invention, a hydrogen-blocking dielectric barrier layer can be produced on the underside of a semiconducting metal oxide plate that has a polycrystalline semiconductor channel of a respective thin-film transistor. In particular, the hydrogen-blocking dielectric barrier layer can be deposited on the sidewalls of an opening for producing a bottom gate electrode. The hydrogen-blocking dielectric barrier layer can also be produced over a top surface of the insulating matrix layer in which openings are created. Optionally, a hydrogen-blocking dielectric capping barrier layer can be produced over the semiconducting metal oxide plates.The hydrogen-blocking dielectric barrier layer and the optional hydrogen-blocking dielectric capping barrier layer prevent hydrogen from diffusing into the semiconducting metal oxide plates or the lower gate electrodes, and thus prevent changes in the electronic surface states of the semiconducting metal oxide plates and changes in the properties of the thin-film transistors. The various aspects of embodiments of the present invention will now be described in more detail.

[0008] In Fig. Figure 1 shows a first exemplary structure according to a first embodiment of the present invention. The first exemplary structure comprises a substrate 8, which can be a semiconductor substrate, such as a commercially available silicon substrate. The substrate 8 can have a semiconductor material layer 9, at least on its upper part. The semiconductor material layer 9 can be a surface part of a solid semiconductor substrate, or it can be an upper semiconductor layer of a semiconductor-on-insulator (SOI) substrate. In one embodiment, the semiconductor material layer 9 comprises a single-crystal semiconductor material, such as single-crystal silicon. In another embodiment, the substrate 8 can be a single-crystal silicon substrate with a single-crystal silicon material.

[0009] In an upper part of the semiconductor material layer 9, STI structures 720 (STI: shallow trench insulation) can be fabricated, which have a dielectric material such as silicon oxide. In each region enclosed laterally by a part of the STI structures 720, suitable doped semiconductor wells, such as p- and n-wells, can be produced. Field-effect transistors 701 can be fabricated above a top surface of the semiconductor material layer 9. Each field-effect transistor 701 can, for example, have: a source electrode 732; a drain electrode 738; a semiconductor channel 735 having a surface portion of the substrate 8 extending between the source electrode 732 and the drain electrode 738; and a gate structure 750. The semiconductor channel 735 can be a single-crystal semiconductor material.Each gate structure 750 can have a gate dielectric 752, a gate electrode 754, a capping gate dielectric 758, and a dielectric gate spacer 756. A source-side metal-semiconductor alloy region 742 can be formed on each source electrode 732, and a drain-side metal-semiconductor alloy region 748 can be formed on each drain electrode 738.

[0010] In an embodiment in which a matrix of memory cells can subsequently be fabricated in a plane of a dielectric material layer, the field-effect transistors 701 can include a circuit that provides functions for operating the matrix of memory cells. In particular, devices in a peripheral region can be configured to control a programming operation, an erase operation, and a sampling (read) operation of the matrix of memory cells. The devices in the peripheral region can, for example, include a sensor circuit and / or a programming circuit. The devices fabricated on the top surface of the semiconductor material layer 9 can include CMOS transistors and optionally other semiconductor devices (such as resistors, diodes, capacitors, etc.) and are collectively referred to as a CMOS circuit 700.

[0011] One or more of the field-effect transistors 701 in the CMOS circuit 700 can have a semiconductor channel 735 that contains a portion of the semiconductor material layer 9 in the substrate 8. If the semiconductor material layer 9 comprises a single-crystal semiconductor material, such as single-crystal silicon, the semiconductor channel 735 of each field-effect transistor 701 in the CMOS circuit 700 can be a single-crystal semiconductor channel, such as a single-crystal silicon channel. In one embodiment, a plurality of field-effect transistors 701 in the CMOS circuit 700 can each have a node that is subsequently electrically connected to a node of a respective ferroelectric memory cell to be manufactured later.For example, several field-effect transistors 701 in the CMOS circuit 700 can each have a source electrode 732 or a drain electrode 738, which is later electrically connected to a node of a respective ferroelectric memory cell to be manufactured later.

[0012] In one embodiment, the CMOS circuit 700 may include a programming control circuit configured to control gate voltages of a group of field-effect transistors 701 used to program a respective ferroelectric memory cell and gate voltages of thin-film transistors to be manufactured later.In this embodiment, the programming control circuit can be configured to provide: a first programming pulse that programs a respective ferroelectric dielectric material layer in a selected ferroelectric memory cell into a first polarization state in which an electrical polarization in the ferroelectric dielectric material points to a first electrode of the selected ferroelectric memory cell; and a second programming pulse that programs the ferroelectric dielectric material layer in the selected ferroelectric memory cell into a second polarization state in which the electrical polarization in the ferroelectric dielectric material points to a second electrode of the selected ferroelectric memory cell.

[0013] In one embodiment, the substrate 8 can be a single-crystal silicon substrate, and the field-effect transistors 701 can each have a portion of the single-crystal silicon substrate as a semiconducting channel. The term "semiconducting element" used here refers to an element with an electrical conductivity of 1.0 × 10⁻⁶. -6 S / cm up to 1.0 × 10 5 S / cm. The term "semiconductor material" used here refers to a material with an electrical conductivity of 1.0 × 10 -6 S / cm up to 1.0 × 10 5 S / cm if the material has no electrical dopants and a doped material with an electrical conductivity of 1.0 S / cm to 1.0 × 10 5 S / cm can be produced after suitable doping with an electrical dopant.

[0014] According to one aspect of the present invention, the field-effect transistors 701 can subsequently be electrically connected to drain electrodes and gate electrodes of access transistors having semiconducting metal oxide plates fabricated over the field-effect transistors 701. In one embodiment, a subset of the field-effect transistors 701 can subsequently be electrically connected to at least one of the drain electrodes and the gate electrodes. The field-effect transistors 701 can, for example, comprise: first word line drivers configured to apply a first gate voltage to first word lines via a first subset of subsequently fabricated metallic lower-level interconnect structures; and second word line drivers configured to apply a second gate voltage to second word lines via a second subset of the metallic lower-level interconnect structures.Furthermore, the 701 field-effect transistors can include bit line drivers configured to apply a bit line bias to bit lines to be manufactured later, and read amplifiers configured to detect an electrical current flowing through the bit lines during a read operation.

[0015] Subsequently, various metallic interconnect structures embedded in dielectric material layers can be fabricated over the substrate 8 and the semiconductor devices (such as the field-effect transistors 701) located thereon. As an illustrative example, the dielectric material layers can include: a first dielectric material layer 601 (occasionally referred to as a dielectric contact plane material layer 601), which may be a layer enclosing a contact structure connected to sources and drains; a first dielectric interconnect plane material layer 610; and a second dielectric interconnect plane material layer 620.The metallic interconnect structures can include: device through-hole structures 612, which are fabricated in the first dielectric material layer 601 and contact a respective component of the CMOS circuit 700; first metal conductor structures 618, which are fabricated in the first dielectric interconnect layer material layer 610; first metal through-hole structures 622, which are fabricated in a lower part of the second dielectric interconnect layer material layer 620; and second metal conductor structures 628, which are fabricated in an upper part of the second dielectric interconnect layer material layer 620.

[0016] The dielectric material layers (601, 610, 620) can comprise a dielectric material such as undoped silicate glass, doped silicate glass, organosilicate glass, amorphous fluorocarbon, porous variants thereof, or combinations thereof. The metallic interconnect structures (612, 618, 622, 628) can each comprise at least one conductive material, which may be a combination of a metallic coating (such as a metal nitride or a metal carbide) and a metallic filler material. Each metallic coating can comprise TiN, TaN, WN, TiC, TaC, and WC, and each metallic filler material can comprise W, Cu, Al, Co, Ru, Mo, Ta, Ti, alloys thereof, and / or combinations thereof. Other suitable metallic coating and filler materials may also be used within the intended scope of protection of the invention.In one embodiment, the first metal via structures 622 and the second metal conductor structures 628 can be fabricated as integrated conductor and via structures using a dual damascene process. The dielectric material layers (601, 610, 620) are referred to here as dielectric lower-level material layers. The metallic interconnect structures (612, 618, 622, 628) fabricated in the dielectric lower-level material layers are referred to here as metallic lower-level interconnect structures.

[0017] Although the present invention is described with reference to an embodiment in which thin-film transistors are fabricated over the second dielectric interconnect layer material layer 620, embodiments in which the memory cell matrix can also be produced in a different metallic interconnect layer are expressly considered here. Furthermore, although the present invention is described with reference to an embodiment in which a semiconductor substrate is used as the substrate 8, embodiments in which an insulating substrate or a conductive substrate is used as the substrate 8 are expressly considered here.

[0018] The group of all dielectric material layers fabricated prior to the fabrication of a matrix of thin-film transistors or a matrix of ferroelectric memory cells is collectively referred to as dielectric lower-level material layers (601, 610, 620). The group of all metallic interconnect structures fabricated in the dielectric lower-level material layers (601, 610, 620) is collectively referred to here as first metallic interconnect structures (612, 618, 622, 628). In general, the first metallic interconnect structures (612, 618, 622, 628) fabricated in at least one dielectric lower-level material layer (601, 610, 620) can be fabricated above the semiconductor material layer 9, which is arranged in the substrate 8.

[0019] According to one aspect of the present invention, thin-film transistors (TFTs) can subsequently be fabricated in a metallic interconnect layer located above the metallic interconnect layers containing the dielectric lower-layer material layers (601, 610, 620) and the first metallic interconnect structures (612, 618, 622, 628). In one embodiment, a planar dielectric material layer of uniform thickness can be fabricated above the dielectric lower-layer material layers (601, 610, 620). The planar dielectric material layer is referred to herein as a planar insulating spacer layer 635. The planar insulating spacer layer 635 comprises a dielectric material such as undoped silicate glass, doped silicate glass, organosilicate glass, or a porous dielectric material and can be deposited by chemical vapor deposition.The thickness of the planar insulating spacer layer 635 can range from 20 nm to 300 nm, but smaller and larger thicknesses can also be used.

[0020] Typically, dielectric interconnect layer layers, such as the dielectric lower-level material layers (601, 610, 620) containing the metallic interconnect structures, such as the first metallic interconnect structures (612, 618, 622, 628), can be fabricated using semiconductor devices. The planar insulating spacer layer 635 can be fabricated over the dielectric interconnect layer layers.

[0021] An etch stop layer 636 can optionally be produced above the planar insulating spacer layer 635. The etch stop layer 636 comprises a dielectric etch stop material that offers higher etch resistance compared to an etching chemical during a subsequent anisotropic etching process. This process is used to etch a dielectric material that is to be deposited later above the dielectric etch stop layer 636. The dielectric etch stop layer 636 can, for example, comprise silicon carbonitride, silicon nitride, silicon oxide nitride, or a dielectric metal oxide such as aluminum oxide. Other suitable etch stop materials are also within the intended scope of protection of the invention. The thickness of the dielectric etch stop layer 636 can range from 2 nm to 40 nm, e.g., 4 nm to 20 nm, but smaller and larger thicknesses can also be used.

[0022] In the Fig. Figures 2A to 2C show a region of the first exemplary structure, corresponding to a region in which a thin-film transistor is to be fabricated later. Although the present invention is described using only one instance of a thin-film transistor, it is understood that several instances of the thin-film transistor can be fabricated simultaneously in each of the exemplary structures of the present invention.

[0023] An insulating matrix layer 42 can be fabricated over the planar insulating spacer layer 635 and the optional dielectric etch stop layer 636. The insulating matrix layer 42 can comprise a dielectric material such as undoped silicate glass, doped silicate glass, organosilicate glass, or a porous dielectric material and can be deposited by chemical vapor deposition. The thickness of the insulating matrix layer 42 can range from 20 nm to 300 nm, but smaller and larger thicknesses are also possible. Several thin-film transistors can then be fabricated over the insulating matrix layer 42. In one embodiment, the multiple thin-film transistors can be arranged along a first horizontal direction hd1 and a second horizontal direction hd2, which can be perpendicular to the first horizontal direction hd1.

[0024] In the Fig. In embodiments 3A to 3C, a photoresist layer 47 can be deposited over a top surface of the insulating matrix layer 42. This photoresist layer can be lithographically structured to create an opening in the area shown. In one embodiment, the opening can be rectangular, having a pair of transverse sidewalls along the first horizontal direction hd1 and a pair of longitudinal sidewalls along the second horizontal direction hd2. An anisotropic etching process can be performed to transfer the structure of the opening in the photoresist layer 47 to an upper part of the insulating matrix layer 42. An opening 11 can be created in the upper part of the insulating matrix layer 42. The opening 11 is also referred to as a bottom-gate opening.

[0025] In one embodiment, the width of the aperture 11 along the first horizontal direction hd1 can be from 20 nm to 300 nm, but smaller and larger widths can also be used. In another embodiment, the length of the aperture 11 along the second horizontal direction hd2 can be from 30 nm to 3000 nm, but smaller and larger lengths can also be used. The depth of the aperture 11 can be equal to the thickness of the insulating matrix layer 42. Thus, a top surface of the optional dielectric etch stop layer 636 or a top surface of the planar insulating spacer layer 635 (in some embodiments where the dielectric etch stop layer 636 is not used) ... (Translator's note: English sentence is incomplete). The photoresist layer 47 can then be removed, for example, by peeling.

[0026] In the Fig. In steps 4A to 4C, a hydrogen-blocking dielectric barrier layer 44 can be fabricated over the insulating matrix layer 42, the planar insulating spacer layer 635, and the optional dielectric etch stop layer 636. The hydrogen-blocking dielectric barrier layer 44 comprises a dielectric material that blocks the diffusion of hydrogen through this layer. To provide a continuous hydrogen-blocking structure, the hydrogen-blocking dielectric barrier layer 44 can extend continuously over a bottom and side walls of the opening 11 and over a top surface of the insulating matrix layer 42.

[0027] In one embodiment, the hydrogen-blocking dielectric barrier layer 44 has (or consists of) a dielectric metal oxide coating containing a dielectric metal oxide material. The dielectric metal oxide coating of the hydrogen-blocking dielectric barrier layer 44 can be deposited on the bottom and side walls of the opening 11 and above the top surface of the insulating matrix layer 42. In another embodiment, the dielectric metal oxide coating of the hydrogen-blocking dielectric barrier layer 44 can be deposited directly onto physically exposed surfaces of the insulating matrix layer 42 and a physically exposed surface of the dielectric etch stop layer 636 (or a physically exposed surface of the planar insulating spacer layer 635 in embodiments where no dielectric etch stop layer is used).

[0028] In one embodiment, the dielectric metal oxide coating of the hydrogen-blocking dielectric barrier layer 44 comprises (or consists of) aluminum oxide or a dielectric transition metal oxide. In another embodiment, the hydrogen-blocking dielectric barrier layer 44 comprises, or consists substantially of, a material from the group consisting of aluminum oxide, chromium oxide, titanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, hafnium oxide, and tantalum oxide, a compound thereof, a homogenized mixture thereof, or a stack of layers thereof. In another embodiment, the hydrogen-blocking dielectric barrier layer 44 comprises, or consists substantially of, a material from the group consisting of aluminum oxide, chromium oxide, and hafnium oxide, a homogenized mixture thereof, or a stack of layers thereof.In one embodiment, the hydrogen-blocking dielectric barrier layer 44 comprises, or consists essentially of, a material from the group consisting of chromium oxide and hafnium oxide, a homogenized mixture thereof, or a stack of layers thereof. In another embodiment, the hydrogen-blocking dielectric barrier layer 44 comprises, or consists essentially of, aluminum oxide. The thickness of the hydrogen-blocking dielectric barrier layer 44 can generally be optimized depending on the residual hydrogen content in adjacent dielectric material layers, such as the insulating matrix layer 42. In embodiments where the insulating matrix layer 42 is deposited by atomic layer deposition, the thickness of the hydrogen-blocking dielectric barrier layer 44 can be smaller.In embodiments where the insulating matrix layer 42 is deposited by chemical vapor deposition, the thickness of the hydrogen-blocking dielectric barrier layer 44 can be greater.

[0029] The hydrogen-blocking dielectric barrier 44 can be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), or a combination thereof. In one embodiment, the hydrogen-blocking dielectric barrier 44 can be deposited by PVD to reduce the amount of residual hydrogen atoms introduced into the hydrogen-blocking dielectric barrier 44 during the deposition process. The hydrogen-blocking dielectric barrier 44 can be conformal, i.e., it can have a uniform thickness throughout. In some embodiments, a CVD or ALD process may be preferred for certain materials because they provide conformalization and better thickness control.In other embodiments, however, a PVD process may be preferred for some other materials, as this avoids the introduction of additional hydrogen from a precursor gas. According to one aspect of the present invention, the thickness of the hydrogen-blocking dielectric barrier 44 can be selected such that it can function effectively as a hydrogen-blocking barrier. For example, if the hydrogen-blocking dielectric barrier 44 consists of aluminum oxide, its thickness can be at least 10 nm and preferably at least 12 nm, e.g., at least 15 nm, to function effectively as a hydrogen-blocking structure. In one embodiment, the hydrogen-blocking dielectric barrier 44 consists of aluminum oxide, and its thickness can be from 10 nm to 50 nm, e.g., from 12 nm to 35 nm or from 15 nm to 25 nm.Typically, the hydrogen-blocking dielectric barrier layer 44 can contain one or more of the aforementioned dielectric metal oxide materials, and it can have a thickness of 10 nm to 50 nm, e.g. from 12 nm to 35 nm or from 15 nm to 25 nm.

[0030] In the Fig. In sections 5A to 5C, at least one conductive material can be deposited in a residual volume of the opening 11. This at least one conductive material can, for example, comprise a metallic barrier coating material (such as TiN, TaN, and / or WN) and a metallic filler material (such as Cu, W, Mo, Co, Ru, etc.). However, other suitable metallic coating and filler materials can also be used within the intended scope of protection of the invention. Excess portions of the at least one conductive material can be removed above the horizontal plane containing the top surface of the hydrogen-blocking dielectric barrier layer 44 by a planarization process, which can be a CMP process (CMP: chemical-mechanical polishing) and / or a recess etching process. A lower gate electrode 15 can be fabricated in the opening 11. A CMP process or a recess etching process can be used as the planarization process.A top surface of the lower gate electrode 15 can lie in the same horizontal plane as the top surface of the hydrogen-blocking dielectric barrier 44. In one embodiment, a horizontally extending portion of the hydrogen-blocking dielectric barrier 44 above the insulating matrix layer 42 can have the same thickness as a horizontally extending portion of the hydrogen-blocking dielectric barrier 44 that lies beneath and contacts a bottom surface of the lower gate electrode 15. Alternatively, the horizontally extending portion of the hydrogen-blocking dielectric barrier 44 above the insulating matrix layer 42 can be thinned collaterally during the planarization process.In this embodiment, the horizontally extending portion of the hydrogen-blocking dielectric barrier 44 above the insulating matrix layer 42 can be thinner than the horizontally extending portion of the hydrogen-blocking dielectric barrier 44 that is located beneath and contacts the underside of the lower gate electrode 15. Typically, the thickness of the horizontally extending portion of the hydrogen-blocking dielectric barrier 44 above the insulating matrix layer 42 can range from 10 nm to 50 nm.

[0031] In the Fig. In 6A to 6C, a continuous lower dielectric gate layer and a continuous semiconducting metal oxide layer can be successively deposited as continuous material layers over the hydrogen-blocking dielectric barrier layer 44 and the lower gate electrode 15. The continuous lower dielectric gate layer can be produced by depositing at least one dielectric gate material over the hydrogen-blocking dielectric barrier layer 44 and the lower gate electrode 15. The dielectric gate material can be, among other things, silicon oxide, silicon nitride, a dielectric metal oxide (such as aluminum oxide, hafnium oxide, yttrium oxide, lanthanum oxide, etc.), or a stack thereof. Other suitable dielectric materials are also within the intended scope of protection of the invention. The dielectric gate material is different from the material of the hydrogen-blocking dielectric barrier layer 44.The dielectric gate material can be deposited by ALD or CVD. The thickness of the continuous lower dielectric gate layer can range from 1 nm to 12 nm, e.g., 2 nm to 6 nm, but smaller and larger thicknesses can also be used.

[0032] The continuous semiconducting metal oxide layer can be deposited over the continuous lower dielectric gate layer. In one embodiment, the semiconducting material is a material which, after suitable doping with electrical dopants (p- or n-dopeds), exhibits an electrical conductivity of 1.0 S / m to 1.0 × 10⁻⁶. 5S / m provides. Exemplary semiconducting materials that can be used for the continuous semiconducting metal oxide layer include, among others, indium gallium zinc oxide (IGZO), indium tungsten oxide, indium zinc oxide, indium tin oxide, gallium oxide, indium oxide, doped zinc oxide, doped indium oxide, doped cadmium oxide, and various other doped variants derived therefrom. Other suitable semiconducting materials are also within the intended scope of protection of the invention. In one embodiment, the semiconducting material of the continuous semiconducting metal oxide layer can be indium gallium zinc oxide.

[0033] The continuous semiconducting metal oxide layer can be a polycrystalline semiconducting material or an amorphous semiconducting material that can later be annealed to a polycrystalline semiconducting material with a larger average grain size. The continuous semiconducting metal oxide layer can be deposited by PVD, but other suitable deposition methods can also be used. The thickness of the continuous semiconducting metal oxide layer can range from 1 nm to 100 nm, e.g., 2 nm to 50 nm or 4 nm to 15 nm, but smaller and larger thicknesses are also possible.

[0034] A photoresist layer (not shown) can be deposited over the continuous semiconducting metal oxide layer and subsequently structured lithographically to produce discrete structured photoresist material parts extending across a respective lower gate electrode 15 along the first horizontal direction hd1. In one embodiment, the horizontal cross-sectional shape of each structured part of the photoresist layer can be a rectangle or a rounded rectangle. The structure in the photoresist layer can be transferred across the continuous semiconducting metal oxide layer and the continuous lower dielectric gate layer by performing an anisotropic etching process. Each structured part of the continuous semiconducting metal oxide layer has semiconducting metal oxide plates 20. Each structured part of the continuous lower dielectric gate layer has a lower gate dielectric 10.

[0035] In one embodiment, the horizontal cross-sectional shape of each semiconducting metal oxide plate 20 can be a rectangle or a rounded rectangle. In one embodiment, each semiconducting metal oxide plate 20 can have a transverse dimension along the first horizontal direction hd1 of 60 nm to 1000 nm, e.g., from 100 nm to 300 nm, but smaller and larger transverse dimensions are also possible. In one embodiment, each semiconducting metal oxide plate 20 can have a transverse dimension along the second horizontal direction hd2 of 20 nm to 500 nm, e.g., from 40 nm to 250 nm, but smaller and larger transverse dimensions are also possible. A ratio of the transverse dimension along the first direction hd1 to the transverse dimension along the second direction hd2 in each semiconducting metal oxide plate 20 can be 0.5 to 4, e.g., 1 to 2, but smaller and larger ratios are also possible.Typically, a vertical stack consisting of a lower gate electrode 15, a lower gate dielectric 10, and a semiconducting metal oxide plate 20 can be fabricated over dielectric lower-plane material layers (601, 610, 620) arranged over a substrate 8. The sidewalls of the lower gate dielectric 10 and the semiconducting metal oxide plate 20 can be vertically aligned, i.e., they can lie in the same vertical planes. Subsequently, the photoresist layer can be removed, for example, by peeling.

[0036] In the Fig. In steps 7A to 7C, a hydrogen-blocking dielectric capping barrier layer 46 can be fabricated over the semiconducting metal oxide plate 20. The hydrogen-blocking dielectric capping barrier layer 46 can comprise a dielectric material that can also be used for the hydrogen-blocking dielectric barrier layer 44. To provide a continuous hydrogen-blocking capping structure, the hydrogen-blocking dielectric capping barrier layer 46 can extend continuously over the top and side walls of the semiconducting metal oxide plate 20, over side walls of the lower gate dielectric 10, and directly onto the physically exposed portions of the top surface of the hydrogen-blocking dielectric barrier layer 44.

[0037] In one embodiment, the hydrogen-blocking dielectric capping barrier layer 46 has (or consists of) a dielectric metal oxide coating containing a dielectric metal oxide material. The dielectric metal oxide coating of the dielectric hydrogen-blocking capping barrier layer 46 can be deposited directly onto physically exposed surfaces of the semiconducting metal oxide plate 20, the lower gate dielectric 10, and the lower gate electrode 15.

[0038] In one embodiment, the dielectric metal oxide coating of the hydrogen-blocking dielectric capping barrier layer 46 comprises (or consists of) aluminum oxide or a dielectric transition metal oxide. In another embodiment, the hydrogen-blocking dielectric capping barrier layer 46 comprises, or consists substantially of, a material from the group consisting of aluminum oxide, chromium oxide, titanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, hafnium oxide, and tantalum oxide, a compound thereof, a homogenized mixture thereof, or a stack thereof. In another embodiment, the hydrogen-blocking dielectric capping barrier layer 46 comprises, or consists substantially of, a material from the group consisting of aluminum oxide, chromium oxide, and hafnium oxide, a homogenized mixture thereof, or a stack thereof.In one embodiment, the hydrogen-blocking dielectric capping barrier layer 46 comprises, or consists substantially of, a material from the group consisting of chromium oxide and hafnium oxide, a homogenized mixture thereof, or a stack of layers thereof. In another embodiment, the hydrogen-blocking dielectric capping barrier layer 46 comprises, or consists substantially of, aluminum oxide.

[0039] The hydrogen-blocking dielectric capping barrier layer 46 can be deposited by PVD, CVD, ALD, or a combination thereof. The hydrogen-blocking dielectric capping barrier layer 46 can be conformal, i.e., it can have the same thickness throughout. According to one aspect of the present invention, the thickness of the hydrogen-blocking dielectric capping barrier layer 46 can be selected to be effective as a hydrogen-blocking capping barrier layer. For example, if the hydrogen-blocking dielectric capping barrier layer 46 is made of aluminum oxide, its thickness can be at least 10 nm and preferably at least 12 nm, e.g., at least 15 nm, to function effectively as a hydrogen-blocking capping structure. In one embodiment, the hydrogen-blocking dielectric capping barrier layer 46 is made of aluminum oxide, and its thickness can be from 10 nm to 50 nm, e.g.,The thickness of the hydrogen-blocking dielectric capping barrier layer 46 can range from 12 nm to 35 nm or from 15 nm to 25 nm. Typically, the hydrogen-blocking dielectric capping barrier layer 46 can contain one or more of the aforementioned dielectric metal oxide materials and can have a thickness of 10 nm to 50 nm, e.g., from 12 nm to 35 nm or from 15 nm to 25 nm.

[0040] A dielectric material layer can be deposited over the hydrogen-blocking dielectric capping barrier layer 46. This dielectric material layer is referred to here as a dielectric electrode plane material layer 48. The dielectric electrode plane material layer 48 can comprise a dielectric material such as undoped silicate glass, doped silicate glass, organosilicate glass, or a stack thereof. Optionally, the electrode plane material layer 48 can be planarized to create a flat top surface. The thickness of the dielectric electrode plane material layer 48, measured from the top surface of a portion of the hydrogen-blocking dielectric capping barrier layer 46 that does not have surface coverage with the semiconducting metal oxide plate 20, can range from 100 nm to 1000 nm, e.g., 200 nm to 500 nm, but smaller and larger thicknesses can also be used.The group consisting of the insulating matrix layer 42, the hydrogen-blocking dielectric barrier layer 44, the hydrogen-blocking dielectric capping barrier layer 46 and the dielectric electrode plane material layer 48 is here referred to as a dielectric TFT plane material layer 40 (TFT: thin-film transistor), i.e., a dielectric material layer that lies in the plane of thin-film transistors.

[0041] In the Fig. In components 8A to 8C, a photoresist layer (not shown) can be deposited over the dielectric TFT plane material layer 40, which can then be lithographically structured to create discrete openings. The structure of the discrete openings in the photoresist layer can be transferred via the dielectric electrode plane material layer 48 and the hydrogen-blocking dielectric capping barrier layer 46 by at least one etching process to create a source opening 51, a drain opening 59, and a lower gate through-contact opening 19.The at least one etching process can comprise a first anisotropic etching process in which the material of the dielectric electrode plane material layer 48 is selectively etched with respect to the material of the hydrogen-blocking dielectric capping barrier layer 46, and an isotropic etching process or a second anisotropic etching process in which the material of the hydrogen-blocking dielectric capping barrier layer 46 is selectively etched with respect to the material of the semiconducting metal oxide plate 20.

[0042] The source opening 51 and the drain opening 59 can be generated at opposite ends of the semiconducting metal oxide plate 20 and can be laterally spaced apart from each other along the first horizontal direction hd1. In one embodiment, an end side wall of the semiconducting metal oxide plate 20, extending laterally along the second horizontal direction hd2, and a pair of side wall segments of the semiconducting metal oxide plate 20, extending laterally along the first horizontal direction hd1, can be physically exposed on the underside of the source opening 51 and the drain opening 59.In one embodiment, an end sidewall of the lower gate dielectric 10, extending laterally along the second horizontal direction hd2, and a pair of sidewall segments of the lower gate dielectric 10, extending laterally along the first horizontal direction hd1, can be physically exposed at the bottom of the source opening 51 and the drain opening 59. A rectangular portion of the top surface of the semiconducting metal oxide plate 20 can be physically exposed at the bottom of the source opening 51 and the drain opening 59. A top surface of the lower gate electrode 15 can be physically exposed at a bottom surface of a back-side electrode through-contact opening 19. Subsequently, the photoresist layer can be removed, for example, by peeling it off.

[0043] In the Fig. In 9A to 9C, at least one conductive material can be deposited in the openings (51, 19, 59) and above the dielectric TFT layer material 40. The at least one conductive material can comprise a metallic coating material and a metallic filler material. The metallic coating material can be a conductive metal nitride or a conductive metal carbide such as TiN, TaN, WN, TiC, TaC, and / or WC. The metallic filler material can be W, Cu, Al, Co, Ru, Mo, Ta, Ti, an alloy thereof, and / or a combination thereof. Other suitable materials within the intended scope of protection of the invention can also be used.

[0044] Excess portions of the at least one conductive material above the horizontal plane containing the top surface of the TFT layer material layer 40 can be removed by a planarization process, which may be a CMP process and / or a recess etching process. Other suitable planarization processes may also be used. Any remaining portion of the at least one conductive material filling the source opening 51 forms a source electrode 52. Any remaining portion of the at least one conductive material filling the drain opening 59 forms a drain electrode 56. Any remaining portion of the at least one conductive material filling the backside electrode through-contact opening 19 forms a backside electrode through-contact structure 18 that contacts a top surface of the lower gate electrode 15.

[0045] In one embodiment, each source electrode 52 can have a metallic source coating 53, which is a remaining portion of the metallic coating material, and a metallic source filler material portion 54, which is a remaining portion of the metallic filler material. Each drain electrode 56 can have a metallic drain coating 57, which is a remaining portion of the metallic coating material, and a metallic drain filler material portion 58, which is a remaining portion of the metallic filler material. Each back-side electrode through-contact structure 18 can have a metallic lower-gate contact coating 16, which is a remaining portion of the metallic coating material, and a metallic lower-gate contact filler material portion 17, which is a remaining portion of the metallic filler material.

[0046] The semiconducting metal oxide plate 20 and a group of electrode structures (52, 15, 56) can be fabricated in a dielectric TFT-plane material layer 40. Top surfaces of the source electrode 52, the drain electrode 56, and the lower gate electrode contact structure 18 can lie in a horizontal plane (i.e., be coplanar with it) that contains a top surface of the dielectric TFT-plane material layer 40.

[0047] In the Fig. 10A to 10C can be a first alternative configuration of the first exemplary structure according to the first embodiment of the present invention from the one described in the Fig. The first exemplary structure shown in Figures 9A to 9C can be derived by omitting the fabrication of the hydrogen-blocking dielectric capping barrier layer 46. In this embodiment, the dielectric electrode-plane material layer 48 can be fabricated directly on the semiconducting metal oxide plate 20 and on physically exposed surfaces of the lower gate dielectric 10, the lower gate electrode 42, and the hydrogen-blocking dielectric barrier layer 44.

[0048] In the Fig. 11A to 11C can represent a second alternative configuration of the first exemplary structure according to the first embodiment of the present invention from the one described in the Fig. The first exemplary structure shown in Figures 9A to 9C can be derived by using a layer stack for the hydrogen-blocking dielectric barrier 44. In this embodiment, the hydrogen-blocking dielectric barrier 44 can have a layer stack comprising (from bottom to top) a silicon nitride coating 44A and a dielectric metal oxide coating 44B. The silicon nitride coating 44A comprises (or consists substantially of) silicon nitride and can have a thickness of 2 nm to 20 nm, e.g., 2 nm to 10 nm. The silicon nitride coating 44A is vertically spaced from the semiconducting metal oxide plate 20 by the dielectric metal oxide coating 44B to prevent the formation of charge-trapping states. The dielectric metal oxide coating 44B can comprise a dielectric metal oxide material that can also be used for the dielectric metal oxide coating of the hydrogen-blocking dielectric barrier 44 shown in the figures. Fig. 4A to 4C is shown and has been described with reference to them.

[0049] According to one aspect of the present invention, the thickness of the dielectric metal oxide coating 44B can be selected such that it is effective as a hydrogen-blocking barrier layer. For example, if the dielectric metal oxide coating 44B consists of aluminum oxide, its thickness can be at least 10 nm and preferably at least 12 nm, e.g., at least 15 nm, to function effectively as a hydrogen-blocking structure. In one embodiment, the dielectric metal oxide coating 44B consists of aluminum oxide, and its thickness can be from 10 nm to 50 nm, e.g., from 12 nm to 35 nm or from 15 nm to 25 nm. Generally, the dielectric metal oxide coating 44B can contain one or more of the aforementioned dielectric metal oxide materials, and it can have a thickness of from 10 nm to 50 nm, e.g., from 12 nm to 35 nm or from 15 nm to 25 nm.In one embodiment, the planarization process used to produce the lower gate electrode 15 can be selective for the material of the dielectric metal oxide coating 44B, such that the dielectric metal oxide coating 44B covers and is arranged above a horizontally extending portion of the silicon nitride coating 44A outside the area of ​​the lower gate dielectric 10.

[0050] In the Fig. 12A to 12C can represent a third alternative configuration of the first exemplary structure according to the first embodiment of the present invention from the one described in the Fig. The second alternative configuration of the first exemplary structure shown in Figures 11A to 11C can be derived by omitting the fabrication of the hydrogen-blocking dielectric capping barrier layer 46. In this embodiment, the dielectric electrode-plane material layer 48 can be fabricated directly on the semiconducting metal oxide plate 20 and on physically exposed surfaces of the lower gate dielectric 10, the lower gate electrode 42, and the hydrogen-blocking dielectric barrier layer 44.

[0051] In the Fig. 13A to 13C can represent a fourth alternative configuration of the first exemplary structure according to the first embodiment of the present invention from the one described in the Fig. The first exemplary structure shown in Figures 9A to 9C can be derived by using a layer stack for the hydrogen-blocking dielectric barrier 44. In this embodiment, the hydrogen-blocking dielectric barrier 44 can comprise a layer stack with (from bottom to top) a dielectric metal oxide coating 44B and a silicon nitride coating 44A. The dielectric metal oxide coating 44B can comprise a dielectric metal oxide material that can also be used for the dielectric metal oxide coating of the hydrogen-blocking dielectric barrier 44 shown in the Fig. 4A to 4C is shown and described with reference to them. The silicon nitride coating 44A has silicon nitride (or consists substantially of it) and can have a thickness of 2 nm to 20 nm, e.g., from 2 nm to 10 nm.

[0052] The horizontally extending portion of the silicon nitride coating 44A, located above the insulating matrix layer 42, can be removed during a planarization process used to fabricate the lower gate electrode 15. For example, the planarization process used to fabricate the lower gate electrode 15 may include a CMP step in which the horizontally extending portion of the silicon nitride coating 44A is collaterally removed during the polishing of the at least one metallic material of the lower gate electrode 15. A top surface of the horizontally extending portion of the dielectric metal oxide coating 44B may be physically exposed outside the area of ​​the lower gate electrode 15 after the CMP process.The lower gate dielectric 10, the source electrode 52, the drain electrode 56, and the hydrogen-blocking dielectric capping barrier layer 46 can be directly fabricated on a top surface of the dielectric metal oxide coating 44B. Contact between the silicon nitride coating 44A and the lower gate dielectric 10 can be minimized to two strips extending laterally along the second horizontal direction hd2.

[0053] The processing steps of the Fig. 5A to 9C are executed to produce the fourth alternative configuration of the first exemplary structure, which is described in the Fig. 13A to 13C is shown.

[0054] In the Fig. 14A to 14C can represent a fifth alternative configuration of the first exemplary structure according to the first embodiment of the present invention from the one described in the Fig. The fourth alternative configuration of the first exemplary structure shown in Figures 13A to 13C can be derived by omitting the fabrication of the hydrogen-blocking dielectric capping barrier layer 46. In this embodiment, the dielectric electrode-plane material layer 48 can be fabricated directly on the semiconducting metal oxide plate 20 and on physically exposed surfaces of the lower gate dielectric 10, the lower gate electrode 42, and the hydrogen-blocking dielectric barrier layer 44.

[0055] In the Fig. Figures 15A to 15C show a second exemplary structure according to a second embodiment of the present invention. The second exemplary structure of Fig. 15A to 15C can be the first exemplary structure of the Fig. 6A to 6C are the same.

[0056] In the Fig. In 16A to 16C, an upper gate dielectric 30 can be produced as follows: deposition of a continuous dielectric upper gate layer with a dielectric gate material; structuring of the continuous upper dielectric gate layer, for example, by applying a photoresist layer over the continuous upper dielectric gate layer and subsequently structuring the photoresist layer; and transfer of the structure in the photoresist layer to the continuous upper dielectric gate layer. Unmasked portions of the continuous upper dielectric gate layer can be removed by a selective etching process in which the material of the continuous upper dielectric gate layer is selectively etched with respect to the material of the semiconducting metal oxide plate 20. The selective etching process can be isotropic or anisotropic. The photoresist layer can be removed, for example, by peeling.

[0057] The upper gate dielectric 30 extends over the semiconducting metal oxide plate 20 along the second horizontal direction hd2. The upper gate dielectric 30 can contain the materials that can be used for the lower gate dielectric 10, and it can have a thickness of 1 nm to 12 nm, e.g., from 2 nm to 6 nm, but smaller and larger thicknesses can also be used.

[0058] In the Fig. 17A to 17C can describe the processing steps of the Fig. Steps 7A to 7C are carried out to produce a hydrogen-blocking dielectric capping barrier layer 46 and a dielectric electrode plane material layer 48. The group consisting of the insulating matrix layer 42, the hydrogen-blocking dielectric barrier layer 44, the hydrogen-blocking dielectric capping barrier layer 46, and the dielectric electrode plane material layer 48 is referred to here as a dielectric TFT plane material layer 40, i.e., a dielectric material layer that lies in the plane of thin-film transistors.

[0059] In the Fig. 18A to 18C can describe the processing steps of Fig. 8A to 8C are implemented with a modification of the structure of the openings in the photoresist layer to create a source opening 51, a drain opening 59, a back-side electrode through-hole 19, and an upper-gate electrode opening 39. The source opening 51, the drain opening 59, and the back-side electrode through-hole 19 can each have the same geometry as in the first exemplary structure of the Fig. 8A to 8C. The upper gate electrode opening 39 can be generated in the region of the upper gate dielectric 30. In one embodiment, the upper gate electrode opening 39 can extend across the semiconducting metal oxide plate 20 along the second horizontal direction hd2 with a uniform width along the first direction hd1.

[0060] The source opening 51 and the drain opening 59 can be generated at opposite ends of the semiconducting metal oxide plate 20 and can be spaced apart laterally along the first horizontal direction hd1. In one embodiment, an end side wall of the semiconducting metal oxide plate 20, extending laterally along the second horizontal direction hd2, and a pair of side wall segments of the semiconducting metal oxide plate 20, extending laterally along the first horizontal direction hd1, can each be physically exposed at the underside of the source opening 51 and the drain opening 59, respectively.In one embodiment, an end sidewall of the lower gate dielectric 10, extending laterally along the second horizontal direction hd2, and a pair of sidewall segments of the lower gate dielectric 10, extending laterally along the first horizontal direction hd1, can each be physically exposed at the bottom of the source opening 51 and the drain opening 59. A rectangular portion of the top surface of the semiconducting metal oxide plate 20 can each be physically exposed at the bottom of the source opening 51 and the drain opening 59. A top surface of the lower gate electrode 15 can be physically exposed at a bottom surface of a back-side electrode through-contact opening 19. Subsequently, the photoresist layer can be removed, for example, by peeling it off.

[0061] In the Fig. 19A to 19C describe the processing steps of Fig. Steps 9A to 9C are performed to deposit at least one conductive material in the openings (51, 19, 39, 59) and above the dielectric TFT plane material layer 40, and to remove excess portions of the at least one conductive material above the horizontal plane containing the top surface of the dielectric TFT plane material layer 40. Each remaining portion of the at least one conductive material filling the source opening 51 forms a source electrode 52. Each remaining portion of the at least one conductive material filling the drain opening 59 forms a drain electrode 56. Each remaining portion of the at least one conductive material filling the backside electrode through-contact opening 19 forms a backside electrode through-contact structure 18 that contacts a top surface of the lower gate electrode 15.Each remaining part of the at least one conductive material filling an upper gate electrode opening 39 forms an upper gate electrode 35.

[0062] In one embodiment, each source electrode 52 can have a metallic source coating 53, which is a remaining portion of the metallic coating material, and a metallic source filler material portion 54, which is a remaining portion of the metallic filler material. Each drain electrode 56 can have a metallic drain coating 57, which is a remaining portion of the metallic coating material, and a metallic drain filler material portion 58, which is a remaining portion of the metallic filler material. Each back-side electrode through-contact structure 18 can have a metallic lower-gate contact coating 16, which is a remaining portion of the metallic coating material, and a metallic lower-gate contact filler material portion 17, which is a remaining portion of the metallic filler material.Each upper gate electrode 35 can have a metallic upper gate electrode coating 36, which is a remaining part of the metallic coating material, and a metallic upper gate electrode filler part 37, which is a remaining part of the metallic filler material.

[0063] The semiconducting metal oxide plate 20 and a group of electrode structures (52, 15, 35, 56) can be fabricated in a dielectric TFT-plane material layer 40. Top surfaces of the source electrode 52, the drain electrode 56, the upper gate electrode 35, and the lower gate electrode contact structure 18 can lie in a horizontal plane (i.e., be coplanar with it) that contains a top surface of the dielectric TFT-plane material layer 40.

[0064] In the Fig. 20A to 20C can be a first alternative configuration of the second exemplary structure according to the second embodiment of the present invention from the one described in the Fig. The second exemplary structure shown in Figures 19A to 19C can be derived by omitting the fabrication of the hydrogen-blocking dielectric barrier layer 46. In this embodiment, the dielectric electrode-plane material layer 48 can be fabricated directly on the semiconducting metal oxide plate 20 and on physically exposed surfaces of the lower gate dielectric 10, the lower gate electrode 42, and the hydrogen-blocking dielectric barrier layer 44.

[0065] In the Fig. 21A to 21C can be a second alternative configuration of the second exemplary structure according to the second embodiment of the present invention from the one described in the Fig. The second exemplary structure shown in Figures 19A to 19C can be derived by using a layer stack for the hydrogen-blocking dielectric barrier 44. In this embodiment, the hydrogen-blocking dielectric barrier 44 can comprise a layer stack with (from bottom to top) a silicon nitride coating 44A and a dielectric metal oxide coating 44B. The silicon nitride coating 44A comprises (or consists substantially of) silicon nitride and can have a thickness of 2 nm to 20 nm, e.g., 2 nm to 10 nm. The silicon nitride coating 44A is vertically spaced from the semiconducting metal oxide plate 20 by the dielectric metal oxide coating 44B to prevent the formation of charge-trapping states. The dielectric metal oxide coating 44B can comprise a dielectric metal oxide material that can be used for the dielectric metal oxide coating of the hydrogen-blocking dielectric barrier 44 shown in the figures. Fig. 4A to 4C is shown and has been described with reference to them.

[0066] According to one aspect of the present invention, the thickness of the dielectric metal oxide coating 44B can be selected such that it is effective as a hydrogen-blocking barrier layer. For example, if the dielectric metal oxide coating 44B consists of aluminum oxide, its thickness can be at least 10 nm and preferably at least 12 nm, e.g., at least 15 nm, to function effectively as a hydrogen-blocking structure. In one embodiment, the dielectric metal oxide coating 44B consists of aluminum oxide, and its thickness can be from 10 nm to 50 nm, e.g., from 12 nm to 35 nm or from 15 nm to 25 nm. Generally, the dielectric metal oxide coating 44B can contain one or more of the aforementioned dielectric metal oxide materials, and it can have a thickness of from 10 nm to 50 nm, e.g., from 12 nm to 35 nm or from 15 nm to 25 nm.In one embodiment, the planarization process used to produce the lower gate electrode 15 can be selective for the material of the dielectric metal oxide coating 44B, such that the dielectric metal oxide coating 44B covers and is arranged above a horizontally extending portion of the silicon nitride coating 44A outside the area of ​​the lower gate dielectric 10.

[0067] In the Fig. 22A to 22C can be a third alternative configuration of the second exemplary structure according to the second embodiment of the present invention from the one described in the Fig. The second alternative configuration of the second exemplary structure shown in Figures 21A to 21C can be derived by omitting the fabrication of the hydrogen-blocking dielectric capping barrier layer 46. In this embodiment, the dielectric electrode-plane material layer 48 can be fabricated directly on the semiconducting metal oxide plate 20 and on physically exposed surfaces of the lower gate dielectric 10, the lower gate electrode 42, and the hydrogen-blocking dielectric barrier layer 44.

[0068] In the Fig. 23A to 23C can represent a fourth alternative configuration of the second exemplary structure according to the second embodiment of the present invention from the one described in the Fig. The second exemplary structure shown in Figures 19A to 19C can be derived by using a layer stack for the hydrogen-blocking dielectric barrier 44. In this embodiment, the hydrogen-blocking dielectric barrier 44 can comprise a layer stack with (from bottom to top) a dielectric metal oxide coating 44B and a silicon nitride coating 44A. The dielectric metal oxide coating 44B can comprise a dielectric metal oxide material that can also be used for the dielectric metal oxide coating of the hydrogen-blocking dielectric barrier 44 shown in the figures. Fig. 4A to 4C is shown and described with reference to them. The silicon nitride coating 44A has silicon nitride (or consists substantially of it) and can have a thickness of 2 nm to 20 nm, e.g., from 2 nm to 10 nm.

[0069] The horizontally extending portion of the silicon nitride coating 44A, located above the insulating matrix layer 42, can be removed during a planarization process used to fabricate the lower gate electrode 15. For example, the planarization process used to fabricate the lower gate electrode 15 may include a CMP step in which the horizontally extending portion of the silicon nitride coating 44A is collaterally removed during the polishing of the at least one metallic material of the lower gate electrode 15. A top surface of the horizontally extending portion of the dielectric metal oxide coating 44B may be physically exposed outside the area of ​​the lower gate electrode 15 after the CMP process.The lower gate dielectric 10, the source electrode 52, the drain electrode 56, and the hydrogen-blocking dielectric capping barrier layer 46 can be directly fabricated on a top surface of the dielectric metal oxide coating 44B. Contact between the silicon nitride coating 44A and the lower gate dielectric 10 can be minimized to two strips extending laterally along the second horizontal direction hd2.

[0070] The processing steps of the Fig. 15A to 19C are executed to produce the fourth alternative configuration of the second exemplary structure, which is described in the Fig. 23A to 23C is shown.

[0071] In the Fig. 24A to 24C can be a fifth alternative configuration of the second exemplary structure according to the second embodiment of the present invention from the one described in the Fig. The fourth alternative configuration of the second exemplary structure shown in Figures 23A to 23C can be derived by omitting the fabrication of the hydrogen-blocking dielectric capping barrier layer 46. In this embodiment, the dielectric electrode-plane material layer 48 can be fabricated directly on the semiconducting metal oxide plate 20 and on physically exposed surfaces of the lower gate dielectric 10, the lower gate electrode 42, and the hydrogen-blocking dielectric barrier layer 44.

[0072] In the Fig. 25A to 25C, a third exemplary structure according to a third embodiment of the present invention can be derived by fabricating a layer stack consisting of the hydrogen-blocking dielectric barrier layer 44 and a gate electrode layer 15L. The hydrogen-blocking dielectric barrier layer 44 can have the same material composition and thickness range as in the first and second embodiments. Furthermore, the hydrogen-blocking dielectric barrier layer 44 can be fabricated using the same deposition method as in the first and second embodiments.

[0073] The gate electrode layer 15L comprises the same material as the gate electrode 15 in the first and second embodiments, and it can have the same thickness range. The gate electrode layer 15L can be deposited using a conformal or a non-conformal deposition process such as CVD, PVD, or ALD.

[0074] In the Fig. In Figures 26A to 26C, the gate electrode layer 15L and the hydrogen-blocking dielectric barrier layer 44 can be fabricated as follows: deposition and lithographic structuring of a photoresist layer (not shown); and transfer of the structure in the photoresist layer through the hydrogen-blocking dielectric barrier layer 44 and the gate electrode layer 15L using an anisotropic etching process, such as a reactive ion etching (RIE) process. A structured portion of the gate electrode layer 15L forms a gate electrode 15. Typically, the gate electrode 15 in the third exemplary structure can have the same size and shape as one of the gate electrodes in the first and second exemplary structures. The hydrogen-blocking dielectric barrier layer 44 can have the same size and shape as the gate electrode 15.In one embodiment, a periphery of an upper surface of the hydrogen-blocking dielectric barrier layer 44 can coincide with a periphery of a lower surface of the gate electrode 15.

[0075] An insulating matrix layer 42 can be fabricated as follows: depositing a dielectric material over the stack consisting of the hydrogen-blocking dielectric barrier layer 44 and the gate electrode 15; and removing portions of the deposited dielectric material over a horizontal plane containing the top surface of the gate electrode 15 by a planarization process, such as a CMP process. The top surface of the insulating matrix layer 42 can be coplanar with the top surface of the gate electrode 15. Typically, the hydrogen-blocking dielectric barrier layer 44 can have the same area as the gate electrode 15, and the gate electrode 15 contacts sidewalls of the insulating matrix layer 42 in the third exemplary structure. The insulating matrix layer 42 can have an opening in which a stack consisting of the hydrogen-blocking dielectric barrier layer 44 and the gate electrode 15 is arranged.

[0076] Subsequently, the processing steps, which refer to the Fig. 6A to 14C have been described, for the provision of the in the Fig. The third exemplary structure shown in 27A to 27C, or variants thereof, may be used for which some of the structural elements of the first exemplary structure are used, provided above the horizontal plane containing the top of the insulating matrix layer 42.

[0077] Alternatively, the processing steps that refer to the Fig. 15A to 24C, to provide the alternative embodiment of the third exemplary structure described in the Fig. 28A to 28C is shown, or variants may be used for which some of the structural elements of the first exemplary structure are used, which are provided above the horizontal plane containing the top of the insulating matrix layer 42.

[0078] In Fig. Figure 28 shows an exemplary structure after the fabrication of thin-film transistors. This exemplary structure can be derived from the first exemplary structures shown in the Fig. 9A to 14C are shown, or are derived from the second exemplary structures shown in the Fig. Figures 19A to 24 show that, for example, second metallic via structures 632 can be fabricated through the dielectric TFT plane material layer 40 and a planar insulating spacer layer 635 on each of the second metallic conductor structures 628 simultaneously with, before or after the fabrication of the source electrodes 52, the drain electrodes 56, the optional upper gate electrodes 35 and the back-side electrode via structures 18.

[0079] A dielectric material layer, referred to here as a third dielectric conduction layer material layer 637, can be deposited above the dielectric TFT-plane material layer 40. Third metal conduction structures 638 can be deposited in the third dielectric conduction layer material layer 637 on each of the metallic structures (52, 56, 35, 18) embedded in the dielectric TFT-plane material layer 40.

[0080] Subsequently, further metallic interconnect structures embedded in further dielectric material layers can be fabricated above the thin-film transistors and the third dielectric interconnect layer 637. In an illustrative example, the dielectric material layers can include, for instance, a fourth dielectric interconnect layer 640, a fifth dielectric interconnect layer 650, and so on. The further metallic interconnect structures can include: third metallic via structures (not shown) and fourth metal conductors 648 embedded in the fourth dielectric interconnect layer 640; fourth metallic via structures 652 and fifth metal conductor structures 658 embedded in the fifth dielectric interconnect layer 650; and so on.

[0081] Optionally, memory cells 150 can be fabricated below or above the thin-film transistors, or in the same plane as them. In embodiments where the thin-film transistors are fabricated as a two-dimensional periodic matrix, the memory cells 150 can be fabricated as a two-dimensional periodic matrix of memory cells 150. Each memory cell 150 can have a magnetic tunnel contact, a ferroelectric tunnel contact, a phase-change memory material, or a vacancy-modulated conductive oxide material portion. Furthermore, each memory cell 150 can have a first electrode 126 made of a metallic material and a second electrode 158, which contains a metallic material and protects an underlying data storage portion of the memory cell 150. Between the first electrode 126 (i.e., the lower electrode) and the second electrode 158 (i.e., the upper electrode), the upper electrode) has a storage element.

[0082] In an illustrative example, in embodiments where the memory cell 150 has a magnetic tunnel contact, the memory cell 150 may have a layer stack comprising, from bottom to top: a first electrode 126; a metallic seed layer 128, which enables crystal growth of overlying material layers; a synthetic antiferromagnetic structure (SAF structure) 140; a tunnel barrier layer 146; a free magnetization layer 148; and a second electrode 158. Although the present invention is described with reference to an embodiment in which the thin-film transistors are used as access transistors for memory cells 150, embodiments in which the thin-film transistors are used as logic devices, as components of a peripheral circuit for a memory matrix, or for other semiconductor circuits are also expressly considered.

[0083] In one embodiment, the substrate 8 is a single-crystal silicon substrate. Dielectric lower-level material layers (601, 610, 620) can be arranged between the single-crystal silicon substrate and the insulating matrix layer 42, embedding metallic lower-level interconnect structures (612, 618, 622, 628). Field-effect transistors 701, each comprising a portion of the single-crystal silicon substrate as a channel, can be embedded in the dielectric lower-level material layers (601, 610, 620) and can be electrically connected to at least one of the gate electrodes (15, 35), the source electrodes 52, and the drain electrodes 56.

[0084] Fig. Figure 29 is a flowchart showing general processing steps for manufacturing the semiconductor device of the present invention. In the Fig. For 1 to 5C, 10A to 14C, 15A to 15C, 20A to 24C, and 25A to 27C, a combination of an insulating matrix layer 42, a hydrogen-blocking dielectric barrier layer 44, and a gate electrode 15 can be fabricated over a substrate 8 in a single step 2910. The gate electrode 15 is positioned over a horizontally extending portion of the dielectric hydrogen-blocking barrier layer 44 and is laterally enclosed by the insulating matrix layer 42. For example, an insulating matrix layer 42 can be fabricated over a substrate 8. An opening 11 can be created in an upper portion of the insulating matrix layer 42. A dielectric hydrogen-blocking barrier layer 44 can be fabricated on physically exposed surfaces of the insulating matrix layer 42 in the opening 11 and over a top surface of the insulating matrix layer 42.A gate electrode (such as a lower gate electrode 15) can be fabricated in the opening 11 on the hydrogen-blocking dielectric barrier 44. Alternatively, a stack of a hydrogen-blocking dielectric barrier 44 and a gate electrode 15 can be fabricated over a substrate 8, and subsequently an insulating matrix layer 42 can be fabricated around the stack of the hydrogen-blocking dielectric barrier 44 and the gate electrode 15.

[0085] In the Fig. 6A to 6C, 10A to 14C, 15A to 15C, 20A to 24C and 26A to 27C, a stack of a gate dielectric (such as a lower gate dielectric 10) and a semiconducting metal oxide plate 20 over a gate electrode (such as the lower gate electrode 15) and over horizontally extending parts of the hydrogen-blocking dielectric barrier layer 44 arranged over the insulating matrix layer 42 can be produced in a step 2920.

[0086] In the Fig. 7A to 14C, 16A to 24C and 26A to 27C, a source electrode 52 and a drain electrode 56 can be produced on end parts of the semiconducting metal oxide plate 20 in one step 2930.

[0087] With joint reference to the Fig. 1 to 29 and according to various embodiments of the present invention, a semiconductor device is provided comprising: an insulating matrix layer 42 having an opening 11 and arranged over a substrate 8; a hydrogen-blocking dielectric barrier 44 extending over a horizontal plane that includes a bottom surface of the insulating matrix layer 42; a gate electrode (such as a bottom gate electrode 15) arranged over a portion of the hydrogen-blocking dielectric barrier 44; a stack of a gate dielectric (such as a bottom gate dielectric 10) and a semiconducting metal oxide plate 20 over a top surface of the gate electrode (such as the bottom gate electrode 15) and over horizontally extending portions of the hydrogen-blocking dielectric barrier 44 arranged over the insulating matrix layer 42;and a source electrode 52 and a drain electrode 56, which contact a respective part of a top surface of the semiconducting metal oxide plate 20.;

[0088] In one embodiment, a semiconductor device is provided comprising a thin-film transistor arranged over a substrate 8. The thin-film transistor comprises: an insulating matrix layer 42 having an opening 11 and arranged over the substrate 8; a hydrogen-blocking dielectric barrier 44 extending continuously over a horizontal plane containing a bottom surface of the insulating matrix layer 42, over side walls of the opening, and over a top surface of the insulating matrix layer 42; and a gate electrode (such as a bottom gate electrode 15) arranged in the opening 11 on the hydrogen-blocking dielectric barrier 44.a stack of a gate dielectric (such as a lower gate dielectric 10) and a semiconducting metal oxide plate 20 over a top surface of the gate electrode (such as the lower gate electrode 15) and over horizontally extending portions of the hydrogen-blocking dielectric barrier layer 44 arranged over the insulating matrix layer 42; and a source electrode 52 and a drain electrode 56 contacting respective portions of a top surface of the semiconducting metal oxide plate 20.

[0089] In one embodiment, the source electrode 52 is arranged above a horizontally extending first part of the hydrogen-blocking dielectric barrier layer 44, and the drain electrode 56 is arranged above a horizontally extending second part of the hydrogen-blocking dielectric barrier layer 44, which is laterally spaced from the horizontally extending first part of the hydrogen-blocking dielectric barrier layer 44 by a horizontally extending intermediate part of the hydrogen-blocking dielectric barrier layer 44, which is arranged below the gate electrode (such as the lower gate electrode 15).

[0090] In one embodiment, the hydrogen-blocking dielectric barrier layer 44 has (or consists of) a dielectric metal oxide coating (44 or 44B) with a dielectric metal oxide material, and it is in contact with a first region of a bottom surface of the gate dielectric (such as the lower gate dielectric 10) under the source electrode 52 and in contact with a second region of the bottom surface of the gate dielectric (such as the lower gate dielectric 10) which is located under the drain electrode 56 and is spaced laterally from the first region of the bottom surface of the gate dielectric (such as the lower gate dielectric 10) by the gate electrode (such as the lower gate electrode 15).

[0091] In one embodiment, the dielectric metal oxide coating (which is referred to as the hydrogen-blocking dielectric barrier layer 44) is in the Fig. 9A to 10C and 19A to 20C or as the dielectric metal oxide coating 44B in the Fig. 13A to 14C and 23A to 24C is embodied) in direct contact with the insulating matrix layer 42 on the side walls of the opening 11.

[0092] In one embodiment, the hydrogen-blocking dielectric barrier layer 44 has a silicon nitride coating 44A in direct contact with the insulating matrix layer 42 on the side walls of the opening 11, as shown in the Fig. 11A to 12C and 21A to 22C are shown.

[0093] In one embodiment, the hydrogen-blocking dielectric barrier layer 44 has a silicon nitride coating 44A in contact with the gate electrode (such as the lower gate electrode 15), which is spaced apart from the insulating matrix layer 42 by the dielectric metal oxide coating 44B, as shown in the Fig. 13A to 14C and 23A to 24C are shown.

[0094] In one embodiment, the dielectric metal oxide coating (44 or 44B) comprises aluminium oxide or a dielectric transition metal oxide.

[0095] In one embodiment, the semiconductor device further comprises a hydrogen-blocking dielectric capping barrier layer 46 which contains a dielectric metal oxide encapsulation material and contacts part of a top surface of part of the semiconducting metal oxide plate 20.

[0096] In one embodiment, each surface of the semiconducting metal oxide plate 20 is in contact with a respective surface of the gate dielectric (such as the lower gate dielectric 10), the source electrode 52 and the drain electrode 56 and a bottom surface of the hydrogen-blocking dielectric capping barrier layer 46.

[0097] In one embodiment, the source electrode 52 contacts a first side wall of the gate dielectric (such as the lower gate dielectric 10), a first end side wall of the semiconducting metal oxide plate 20 and a first region of a top surface of the semiconducting metal oxide plate 20, and the drain electrode 56 contacts a second side wall of the gate dielectric (such as the lower gate dielectric 10), a second end side wall of the semiconducting metal oxide plate 20 and a second region of the top surface of the semiconducting metal oxide plate 20.

[0098] According to another aspect of the present invention, a semiconductor device is provided which has a thin-film transistor arranged over a substrate.The thin-film transistor comprises: an insulating matrix layer 42 having an opening 11 and arranged over a substrate 8; a hydrogen-blocking dielectric barrier layer 44 extending continuously over a bottom and side walls of the opening 11 and over a top surface of the insulating matrix layer 42; a lower gate electrode 15 arranged in the opening 11 on the hydrogen-blocking dielectric barrier layer 44; a stack of a lower gate dielectric 10 and a semiconducting metal oxide plate 20 over a top surface of the lower gate electrode 15 and over horizontally extending portions of the hydrogen-blocking dielectric barrier layer 44 arranged over the insulating matrix layer 42; a stack of an upper gate dielectric 30 and an upper gate electrode 35 arranged over the lower gate electrode 15 and in a top view (i.e.,, in a transparent representation along the vertical direction, which is perpendicular to the top of the substrate 8) has an area coverage with the lower gate electrode 15; and a source electrode 52 and a drain electrode 56, which contact a respective part of a top of the semiconducting metal oxide plate 20.

[0099] In one embodiment, the semiconductor device comprises: a dielectric material layer (such as a dielectric electrode plane material layer 48) that laterally surrounds the stack of the lower gate dielectric 10 and the semiconducting metal oxide plate 20; and a backside electrode through-contact structure 18 that contacts a top surface of the lower gate electrode 15, wherein top surfaces of the source electrode 52, the drain electrode 56, the upper gate electrode 35 and the backside electrode through-contact structure 18 lie in a horizontal plane that contains a top surface of the dielectric material layer (such as the dielectric electrode plane material layer 48).

[0100] In one embodiment, the hydrogen-blocking dielectric barrier layer 44 has a dielectric metal oxide coating (44 or 44B) with a dielectric metal oxide material in contact with a first region of a bottom surface of the lower gate dielectric 10 and in contact with a second region of the bottom surface of the lower gate dielectric 10, which is spaced laterally from the first region of the bottom surface of the lower gate dielectric 10 by the lower gate electrode 15.

[0101] In one embodiment, the semiconductor device further comprises a hydrogen-blocking dielectric capping barrier layer 46, which contacts a first part of a top surface of the semiconducting metal oxide plate 20, which is arranged between the upper gate dielectric 30 and the source electrode 52, and a second part of the top surface of the semiconducting metal oxide plate 20, which is arranged between the upper gate dielectric 30 and the drain electrode 56.

[0102] The various embodiments of the present invention can be used to reduce hydrogen diffusion into the semiconducting metal oxide plate 20 by providing hydrogen diffusion barrier structures comprising the hydrogen-blocking dielectric barrier layer 44, the optional hydrogen-blocking dielectric capping barrier layer 46, the source electrode 52, the drain electrode 56, and the optional upper gate electrode 35. By blocking hydrogen diffusion into the semiconducting metal oxide plate 20, changes in the electronic surface states of the semiconducting metal oxide plate 20 are prevented, and thus the properties of the thin-film transistor are kept constant throughout its lifetime.

Claims

[1] Semiconductor device with: an insulating matrix layer (42) which has an opening (11) and is arranged over a substrate (8); a hydrogen-blocking dielectric barrier layer (44) extending over a horizontal plane containing a bottom side of the insulating matrix layer (42); a gate electrode (15) which is arranged in the opening (11) on the hydrogen-blocking dielectric barrier layer (44); a stack of a gate dielectric (10) and a semiconducting metal oxide plate (20) above a top surface of the gate electrode (15) and above horizontally extending portions of the hydrogen-blocking dielectric barrier layer (44) arranged above the insulating matrix layer (42); and a source electrode (52) and a drain electrode (56) that contact respective parts of a top side of the semiconducting metal oxide plate (20), wherein the hydrogen-blocking dielectric barrier layer (44) has a dielectric metal oxide coating (44B) with a dielectric metal oxide material in contact with a first region of a bottom surface of the gate dielectric (10) below the source electrode (52) and in contact with a second region of the bottom surface of the gate dielectric (10) which is located below the drain electrode (56) and is spaced laterally from the first region of the bottom surface of the gate dielectric (10) by the gate electrode (15), wherein the hydrogen-blocking dielectric barrier layer (44) has a silicon nitride coating (44A) which is in contact with the gate electrode (15) and is spaced apart from the insulating matrix layer (42) by the dielectric metal oxide coating (44B). [2] Semiconductor device according to claim 1, wherein the dielectric metal oxide coating (44B) extends continuously over side walls of the opening (11) and over a top surface of the insulating matrix layer (42). [3] Semiconductor device according to claim 1 or 2, wherein the source electrode (52) is arranged above a horizontally extending first part of the dielectric metal oxide coating (44B), and the drain electrode (56) is arranged above a horizontally extending second part of the dielectric metal oxide coating (44B), which is laterally spaced from the horizontally extending first part of the dielectric metal oxide coating (44B) by a horizontally extending intermediate part of the dielectric metal oxide coating (44B) which is arranged below the gate electrode (15). [4] Semiconductor device according to any of the preceding claims, wherein the dielectric metal oxide coating (44B) comprises aluminium oxide or a dielectric transition metal oxide. [5] Semiconductor device according to one of the preceding claims, further comprising a hydrogen-blocking dielectric capping barrier layer (46) containing a dielectric metal oxide encapsulation material and contacting part of a top surface of part of the semiconducting metal oxide plate (20). [6] Semiconductor device according to claim 5, wherein each surface of the semiconducting metal oxide plate (20) is in contact with a respective surface selected from a top surface of the gate dielectric (10), surfaces of the source electrode (52), surfaces of the drain electrode (56) and a bottom surface of the hydrogen-blocking dielectric capping barrier layer (46). [7] Semiconductor device according to any one of the preceding claims, wherein the source electrode (52) contacts a first side wall of the gate dielectric (10) and a first region of a top surface of the semiconducting metal oxide plate (20), and the drain electrode (56) contacts a second side wall of the gate dielectric (10) and a second area of ​​the top of the semiconducting metal oxide plate (20). [8] Semiconductor device according to any of the preceding claims, wherein the substrate (8) comprises a single-crystal silicon substrate, dielectric lower plane material layers (601, 610, 620) embedding metallic lower plane interconnect structures (612, 618, 622, 628) are arranged between the single-crystal silicon substrate (8) and the insulating matrix layer (42), and Field-effect transistors (701), which have a respective part of the single-crystal silicon substrate (8) as a channel, are embedded in the dielectric lower-level material layers (601, 610, 620) and are electrically connected to the gate electrode (15), the source electrode (52) and / or the drain electrode (56). [9] Semiconductor device with a thin-film transistor arranged over a substrate (8), wherein the thin-film transistor has the following features: an insulating matrix layer (42) which has an opening (11) and is arranged over the substrate (8); a hydrogen-blocking dielectric barrier layer (44) extending over a horizontal plane containing a bottom surface of the insulating matrix layer (42), over side walls of the opening (11) and over a top surface of the insulating matrix layer (42); a lower gate electrode (15) which is arranged in the opening (11) on the hydrogen-blocking dielectric barrier layer (44); a stack of a lower gate dielectric (10) and a semiconducting metal oxide plate (20) over a top surface of the lower gate electrode (15) and over horizontally extending portions of the hydrogen-blocking dielectric barrier layer (44) arranged over the insulating matrix layer (42); a stack consisting of an upper gate dielectric (30) and an upper gate electrode (35) arranged above the lower gate electrode (15) and having a surface overlap with the lower gate electrode (15) in a top view; and a source electrode (52) and a drain electrode (56) that contact a respective part of a top surface of the semiconducting metal oxide plate (20), wherein the hydrogen-blocking dielectric barrier layer (44) comprises a dielectric metal oxide coating (44B) with a dielectric metal oxide material which extends continuously over the horizontal plane containing the bottom of the insulating matrix layer (42), over side walls of the opening (11) and over the top of the insulating matrix layer (42) and is in contact with a first region of a bottom of the lower gate dielectric (10) and in contact with a second region of the bottom of the lower gate dielectric (10) which is laterally spaced from the first region of the bottom of the lower gate dielectric (10) by the lower gate electrode (15), wherein the hydrogen-blocking dielectric barrier layer (44) has a silicon nitride coating (44A) which is in contact with the lower gate electrode (15) and is spaced apart from the insulating matrix layer (42) by the dielectric metal oxide coating (44B). [10] Semiconductor device according to claim 9, further comprising: a dielectric material layer (48) that laterally surrounds the stack of the lower gate dielectric (10) and the semiconducting metal oxide plate (20); and a backside electrode through-contact structure (18) that contacts a top side of the lower gate electrode (15), wherein top sides of the source electrode (52), the drain electrode (56), the upper gate electrode (35) and the backside electrode through-contact structure (18) lie in a horizontal plane that contains a top side of the dielectric material layer (48). [11] Semiconductor device according to claim 9 or 10, further comprising a hydrogen-blocking dielectric capping barrier layer (46) that contacts a first part of a top surface of the semiconducting metal oxide plate (20) located between the upper gate dielectric (30) and the source electrode (52), and a second part of the top surface of the semiconducting metal oxide plate (20) located between the upper gate dielectric (30) and the drain electrode (56). [12] Method for manufacturing a semiconductor device comprising the following steps: Producing a combination of an insulating matrix layer (42), a hydrogen-blocking dielectric barrier layer (44) and a gate electrode (15) over a substrate (8), wherein the gate electrode (15) is arranged over a horizontally extending part of the hydrogen-blocking dielectric barrier layer (44) and is enclosed laterally by the insulating matrix layer (42); Forming a stack of a gate dielectric (10) and a semiconducting metal oxide plate (20) over the gate electrode (15) and over horizontally extending portions of the hydrogen-blocking dielectric barrier layer (44) arranged over the insulating matrix layer (42); and Producing a source electrode (52) and a drain electrode (56) on end parts of the semiconducting metal oxide plate (20), where: the hydrogen-blocking dielectric barrier layer (44) has a dielectric metal oxide coating (44B) with a dielectric metal oxide material, the gate dielectric (10) is produced directly on horizontally extending parts of the dielectric metal oxide coating (44B), and the hydrogen-blocking dielectric barrier layer (44) has a silicon nitride coating (44A) which is in contact with the gate electrode (15) and is spaced apart from the insulating matrix layer (42) by the dielectric metal oxide coating (44B). [13] The method of claim 12, further comprising generating an opening (11) in an upper part of the insulating matrix layer (42) prior to producing the hydrogen-blocking dielectric barrier layer (44), wherein the dielectric metal oxide coating (44B) is produced on physically exposed surfaces of the insulating matrix layer (42) in the opening (11) and over a top surface of the insulating matrix layer (42), and the gate electrode (15) is produced in the opening (11) on the silicon nitride coating (44A). [14] Method according to claim 12 or 13, wherein the gate dielectric is produced directly on a top surface of the gate electrode. [15] Method according to any one of claims 12 to 14, wherein the dielectric metal oxide coating (44B) comprises aluminium oxide or a dielectric transition metal oxide. [16] Method according to any one of claims 12 to 15, further comprising producing a hydrogen-blocking dielectric capping barrier layer (46) comprising a further dielectric metal oxide material on a top side of part of the semiconducting metal oxide plate (20). [17] Method according to any one of claims 12 to 16, further comprising producing a dielectric material layer (48) over the semiconducting metal oxide plate (20) directly on a part of a top surface of the dielectric metal oxide coating (44B), wherein the source electrode (52) and the drain electrode (56) are produced through the dielectric material layer (48).

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