METALLGATE FIN ELECTRODE STRUCTURE AND METHOD

Abstract

Procedure with the following steps: Forming a fin (66) over a substrate (50); Creating a dummy gate structure over the fin (66); Creating a source / drain area on each side of the dummy gate structure; Deposition of a first interlayer dielectric over the source / drain region; Removing the first interlayer dielectric and creating a self-aligning mask (89) over the first interlayer dielectric; Performing a gate replacement cycle to replace the dummy gate structure with a replacement metal gate, wherein the gate replacement cycle includes the following: Removing the dummy gate structure to create an initial recess (86), Deposition of a gate dielectric (101, 103) in the first recess (86), Creating a metal gate (105) over the gate dielectric (101, 103), Deposition of a metallic filler material (109) over the metal gate (105), and Etching back the gate dielectric (101, 103), the metal gate (105) and the metallic filler material (109) to produce an electrode fin from the metallic filler material (109); and Providing a gate contact (124) that contacts a side wall of the electrode fin, wherein the electrode fin has a seam (111) extending downwards along the electrode fin.

Description

background

[0001] Semiconductor devices are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by successively depositing insulating or dielectric material layers, conductive material layers, and semiconductor material layers onto a semiconductor substrate. The different material layers are then structured by lithography to create circuit components and elements on the substrate.

[0002] The semiconductor industry is constantly improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the smallest feature size, thus enabling the integration of more components in a given area. However, reducing the smallest feature size introduces further problems that need to be addressed.

[0003] US Patent 2017 / 0194209 A1 discloses a process for manufacturing a semiconductor device in which a dummy gate structure is formed over a substrate. A first insulating layer is formed over the dummy gate structure. The dummy gate structure is removed to form a gate space within the first insulating layer. A first conductive layer is formed within the gate space to create a reduced gate space. The reduced gate space is filled with a second conductive layer made of a different material than the first conductive layer. The filled first conductive layer and the second conductive layer are recessed to form a first gate recess. A third conductive layer is formed over the first conductive layer and the second conductive layer within the first gate recess.After deepening the filled first conductive layer and the second conductive layer, the second conductive layer protrudes from the first conductive layer.

[0004] US Patent 2021 / 0028290 A1 discloses a semiconductor device comprising a channel component of a transistor and a gate component arranged above the channel component. The gate component comprises: a dielectric layer, a first exit-work metal layer arranged above the dielectric layer, a filler metal layer arranged above the first exit-work metal layer, and a second exit-work metal layer arranged above the filler metal layer.

[0005] The invention is defined in the claims. Brief description of the drawings

[0006] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. Rather, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 shows an example of a nanostructured field-effect transistor (nano-FET) in a three-dimensional representation according to some embodiments. The Fig. 2A, Fig. 2B, Fig. 2C, Fig. 2D, Fig. 2E, Fig. 3A, Fig. 3B, Fig. 3C, Fig. 4A, Fig. 4B, Fig. 5A, Fig. 5B, Fig. 6A, Fig. 6B, Fig. 6C, Fig. 7A, Fig. 7B, Fig. 7C, Fig. 8, Fig. 9, Fig. 10A, Fig. 10B, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15A, Fig. 15B, Fig. 16, Fig. 17, Fig. 18A, Fig. 18B, Fig. 18C, Fig. 19A, Fig. 19B, Fig. 19C, Fig. 19D, Fig. 20A, Fig. 20B, Fig. 20C and Fig. Figures 20D show sectional views of intermediate stages in the fabrication of nano-FETs according to some embodiments. The Fig. 21A, Fig. 21B, Fig. 21C and Fig. Figures 21D are sectional views of a nano-FET according to embodiments. The Fig. 22A, Fig. 22B, Fig. 22C and Fig. Figures 22D are sectional views of a FinFET according to some embodiments. Detailed description

[0007] The disclosure below provides many different embodiments or examples for implementing various features of the disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the fabrication of a first element over or on top of a second element in the description below may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, such that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present disclosure.This repetition serves the purpose of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed.

[0008] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. These spatially relative terms are intended to encompass orientations of the device in use or operation beyond the orientation shown in the figures. The device may be oriented differently (rotated by 90° or in a different orientation), and the spatially relative descriptors used here can be interpreted accordingly.

[0009] As the gate distance decreases in advanced technology nodes, the use of self-aligned contacts becomes essential. However, the use of self-aligned contacts increases the risk of an end structure being etched in a way that could cause undesirable electrical problems. Therefore, the structures should be designed to help avoid such undesirable outcomes. In some embodiments, a larger gate contact is provided for reduced gate resistance in a self-aligned contact scheme. If a spare gate electrode is recessed to accommodate a gate mask, a gate-filling portion of the gate contact is etched to create a finned gate electrode. When a subsequently fabricated gate contact is made with the finned gate electrode, the increased area results in reduced gate resistance.And since the height of a dielectric low-k layer can be controlled with respect to the fin-gate electrode, the gap-filling area above the fin-gate electrode can also be controlled for the contact subsequently produced.

[0010] Some embodiments are described below in a specific context, namely with a die featuring nanoFETs. However, various embodiments can also be used for dies featuring other types of transistors, such as fin field-effect transistors (FinFETs), planar transistors, or the like, instead of or in combination with the nanoFETs. Some embodiments are also described below in connection with FinFETs.

[0011] Fig. Figure 1 shows an example of nanoFETs, e.g., nanowire FETs, nanolayer FETs (nanoFETs), or the like, in a three-dimensional representation according to some embodiments. The nanoFETs have nanostructures 55 (e.g., nanolayers, nanowires, or the like) over fins 66 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructures 55 function as channel regions for the nanoFETs. The nanostructures 55 can be p-nanostructures, n-nanostructures, or a combination thereof. Insulation regions 68 are arranged between adjacent fins 66, which can extend beyond and project between adjacent insulation regions 68. Although the isolation regions 68 are described / represented as regions that are separated from the substrate 50, the term ‘substrate’ used here can refer to the semiconductor substrate alone or to a combination of the semiconductor substrate and the isolation regions.And although a lower part of the fins 66 is depicted as individual materials associated with the substrate 50, the lower part of the fins 66 and / or the substrate 50 can consist of only one material or of a plurality of materials. In this context, the fins 66 refer to the part that extends between adjacent insulation areas 68.

[0012] Dielectric gate layers 100 are arranged over the top surfaces of the fins 66 and along the top, side, and bottom surfaces of the nanostructures 55. Gate electrodes 102 are located above the dielectric gate layers 100. Source / drain epitaxy regions 92 are arranged on the fins 66 on opposite sides of the dielectric gate layers 100 and the gate electrodes 102.

[0013] Fig. Figure 1 also shows reference cross-sections that are used in later figures. A cross-section A - A' runs along a longitudinal axis of a gate electrode 102 and in a direction that is, for example, perpendicular to the direction of current flow between source / drain epitaxy regions 92 of a nanoFET. A cross-section B - B' is perpendicular to cross-section A - A' and parallel to a longitudinal axis of a fin 66 of the nanoFET and runs in a direction of, for example, current flow between the source / drain epitaxy regions 92 of the nanoFET. A cross-section C - C' is parallel to cross-section A - A' and passes through the source / drain epitaxy regions 92 of the nanoFETs. For clarity, subsequent figures refer to these reference cross-sections.

[0014] Some embodiments discussed here relate to nanoFETs fabricated using a gate-last process. Other embodiments may employ a gate-first process. Furthermore, some embodiments consider aspects used in planar devices, such as planar FETs, or in fin field-effect transistors (FinFETs).

[0015] The Fig. Figures 2 to 20D are sectional views of intermediate stages in the fabrication of nanoFETs according to some embodiments. Fig. 2A, Fig. 2B, Fig. 2C, Fig. 2D, Fig. 2E, Fig. 3C, Fig. 6A, Fig. 7A, Fig. 10A, Fig. 18A, Fig. 19A and Fig. 20A shows the reference cross-section A - A', which is in Fig. 1 is shown. Fig. 3B, Fig. 4B, Fig. 5B, Fig. 6B, Fig. 7B, Fig. 8, Fig. 9, Fig. 10B, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15A, Fig. 15B, Fig. 16, Fig. 17, Fig. 18B, Fig. 19B and Fig. 20B shows the reference cross-section B - B', which is in Fig. 1 is shown. Fig. 3A, Fig. 4A, Fig. 5A, Fig. 6C, Fig. 7C, Fig. 18C, Fig. 19D and Fig. 20D shows the reference cross-section C - C', which is in Fig. 1 is shown. Fig. 19C and Fig. 20C show reference cross-sections that correspond to the one in Fig. 1 shown reference cross-section B - B' are parallel.

[0016] In the Fig. 2A and Fig. In step 2B, a substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a solid semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p- or n-type dopant) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. In general, an SOI substrate comprises a layer of semiconductor material fabricated on an insulating layer. The insulating layer may be, for example, a buried oxide layer (BOX layer), a silicon oxide layer, or the like. The insulating layer is fabricated on a substrate, most often a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used.In some embodiments, the semiconductor material of substrate 50 may comprise: silicon; germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor, such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide phosphide; or combinations thereof.

[0017] The substrate 50 has an n-region 50N and a p-region 50P. The n-region 50N can be used to fabricate n-type devices, such as NMOS transistors, e.g., n-nanoFETs, and the p-region 50P can be used to fabricate p-type devices, such as PMOS transistors, e.g., p-nanoFETs. The n-region 50N can be physically separated from the p-region 50P (as represented by a divider 20), and any number of device elements (e.g., other active devices, doped regions, isolation structures, etc.) can be arranged between the n-region 50N and the p-region 50P. Although only one n-range 50N and one p-range 50P are shown, any number of n-ranges 50N and p-ranges 50P can be provided.

[0018] In the Fig. 2A and Fig. In step 2B, a multilayer stack is fabricated over substrate 50, which is then structured to form nanostructures 55. The multilayer stack comprises alternating layers of first semiconductor layers and second semiconductor layers. As explained below, the first semiconductor layers are structured during the fabrication of the nanostructures 55 to create first nanostructures 52A to 52C (collectively referred to as first nanostructures 52). The second semiconductor layers are structured during the fabrication of the nanostructures 55 to create second nanostructures 54A to 54C (collectively referred to as second nanostructures 54). For illustrative purposes, and as explained in more detail later, the second semiconductor layers are removed and the first semiconductor layers are structured to create channel regions of nano-FETs in the p-region 50P.Furthermore, the first semiconductor layers are removed and the second semiconductor layers are structured to create channel regions of nano-FETs in the n-region 50N. However, in some embodiments, the first semiconductor layers can be removed and the second semiconductor layers can be structured to create channel regions of nano-FETs in the n-region 50N, and the second semiconductor layers can be removed and the first semiconductor layers can be structured to create channel regions of nano-FETs in the p-region 50P.

[0019] In further embodiments, the first semiconductor layers can be removed and the second semiconductor layers can be structured to create channel regions of nano-FETs in the n-region 50N and the p-region 50P. In other embodiments, the second semiconductor layers can be removed and the first semiconductor layers can be structured to create channel regions of nano-FETs in the n-region 50N and the p-region 50P. In some embodiments, the channel regions in the n-region 50N and the p-region 50P can have the same material composition (e.g., silicon or another semiconductor material) and can be fabricated simultaneously. Fig. 21A, Fig. 21B, Fig. 21C and Fig. Figure 21D shows a structure resulting from embodiments in which the channel regions in the p-region 50P and the n-region 50N, for example, have silicon.

[0020] The multilayer stack, structured as the nanostructures 55, is shown for illustrative purposes as a stack with three layers, each consisting of the first semiconductor layers (corresponding, for example, to the first nanostructures 52) and the second semiconductor layers (corresponding, for example, to the second nanostructures 54). In some embodiments, the multilayer stack (before structuring as nanostructures 55) can comprise any number of first and second semiconductor layers. Each of the layers of the multilayer stack can be epitaxially grown using a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), vapor-phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like.In various embodiments, the first semiconductor layers (corresponding to the first nanostructures 52) can be made from a first semiconductor material suitable for p-nanoFETs, such as silicon germanium or the like, and the second semiconductor layers (corresponding to the second nanostructures 54) can be made from a second semiconductor material suitable for n-nanoFETs, such as silicon, silicon-carbon, or the like. For illustrative purposes, the multilayer stack (structured as the nanostructures 55) is shown as a stack with a bottommost semiconductor layer suitable for p-nanoFETs. In some embodiments, the multilayer stack can be fabricated such that the bottommost layer is a semiconductor layer suitable for n-nanoFETs.

[0021] The first and second semiconductor materials can be materials with high etch selectivity with respect to each other. Therefore, the first semiconductor layers can be removed from the first semiconductor material without significantly removing the second semiconductor layers from the second semiconductor material in the n-region (50N), allowing the second semiconductor layers to be structured to create channel regions of n-nanoFETs. Similarly, the second semiconductor layers can be removed from the second semiconductor material without significantly removing the first semiconductor layers from the first semiconductor material in the p-region (50P), allowing the first semiconductor layers to be structured to create channel regions of p-nanoFETs.

[0022] Let's stick with the Fig. 2A and Fig. 2B, in which, in some embodiments, fins 66 are fabricated in the substrate 50 and nanostructures 55 are fabricated from the multilayer stack. In some embodiments, the nanostructures 55 and the fins 66 can be fabricated in the multilayer stack and the substrate 50, respectively, by etching trenches in the multilayer stack and the substrate 50, respectively. The etching can be performed using any suitable etching method, such as reactive ion etching (RIE), neutral beam etching (NBE), or the like, or a combination thereof. The etching can be anisotropic. By fabricating the nanostructures 55 by etching the multilayer stack, first nanostructures 52A to 52C (collectively referred to as first nanostructures 52) can be defined from the first semiconductor layers, and second nanostructures 54A to 54C (collectively referred to as second nanostructures 54) can be defined from the second semiconductor layers.The first nanostructures 52 and the second nanostructures 54 can in turn be collectively referred to as nanostructures 55.

[0023] The fins 66 and the nanostructures 55 can be structured using any suitable method. For example, the fins 66 and the nanostructures 55 can be structured using one or more photolithography processes, such as dual or multiple structuring processes. In general, dual or multiple structuring processes combine photolithographic and self-aligning processes, enabling the creation of structures with, for example, grid spacings smaller than those achievable with a single direct photolithography process. For example, in one embodiment, a sacrificial layer is produced over a substrate and then structured using a photolithography process. Spacers are produced along the structured sacrificial layer using a self-aligning process.The sacrificial layer is then removed, and the remaining spacers can then be used to structure the fins 66.

[0024] For illustrative purposes, the fins 66 in the n-region 50N and the p-region 50P are shown as having essentially the same widths. In some embodiments, the widths of the fins 66 in the n-region 50N may be greater or smaller than those of the fins 66 in the p-region 50P. Furthermore, while the fins 66 and the nanostructures 55 are each shown with a uniform width, in other embodiments the fins 66 and / or the nanostructures 55 may have conical sidewalls, such that the width of each of the fins 66 and / or the nanostructures 55 increases continuously in one direction towards the substrate 50. In these embodiments, each of the nanostructures 55 may have a different width and be trapezoidal.

[0025] After structuring the fins 66, STI regions 68 (STI: shallow trench insulation) are created adjacent to the fins 66. The STI regions 68 can be created by depositing an insulating material over the substrate 50, the fins 66, and the nanostructures 55, and between adjacent fins 66. The insulating material can be an oxide, such as silicon dioxide, a nitride, or the like, or a combination thereof, and can be deposited by high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD), or the like, or a combination thereof. Other insulating materials deposited by a suitable method can also be used. In the illustrated embodiment, the insulating material is silicon dioxide deposited by an FCVD process. After the insulating material has been deposited, an annealing process can be carried out.In one embodiment, the insulating material is deposited such that excess insulating material covers the nanostructures 55. Although the insulating material is shown as a single layer, several layers can be used in some embodiments. For example, in some embodiments, a coating (not shown individually) can first be produced along the surfaces of the substrate 50, the fins 66, and the nanostructures 55. Subsequently, a filler material, such as one of those mentioned above, can be deposited over the coating.

[0026] A removal process is then performed on the insulating material to remove excess insulating material covering the nanostructures 55. In some embodiments, a planarization process, such as chemical-mechanical polishing (CMP), a back-etching process, a combination thereof, or the like, can be used. The planarization process exposes the nanostructures 55 so that the top surfaces of the nanostructures 55 and the insulating material are at the same level after completion of the planarization process.

[0027] The insulating material is then recessed to create the STI regions 68. The insulating material is recessed such that upper portions of the fins 66 protrude between adjacent STI regions 68 in the n-region 50N and the p-region 50P. The top surfaces of the STI regions 68 can be flat, as shown, convex, concave (such as "dishing"), or a combination thereof. The top surfaces of the STI regions 68 can be produced flat, convex, and / or concave by suitable etching. The STI regions 68 can be recessed using a suitable etching process, such as one that is selective for the insulating material (e.g., one that etches the insulating material at a higher rate than the material of the fins 66 and the nanostructures 55). For example, oxide removal can be performed. B. using dilute hydrofluoric acid (dHF acid).

[0028] The method described above is only one example of how the fins 66 and the nanostructures 55 can be fabricated. In some embodiments, the fins 66 and / or the nanostructures 55 can be fabricated using a mask and an epitaxial growth process. For example, a dielectric layer can be fabricated over a top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures can be grown epitaxially in the trenches, and the dielectric layer can be recessed such that the epitaxial structures protrude from the dielectric layer to form the fins 66 and / or the nanostructures 55. The epitaxial structures can incorporate the alternating semiconductor materials discussed above, such as the first and second semiconductor materials.In some embodiments where the epitaxial structures are grown epitaxially, the epitaxially grown materials can be doped in situ during growth, thus eliminating the need for prior and / or subsequent implantations, but in-situ and implantation doping can also be used together.

[0029] Furthermore, the first semiconductor layers (and the resulting first nanostructures 52) and the second semiconductor layers (and the resulting second nanostructures 54) are presented and discussed here as layers that, for illustrative purposes only, have the same materials in the p-region 50P and the n-region 50N. Therefore, in some embodiments, the first semiconductor layers and / or the second semiconductor layers in the p-region 50P and the n-region 50N may be of different materials, or they may be fabricated in a different sequence.

[0030] Furthermore, in the Fig. 2A and Fig. 2B Suitable wells (not shown individually) are generated in the fins 66, the nanostructures 55, and / or the STI regions 68. In embodiments with different well types, different implantation steps can be performed for the n region 50N and the p region 50P using a photoresist or other masks (not shown individually). For example, a photoresist can be produced over the fins 66 and the STI regions 68 in the n region 50N and the p region 50P. The photoresist is structured to expose the p region 50P. The photoresist can be produced by spin coating and can be structured using suitable photolithographic methods.After the photoresist has been structured, implantation with an n-doper can be performed in the p-region 50P, and the photoresist can act as a mask to largely prevent implantation of n-dopers in the n-region 50N. The n-dopers can be phosphorus, arsenic, antimony, or the like, concentrated in the region to a concentration of approximately 10. 13 atoms / cm² 3 up to about 10 14 atoms / cm² 3 The photoresist is implanted. After implantation, it is removed, for example, using a suitable detachment process.

[0031] Prior to or following the implantation of the p-region 50P, a photoresist or other mask (not shown individually) can be fabricated over the fins 66, the nanostructures 55, and the STI regions 68 in the p-region 50P and the n-region 50N. The photoresist is patterned to expose the n-region 50N. The photoresist can be fabricated by spin coating and can be patterned using suitable photolithographic techniques. After the photoresist has been patterned, implantation with a p-doping agent can be performed in the n-region 50N, and the photoresist can act as a mask to largely prevent p-doping agents from being implanted into the p-region 50P. The p-doping agents can be boron, boron fluoride, indium, or the like, concentrated in the region to a concentration of approximately 10 13 atoms / cm² 3 up to about 10 14 atoms / cm² 3The photoresist can be implanted. After implantation, it can be removed, for example, using a suitable detachment process.

[0032] Following implantation of the n-region 50N and the p-region 50P, a tempering process can be performed to repair implantation damage and activate the implanted p- and / or n-doping materials. In some embodiments, the grown materials of the epitaxial fins can be doped in situ during growth, thus eliminating the need for implantation; however, in-situ and implantation doping can also be used together.

[0033] In Fig. In step 2E, a dielectric dummy layer 70 is fabricated over the fins 66 and / or the nanostructures 55. The dielectric dummy layer 70 can be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and can be deposited or thermally grown using suitable methods. A dummy gate layer 72 is fabricated over the dielectric dummy layer 70, and a mask layer 74 is fabricated over the dummy gate layer 72. The dummy gate layer 72 can be deposited over the dielectric dummy layer 70 and subsequently planarized, for example, using CMP. The mask layer 74 can be deposited over the dummy gate layer 72.The dummy gate layer 72 can be a conductive or non-conductive material selected from a group consisting of amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 72 can be deposited by physical vapor deposition (PVD), continuous vapor deposition (CVD), sputtering, or other methods for depositing the selected material. The dummy gate layer 72 can also be made of other materials that exhibit high etch selectivity with respect to etching the isolation regions. The mask layer 74, for example, can be silicon nitride, silicon oxide nitride, or the like. In this example, only one dummy gate layer 72 and only one mask layer 74 are fabricated across the n region 50N and the p region 50P.It should be noted that, for illustrative purposes, the dielectric dummy layer 70 is shown as a layer covering only the fins 66 and the nanostructures 55. In some embodiments, the dielectric dummy layer 70 can be deposited to cover the STI regions 68, such that the dielectric dummy layer 70 extends between the dummy gate layer 72 and the STI regions 68.

[0034] The Fig. Figures 3A to 20D show various further steps in the manufacture of exemplary devices. Fig. 3A, Fig. 4A, Fig. 5A, Fig. 6A, Fig. 6C, Fig. 7A, Fig. 7C, Fig. 18C, Fig. 19D and Fig. 20D show structural elements in the n-region 50N or the p-region 50P.

[0035] In the Fig. 3A to 3C can use mask layer 74 (see Fig. 2E) can be structured using suitable photolithography and etching techniques to produce masks 78. The structure of the masks 78 can then be transferred to the dummy gate layer 72 and the dielectric dummy layer 70 to produce dummy gates 76 and dummy gate dielectrics 71, respectively. The dummy gates 76 cover respective channel regions of the fins 66. The structure of the masks 78 can be used to physically separate each dummy gate 76 from adjacent dummy gates 76. The dummy gates 76 can also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of the respective fins 66.

[0036] Then, about the one in the Fig. In the structures shown in Figures 3A to 3C, a first spacer layer and a second spacer layer are fabricated and then etched to produce first spacers 81 and second spacers 83, respectively. After the first and second spacer layers have been fabricated, they are patterned to act as spacers for creating self-aligned source / drain regions. The first spacer layer is fabricated at the following locations: on the top surfaces of the STI regions 68; on the top surfaces and side walls of the fins 66, the nanostructures 55, and the masks 78; and on the side walls of the dummy gates 76 and the dummy gate dielectrics 71. The second spacer layer is deposited over the first spacer layer. The first spacer layer can be fabricated from silicon oxide, silicon nitride, silicon oxide nitride, or the like by processes such as thermal oxidation or by CVD, ALD, or the like.The second spacer layer can be made from a material that has a different etch rate than the material of the first spacer layer, such as silicon oxide, silicon nitride, silicon oxide nitride or the like, and can be deposited by CVD, ALD or the like.

[0037] After the fabrication of the first spacer layer and before the fabrication of the second spacer layer, implantations for lightly doped source / drain regions (LDD regions; not shown individually) can be performed. In embodiments with different device types, a procedure similar to that described above can be used. Fig. 2A and Fig. In the implantations discussed in Section 2B, a mask, such as a photoresist, is fabricated over the n-region 50N, leaving the p-region 50P exposed, and dopants of a suitable doping type (e.g., p-conducting) can be implanted into the exposed fins 66 and nanostructures 55 in the p-region 50P. The mask can then be removed. The n-doping materials can be some of the n-doping materials discussed above, and the p-doping materials can be some of the p-doping materials discussed above. The lightly doped source / drain regions can have a doping concentration of approximately 1 × 10 15atoms / cm² 3 up to about 1 × 10 19 atoms / cm² 3 have. A tempering process can repair implant damage and activate the implanted dopants.

[0038] The first and second spacer layers are then etched to produce first spacers 81 and second spacers 83. As will be explained in more detail later, the first spacers 81 and second spacers 83 are used to act as subsequently fabricated self-aligned source / drain regions and to protect sidewalls of the fins 66 and / or the nanostructures 55 during subsequent processing. The first and second spacer layers can be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), or the like. In some embodiments, the material of the second spacer layer has a different etch rate than the material of the first spacer layer, so that the first spacer layer can act as an etch stop layer during the structuring of the second spacer layer.The second spacer layer can, for example, be etched using an anisotropic etching process, with the first spacer layer acting as an etch stop layer and remaining parts of the second spacer layer being able to form the second spacers 83, as in . Fig. 3A is shown. Subsequently, the second spacers 83 act as a mask during the etching of exposed parts of the first spacer layer, so that the first spacers 81 are formed, as shown in the Fig. 3A is shown.

[0039] As also in Fig. As shown in Figure 3A, the first spacers 81 and the second spacers 83 are arranged on the side walls of the fins 66 and / or the nanostructures 55. As shown in Fig. As shown in Figure 3B, in some embodiments the first and second spacer layers adjacent to the masks 78, the dummy gates 76, and the dummy gate dielectrics 71 can be removed. In some embodiments, only the second spacer layer can be removed, and the first spacers 81 can remain on the side walls of the masks 78, the dummy gates 76, and dielectric dummy layers 60. In other embodiments, a portion of the second spacers 83 can remain above the first spacers 81 adjacent to the masks 78, the dummy gates 76, and the dummy gate dielectrics 71.

[0040] It should be noted that the preceding disclosure generally describes a method for fabricating spacers and LDD regions. However, other methods and procedures can also be used. For example, fewer or more spacers can be used, a different sequence of steps can be employed (e.g., the first spacers 81 can be structured before the deposition of the second spacer layer 82), additional spacers can be fabricated and removed, and / or the like. Furthermore, the n- and p-devices can be fabricated using different structures and steps.

[0041] In the Fig. 4A and Fig. 4B In some embodiments, first recesses 86 are created in the fins 66, the nanostructures 55, and the substrate 50. Subsequently, source / drain epitaxy regions are created in the first recesses 86. The first recesses 86 can extend through the first nanostructures 52 and the second nanostructures 54 and into the substrate 50. As in Fig. As shown in Figure 9A, the top surfaces of the STI regions 68 can be at the same level as the bottom surfaces of the first recesses 86. In various embodiments, the fins 66 can be etched such that the bottom surfaces of the first recesses 86 are located below the top surfaces of the STI regions 68, or the like. The first recesses 86 can be produced by etching the fins 66, the nanostructures 55, and the substrate 50 using anisotropic etching processes such as RIE, NBE, or the like. The first spacers 81, the second spacers 83, and the masks 78 mask parts of the fins 66, the nanostructures 55, and the substrate 50 during the etching processes used to produce the first recesses 86. A single etching process or multiple etching processes can be used to etch each layer of the nanostructures 55 and / or the fins 66.To stop the etching of the first recesses 86 after reaching a desired depth, time-controlled etching processes can be used.

[0042] Then, portions of the sidewalls of the layers of the multilayer stack 64, which are made from the first semiconductor materials (e.g., the first nanostructures 52) exposed by the first recesses 86, are etched to create sidewall recesses (corresponding to the depicted internal spacers 90) in the n-region 50N. Portions of the sidewalls of the layers of the multilayer stack 56, which are made from the second semiconductor materials (e.g., the second nanostructures 54) exposed by the first recesses 86, are etched to create sidewall recesses in the p-region 50P. Although the sidewalls of the first nanostructures 52 and the second nanostructures 54 in the sidewall recesses are shown as straight sidewalls, they can also be concave or convex. The sidewalls can be etched using isotropic etching processes, such as wet etching or the like.The p-region 50P can be protected with a mask (not shown), while etchants selective for the first semiconductor materials are used to etch the first nanostructures 52, so that the second nanostructures 54 and the substrate 50 remain relatively unetched compared to the first nanostructures 52 in the n-region 50N. Similarly, the n-region 50N can be protected with a mask (not shown), while etchants selective for the second semiconductor materials are used to etch the second nanostructures 54, so that the first nanostructures 52 and the substrate 50 remain relatively unetched compared to the second nanostructures 54 in the p-region 50P. In an embodiment where the first nanostructures 52 are, for example, SiGe and the second nanostructures 54 are, for example,If Si or SiC are present, a dry etching process with tetramethylammonium hydroxide (TMAH), hydrated ammonia (NH4OH) or the like can be used to etch sidewalls of the first nanostructures 52 in the n-region 50N, and a wet or dry etching process with hydrogen fluoride, another fluorine-based etchant or the like can be used to etch sidewalls of the second nanostructures 54 in the p-region 50P.

[0043] After the sidewall recesses have been created, the first internal spacers 90 are fabricated in the sidewall recesses. These first internal spacers 90 act as insulating elements between subsequently created source / drain regions and a gate structure. As will be explained in more detail later, source / drain regions are created in the first recesses 86, while the first nanostructures 52 in the n-region 50N and the second nanostructures 54 in the p-region 50P are replaced by corresponding gate structures.

[0044] The first internal spacers 90 can be fabricated by depositing an internal spacer layer (not shown separately) over the structures. The internal spacer layer can be deposited using a conformal deposition process, such as CVD, ALD, or the like. The internal spacer layer can be made of a material such as silicon nitride or silicon oxide nitride, but any suitable material can be used, such as materials with a low dielectric constant (low-k materials) having a k-value of less than approximately 3.5. The internal spacer layer can be anisotropically etched to fabricate the first internal spacers 90.Although the outer side walls of the first inner spacers 90 are shown as side walls that are flush with the side walls of the second nanostructures 54 in the n-region 50N and with the side walls of the first nanostructures 52 in the p-region 50P, the outer side walls of the first inner spacers 90 can also extend beyond the side walls of the second nanostructures 54 and / or the first nanostructures 52 or be recessed relative to them.

[0045] Furthermore, the outer side walls of the first 90° internal spacers are Fig. 4B are shown straight, but they can also be concave or convex. The spacer layer can be etched using an anisotropic etching process such as RIE, NBE, or the like. The first spacers 90 can be used to prevent damage to subsequently generated source / drain regions (such as the source / drain epitaxy regions 92, which are described below with reference to the Fig. 5A to 5C will be discussed) to avoid subsequent etching processes, such as etching processes used to manufacture gate structures.

[0046] In the Fig. 5A to 5C generate source / drain epitaxy regions 92 in the first recesses 86. In some embodiments, the source / drain epitaxy regions 92 can apply a mechanical stress to the second nanostructures 54 in the n-region 50N and to the first nanostructures 52 in the p-region 50P, thereby improving performance. As shown in Fig. As shown in Figure 5B, the source / drain epitaxy regions 92 are generated in the first recesses 86 such that each dummy gate 76 is located between respective adjacent pairs of source / drain epitaxy regions 92. In some embodiments, the first spacers 81 are used to separate the source / drain epitaxy regions 92 from the dummy gates 76, and the first internal spacers 90 are used to separate the source / drain epitaxy regions 92 from the nanostructures 55 at a suitable lateral distance so that the source / drain epitaxy regions 92 do not short-circuit subsequently fabricated gates of the resulting nano-FETs.

[0047] The source / drain epitaxy regions 92 in the n-region 50N, e.g., the NMOS region, can be generated by masking the p-region 50P, e.g., the PMOS region. The source / drain epitaxy regions 92 are then grown epitaxially in the first recesses 86 in the n-region 50N. The source / drain epitaxy regions 92 can consist of a material suitable for n-nanoFETs. For example, if the second nanostructures 54 are silicon, the source / drain epitaxy regions 92 can consist of materials that exert a tensile stress on the second nanostructures 54, such as silicon, silicon carbide, phosphor-doped silicon carbide, silicon phosphide, or the like. The source / drain epitaxy regions 92 can have surfaces that are raised relative to the respective surfaces of the nanostructures 55, and they can have chamfers.

[0048] The source / drain epitaxy regions 92 in the p-region 50P, e.g., the PMOS region, can be generated by masking the n-region 50N, e.g., the NMOS region. The source / drain epitaxy regions 92 are then epitaxially grown in the first recesses 86 in the p-region 50P. The source / drain epitaxy regions 92 can be composed of a material suitable for p-nanoFETs. If the first nanostructures 52 are, for example, silicon germanium, then the source / drain epitaxy regions 92 can be composed of materials that exert a compressive stress on the first nanostructures 52, such as silicon germanium, boron, boron-doped silicon germanium, germanium, germanium-tin, or the like. The source / drain epitaxy regions 92 may also have surfaces that are raised relative to the respective surfaces of the multilayer stack 56, and they may have chamfers.

[0049] The source / drain epitaxy regions 92, the first nanostructures 52, the second nanostructures 54, and / or the substrate 50 can be implanted with dopants to create source / drain regions, similar to the process discussed above for fabricating lightly doped source / drain regions, and can subsequently be annealed. The source / drain regions can have a doping concentration of approximately 1 × 10 19 atoms / cm² 3 up to about 1 × 10 21 atoms / cm² 3 The n- and / or p-doping agents for the source / drain regions can be those discussed above. In some embodiments, the source / drain epitaxy regions 92 can be doped in situ during growth.

[0050] Through the epitaxy processes used to generate the source / drain epitaxy regions 92 in the n-region 50N and the p-region 50P, the top surfaces of the source / drain epitaxy regions 92 have chamfers that extend laterally outwards beyond the side walls of the nanostructures 55. In some embodiments, these chamfers cause adjacent source / drain epitaxy regions 92 of the same nanoFET to merge, as shown in Fig. Figure 5A is shown. In other embodiments, adjacent source / drain epitaxy regions 92 remain separated after the epitaxy process is complete. The first spacers 81 can be fabricated up to the top surface of the STI regions 68, thus blocking epitaxial growth. In other embodiments, the first spacers 81 can cover portions of the sidewalls of the nanostructures 55, further blocking epitaxial growth. In some further embodiments, the spacer etching used to fabricate the first spacers 81 can be modified to remove the spacer material, allowing the epitaxially grown region to extend to the surface of the STI region 68.

[0051] The source / drain epitaxy regions 92 can have one or more semiconductor material layers. For example, the source / drain epitaxy regions 92 can have a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers can be used for the source / drain epitaxy regions 92. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C can be made of different semiconductor materials and can be doped to different doping concentrations. In some embodiments, the first semiconductor material layer 92A can have a doping concentration that is lower than that of the second semiconductor material layer 92B and higher than that of the third semiconductor material layer 92C.In embodiments in which the source / drain epitaxy regions 92 have three semiconductor material layers, the first semiconductor material layer 92A can first be deposited, then the second semiconductor material layer 92B can be deposited over the first semiconductor material layer 92A, and the third semiconductor material layer 92C can be deposited over the second semiconductor material layer 92B.

[0052] In the Fig. In 6A to 6C, a first interlayer dielectric (ILD) 96 is applied over the layer in the Fig. 3C, Fig. 5B and Fig. The structure shown in 5A is deposited (the processes of Fig. 4A to 5B do not change the one in Fig. (cross-section shown in Figure 3C). The first ILD 96 can be made of a dielectric material and can be deposited using a suitable method such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Suitable dielectric materials include phosphosilicate glass (PSG), borosilicate glass (BSG), boron phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials deposited using a suitable method can also be used. In some embodiments, a contact etch stop layer (CESL) 94 is deposited between the first ILD 96 and the source / drain epitaxy regions 92, the masks 78, and the first spacers 81. The CESL 94 can comprise a dielectric material, such as silicon nitride, silicon oxide, silicon oxide nitride, or the like, which has a different etch rate than the material of the overlying first ILD 96.

[0053] In the Fig. In embodiments 7A to 7C, a planarization process, such as a CMP, can be performed to bring the top surface of the first ILD 96 to the same level as the top surfaces of the dummy gates 76 or the masks 78. The planarization process can also remove the masks 78 on the dummy gates 76 and portions of the first spacers 81 along the side walls of the masks 78. After the planarization process, the top surfaces of the dummy gates 76, the first spacers 81, and the first ILD 96 are at the same level within process variations. Accordingly, the top surfaces of the dummy gates 76 are exposed by the first ILD 96. In some embodiments, the masks 78 can remain, and in this case, the planarization process brings the top surface of the first ILD 96 to the same level as the top surfaces of the masks 78 and the first spacers 81.

[0054] In Fig. 8. After the planarization process, the top surface of the first ILD 96 can be spared using a suitable etching process, such as an etching process that is selective for the material of the first ILD 96 (e.g., one that etches the material of the first ILD 96 at a higher rate than the material of the dummy gates 76). For example, oxide removal using dilute hydrofluoric acid (dHF) can be employed.

[0055] In Fig. 9 After the first ILD 96 has been removed, a self-aligning mask 89 can be deposited in the recesses, and then the top of the self-aligning mask 89 can be planarized to re-expose the tops of the dummy gates 76.

[0056] In the Fig. 10A and Fig. In step 10B, the dummy gates 76 and, if present, the masks 78 are removed in one or more etching steps, creating second recesses 98. Portions of the dielectric dummy layers 60 in the second recesses 98 are also removed. In some embodiments, the dummy gates 76 and the dielectric dummy layers 60 are removed using an anisotropic dry etching process. The etching process can, for example, be a dry etching process using one or more reactive gases that selectively etch the dummy gates 76 at a higher rate than the first ILD 96 or the first spacers 81. Each second recess 98 exposes and / or covers portions of the nanostructures 55, which function as channel regions in subsequently completed nanoFETs. The parts of the nanostructures 55, which function as the channel regions, are arranged between adjacent pairs of the source / drain epitaxy regions 92.During removal, the dielectric dummy layers 60 can be used as etch stop layers when etching the dummy gates 76. The dielectric dummy layers 60 can be removed after the dummy gates 76 have been removed.

[0057] The first nanostructures 52 in the n-region 50N and the second nanostructures 54 in the p-region 50P are removed, thus enlarging the second recesses 98. The first nanostructures 52 can be removed by fabricating a mask (not shown) over the p-region 50P and performing an isotropic etching process, such as wet etching or the like, using etchants that are selective for the materials of the first nanostructures 52, while the second nanostructures 54, the substrate 50, and the STI regions 68 remain relatively unetched compared to the first nanostructures 52. In embodiments where the first nanostructures 52 comprise, for example, SiGe and the second nanostructures 54A to 54C, the second nanostructures 54A to 54C are made of SiGe, the second nanostructures 54A to 54C are made of SiGe. B. Si or SiC, tetramethylammonium hydroxide (TMAH), hydrated ammonia (NH4OH) or the like can be used to remove the first nanostructures 52 in the n-range 50N.

[0058] The second nanostructures 54 in the p-region 50P can be removed by fabricating a mask (not shown) over the n-region 50N and performing an isotropic etching process, such as wet etching or the like, using etchants that are selective for the materials of the second nanostructures 54, while the first nanostructures 52, the substrate 50, and the STI regions 68 remain relatively unetched compared to the second nanostructures 54. In embodiments where the second nanostructures 54 comprise, for example, SiGe and the first nanostructures 52 comprise, for example, Si or SiC, hydrogen fluoride, another fluorine-based etchant, or the like can be used to remove the second nanostructures 54 in the p-region 50P.

[0059] In other embodiments, the channel regions in the n-region 50N and the p-region 50P can be generated simultaneously, for example by removing the first nanostructures 52 in the n-region 50N and the p-region 50P or by removing the second nanostructures 54 in the n-region 50N and the p-region 50P. In these embodiments, the channel regions of the n-nano-FETs and the p-nano-FETs can have the same material composition, such as silicon, silicon germanium, or the like. Fig. Figures 21A to 21D show a structure resulting from embodiments in which the channel regions in the p-region 50P and the n-region 50N are provided by the second nanostructures 54 and, for example, comprise silicon.

[0060] In the Fig. 11, Fig. 12, Fig. 13 to Fig. 14. Replacement gates are manufactured to enclose the channel areas in the n-range 50N and the p-range 50P. The illustrations in the Fig. 11, Fig. 12, Fig. 13 to Fig. Figure 14 shows enlarged representations of further processes that take place in the areas of the dashed boxes F11N and F11P in Fig. 10B for the n-range 50N or the p-range 50P.

[0061] In Fig. 11. Dielectric gate layers 100 are fabricated for the replacement gates. The dielectric gate layers 100 are conformally deposited in the second recesses 98. In the n-region 50N, the dielectric gate layers 100 can be fabricated on the top and side walls of the substrate 50 and on the top, side walls, and bottom surfaces of the second nanostructures 54. In the p-region 50P, the dielectric gate layers 100 can be fabricated on the top and side walls of the substrate 50 and on the top, side walls, and bottom surfaces of the first nanostructures 52. The dielectric gate layers 100 can also be fabricated on the top surfaces of the self-aligning mask 89, the CESL 94, the first spacers 81 (if present), and the STI regions 68.

[0062] In some embodiments, the dielectric gate layers 100 comprise one or more dielectric layers, such as an oxide, a metal oxide, or the like, or combinations thereof. For example, in some embodiments, the dielectric gate layers 100 may have a first gate dielectric 101 (containing, for example, silicon oxide or the like) and a second gate dielectric 103 (containing, for example, a metal oxide or the like) over the first gate dielectric 101. In some embodiments, the first gate dielectric 101 may be a low-k dielectric material (with a k-value of less than about 3.9), such as silicon nitride, silicon carbide, silicon oxide, a low-k dielectric such as a carbon-doped oxide, an extremely low-k dielectric such as porous carbon-doped silicon dioxide, or the like, or a combination thereof.The second gate dielectric 103 can have a dielectric material with an opposite k-value (a high k-value as opposed to a low k-value), and in these embodiments the second gate dielectric 103 can have a k-value greater than about 7.0, and can have a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium or lead, or combinations thereof, for example hafnium oxide, aluminum oxide, zirconium oxide, lanthanum oxide, manganese oxide, barium oxide, titanium oxide or lead oxide.

[0063] The structures of the dielectric gate layers 100 can be the same or different in the n-region 50N and the p-region 50P. For example, the n-region 50N can be masked or unmasked in the p-region 50P during the fabrication of the dielectric gate layers 100. In embodiments where the n-region 50N is unmasked, the dielectric gate layers 100 in the n-regions 50N can be fabricated simultaneously. Methods such as MBD, ALD, PECVD, plasma-enhanced atomic layer deposition (PEALD), and similar techniques can be used to fabricate the dielectric gate layers 100.

[0064] In the Fig. 12 and Fig. 13 The gate electrodes are deposited over the dielectric gate layers 100, and they can comprise several layers, which are selected and deposited according to the desired work function of the resulting gate. A filler portion of the gate electrodes can then be deposited to fill the remaining portions of the second recesses 98. The gate electrodes can have a metal gate 105 with a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multilayers thereof. Fig. Although single-layer metal gates 105 are shown in Figure 12, the metal gates 105 can have any number of coating layers and any number of output work adjustment layers. Any combination of the layers forming the metal gate 105 can be deposited in the n-region 50N between adjacent second nanostructures 54 and between nanostructure 54A and substrate 50, and in the p-region 50P between adjacent first nanostructures 52.

[0065] For example, in one embodiment the metal gate 105 may have one or more layers of silicon oxide, hafnium oxide, lanthanum oxide, aluminum oxide, titanium nitride, tantalum nitride, titanium silicon nitride, tungsten carbonitride, tungsten nitride, titanium aluminum nitride, molybdenum nitride, tantalum aluminum carbide, titanium aluminide or the like or combinations thereof.

[0066] In some embodiments, the metal gate 105 can fuse around the second nanostructures 54 in the n-region 50N and around the first nanostructures 52 in the p-region 50P, while in other embodiments an additional space can remain after the deposition of the metal gate 105 for layers to be produced later.

[0067] After the fabrication of the metal gate 105, an adhesive layer 107 (which can also be referred to as an "adhesive layer") can be conformally deposited in the second recesses 98 to enable adhesion for a subsequently deposited metallic filler material 109. The adhesive layer 107 can be conformally deposited over the metal gate 105. In some embodiments, the adhesive layer 107 can comprise titanium nitride, tantalum nitride, or the like. The adhesive layer 107 can be deposited by molecular beam deposition (MBD), ALD, PECVD, PEALD, and the like at a temperature of 200 °C to 500 °C. For example, if titanium nitride is deposited using an ALD process, cycles with TiCl4 and NH3 can be used to build up ALD-deposited layers. When titanium niride is deposited using a PEALD process, cycles with tetrakis(dimethylamino)titanium (TDMAT) and NH3 can be used to build up PEALD-deposited layers.The resulting thickness of the adhesive layer 107 can be approximately 0.5 nm to approximately 1.5 nm (approximately 5 Å to approximately 15 Å). In some embodiments, the adhesive layer 107 can fuse around the second nanostructures 54 in the n-region 50N and around the first nanostructures 52 in the p-region 50P, while in other embodiments, an additional space can remain after the deposition of the adhesive layer 107 for layers to be produced later.

[0068] In Fig. 13 A metallic filler material 109 is deposited as the remaining parts of the gate electrodes 102 (which comprise the metal gates 105, the adhesive layer 107, and the metallic filler material 109) to fill the remaining parts of the second recesses 98. The metallic filler material 109 can be deposited over the adhesive layer 107. In some embodiments, the metallic filler material 109 is tungsten, molybdenum-cobalt, ruthenium, aluminum, a combination thereof, or the like, deposited by CVD, ALD, PECVD, PEALD, or the like.Due to the conformal deposition of the metallic filler material 109 and the high aspect ratio of the second recesses 98, a vertical seam 111 can be formed in the metallic filler material 109. The vertical seam 111 extends from the top surface of the metallic filler material 109 to a lower end, the lower end of which does not extend completely through the metallic filler material 109 but terminates at a point between the bottom and top surfaces. The vertical seam 111 can be observed based on various defining features. In some embodiments, the vertical seam 111 in the metallic filler material 109 can have small cavities with a width of up to approximately 1 nm (10 Å) (i.e., from 0 to 1 nm (10 Å)), which can extend continuously or discontinuously along the length of the vertical seam 111.Another feature of the vertical seam 111 is that it has a lower density than other parts of the metallic filler material 109. Even if no voids were to form, the vertical seam 111 would still have a lower density than the other parts of the metallic filler material 109, which have a substantially uniform density. A further feature of the vertical seam 111 is a disruption in the uniformity of the structure of the metallic filler material 109. As will be explained in more detail later, the metallic filler material 109 can be deposited using a conformal deposition process that creates a specific structure along each exposed surface. As the metallic filler material 109 is built up, the right surface in the second recesses 98 approaches the left surface of the second recesses 98. When they meet, the structure is different, resulting in the vertical seam 111.For example, if ALD processes are used for the deposition processes, deposition cycles are employed to produce multiple thin films, which crosslink with each other during deposition. However, at the vertical seam 111 of the metallic filler material 109, the extent of crosslinking is measurably less than that between the deposited layers. For example, the extent of crosslinking may be 40% to 80% less than the extent of crosslinking of the other layers. It should be noted that the vertical seam 111 can be observed using methods known to the average person skilled in the art.

[0069] The metallic filler material 109 can be deposited using a suitable process such as CVD, ALD, PECVD, or PEALD, but other methods can also be used. For example, if ALD is used for tungsten deposition, the metallic filler material 109 can be deposited using WF6 as a precursor gas and B2H6 or SiH4 (with H2) as a reaction gas to enable a reaction in which tungsten is deposited and BF3 or SiHF6 and HF are formed as byproducts. The process can be carried out by providing alternating pulses of the precursor gas and the reaction gas to the deposition site, with purge pulses using argon in between. The process temperature can be approximately 275 °C to 300 °C, and the process pressure can be approximately 666 Pa to 4 kPa (5 Torr to 30 Torr). Each deposited layer of tungsten can crosslink with the preceding layer, forming a crystalline structure.

[0070] The dielectric gate layers 100 in the n-region 50N and the p-region 50P can be fabricated simultaneously, so that the dielectric gate layers 100 in each region are made of the same materials, and the gate electrodes 102 (comprising the metal gates 105, the adhesive layer 107, and the metallic filler material 109) can also be fabricated simultaneously, so that the gate electrodes in each region are made of the same materials. In some embodiments, the dielectric gate layers 100 in each region can be fabricated using different processes, so that they can be made of different materials and / or have different numbers of layers, and / or the gate electrodes in each region can be fabricated using different processes, so that they can be made of different materials and / or have different numbers of layers.When different processes are used, various masking steps can be employed to mask and expose the corresponding areas.

[0071] After the recession of the dielectric gate layers 100 and the gate electrodes 102, the chemical composition of the gate structure can consist of tungsten, boron, silicon, fluorine and chlorine in a graduated concentration from the metallic filler material 109 to the gate dielectric 101.

[0072] In Fig. 14. After filling the second recesses 98, a planarization process, such as CMP, can be performed to remove the excess portions of the dielectric gate layers 100 and the gate electrode material 102 (comprising the metal gates 105, the adhesive layer 107, and the metallic filler material 109) located above the top surface of the self-aligning mask 89. The remaining portions of the gate electrode material 102 and the dielectric gate layers 100 thus form substitute gate structures of the resulting nano-FETs. The gate electrodes 102 and the dielectric gate layers 100 can be collectively referred to as the “gate structures.”

[0073] In the Fig. 15A and Fig. In 15B, the gate structure (comprising the dielectric gate layers 100 and the corresponding gate electrodes 102 located above it) is selectively etched, creating third recesses 99 directly above the gate structure and between opposing parts of the CESL 94. The selective etching process allows a fin-shaped portion of the metallic filler material 109, i.e., a fin electrode 109f, to remain, projecting upwards into the third recesses 99. The fin electrode 109f can be used to provide a reduced dimension for contacts with the gate structures and the source / drain regions. The fin electrode 109f also reduces gate resistance by increasing the contact area for the gate contacts. This improves performance, even as gate sizes continue to decrease.

[0074] The materials of the first gate dielectric 101, the second gate dielectric 103, the metal gate 105, the adhesive layer 107, and the metallic filler 109 can each have different etch selectivities for different etchants. The third recesses 99 can be created by using a suitable etchant for the replacement gate structure. The etchants can be applied using a wet or dry etching process, and they can be applied in any order. In some embodiments, several etchants can be used simultaneously. The process variables can be adjusted to achieve a desired result, including etch depth and etch selectivity. Although it is shown that the second gate dielectric 103, the metal gate 105, and the adhesive layer 107 in the third recesses 99 are each etched to the same depth, it is understood that they can each have different etch depths.In some embodiments, the etching of the first gate dielectric 101, the second gate dielectric 103, the metal gate 105, the adhesive layer 107, and the metallic filler material 109 can each be carried out for a duration of 1 s to 300 s and at a process temperature of approximately 50 °C to approximately 120 °C. The etching can be performed in several etching and optional cleaning cycles using RF current-assisted etching methods to activate the corresponding etchants.

[0075] For example, the first gate dielectric 101 can be etched with an RF-containing etchant, the second gate dielectric 103 can be etched with a Cl-containing etchant such as BCl3 and CH4, and the metal gate 105 and the adhesive layer 107 can be etched with Cl2, BCl3, O2, CF4, or N2 etchants. It is understood that these etchants are only examples and can be changed depending on the material composition of each of the layers. In some embodiments, the metallic filler 109 can be etched with etchants containing N2, NF3, O2, BCl3, and Cl2, or Cl2 and O2. The metallic filler 109 can be etched in a separate process to produce the fin electrode 109f. In other embodiments, no separate etching process is required to produce the fin electrode 109f.In these embodiments, minor etching resulting from one or more of the etching processes for the first gate dielectric 101, the second gate dielectric 103, the metal gate 105, and the adhesive layer 107 can cause the metallic filler material 109 to be partially recessed and etched at a lower effective etch rate, thus forming the fin electrode 109f. In both cases, the shape of the fin electrode 109f is shown with a rounded top surface, but depending on the etching conditions and the etching sequence, it can also be rectangular, trapezoidal, oval, or rhombus-shaped. As in . Fig. As shown in the circular cutout in Figure 15A, the upper surface of the fin electrode 109f can have a depression 109d centered on the vertical seam 111, resulting in an m-shape in a sectional view. A similar depression 109d can also be observed for one of the aforementioned shapes as well as for the variant described below with reference to Fig. 15B is discussed.

[0076] In Fig. In Figure 15A, the first gate dielectric 101 is depicted such that, after completion of the etching processes, it extends vertically further than the fin electrode 109f. The first gate dielectric 101 extends beyond the vertical dimension of the fin electrode 109f by a distance d1. Fig. Figure 15B shows the first gate dielectric 101 extending vertically with a distance d2 not as far as the fin electrode 109f. Distances d1 and d2 can each be approximately 0 nm to approximately 20 nm. In other words, the height of the first gate dielectric 101 can vary relative to the height of the fin electrode 109f such that it lies within a range that is less than the total distance by the distance d2 up to a distance d1 that is greater than the height of the fin electrode 109f. The height h1 of the fin electrode 109f that protrudes from (i.e., is not covered by) the adhesive layer 107 and / or the metal gate 105 can be approximately 0 nm to 8 nm. If the first gate dielectric 101 is taller than the fin electrode 109f, as shown in Figure 15B, the height h1 of the fin electrode 109f can be approximately 0 nm to 8 nm. Fig. As shown in Figure 15A, the risk of the subsequently produced source / drain contact being unintentionally short-circuited with the subsequently produced gate contact is reduced, but the gap-filling window is also reduced (e.g., by depositing the subsequently produced gate contact). Conversely, if the first gate dielectric 101 is lower than the fin electrode 109f, the gap-filling window is increased, but the risk of the source / drain being unintentionally short-circuited with the gate increases. Therefore, these parameters can be adjusted to comply with the design tolerances of the device.

[0077] In Fig. 16. A gate mask 114, comprising one or more layers of a dielectric material such as silicon nitride, silicon oxide nitride, or the like, is filled into the third recesses 99. The gate mask 114 can be manufactured using materials and processes similar to those used to manufacture the self-aligning mask 89.

[0078] In Fig. 17 A planarization process is performed to remove excess portions of the dielectric material of the gate mask 114 that extend over the self-aligning mask 89. Gate contacts manufactured later (such as gate contacts 124, which are referred to later in the Fig. 20A to 20D are discussed) penetrate the gate mask 114 to contact the top surfaces of the recessed dielectric gate layers 100 and the gate electrodes 102.

[0079] In the Fig. 18A to 18C, 19A to 19D and 20A to 20C replace the preceding representations (such as those found in the Fig. 10A and Fig. (shown in 10B) resumed after the Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15, Fig. 16 to Fig. The 17 processes shown have been carried out. In the Fig. In 18A to 18C, 19A to 19D and 20A to 20C, the first gate dielectric 101 is shown as a separate layer, while the second gate dielectric 103, the metal gate 105, the adhesive layer 107 and the fin electrode 109f are combined into a single gate structure 113. Fig. Figures 18A to 18C show extended representations of the structure of Fig. 17 in different cross-sections.

[0080] In the Fig. In 19A to 19D, a second ILD 115 is deposited over the self-aligning mask 89 and the gate mask 114. In some embodiments, the second ILD 115 is a flowable layer produced by FCVD. In other embodiments, the second ILD 115 is made from a dielectric material such as PSG, BSG, BPSG, USG, or the like, and can be deposited by a suitable method such as CVD, PECVD, or the like.

[0081] In the Fig. In processes 19A to 19D, the second ILD 115, the self-aligning mask 89, the first ILD 96, the CESL 94, and the gate masks 114 are etched to create fourth recesses 118 that expose the surfaces of the source / drain epitaxy regions 92 and / or the fin electrode 109f of the gate structure 113. The fourth recesses 118 can be created by etching with an anisotropic etching process such as RIE, NBE, or the like. In some embodiments, the fourth recesses 118 can be etched by a first etching process through the second ILD 115, by a second etching process through the self-aligning mask 89, by a third etching process through the first ILD 96, by a fourth etching process through the gate masks 114, and by a fifth etching process through the CESL 94.In some embodiments, the fourth etching process can be performed simultaneously with the second or third etching process, depending on the materials used for the respective materials being etched. A mask, such as a photoresist, can be fabricated and structured over the second ILD 115 to protect parts of the second ILD 115 from the first and second etching processes. In some embodiments, the etching process can be an over-etch, and therefore the fourth recesses 118 can extend into the source / drain epitaxy regions 92 and / or the gate structures 113. An underside of the fourth recesses 118 can be at the same level as the source / drain epitaxy regions 92 and / or the gate structure 113, e.g., at the same level as them or at the same distance from the substrate as they are, or they can be lower than the source / drain epitaxy regions 92 and / or the gate structure 113, e.g.,closer to the substrate. The . Fig. 19B and Fig. Figure 19C shows that the fourth recesses 118 expose the source / drain epitaxy regions 92 and the gate structure 113 in different cross-sections, but in different embodiments a sectional view can contain both groups of fourth recesses 118 in the same cross-section.

[0082] After the fourth recesses 118 have been created, silicide regions 110 are produced over the source / drain epitaxy regions 92. In some embodiments, the silicide regions 110 are produced as follows. First, a metal (not shown) is deposited over the exposed portions of the source / drain epitaxy regions 92. This metal can react with the semiconductor materials of the underlying source / drain epitaxy regions 92 (e.g., silicon, silicon germanium, germanium) to form silicide or germanide regions. The metal can be nickel, cobalt, titanium, tantalum, platinum, tungsten, another precious metal, another refractory metal, a rare-earth metal, or an alloy thereof. Subsequently, a thermal annealing process is carried out to produce the silicide regions 110. Then, the unreacted portions of the deposited metal are removed, for example, by an etching process.Although the silicide regions 110 are referred to as silicide regions, they can also be germanide regions or silicon germanide regions (i.e., regions containing both silicide and germanide). In one embodiment, the silicide region 110 contains TiSi and has a thickness of approximately 2 nm to approximately 10 nm.

[0083] Then in the Fig. 20A to 20D Contacts 122 and 124 (which can also be referred to as contact pins) are manufactured in the fourth recesses 118. Contacts 122 and 124 can each have one or more layers, such as barrier layers, diffusion layers, and filler materials. In some embodiments, for example, contacts 122 and 124 can each have a barrier layer and a conductive material, and they can each be electrically connected to an underlying conductive structural element (e.g., the gate structure 113 and / or the silicide region 110). Contacts 124 are electrically connected to the gate structure 113 and surround the fin electrode 109f, and they can be referred to as gate contacts. Contacts 122 are electrically connected to the silicide regions 110 and can be referred to as source / drain contacts. The barrier layer can be titanium, titanium nitride, tantalum, tantalum nitride, or the like.The conductive material can be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as CMP, can be performed to remove excess material from one surface of the second ILD 115.

[0084] The Fig. Figures 21A to 21D show sectional views of a device according to some alternative embodiments. Fig. 21A shows a reference cross-section A - A' which is in Fig. 1 is shown. Fig. 21B shows a reference cross-section B - B', which is in Fig. 1 is shown. Fig. 21C shows a cross-section parallel to and through the fin of the reference cross-section B - B' of Fig. 1 is running. Fig. 21D shows a reference cross-section C - C', which is in Fig. 1 is shown. In the Fig. 21A to 21D denote similar reference numbers, similar elements, which are associated with similar processes as those in the Fig. The structure shown in 20A to 20D can be produced. Fig. However, nanostructures 21A to 21D have channel regions in the n-region 50N and the p-region 50P made of the same material. For example, the second nanostructures 54, which contain silicon, provide channel regions for p-nanoFETs in the p-region 50P and for n-nanoFETs in the n-region 50N. The structure of Fig. 21A to 21D can be fabricated, for example, as follows: simultaneous removal of the first nanostructures 52 from the p-region 50P and the n-region 50N; deposition of dielectric gate layers 100 and gate electrodes 113P (e.g., gate electrodes suitable for a p-nano-FET) around the second nanostructures 54 in the p-region 50P; and deposition of the dielectric gate layers 100 and gate electrodes 113N (e.g., gate electrodes suitable for an n-nano-FET) around the second nanostructures 54 in the n-region 50N. In these embodiments, the materials of the source / drain epitaxy regions 92 in the n-region 50N can differ from those in the p-region 50P, as described above.

[0085] The Fig. Figures 22A to 22D show sectional views of a device according to some alternative embodiments in which a FinFET is used instead of a Nano-FET. Fig. 22A shows a sectional view corresponding to the reference cross-section A - A' of Fig. 1 is similar (except that it passes through a FinFET). Fig. 21B shows a cross-section similar to the reference cross-section B - B' of Fig. 1 (with the exception that it passes through a FinFET). Fig. 22C shows a cross-section parallel to the cross-section of Fig. 22B is and also runs through the fin. Fig. 22D shows a cross-section similar to the reference cross-section C - C' of Fig. 1 (with the exception that it passes through a FinFET). In the Fig. 22A to 22D denote similar reference numbers, similar elements, which are associated with similar processes, such as the structure of the Fig.20A to 20D are manufactured. The fins 66 are made from a single semiconductor material instead of alternating semiconductor layers 64. Channel regions 66' are regions of the fins 66 that are covered by the dielectric gate layers 100 and the gate structures 113. The structures shown are the same for the p-region 50P and the n-region 50N, but the materials of the gate structures 113 and the source / drain epitaxy regions 92 can differ depending on the region in which the device is manufactured, as explained above.

[0086] These embodiments can offer advantages. For example, a gate electrode fin allows for an increase in the contact area with a gate contact positioned above it. The increased contact area, in turn, enables a reduced gate resistance and a more efficient device. Furthermore, the gap-filling window can be controlled by adjusting the height of the dielectric low-k gate layer, providing flexibility in design choices as gate sizes continue to decrease. These embodiments can be used in both nanoFET and FinFET devices, advantageously offering flexibility in transistor design.

Claims

[1] Procedure with the following steps: Forming a fin (66) over a substrate (50); Creating a dummy gate structure over the fin (66); Creating a source / drain area on each side of the dummy gate structure; Deposition of a first interlayer dielectric over the source / drain region; Removing the first interlayer dielectric and creating a self-aligning mask (89) over the first interlayer dielectric; Performing a gate replacement cycle to replace the dummy gate structure with a replacement metal gate, wherein the gate replacement cycle includes the following: Removing the dummy gate structure to create an initial recess (86), Deposition of a gate dielectric (101, 103) in the first recess (86), Creating a metal gate (105) over the gate dielectric (101, 103), Deposition of a metallic filler material (109) over the metal gate (105), and Etching back the gate dielectric (101, 103), the metal gate (105) and the metallic filler material (109) to produce an electrode fin from the metallic filler material (109); and Providing a gate contact (124) that contacts a side wall of the electrode fin, wherein the electrode fin has a seam (111) extending downwards along the electrode fin. [2] Method according to claim 1, wherein the fin (66) has alternating first and second nanostructures (54) under the dummy gate structure, wherein the gate replacement cycle further comprises: Enlarging the first recess (86) by removing the first nanostructures (52) beneath the dummy gate structure. [3] Method according to claim 1 or 2, wherein the gate replacement cycle further comprises depositing an adhesive layer (107) over the metal gate (105) prior to depositing the metallic filler material (109). [4] Method according to claims 1 to 3, wherein the electrode fin has a recess (109d) in its upper surface, wherein the recess (109d) corresponds to the seam (111). [5] A method according to any of the preceding claims, further comprising: Filling an area above the electrode fin with a gate mask (114); Deposition of a second interlayer dielectric over the gate mask (114); Creating a second recess (98) in the second interlayer dielectric and through the gate mask (114), wherein the second recess (98) exposes the electrode fin; and Establishing the gate contact (124) in the second recess (98). [6] Method according to one of the preceding claims, wherein after the production of the electrode fin a vertical extent of the gate dielectric (101, 103) extends further than the electrode fin and a vertical extent of the metal gate (105) is smaller than the electrode fin. [7] Method according to any one of the preceding claims, wherein the gate dielectric (101, 103) has a first layer of a dielectric low-k material and a second layer of a dielectric high-k material, and When etching back the gate dielectric (101, 103), the first layer is etched separately from the second layer, with the second layer being etched deeper than the first layer. [8] Method according to claim 7, wherein the dielectric high-k material comprises hafnium oxide. [9] Procedure with the following steps: Structuring a semiconductor substrate to produce a semiconductor fin; Creating a dummy gate structure over the semiconductor fin; Recessing the semiconductor fin on a first side of the dummy gate structure to create a first recess (86): Separation of a source / drain area in the first recess (86); Deposition of a first interlayer dielectric over the source / drain region; Removing the dummy gate structure to create a second recess (98) in the first interlayer dielectric, wherein the second recess (98) exposes a channel region (66') of the semiconductor fin; Deposition of a gate dielectric (101, 103) in the second recess (98) above the channel area (66'); Deposition of exit work layers in the second recess (98) above the gate dielectric (101, 103); Deposition of a metallic filler material (109) over the exit working layers; Etching back the gate dielectric (101, 103) and the exit work layers to create a third recess (99) in the first interlayer dielectric, wherein part of the metallic filler material (109) remains in the third recess (99) as a fin electrode (109f); and Establishing a self-aligned contact in the third recess (99), wherein the self-aligned contact is connected to vertical parts of the fin electrode (109f), which also includes the following: Omission of the first interlayer dielectric; and Producing a second mask layer over the first interlayer dielectric, wherein one top side of the second mask layer is aligned with one top side of the dummy gate structure, Establishing self-aligned contact includes the following: Deposition of a second interlayer dielectric over the second mask layer and over the fin electrode (109f); Creating an opening through the second interlayer dielectric, wherein creating the opening comprises using the second mask layer as an etching mask, the opening exposing the fin electrode (109f); and Deposition of the self-aligned contact in the opening and on the fin electrode (109f). [10] Method according to claim 9, wherein the semiconductor fin has alternating layers of a first nanostructure (52) and a second nanostructure (54), the method further comprising: Fabrication of first internal spacers in the first recess (86) at exposed ends of the first nanostructures (52); and Enlarging the second recess (98) by removing the layers of the first nanostructures (52), wherein the channel region (66') has the layers of the second nanostructures (54) separated by the first internal spacers (90). [11] Method according to claim 9 or 10, wherein the gate dielectric (101, 103) comprises a first gate dielectric (101) and a second gate dielectric (103), wherein the first gate dielectric (101, 103) comprises a dielectric low-k material and the second gate dielectric (101, 103) comprises a dielectric high-k material. [12] Structure with: a first nanostructure (52); a second nanostructure (54) arranged above the first nanostructure (52), wherein the second nanostructure (54) is separated from the first nanostructure (52) by a first internal spacer (90) at one end of the first nanostructure (52) and by a second internal spacer at an opposite end of the first nanostructure (52); a first source / drain region located adjacent to the first internal spacer (90), wherein the first source / drain region contacts the first nanostructure (52) and the second nanostructure (54); a gate structure (113) located adjacent to the first internal spacer (90) opposite the first source / drain region, wherein the gate structure (113) encloses the first and second nanostructures (54), the gate structure (113) extending vertically higher than the source / drain region, the gate structure (113) comprising a first dielectric layer, a metal gate (105) and a gate filling, the gate filling having a fin portion projecting from the metal gate (105); and a gate contact (124) which is arranged on both sides of the fin part, wherein a part of the gate contact (124) is arranged between the fin part and the first dielectric layer, wherein the first dielectric layer has a vertical extent which is greater than that of the fin part. [13] Structure according to claim 12, further comprising a second dielectric layer arranged between the first dielectric layer and the metal gate (105), wherein the second dielectric layer has a k-value opposite to that of the first dielectric layer. [14] Structure according to claim 13, wherein the first dielectric layer comprises a dielectric low-k material, while the second dielectric layer comprises a dielectric high-k material, wherein the second dielectric layer comprises a metal oxide or silicate of hafnium, aluminium, zirconium, lanthanum, manganese, barium, titanium or lead, or a combination thereof. [15] Structure according to one of claims 12 to 14, wherein the gate contact (124) has a side wall interface with the fin part, wherein the side wall interface has a vertical length of 0 nm to 8 nm. [16] Structure according to one of claims 12 to 14, wherein the fin part has a vertical seam (111) extending downwards along a center line of the fin part.

Images