Method of forming a bottom electrode via for a memory device

Abstract

Integrated chip structure (100, 200, 300, 400, 500, 600) which includes: a lower insulating structure (108) disposed over a lower dielectric structure (104L) surrounding one or more lower interconnects (106); a bottom electrode via (109) surrounded by one or more inner sidewalls of the bottom insulating structure (108) and comprising a barrier (110) surrounding a conductive core (114), the barrier (110) comprising a sidewall disposed along the one or more inner sidewalls of the bottom insulating structure (108) and a horizontally covering segment projecting outwardly from the sidewall to above a top surface of the bottom insulating structure (108); a lower electrode (116) disposed on the lower electrode via (109); a data storage structure (118) over the lower electrode (116); a top electrode (120) above the data storage structure (118); and an adhesive layer (112) disposed on the barrier (110), wherein the lower electrode (116) contacts a top surface of the adhesive layer (112) and the barrier (110), wherein a material of the adhesive layer (112) has a higher corrosion potential than a material of the conductive core (114).

Description

BACKGROUND

[0001] Many modern electronic devices contain electronic memory configured to store data. The electronic memory can be volatile memory or non-volatile memory. Volatile memory stores data when it receives power, while non-volatile memory is capable of storing data when the power is interrupted. Magneto-resistive random-access (MRAM) memory is a promising candidate for a next-generation non-volatile memory technology. MRAM devices use magnetic tunnel junctions (MTJs) to store data in a manner that enables fast data access and low power consumption.

[0002] US 2020 / 0 303 629 A1 discloses an integrated circuit comprising an interlayer dielectric structure laterally surrounding a conductive connection. US 2021 / 0 384 413 A1 is directed to a method for forming an integrated chip. DE 197 57 119 A1 discloses a method for chemical-mechanical polishing of a semiconductor wafer. US 2021 / 0 343 932 A1 discloses a semiconductor structure. DE 10 2016 100 002 A1 describes a method for manufacturing a semiconductor device. DE 10 2021 113 058 A1 describes an MTJ device. US 2021 / 0 057 639 A1 discloses a method for forming a magnetic random access memory. CN 1 14 421 909 A discloses a method for optimizing defects in the FBAR cavity planarization process. The invention is defined by the independent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with common industry practice, various structural elements are not drawn to scale. Rather, the dimensions of the various structural elements may be exaggerated or reduced as needed for clarity of discussion. Fig. 1 illustrates a cross-sectional view of some embodiments of an integrated chip structure including a memory device disposed over a multi-layer bottom electrode via having a relatively flat top surface. Fig. 2 illustrates a cross-sectional view of some additional embodiments of an integrated chip structure including a magnetic random-access memory (MRAM) device disposed over an exposed multi-layer bottom electrode via. Fig. 3A-3B illustrate cross-sectional views of some additional embodiments of an integrated chip structure including an MRAM device disposed over an exposed multi-layer bottom electrode via. Fig. 4 illustrates a cross-sectional view of some additional embodiments of an integrated chip structure including an MRAM device disposed over an exposed multi-layer bottom electrode via. Fig. 5 illustrates a cross-sectional view of some additional embodiments of an integrated chip structure including an MRAM device disposed over an exposed multi-layer bottom electrode via. Fig. 6 illustrates a cross-sectional view of some additional embodiments of an integrated chip structure including an MRAM device disposed over a disclosed multi-layer bottom electrode via. Fig. 7-19 illustrate cross-sectional views showing some embodiments of a method for forming an integrated chip structure including a memory device disposed over a multi-layer bottom electrode via having a relatively flat top surface. Fig. 20 illustrates a flow diagram of some embodiments of a method for forming an integrated chip structure including a memory device disposed over a multi-layer bottom electrode via having a relatively flat top surface. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments or examples for implementing various features of the subject matter discussed herein. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, in the following description, forming a first structural element over or on top of a second structural element may include embodiments where the first and second structural elements are formed in direct contact, and may also include embodiments where additional structural elements may be formed between the first and second structural elements such that the first and second structural elements are not necessarily in direct contact. Furthermore, the present disclosure may repeat reference numbers and / or letters throughout the various examples.This repetition is for the purpose of simplicity and clarity and does not automatically create a relationship between the various embodiments and / or devices discussed.

[0005] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein for convenience of description to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation besides the orientation shown in the figures. The device may also be oriented differently (rotated 90 degrees, or other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0006] Magnetoresistive random-access memory (MRAM) devices comprise a magnetic tunnel junction (MTJ) structure arranged vertically in a back-end-of-the-line (BEOL) interconnect stack between a bottom electrode and a top electrode. The MTJ comprises a pinned layer and a free layer separated vertically by a tunnel barrier layer. The magnetic orientation of the pinned layer is static (i.e., fixed), while a magnetic orientation of the free layer is capable of alternating between a parallel device and an anti-parallel device with respect to that of the pinned layer. The parallel device forms a low-resistance state that digitally stores data as a first data state (for example, a logic "0").The anti-parallel device forms a high-impedance state that stores data digitally as a second data state (for example, a logical “1”).

[0007] The bottom electrode of an MRAM device may be disposed over a bottom electrode via that couples the bottom electrode to an underlying bottom interconnect. The bottom electrode via may be formed by depositing a bottom insulation structure over the bottom interconnect and then patterning the bottom insulation structure to form a bottom electrode via opening that exposes the bottom interconnect. An adhesive layer is formed within the bottom electrode via opening, followed by the formation of a conductive material on the adhesive layer and within the bottom electrode via opening. A chemical mechanical planarization (CMP) process is then performed to remove the excess of the conductive material and adhesive layer from the bottom insulation structure.It has been found that as the size of the bottom-electrode via decreases (e.g., to nodes of 16 nm or less), catch defects (e.g., breakouts located along opposite upper outer corners of the conductive material) may be more common along outer edges of the conductive material facing the adhesive layer. This is because the conductive material (e.g., tungsten) may have a lower corrosion potential than the adhesive layer (e.g., TiN), causing galvanic corrosion between the conductive material and the adhesive layer in the presence of a CMP slurry (e.g., an electrolyte). The galvanic corrosion causes an oxide layer along outer edges of the conductive material. The oxide is subsequently removed during the CMP process, leaving behind catch defects.

[0008] It has also been found that capture defects within a bottom electrode via can cause problems in overlying layers of an MRAM device. For example, capture defects can affect the grain orientation of an overlying bottom electrode, thus increasing the roughness of the bottom electrode. The increased roughness of the bottom electrode leads to increased roughness of the pinned layer of an MTJ, which can degrade the performance of the MTJ (for example, through the formation of defects in an overlying magnesium oxide (MgO) tunnel junction layer). Such degraded performance can result in increased leakage current, lower tunnel magnetoresistance (TMR), a smaller read window, and / or failure of an associated MRAM device.

[0009] The present disclosure relates to an integrated chip structure comprising a memory device disposed over a multi-layer bottom electrode via having a relatively flat top surface. In some embodiments, the integrated chip structure comprises a bottom insulation structure disposed over a bottom dielectric structure surrounding one or more bottom interconnects. A bottom electrode via is disposed directly between one or more inner sidewalls of the bottom insulation structure. A bottom electrode is disposed on the bottom electrode via, a data storage structure is disposed over the bottom electrode, and a top electrode is disposed over the data storage structure.The bottom electrode via comprises an adhesive layer disposed along the one or more inner sidewalls of the lower insulating structure and surrounding a conductive core. The bottom electrode via is formed by a mechanical polishing process using a first slurry, followed by a subsequent polishing process using a second slurry free of an oxidant. By performing the polishing process with a slurry free of an oxidant, galvanic corrosion along outer edges of the conductive core is reduced, thereby reducing trap defects within the conductive core.By reducing trap defects within the conductive core, the bottom electrode via has a relatively flat top surface, which mitigates defects within an overlying data storage layer (for example, a magnetic tunnel junction structure).

[0010] Fig. 1 illustrates a cross-sectional view of some embodiments of an integrated chip structure 100 including a memory device disposed over a multi-layer bottom electrode via having a relatively flat top surface.

[0011] The integrated chip structure 100 includes a bottom dielectric structure 104L disposed over a substrate 102. The bottom dielectric structure 104L surrounds one or more bottom interconnects 106. A bottom isolation structure 108 is disposed over the bottom dielectric structure 104L. The bottom isolation structure 108 includes one or more inner sidewalls extending between a top surface of the bottom isolation structure and a bottom surface of the bottom isolation structure 108. The bottom isolation structure 108 further includes one or more curved outer sidewalls 108c facing away from the one or more inner sidewalls. The one or more curved outer sidewalls 108c are coupled to the top surface of the bottom isolation structure 108.

[0012] A bottom electrode via 109 is disposed directly between the one or more inner sidewalls of the bottom insulation structure 108. The bottom electrode via 109 extends continuously from directly between the one or more inner sidewalls of the bottom insulation structure 108 to above the top of the bottom insulation structure 108. The bottom electrode via 109 includes a barrier 110 that extends continuously from along the one or more inner sidewalls of the bottom insulation structure 108 to above the top of the bottom insulation structure 108. The barrier 110 includes a sidewall that extends along the one or more inner sidewalls of the bottom insulation structure 108 and a horizontally extending segment (e.g., a horizontally covering segment) that projects outward from the sidewall to above the top surface of the bottom insulation structure.An adhesive layer 112 is disposed on the barrier 110, and a conductive core 114 is disposed on the adhesive layer 112. The adhesive layer 112 separates the barrier 110 laterally and vertically from the conductive core 114. In some embodiments, the barrier 110 extends vertically to the uppermost surfaces of the adhesive layer 112 and the conductive core 114. In some embodiments, the uppermost surfaces of the barrier 110, the adhesive layer 112, and the conductive core 114 are substantially coplanar.

[0013] A memory device 115 is disposed over the bottom electrode via 109. The memory device 115 includes a bottom electrode 116 separated from a top electrode 120 by a data storage structure 118. The bottom electrode 116 has a bottom surface that physically contacts the top surfaces of the barrier 110, the adhesive layer 112, and the conductive core 114. In some embodiments, the bottom surface of the bottom electrode 116 extends laterally beyond the outermost sidewalls of the adhesive layer 112 and the conductive core 114.

[0014] An upper dielectric structure 104U is disposed along the curved outer sidewalls 108c of the lower isolation structure 108 and along opposite sides of the bottom electrode via 109 and the memory device 115. In some embodiments, the upper dielectric structure 104U may physically contact the curved outer sidewalls 108c of the lower isolation structure 108 and the opposite sides of the bottom electrode via 109 and the memory device 115. An upper interconnect structure 122 extends through the upper dielectric structure 104U and contacts the top electrode 120.

[0015] In some embodiments, the conductive core 114 may comprise or be a material that has a lower corrosion potential than the material of the adhesive layer 112. For example, the conductive core 114 may comprise and / or be tungsten, while the adhesive layer 112 may comprise and / or be titanium. As the size of the bottom electrode via 109 decreases, tungsten may impart good electrical properties (e.g., resistivity, electromigration, etc.), low diffusivity, and good gap-filling properties to the conductive core 114. However, due to the corrosion difference between the conductive core 114 and the adhesive layer 112, tungsten is susceptible to the formation of trap defects along its outer edges in the presence of an electrolyte (e.g., a CMP slurry with an oxidizer).The disclosed bottom electrode via 109 is formed by a process that uses a polishing process to minimize the formation of catch defects along outer edges of the conductive core 114, thereby making the top surface of the conductive core 114 substantially coplanar with the top surfaces of the barrier 110 and the adhesive layer 112. Minimizing catch defects within the conductive core 114 improves the electrical properties of the bottom electrode 116 and / or the data storage structure 118, thereby improving the operation of the memory device 115.

[0016] Fig. 2 illustrates a cross-sectional view of some additional embodiments of an integrated chip structure 200 including a magnetic random access memory (MRAM) device disposed over a multi-layer bottom electrode via having a relatively flat top surface.

[0017] The integrated chip structure 200 includes a bottom insulation structure 108 disposed over a bottom dielectric structure 104L surrounding one or more bottom interconnects 106 over a substrate 102. The bottom insulation structure 108 includes one or more inner sidewalls extending between a top surface and a bottom surface of the bottom insulation structure 108. In some embodiments, the bottom insulation structure 108 includes multiple dielectric layers stacked one above the other. For example, in some embodiments, the bottom insulation structure 108 may include a first bottom insulation layer 202 and a second bottom insulation layer 204 over the first bottom insulation layer 202.

[0018] In some embodiments, the first lower insulating layer 202 may comprise a carbide (e.g., silicon carbide), a nitride (e.g., silicon nitride), or the like. In some embodiments, the second lower insulating layer 204 may comprise an oxide, such as silicon-rich oxide (SRO), silicon dioxide, or the like. In some embodiments, the first lower insulating layer 202 may have a thickness ranging between about 10.0 nanometers (nm) and about 20.0 nm, between about 12.5 nm and about 15.0 nm, about 15.0 nm, or other similar values. In some embodiments, the second lower insulating layer 204 may have a thickness that is in a range between about 25.0 nm and about 100.0 nm, between about 50.0 nm and about 90.0 nm, about 80.0 nm, about 55.0 nm, or other similar values.

[0019] A bottom electrode via 109 is disposed directly between the one or more inner sidewalls of the bottom insulating structure 108. The bottom electrode via 109 includes a barrier 110, an adhesive layer 112 on the barrier 110, and a conductive core 114 on the adhesive layer 112. In some embodiments, the barrier 110 includes a sidewall extending along the one or more inner sidewalls of the bottom insulating structure 108 and a horizontally extending surface projecting outwardly from the sidewall to above the top surface of the bottom insulating structure 108.

[0020] In some embodiments, the barrier 110 may comprise a metal nitride such as titanium nitride, tantalum nitride, or the like. In some embodiments, the barrier 110 may have a thickness ranging between about 2.5 nm and about 10.0 nm, between about 5.0 nm and about 8.5 nm, about 8.0 nm, or other similar values. In some embodiments, the thickness of the barrier 110 along the sidewall may be different from (e.g., greater than) the thickness of the barrier along the horizontally extending surface. In some embodiments, the adhesive layer 112 may comprise a metal nitride such as titanium nitride, tantalum nitride, or the like. In some embodiments, the adhesive layer 112 may have a thickness ranging between about 5.0 nm and about 10.0 nm, between about 5.0 nm and about 7.5 nm, about 6.0 nm, or other similar values.In some embodiments, the conductive core 114 may comprise and / or be tungsten, copper, or the like. In some embodiments, the conductive core 114 may have a height ranging between approximately 50.0 nm and approximately 150.0 nm, between approximately 75.0 nm and approximately 100.0 nm, approximately 100.0 nm, or other similar values.

[0021] A memory device 115 is disposed over the bottom electrode via 109. The memory device 115 includes a bottom electrode 116 separated from a top electrode 120 by a data storage structure 118. The bottom electrode 116 has a bottom surface that physically contacts the top surfaces of the barrier 110, the adhesive layer 112, and the conductive core 114. In some embodiments, the bottom electrode 116 and / or the top electrode 120 may comprise a metal (e.g., tantalum, titanium, tungsten, or the like), a metal nitride (e.g., tantalum nitride, titanium nitride, or the like), or the like. In some embodiments, the adhesive layer 112 and the bottom electrode 116 may comprise or be the same material.

[0022] In some embodiments, the bottom electrode 116 may have outer sidewalls that are sloped to have slopes substantially similar to the slopes of the outer sidewalls of the data storage structure 118 and / or the top electrode 120. In other embodiments, the bottom electrode 116 may have outer sidewalls that are sloped to have slopes that are different from the slopes of the outer sidewalls of the data storage structure 118 and / or the top electrode 120. In some embodiments, the bottom electrode 109 may have outer sidewalls that are sloped to have slopes substantially similar to the slopes of the outer sidewalls of the bottom electrode 116, the data storage structure 118, and / or the top electrode 120.In other embodiments, the bottom electrode via 109 may have outer sidewalls that are sloped to have slopes that are different from the slopes of the outer sidewalls of the bottom electrode 116, the data storage structure 118, and / or the top electrode 120.

[0023] In some embodiments, the data storage structure 118 may include a magnetic tunnel junction (MTJ) structure. In such embodiments, the data storage structure 118 may include a pinned layer 206 separated from a free layer 210 by a dielectric tunnel barrier 208. The pinned layer 206 has a fixed magnetization, while the free layer 210 has a magnetization that can be changed during operation (through the tunnel magnetoresistance (TMR) effect) to either parallel (i.e., a "P" state) or antiparallel (i.e., an "AP" state) with respect to the magnetization of the pinned layer 206. A relationship between the magnetizations of the pinned layer 206 and the free layer 210 forms an ohmic state of the MTJ and thereby enables the MTJ to store a data state.

[0024] A top dielectric structure 104U is disposed over the bottom insulation structure 108 and the memory device 115. In various embodiments, the top dielectric structure 104U may comprise silicon dioxide, carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphorus silicate glass (PSG), borophosphosilicate glass (BPSG), fluorine silicate glass (FSG), a porous dielectric material (e.g., porous carbon-doped silicon dioxide), or the like. A top interconnect structure 122 extends through the top dielectric structure 104U and contacts the top electrode 120. In some embodiments, the top interconnect structure 122 may comprise an interconnect via and / or an interconnect wire. In various embodiments, the top interconnect structure 122 may comprise copper, tungsten, aluminum, or the like.

[0025] Fig. 3 illustrates a cross-sectional view of some additional embodiments of an integrated chip structure 300 including an MRAM device disposed over a multi-layer bottom electrode via having a relatively flat top surface.

[0026] The integrated chip structure 300 includes a bottom insulation structure 108 disposed over a bottom dielectric structure 104L surrounding one or more bottom interconnects 106 over a substrate 102. A bottom electrode via 109 is disposed directly between one or more inner sidewalls of the bottom insulation structure 108. The bottom electrode via 109 includes a barrier 110, an adhesive layer 112, and a conductive core 114. A memory device 115 is disposed on the bottom electrode via 109. The memory device 115 includes a bottom electrode 116 separated from a top electrode 120 by a data storage structure 118. The lower electrode 116 rests on uppermost surfaces of the barrier 110, the adhesive layer 112 and the conductive core 114.

[0027] The barrier 110 includes a sidewall extending along one or more inner sidewalls of the lower insulating structure 108, a horizontally extending surface projecting outwardly from the sidewall above a top surface of the lower insulating structure 108, and an outermost sidewall 302 connected to the horizontally extending surface. The outermost sidewall 302 of the barrier 110 is located directly above the top surface of the lower insulating structure 108. In some embodiments, the outermost sidewall 302 of the barrier 110 is laterally recessed from a curved outer sidewall 108c of the lower insulating structure 108 by a first non-zero distance 304. In such embodiments, the uppermost surface of the lower insulating structure 108, which is directly coupled to a curved outer sidewall 108c of the lower insulating structure 108, extends laterally beyond the outermost sidewall 302 of the barrier 110.In some additional embodiments, the outermost sidewall of the barrier 110 is also laterally recessed from an outermost sidewall 302 of the bottom electrode 116 by a second non-zero distance 306 such that the bottom electrode 116 overhangs the barrier 110 (e.g., such that the barrier 110 is undercut such that the outermost sidewall 302 is directly below a bottom surface of the bottom electrode 116). In some such embodiments, the top dielectric structure 104U may vertically contact the top surface of the bottom insulating structure 108 and the bottom surface of the bottom electrode 116.

[0028] In some alternative embodiments shown in cross-sectional view 308 of Fig. 3B, the outermost sidewall 302 of the barrier 110 is substantially coplanar with the outermost sidewall of the bottom electrode 116. In some such embodiments, both the outermost sidewall 302 of the barrier 110 and the outermost sidewall of the bottom electrode 116 are laterally recessed from the curved outer sidewalls 108c of the bottom insulating structure 108 by a third non-zero distance 310. In some such embodiments, the top dielectric structure 104U may vertically contact the top surface of the bottom insulating structure 108.

[0029] Fig. 4 illustrates a cross-sectional view of some additional embodiments of an integrated chip structure 400 including an MRAM device disposed over a multi-layer bottom electrode via having a relatively flat top surface.

[0030] The integrated chip structure 400 includes a substrate 102 having an embedded memory region 402 and a peripheral region 404. Within the embedded memory region 402, a bottom electrode via 109 is disposed within a bottom isolation structure 108 above a substrate 102. A memory device 115 is disposed on the bottom electrode via 109. One or more bottom interconnects 106 are configured to couple the memory device 115 to an access device 406 disposed on and / or within the substrate 102. In some embodiments, the access device 406 may comprise a MOSFET device (e.g., a planar FET, a FinFET, a gate-all-around (GAA) device, a nanolayer device, or the like) having a gate structure laterally disposed between a source region and a drain region.In some embodiments, the gate structure may include a gate electrode separated from the substrate 102 by a gate dielectric. In some such embodiments, the source region is coupled to a source line SL, and the gate structure is coupled to a word line WL. In other embodiments, the access device 406 may include a HEMT, a BJT, a JFET, or the like.

[0031] The memory device 115 includes a data storage structure 118 disposed between a bottom electrode 116 and a top electrode 120. The bottom electrode 116 is disposed over the bottom electrode via 109, and a seed layer 408 is disposed over the bottom electrode 116. The seed layer 408 separates the bottom electrode 116 from the data storage structure 118. In some embodiments, the seed layer 408 may include a tantalum nitride layer having a thickness between about 1.0 nm and about 4.0 nm, between about 1.0 nm and about 2.0 nm, about 2.0 nm, or other similar values. In some embodiments, the data storage structure 118 includes a magnetic tunnel junction (MTJ) structure. In such embodiments, the data storage structure 118 may include a pinned layer 206 separated from a free layer 210 by a dielectric tunnel barrier 208.Because the bottom electrode via 109 has a substantially flat top surface, the seed layer 408 can be used to form the pinned layer 206 with a relatively low roughness, thereby reducing defects in the dielectric tunnel barrier 208 (e.g., an MgO dielectric tunnel barrier).

[0032] In some embodiments, the top electrode 120 comprises a multi-layer structure. For example, the top electrode 120 may comprise a first top electrode layer 410, a second top electrode layer 412 on the first top electrode layer 410, and a third top electrode layer 414 on the second top electrode layer 412. In some embodiments, the first top electrode layer 410 may comprise a first metal (e.g., ruthenium), the second top electrode layer 412 may comprise a second metal (e.g., tungsten), and the third top electrode layer 414 may comprise a third metal (e.g., tantalum).

[0033] A protection layer 416 covers sidewalls of the memory device 115 and the bottom insulation structure 108. In some embodiments, the protection layer 416 may comprise an oxide (e.g., silicon-rich oxide, silicon dioxide, etc.), a nitride (e.g., silicon nitride, silicon oxynitride, etc.), a carbide (e.g., silicon carbide, silicon oxycarbide, etc.), or the like. A top interconnect structure 122 is disposed within a top dielectric structure 104U above the protection layer 416. The top interconnect structure 122 extends from a top surface of the top dielectric structure 104U to the topmost electrode 120. In some embodiments, the top interconnect structure 122 may comprise an interconnect via 418 and / or an interconnect wire 420. In some embodiments, the upper interconnect structure 122 may be a bit line BL and / or may be coupled to a bit line BL.

[0034] Within the peripheral region 404, an additional semiconductor device 422 is disposed on the substrate 102. The additional semiconductor device 422 may comprise a transistor device (e.g., a planar FET, a FinFET, a GAA device, etc.). The additional semiconductor device 422 is coupled to one or more additional lower interconnects 424. The one or more additional lower interconnects 424 are further coupled to one or more additional interconnects 426 that are laterally separated from the memory device 115.

[0035] Fig. 5 illustrates a cross-sectional view of some additional embodiments of an integrated chip structure 500 including an MRAM device disposed over a multi-layer bottom electrode via having a relatively flat top surface.

[0036] The integrated chip structure 500 includes a bottom electrode via 109 disposed over one or more bottom interconnects 106 within a bottom dielectric structure 104L over a substrate 102. The bottom electrode via 109 couples the one or more bottom interconnects 106 to a memory device 115 having a data storage structure 118 disposed between a bottom electrode 116 and a top electrode 120. The bottom electrode via 109 includes a barrier 110, an adhesive layer 112 over the barrier 110, and a conductive core 114 over the adhesive layer 112.

[0037] In some embodiments, the barrier 110 may have a first thickness 502 along one or more inner sidewalls of the lower insulating structure 108 and a second thickness 504 directly above a top surface of the lower insulating structure 108. In some embodiments, the first thickness 502 may be greater than the second thickness 504. In some embodiments, the first thickness 502 may be in a range between about 40% and about 70% greater than the second thickness 504. For example, the first thickness 502 may be in a range between about 7 nm (nanometers) and about 10 nm, may be between about 8 nm and about 9 nm, may be about 8.4 nm, or may be other similar values, while the second thickness 504 may be in a range between about 4 nm and about 6 nm, may be between about 5 nm and about 6 nm, may be about 5.4 nm, or may be other similar values.In some embodiments, the barrier 110 may have a third thickness 508, measured along a line oriented at an angle of approximately 45° with respect to a top surface of the barrier 110 and perpendicular to a surface of the lower insulating structure 108. The third thickness 508 is greater than the first thickness 502. In some embodiments, the third thickness 508 may be a maximum thickness of the barrier 110.

[0038] In some embodiments, a top surface of the conductive core 114 may be recessed a first non-zero distance 506 below a top surface of the barrier 110. In some embodiments, the first non-zero distance 506 may range between about 0.5 nm and about 3 nm, may range between about 1 nm and about 2 nm, may be about 1.9 nm, about 1.5 nm, about 1.3 nm, or about 0.9 nm, or may be other similar values. In some embodiments, the conductive core 114 may have a width that varies across the height of the conductive core 114. In some embodiments, the conductive core 114 may have a maximum width at a location a non-zero distance below the top surface of the conductive core 114. In some such embodiments, catch defects may be present along outer edges of the conductive core 114.However, the capture defects have a relatively small size (e.g., less than about 1 nm, less than about 0.5 nm, or other similar values) so that they have only a minimal impact on the data storage structure 118.

[0039] Fig. 6 illustrates a cross-sectional view of some additional embodiments of an integrated chip structure 600 including an MRAM device disposed over a multi-layer bottom electrode via having a relatively flat top surface.

[0040] The integrated chip structure 600 includes a memory device 115 disposed within a dielectric structure 104 disposed over a substrate 102. In some embodiments, the dielectric structure 104 includes a plurality of stacked inter-layer dielectric (ILD) layers 104a-104g. The plurality of stacked ILD layers 104a-104g includes one or more lower ILD layers 104a-104f laterally surrounding one or more lower interconnects 106 including conductive contacts, interconnect wires, and interconnect vias. In some embodiments, the plurality of stacked ILD layers 104a-104g may include one or more of silicon dioxide, SiCOH, a fluorosilicate glass, a phosphate glass (e.g., borophosphate silicate glass), or the like.In some embodiments, the one or more lower interconnects 106 may comprise a conductive metal such as copper, aluminum, and / or tungsten. In some embodiments, two or more adjacent ones of the plurality of stacked ILD layers 104a-104g may be separated by an etch stop layer (not shown) comprising a nitride, a carbide, or the like.

[0041] A bottom isolation structure 108 is located above the one or more bottom ILD layers 104a-104f. The bottom isolation structure 108 includes one or more inner sidewalls forming an opening extending through the bottom isolation structure 108. In various embodiments, the bottom isolation structure 108 may include a first bottom isolation layer 202 and a second bottom isolation layer 204 above the first bottom isolation layer 202. A bottom electrode via 109 is disposed between the one or more inner sidewalls of the bottom isolation structure 108. The bottom electrode via 109 couples the one or more bottom interconnects 106 to a memory device 115. In some embodiments, the memory device 115 includes a bottom electrode 116 separated from a top electrode 120 by a data storage structure 118.In some embodiments, the top electrode 120 may extend laterally beyond one or more sides of the data storage structure 118. In some embodiments, the top electrode 120 may serve as a bit line or may be electrically coupled to a bit line. In some embodiments, the top electrode 120 may be disposed over a top surface of the ILD layer 104g and / or a protection layer 416.

[0042] In some embodiments, the one or more lower interconnects 106 may include an interconnect wire 107 that extends laterally from directly below the storage device 115 to laterally outside the storage device 115. In some such embodiments, the interconnect wire 107 may couple the storage device 115 to an access device 406 that is also laterally outside the storage device 115. In some embodiments, the access device 406 may be disposed within a peripheral region 404 that is laterally outside the embedded storage region 402.

[0043] Fig. 7-19 illustrate cross-sectional views 700-1900 showing some embodiments of a method for forming an integrated chip structure including a memory device disposed over a multi-layer bottom electrode via having a relatively flat top surface. Although the Fig. 7-19 with reference to a method, it is understood that the Fig. 7-19 are not limited to such a method, but rather can stand alone as structures independent of the method.

[0044] As shown in cross-sectional view 700 of Fig. 7, a substrate 102 is provided. In various embodiments, the substrate 102 may be any type of semiconductor body (e.g., silicon, SiGe, SOI, etc.), such as a semiconductor wafer and / or one or more dies on a wafer, as well as any other type of semiconductor and / or epitaxial layers associated therewith. In some embodiments, the substrate 102 includes an embedded memory region 402 and a peripheral region 404 (e.g., a logic region, a chip boundary region, etc.).

[0045] In some embodiments, an access device 406 is formed on the substrate 102 within the embedded memory region 402. In some embodiments, the access device 406 may include a transistor (e.g., a planar FET, a FinFET, a GAA transistor, a nanolayer transistor, or the like). In some embodiments, the access device 406 may be formed by depositing a gate dielectric film and a gate electrode film over the substrate 102. The gate dielectric film and the gate electrode film are then patterned to form a gate dielectric and a gate electrode. The substrate 102 may then be implanted to form a source region and a drain region within the substrate 102 on opposite sides of the gate electrode.In some embodiments, an additional semiconductor device 422 may be formed on the substrate 102 within the peripheral region 404.

[0046] In some embodiments, one or more lower interconnects 106 may be formed within a lower dielectric structure 104L formed over the embedded memory region 402 of the substrate 102. In some embodiments, the lower dielectric structure 104L may include one or more stacked ILD layers. In some embodiments, the one or more lower interconnects 106 may include one or more of a conductive contact, an interconnect wire, and an interconnect via.The one or more lower interconnects 106 may be formed by forming an ILD layer of the one or more lower ILD layers (e.g., an oxide, a low-k dielectric, or an ultra-low-k dielectric) over the substrate 102, selectively etching the ILD layer to form a via and / or a trench within the ILD layer, forming a conductive material (e.g., copper, aluminum, etc.) within the via and / or the trench, and performing a planarization process (e.g., a chemical mechanical planarization process) to remove excess conductive material over the ILD layer. In some embodiments, one or more additional lower interconnects 424 may be formed within the lower dielectric structure 104L over the peripheral region 404 of the substrate 102.

[0047] As shown in cross-sectional view 800 of Fig. 8, a lower insulation structure 108 is formed over the lower dielectric structure 104L. In some embodiments, the lower insulation structure 108 comprises a plurality of different stacked dielectric materials. For example, in some embodiments, the lower insulation structure 108 comprises a first lower insulation layer 202 and a second lower insulation layer 204 over the first lower insulation layer 202. In some embodiments, the first lower insulation layer 202 may comprise silicon-rich oxide, silicon carbide, silicon nitride, or the like. In some embodiments, the second lower insulation layer 204 may comprise silicon carbide, silicon nitride, or the like.In some embodiments, the lower insulation structure 108 may be formed by one or more deposition processes (e.g., a PVD process, a CVD process, a PE-CVD process, high-density ionized metal plasma (IMP) deposition, high-density inductively coupled plasma (ICP) deposition, a sputtering process, low-pressure chemical vapor deposition (LP-CVD), or the like).

[0048] As shown in cross-sectional view 900 of Fig. 9, the lower insulation structure 108 is patterned to form a bottom electrode via opening 902 extending through the lower insulation structure 108 to expose the one or more lower interconnects 106. In some embodiments, the bottom electrode via opening 902 may be formed according to a first patterning process. In some embodiments, the first patterning process may be performed by selectively contacting the lower insulation structure 108 with a first etchant 904 according to a first mask 906. The first patterning process forms the bottom electrode via opening 902 defined by one or more inner sidewalls of the lower insulation structure 108.In some embodiments, the first etchant 904 may comprise a plasma etchant having a fluorine-based etch chemistry (e.g., an SF6 plasma or the like). In some embodiments, the first mask 906 may comprise a photoresist, a hard mask, or the like.

[0049] As shown in the cross-sectional view 1000 of Fig. 10, a barrier layer 1004 is formed within the bottom electrode via opening 902 and over the bottom isolation structure 108. In some embodiments, the barrier layer 1004 may comprise a metal nitride such as titanium nitride, tantalum nitride, or the like. In various embodiments, the barrier layer 1004 may be formed to a thickness ranging between approximately 5.0 nm and approximately 10.0 nm, between approximately 7.5 nm and approximately 8.5 nm, approximately 8.0 nm, or other similar values. In some embodiments, the barrier layer 1004 may be formed by a deposition process (e.g., a PVD process, a CVD process, a PE-CVD process, a high-density IMP deposition, a high-density ICP deposition, a sputtering process, an LP-CVD process, or the like).

[0050] As shown in cross-sectional view 1100 of Fig. 11, an adhesive interlayer 1102 is formed within the bottom electrode via opening 902 and over the barrier layer 1004. In some embodiments, the adhesive interlayer 1102 may comprise a metal nitride such as titanium nitride, tantalum nitride, or the like. In some embodiments, the adhesive interlayer 1102 may be formed to a thickness ranging between about 5.0 nm and about 10.0 nm, between about 5.0 nm and about 7.5 nm, about 6.0 nm, or other similar values. In some embodiments, the adhesive interlayer 1102 may be formed by a deposition process (e.g., a PVD process, a CVD process, a PE-CVD process, a high-density IMP deposition, a high-density ICP deposition, a sputtering process, an LP-CVD process, or the like).

[0051] As shown in the cross-sectional view 1200 of Fig. 12, a conductive core material 1202 is formed within the bottom electrode via opening 902 and over the interlayer adhesive layer 1102. In some embodiments, the conductive core material 1202 may comprise and / or be tungsten. In some embodiments, the conductive core material 1202 may be formed to a thickness ranging between about 5.0 nm and about 150.0 nm, between about 75.0 nm and about 100.0 nm, about 100.0 nm, or other similar values. In some embodiments, the conductive core material 1202 may include surfaces defining a recess 1204 disposed along a top surface of the conductive core material 1202.In some embodiments, the conductive core material 1202 may be formed by a deposition process (e.g., a PVD process, a CVD process, a PE-CVD process, a high-density IMP deposition, a high-density ICP deposition, a sputtering process, an LP-CVD process, or the like) and / or a plating process (e.g., electroplating, electroless plating, etc.).

[0052] As shown in cross-sectional view 1300 of Fig. 13, a mechanical polishing process 1302 is performed on the conductive core material 1202. The mechanical polishing process 1302 removes a portion of the conductive core material 1202 such that the upper surfaces of the barrier layer 1004, the adhesive interlayer 1102, and the lower insulating structure 108 are exposed. In some embodiments, the mechanical polishing process 1302 may also remove portions of the barrier layer 1004, the adhesive interlayer 1102, and / or the lower insulating structure 108. In some embodiments, the mechanical polishing process 1302 may use a first slurry 1304 comprising an oxidizing agent. In some embodiments, the oxidizing agent may comprise hydrogen peroxide (H2O2), ferric nitrate (Fe(NO3)3), or other similar oxidizing agents.

[0053] In some embodiments, the first slurry 1304 may include a first pH value. The first pH value may range between about 2 and about 9, may be between about 2 and about 3, may be about 2.2, or may have other similar values. The first slurry 1304 may be configured to adjust the mechanical polishing process 1302 to a first removal rate for the conductive core material 1202, a second removal rate for the barrier layer 1004, and a third removal rate for the lower insulation structure 108. In some embodiments, the first removal rate is much greater than the second removal rate, and the second removal rate is much greater than the third removal rate. For example, the first removal rate may be about 159.5 nm / min, the second removal rate may be about 9.5 nm / min, and the third removal rate may be about 1.3 nm / min.The relatively high initial removal rate allows the mechanical polishing process 1302 to quickly remove the conductive core material 1202, thereby achieving high throughput.

[0054] After completion of the mechanical polishing process 1302, the barrier layer 1004 may have a first thickness 1306 directly above the top surface of the lower insulating structure 108. In various embodiments, the first thickness 1306 may be in a range between approximately 8 nm and approximately 10 nm, may be between approximately 8 nm and approximately 10 nm, may be approximately 9 nm, may be approximately 8.4 nm, or may have other similar values. In some embodiments, after completion of the mechanical polishing process 1302, the conductive core material 1202 may include one or more capture defects 1308 along outer edges of the conductive core material 1202. The one or more capture defects 1308 include recessed areas (e.g., one or more breakouts) along the outer edges of the conductive core material 1202.In some embodiments, the one or more capture defects 1308 may extend to depths ranging between about 2.5 nm and about 7.5 nm, between about 4.0 nm and about 6.0 nm, or other similar values. In some embodiments, a cup-shaped region 1310 may also be present after completion of the mechanical polishing process. The cup-shaped region 1310 includes a region of the barrier layer 1004, the adhesive interlayer 1102, and / or the conductive core material 1202 that is recessed below a top surface of the barrier layer 1004. In some embodiments, the cup-shaped region 1310 may have a first maximum depth 1312 ranging between about 4 nm and about 5 nm, about 5 nm, about 4.7 nm, about 4.5 nm, or about 4.2 nm, or other similar values.

[0055] As shown in the cross-sectional view 1400 of Fig. 14, a polishing process 1402 is performed on the barrier layer 1004, the adhesive layer (for example, 1102 of Fig. 13) and the conductive core material (for example 1202 of Fig. 13) is performed to form a conductive core 114 on an adhesive layer 112. In some embodiments, the polishing process 1402 may use a second slurry 1404 that is free of an oxidant (e.g., does not contain an oxidant). Using a second slurry 1404 that is free of an oxidant reduces galvanic corrosion between the conductive core 114 and the adhesive layer 112, thereby minimizing a size of the one or more capture defects along outer edges of the conductive core 114. By minimizing the size of the one or more capture defects along outer edges of the conductive core 114, the polishing process 1402 is able to form a more planar top interface extending along the top surfaces of the conductive core 114, the adhesive layer 112, and the barrier layer 112.By using the polishing process to form a planar top interface, overlying layers are planar, thereby improving the performance of an overlying data storage structure (for example, an overlying MTJ).

[0056] The polishing process 1402 may also reduce a depth of the cup-shaped region from a first maximum depth (for example, 1312 in Fig. 14) to a second maximum depth 1406. In some embodiments, the second maximum depth 1406 is in a range between about 0.5 nm and about 2 nm, is less than 2 nm, about 1.9 nm, about 1.5 nm, about 1.3 nm, about 0.9 nm, or may be other similar values. In some embodiments, the polishing process 1402 may reduce a depth of the cup-shaped region by about 40% to about 50%. For example, the polishing process 1402 may reduce a maximum depth of the cup-shaped region from a first maximum depth (e.g., 1312 in Fig. 13) of approximately 4.7 nm to a second maximum depth 1406 of approximately 1.9 nm.

[0057] In some embodiments, the polishing process 1402 may also reduce the thickness of a portion of the barrier layer 1004 within the embedded memory region 402. For example, the polishing process 1402 may reduce a thickness of the barrier layer 1004 directly above the top surface of the lower isolation structure 108 from the first thickness (e.g., 1308 of Fig. 13) to a second thickness 1408 that is less than the first thickness. In some embodiments, the polishing process 1402 may reduce the thickness of the barrier layer 1004 directly above the top surface of the lower isolation structure 108 by approximately 30% to approximately 40%. For example, in some embodiments, the polishing process 1402 may reduce the thickness of the barrier layer 1004 from a first thickness of approximately 8.4 nm to a second thickness 1408 of approximately 5.4 nm. Reducing the thickness of the barrier layer 1004 directly above the top surface of the lower isolation structure 108 may result in the barrier layer 1004 having a greater thickness along the one or more inner sidewalls of the lower isolation structure 108 than directly above the top surface of the lower isolation structure 108.

[0058] In some embodiments, the polishing process 1402 may result in the barrier layer 1004 having different thicknesses in different regions of a substrate 102. For example, the barrier layer 1004 may have a second thickness 1408 within the embedded memory region 402 and a third thickness 1410 within the peripheral region 404. In some embodiments, the second thickness may be less than the third thickness 1410. For example, the second thickness 1408 may be approximately 3.0 nm, while the third thickness 1410 is approximately 7.0 nm. In some embodiments, the thickness difference between the second thickness 1408 and the third thickness 1410 may be due to a stress effect of the polishing process 1402 caused by a high density of bottom electrode vias within a memory array of the embedded memory region 402.The stress effect causes the barrier layer 1004 to be removed more quickly in the embedded memory region 402 than in the peripheral region 404.

[0059] In some embodiments, the second slurry 1404 may include a second pH value. The second pH value may be higher than the first pH value. In various embodiments, the second pH value may be in a range between about 4 and about 8, may be between about 5 and about 7, may be about 6, or may have other similar values. The second slurry 1404 may be configured to have a first removal rate for the conductive core material, a second removal rate for the barrier layer, and a third removal rate for the lower insulation structure. In some embodiments, the first removal rate is approximately equal to the second removal rate and less than the third removal rate. In some embodiments, the first removal rate is between about 0.0 nm / min and about 0.5 nm / min, the second removal rate is between about 0.0 nm / min and about 0.5 nm / min, and the third removal rate is about 335.0 nm / min.In some embodiments, the polishing process 1402 may be performed for a period of time ranging between about 200 seconds and about 300 seconds, between about 225 seconds and about 250 seconds, about 240 seconds, or other similar values.

[0060] In some embodiments, the second slurry 1404 may contain a water-soluble polymer, cerium hydroxide (Ce(OH)4), imidazole (C3H4N2), acetic acid (C2H4O2), and / or purified water. The water-soluble polymer content may be between about 0.5% and about 10% of the weight of the second slurry. The cerium hydroxide content may be between about 0.1% and about 1.0% of the weight of the second slurry. The imidazole content may be less than about 1% of the weight of the second slurry. The acetic acid content may be less than about 1% of the weight of the second slurry. The purified water content may be between about 89.9% and about 99.4% of the weight of the second slurry.

[0061] As shown in the cross-sectional view 1500 of Fig. 15, a bottom electrode layer 1502 is formed over the barrier layer 1004, the adhesive layer 112, and the conductive core 114. The bottom electrode layer 1502 may be formed to contact the conductive core 114. In various embodiments, the bottom electrode layer 1502 may comprise a metal (e.g., tantalum), a metal nitride (e.g., tantalum nitride), or the like. In some embodiments, the bottom electrode layer 1502 may be formed by one or more deposition processes (e.g., a PVD process, a CVD process, a PE-CVD process, a high-density IMP deposition, a high-density ICP deposition, a sputtering process, an LP-CVD process, or the like).

[0062] A data storage layer 1504 is formed over the bottom electrode layer 1502. The data storage layer 1504 may be formed to contact the bottom electrode layer 1502. In various embodiments, the data storage layer 1504 may include a magnetic tunnel junction (MTJ) structure. In some embodiments, the data storage layer 1504 may be formed by one or more deposition processes (e.g., a PVD process, a CVD process, a PE-CVD process, a high-density IMP deposition, a high-density ICP deposition, a sputtering process, an LP-CVD process, or the like).

[0063] A top electrode structure 1506 is formed over the data storage layer 1504. The top electrode structure 1506 may be formed to contact the data storage layer 1504. In various embodiments, the top electrode structure 1506 may comprise a metal (e.g., titanium), a metal nitride (e.g., titanium nitride), or the like. In some embodiments, the top electrode structure 1506 may comprise a multi-layer structure. For example, the top electrode layer may comprise a first top electrode layer 1508, a second top electrode layer 1510, and a third top electrode layer 1512. The first top electrode layer 1508 may comprise a first metal (e.g., ruthenium), the second top electrode layer 1510 may comprise a second metal (e.g., tungsten), and the third top electrode layer 1512 may comprise a third metal (e.g., tantalum).In some embodiments, the top electrode structure 1506 may be formed by one or more deposition processes (e.g., a PVD process, a CVD process, a PE-CVD process, a high-density IMP deposition, a high-density ICP deposition, a sputtering process, an LP-CVD process, or the like).

[0064] As shown in the cross-sectional view 1600 of Fig. 16, a second mask 1602 is formed over the top electrode structure 1506. In some embodiments, the second mask 1602 may have a multi-layer structure. For example, the second mask 1602 may include a first oxide 1604 (e.g., a silicon-rich oxide, silicon oxynitride, or the like), an advanced patterning film (APF) 1606, and a second oxide 1608 (e.g., a silicon-rich oxide, silicon oxynitride, or the like). In some additional embodiments, the second mask 1602 may further include an anti-reflective coating 1610 on the second oxide 1608 and a photoresist material 1612 on the anti-reflective coating 1610.In various embodiments, the first oxide 1604, the APF 1606, and the second oxide 1608 may be formed by deposition processes (e.g., a PVD process, a CVD process, a PE-CVD process, a high-density IMP deposition, a high-density ICP deposition, a sputtering process, an LP-CVD process, or the like).

[0065] As shown in the cross-sectional view 1700 of Fig. 17, a second patterning process is performed. The second patterning process etches the top electrode structure (1506 of Fig. 16), the data storage layer (for example 1504 of Fig. 16) and the lower electrode layer (for example 1502 of Fig. 16) to form a memory device 115 having a data storage structure 118 disposed between a bottom electrode 116 and a top electrode 120. In some additional embodiments, the second patterning process also etches the barrier layer (e.g., 1004 of Fig. 14) to form a bottom electrode via 109 having a barrier 110 separated from the conductive core 114 by the adhesive layer 112. In some additional embodiments, the second patterning process also etches the bottom insulating structure 108 to form curved outer sidewalls 108c of the bottom insulating structure 108. In some embodiments, the second patterning process selectively contacts the top electrode structure, the data storage layer, and the bottom electrode layer with a second etchant 1702 according to the second mask 1602. In some embodiments, the second patterning process may include a focused ion beam etching (FIBE) process. In other embodiments, the second patterning process may be a reactive ion etching process, an ion beam etching process, a sputter etching process, or the like.

[0066] As shown in the cross-sectional view 1800 of Fig. 18, a third patterning process is performed. The third patterning process removes the second mask (for example, 1602 from Fig. 17), the top electrode structure (for example 1506 of Fig. 17), the data storage layer (for example 1504 of Fig. 17) and the lower electrode layer (for example 1502 of Fig. 17) within the peripheral region 404. In some embodiments, the third patterning process may further form the barrier layer (e.g., 1004 of Fig. 17) and remove a portion of the lower insulation structure 108 (e.g., the second lower insulation layer 204) within the peripheral region 404. In some embodiments, the third patterning process may be performed by contacting the peripheral region 404 with one or more etchants 1802, with a third mask 1804 disposed over the embedded memory region 402. In some embodiments, an embedded memory region ILD layer 1806 is formed within the embedded memory region 402 before the third mask 1804 is formed.

[0067] As shown in the cross-sectional view from 1900 by Fig. 19, a top dielectric structure 104U is formed over the memory device 115. In some embodiments, the top dielectric structure 104U may be formed by a deposition process (e.g., a PVD process, a CVD process, a PE-CVD process, a high-density IMP deposition, a high-density ICP deposition, a sputtering process, an LP-CVD process, or the like). In various embodiments, the top dielectric structure 104U may comprise silicon dioxide, carbon-doped silicon dioxide, silicon oxynitride, BSG, PSG, BPSG, FSG, a porous dielectric material (e.g., porous carbon-doped silicon dioxide), or the like.

[0068] A top interconnect structure 122 is formed in the top dielectric structure 104U within the embedded memory region 402, and one or more additional interconnect connections 426 are formed in the top dielectric structure 104U within the peripheral region 404. In some embodiments, the top interconnect structure 122 may include an interconnect via and / or an interconnect wire. In some embodiments, the one or more additional interconnect connections 426 may include an interconnect via and an interconnect wire.The upper interconnect structure 122 and the one or more additional interconnect connections 426 may be formed simultaneously by selectively etching the upper dielectric structure 104U to form via holes and / or trenches within the upper dielectric structure 104U, forming a conductive material (e.g., copper, aluminum, etc.) within the via holes and / or trenches, and performing a planarization process (e.g., a chemical mechanical planarization process). In some embodiments, the planarization process may include a chemical mechanical planarization (CMP) process.

[0069] Fig. 20 illustrates a flowchart of some embodiments of a method 2000 for forming an integrated chip structure including a memory device disposed over a multi-layer bottom electrode via having a relatively flat top surface.

[0070] Although the method 2000 is illustrated and described herein as a series of actions or events, it should be understood that the illustrated order of such actions or events should not be construed in a limiting sense. For example, some actions may be performed in a different order than shown and / or described herein and / or concurrently with other actions or events. Furthermore, not all of the illustrated actions may be required to implement one or more aspects or embodiments of the description provided herein. Moreover, one or more of the actions shown herein may be performed in one or more separate actions and / or phases.

[0071] In Action 2002, one or more lower interconnects are formed within a lower dielectric structure formed over a substrate.

[0072] Fig. 7 illustrates a cross-sectional view 700 of some embodiments according to Action 2002.

[0073] In Action 2004, a lower insulating structure is formed over the lower dielectric structure. Fig. 8 illustrates a cross-sectional view 800 of some embodiments according to Action 2004.

[0074] In Action 2006, the lower insulation structure is patterned to form a bottom electrode via (BEVA) opening that exposes the one or more lower interconnects. Fig. 9 illustrates a cross-sectional view 900 of some embodiments according to Action 2006.

[0075] In Action 2008, a bottom electrode via structure is formed within the BEVA opening and over the bottom insulation structure. In some embodiments, the bottom electrode via layer may be formed according to Actions 2010-2018.

[0076] In Action 2010, a barrier layer is formed within the BEVA opening and above the lower insulation structure. Fig. 10 illustrates a cross-sectional view 1000 of some embodiments according to Action 2010.

[0077] In Action 2012, an adhesive interlayer is formed within the BEVA opening and above the barrier layer. Fig. 11 illustrates a cross-sectional view 1100 of some embodiments according to the 2012 Action.

[0078] In Action 2014, a conductive core material is formed within the BEVA opening and above the adhesive interlayer. Fig. 12 illustrates a cross-sectional view 1200 of some embodiments according to the 2014 Action.

[0079] In Action 2016, a mechanical polishing process is performed to remove portions of the barrier layer, the adhesive interlayer, and / or the conductive core material. Fig. 13 illustrates a cross-sectional view 1300 of some embodiments according to the 2016 Action.

[0080] In Action 2018, a polishing process without oxidizer is performed to remove portions of the barrier layer, the adhesive interlayer and / or the conductive core material and to form the bottom electrode via structure. Fig. 14 illustrates a cross-sectional view 1400 of some embodiments according to the 2018 Action.

[0081] In Action 2020, a bottom electrode layer is formed over the bottom electrode via structure. Fig. 15 illustrates a cross-sectional view 1500 of some embodiments according to the 2020 campaign.

[0082] In Action 2022, a data storage layer is formed over the bottom electrode layer. Fig. 15 illustrates a cross-sectional view 1500 of some embodiments according to Action 2022.

[0083] In action 2024, a top electrode layer is formed over the data storage layer. Fig. 15 illustrates a cross-sectional view 1500 of some embodiments according to action 2024.

[0084] At action 2026, the bottom electrode via structure, the bottom electrode layer, the data storage layer, and the top electrode layer are patterned to form a memory device over a bottom electrode via. Fig. 16-17 illustrate cross-sectional views 1600-1700 of some embodiments corresponding to Action 2026.

[0085] At action 2028, an upper interconnect structure is formed on the memory device. Fig. 18 illustrates a cross-sectional view 1800 of some embodiments corresponding to action 2028.

[0086] Accordingly, in some embodiments, the present disclosure relates to an integrated chip structure including a magnetic random access memory (MRAM) device disposed over a multilayer bottom electrode via formed using an oxidant-free polishing process. The oxidant-free polishing process mitigates trap defects to provide the bottom electrode via with a substantially flat top surface, reducing defects within an overlying data storage structure.

[0087] In some embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure includes: a bottom insulation structure disposed over a bottom dielectric structure surrounding one or more bottom interconnects; a bottom electrode via surrounded by one or more inner sidewalls of the bottom insulation structure and comprising a barrier surrounding a conductive core; a bottom electrode disposed on the bottom electrode via; a data storage structure over the bottom electrode; a top electrode over the data storage structure; and the barrier having a sidewall disposed along the one or more inner sidewalls of the bottom insulation structure and a horizontally covering segment projecting outwardly from the sidewall to above a top surface of the bottom insulation structure.In some embodiments, the integrated chip structure further comprises an adhesive layer disposed on the barrier, wherein the bottom electrode contacts the top surface of the adhesive layer and the barrier. In some embodiments, the barrier has an outer sidewall located directly below a bottom surface of the bottom electrode and directly above the top surface of the bottom insulation structure. In some embodiments, the outer sidewall of the barrier is laterally separated from an outer sidewall of the bottom electrode by a non-zero distance. In some embodiments, the top surface of the bottom insulation structure extends laterally beyond an outer sidewall of the barrier. In some embodiments, the barrier has a first thickness along the one or more inner sidewalls and a second thickness directly above the top surface of the bottom insulation structure, wherein the first thickness is greater than the second thickness.In some embodiments, the barrier has a third thickness measured along a line oriented at an angle of approximately 45° with respect to a top surface of the barrier and perpendicular to a surface of the lower insulating structure, the third thickness being greater than the first thickness.

[0088] In other embodiments, the present disclosure relates to an integrated chip structure. The integrated chip structure comprises: a bottom insulation structure disposed over one or more bottom interconnects, the bottom insulation structure having one or more inner sidewalls disposed over the one or more bottom interconnects; a bottom electrode via surrounded by the one or more inner sidewalls and comprising: a barrier disposed along the one or more inner sidewalls and over the bottom insulation structure; an adhesive layer disposed on the barrier; a tungsten core disposed on the adhesive layer; a bottom electrode disposed on the bottom electrode via; a magnetic tunnel junction structure disposed over the bottom electrode;a top electrode disposed above the magnetic tunnel junction structure; and wherein the bottom electrode contacts the top surface of the barrier, the adhesive layer, and the tungsten core and is vertically separated from a top surface of the bottom insulating structure. In some embodiments, the barrier has a horizontally covering surface that projects outward from a sidewall of the barrier beyond the top surface of the bottom insulating structure; and the barrier completely covers opposing outer sidewalls of the adhesive layer, as viewed in a cross-sectional view. In some embodiments, the tungsten core has a width that varies across a height of the tungsten core, with the tungsten core having a maximum width at a location a non-zero distance below a top surface of the tungsten core. In some embodiments, the adhesive layer and the bottom electrode are the same material.

[0089] In further embodiments, the present disclosure relates to a method of forming an integrated chip structure. The method includes: forming a lower insulation structure over a lower dielectric structure surrounding one or more lower interconnects; patterning the lower insulation structure to form a lower electrode via opening exposing the one or more lower interconnects; forming a barrier layer within the lower electrode via and over the lower insulation structure; forming a conductive core material over the barrier layer; performing a mechanical polishing process to remove a first portion of the conductive core material; performing a polishing process,to remove a second portion of the conductive core material and form a conductive core; forming a bottom electrode layer on the conductive core and the barrier layer; forming a data storage layer on the bottom electrode layer; and forming a top electrode layer on the data storage layer. In some embodiments, the method further comprises using a focused ion beam etching (FIBE) process to pattern the top electrode layer, the data storage layer, the bottom electrode layer, the barrier layer, and the bottom insulation structure. In some embodiments, the FIBE process causes the bottom insulation structure to have one or more curved outer sidewalls,that point away from the conductive core material and that are coupled to a top surface of the lower insulation structure. In some embodiments, the mechanical polishing process forms a cup-shaped region of the conductive core material that is recessed below a top surface of the barrier layer. In some embodiments, the mechanical polishing process forms one or more capture defects having a first depth and disposed along outer edges of the conductive core material. In some embodiments, the polishing process reduces the first depth of the one or more capture defects to a second depth that is less than the first depth. In some embodiments, the polishing process is performed using a slurry,which is free of an oxidizing agent. In some embodiments, the method further comprises: forming an intermediate adhesive layer on the barrier layer; and forming the conductive core material on the intermediate adhesive layer. In some embodiments, the polishing process causes the barrier layer to have a first thickness within an embedded storage region including the bottom electrode via opening and a second thickness in a peripheral region outside the embedded storage region, the second thickness being greater than the first thickness.

Claims

[1] Integrated chip structure (100, 200, 300, 400, 500, 600) comprising: a lower insulating structure (108) disposed over a lower dielectric structure (104L) surrounding one or more lower interconnects (106); a bottom electrode via (109) surrounded by one or more inner sidewalls of the bottom insulating structure (108) and comprising a barrier (110) surrounding a conductive core (114), the barrier (110) comprising a sidewall disposed along the one or more inner sidewalls of the bottom insulating structure (108) and a horizontally covering segment projecting outwardly from the sidewall to above a top surface of the bottom insulating structure (108); a lower electrode (116) disposed on the lower electrode via (109); a data storage structure (118) over the lower electrode (116); a top electrode (120) above the data storage structure (118); and an adhesive layer (112) disposed on the barrier (110), wherein the lower electrode (116) contacts a top surface of the adhesive layer (112) and the barrier (110), wherein a material of the adhesive layer (112) has a higher corrosion potential than a material of the conductive core (114). [2] The integrated chip structure of claim 1, wherein the barrier (110) has an outermost sidewall (302) connected to the horizontally covering segment and located directly below a lower surface of the lower electrode (116) and directly above the top surface of the lower insulation structure (108). [3] The integrated chip structure of claim 2, wherein the outermost sidewall (302) of the barrier (110) is laterally separated from an outer sidewall of the bottom electrode (116) by a non-zero distance. [4] The integrated chip structure of claim 1, wherein the top surface of the lower isolation structure (108) extends laterally beyond an outer sidewall of the barrier (110). [5] The integrated chip structure of claim 4, wherein the barrier (110) has a first thickness along the one or more inner sidewalls and a second thickness directly above the top of the lower isolation structure (108), the first thickness being greater than the second thickness. [6] The integrated chip structure of any preceding claim, wherein the conductive core (114) comprises tungsten and wherein the adhesive layer comprises titanium. [7] Integrated chip structure comprising: a lower insulation structure (108) disposed over one or more lower interconnects (106), the lower insulation structure (108) comprising one or more inner sidewalls forming an opening extending through the lower insulation structure and disposed over the one or more lower interconnects (106); a bottom electrode via (109) surrounded by the one or more inner sidewalls and comprising: a barrier (110) within the opening, the barrier being disposed along the one or more inner sidewalls and above the lower insulation structure (108); an adhesive layer (112) within the opening disposed over the barrier (110), the adhesive layer comprising titanium; and a tungsten core within the opening disposed over the adhesive layer (112); a lower electrode (116) disposed on the lower electrode via (109); a magnetic tunnel junction structure disposed over the lower electrode (116); and a top electrode (120) disposed above the magnetic tunnel junction structure; wherein the lower electrode (116) contacts a top surface of the barrier (110), the adhesive layer (112) and the tungsten core and is vertically separated from a top surface of the lower insulating structure (108). [8] Integrated chip structure according to claim 7, the barrier (110) comprises a horizontally covering surface which projects outwardly from a side wall of the barrier (110) beyond the top of the lower insulating structure (108); and wherein the barrier (110) - viewed in a cross-sectional view - completely covers opposite outer side walls of the adhesive layer (112). [9] The integrated chip structure of claim 7, wherein the tungsten core has a width that varies across a height of the tungsten core, the tungsten core having a maximum width at a location that is a distance equal to zero below a top surface of the tungsten core. [10] The integrated chip structure of claim 7, wherein the adhesive layer (112) and the lower electrode (116) are a same material. [11] A method of forming an integrated chip structure, comprising: Forming a lower insulating structure (108) over a lower dielectric structure surrounding one or more lower interconnects (106); Patterning the lower insulation structure (108) to form a lower electrode via opening (902) exposing the one or more lower interconnects (106); Forming a barrier layer (1004) within the bottom electrode via opening (902) and over the bottom insulation structure (108); Forming a conductive core material (1202) over the barrier layer; performing a mechanical polishing process (1302) to remove a first portion of the conductive core material; Performing a polishing process (1402) to remove a second portion of the conductive core material and form a conductive core (114), wherein the polishing process is performed using a slurry that is free of an oxidizing agent; Forming a lower electrode layer (1502) on the conductive core and the barrier layer; Forming a data storage layer (1504) on the bottom electrode layer; and Forming a top electrode layer (1506) on the data storage layer. [12] The method of claim 11, further comprising: Using a focused ion beam etching process to pattern the top electrode layer, the data storage layer, the bottom electrode layer, the barrier layer and the bottom insulation structure (108). [13] The method of claim 12, wherein the focused ion beam etching process causes the lower insulating structure (108) to have one or more curved outer sidewalls facing away from the conductive core material and connected to a top surface of the lower insulating structure (108). [14] The method of claim 11, wherein the mechanical polishing process forms a cup-shaped region of the conductive core material recessed beneath a top surface of the barrier layer. [15] The method of claim 11, wherein the polishing process reduces the first depth of the one or more trap defects to a second depth that is less than the first depth. [16] The method of claim 11, further comprising: Forming an intermediate adhesive layer on the barrier layer; and Forming the conductive core material on the adhesive interlayer.

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