SEMICONDUCTOR DEVICE WITH METAL NITRIDE LAYER AND A METHOD FOR MANUFACTURING THE SAME

Abstract

A semiconductor device (100) comprising a semiconductor substrate (10) and a metal nitride layer (20) above the semiconductor substrate (10), wherein the metal nitride layer (20) forms at least one interface region (15) with the semiconductor substrate (10), wherein the nitrogen content in the metal nitride layer (20) has a maximum at or at a depth of a few atomic layers from the at least one interface region (15), and the maximum is obtained by a method according to any one of claims 9 to 14.

Description

TECHNICAL FIELD

[0001] The present disclosure generally relates to semiconductor devices comprising a metal nitride layer as a metallization structure for ohmic contacts to a semiconductor substrate, in particular a metallization structure for ohmic backside contacts. Furthermore, embodiments relate to methods for producing semiconductor devices comprising a metal nitride layer for forming ohmic contacts. BACKGROUND

[0002] Semiconductor devices include metal or metallization structures for contacting the active regions of the semiconductor substrate. For example, Al-based metal structures or layers are typically formed in contact with active regions on the front side of the semiconductor substrate. Bond wires attached to the Al-based metal structures provide the connection to leadouts of the package into which the semiconductor device is integrated or embedded. Examples of packages include discrete TO packages for accommodating a single semiconductor device or power modules that house two or more separate semiconductor devices.

[0003] Vertical semiconductor devices require additional electrical contact on the backside of the semiconductor device, provided by a so-called backside metallization. In addition to providing a low-resistance ohmic contact to the semiconductor substrate, the backside metallization also provides a mechanical connection between the semiconductor substrate and a package or carrier substrate. Typically, the backside metallization is soldered to a lead frame. The metallization structures and solder connections must be reliable throughout the lifetime of the semiconductor device and should withstand mechanical stress caused by thermal cycling, which occurs during operation of the semiconductor device.

[0004] To provide a good and reliable ohmic connection, a metal layer capable of forming a metal silicide interface with the semiconductor substrate is typically formed in direct contact with the semiconductor substrate. In the case of ohmic backside contacts, for example, for contacting the drain side of SiC MOSFETs, they can be realized using a NiSi metal and an LTA (laser thermal annealing) process.

[0005] In the current processes used to fabricate these contacts, the process window for laser energy during LTA is relatively small due to tool limitations and a weakness in the integration scheme. Several problems arise, such as NiSi bumps, the influence of surface roughness resulting from grinding, the generation of silicon dioxide particles within the metal layer or at the SiC / metal interface, or of carbon grains or a carbon layer on the metal, within the silicide layer, or at the SiC / metal interface. At least some of these problems cause mechanical instability of the backside metallization due to, for example, delamination or die cracks within the metal layer or the stack of layers above the SiC substrate.Therefore, this situation may cause a yield loss during the manufacturing process or at least reduce the reliability of the resulting semiconductor devices.

[0006] JP - H09 283 738 A, US 2004 / 0 029 377 A1, US 2019 / 0 164 822 A1, and US 6 028 003 A all describe semiconductor devices with nitride layers on a semiconductor substrate with an interface formed between them. Depending on the manufacturing process, different concentration distributions form in this interface.

[0007] Attempts have been made to reduce the formation of carbon clusters by appropriately selecting the material composition of the metal layer and the process conditions for thermal annealing. However, there is a need to provide alternative manufacturing processes for semiconductor devices that offer wider process windows for LTA and reduce or eliminate the formation of byproducts such as the formation of carbon clusters or graphite layers. Furthermore, there is a need to provide semiconductor devices with reliable contacts in a simple and cost-effective manner. SUMMARY

[0008] According to one embodiment, a semiconductor device comprises a semiconductor substrate and a metal nitride layer above the semiconductor substrate. The metal nitride layer forms at least one interface region with the semiconductor substrate, wherein the nitrogen content in the metal nitride layer has a maximum at or within a depth of a few atomic layers from the at least one interface region, and the maximum is obtained by a method described herein. Accordingly, semiconductor devices with good electrical performance can be obtained.

[0009] According to another embodiment, a method for producing a semiconductor device having a metal nitride layer above a semiconductor substrate is described. The method may comprise the steps of providing a semiconductor substrate, treating the surface of the semiconductor substrate by means of a grinding or thinning process, and depositing a metal nitride layer above the semiconductor substrate, thereby forming at least one interface region with the semiconductor substrate. The method further comprises a step of thermally annealing at least the metal nitride layer. The thermal annealing is performed such that nitrogen atoms or molecules from the metal nitride layer are enriched in the at least one interface region, thereby forming a maximum of a nitrogen content in the metal nitride layer at or within a depth of a few atomic layers from the at least one interface region."Maximum" in the context of this application means a local increase in the nitrogen content within the metal nitride layer that is greater than the average nitrogen content in the metal nitride layer. In some embodiments, the highest local nitrogen concentration within the metal nitride layer can be measured in this region; therefore, it is referred to as the "maximum."

[0010] Additional steps may be performed, or the sequence of steps may vary, if the general concept of providing a metal nitride layer above the semiconductor substrate with a maximum nitrogen content in the metal nitride layer at or near the interface region can be maintained. This method offers a wider process window for LTA compared to conventional manufacturing processes and produces semiconductor devices with good electrical performance.

[0011] Of course, the present disclosure is not limited to the above features and advantages. Indeed, one skilled in the art will recognize additional features and advantages upon reading the following detailed description and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The elements of the drawings are not necessarily to scale relative to one another; instead, emphasis is placed on illustrating the principles of the invention. Like reference numerals indicate correspondingly similar parts. The features of the various illustrated examples may be combined, except where mutually exclusive.

[0013] Examples are shown in the drawings and are described in detail in the description that follows.

[0014] Fig. 1 to 3 illustrate an embodiment of a method for producing a semiconductor device with a metal nitride layer, wherein: Fig. 1 illustrates a semiconductor substrate, Fig. Figure 2 illustrates a semiconductor substrate with a deposited metal nitride layer, and Fig. Figure 3 illustrates the semiconductor substrate with a metal nitride layer after thermal annealing. Fig. 4 illustrates an embodiment of a semiconductor device having a metal nitride layer and an exemplary profile of an N2 content after thermal annealing. DETAILED DESCRIPTION

[0015] In the following detailed description, semiconductor devices with metal nitride layers as ohmic contact layers and methods for manufacturing them in a simple and cost-effective manner are described. The semiconductor substrate may comprise or consist of at least one semiconductor wafer or one or more epitaxial layers. The epitaxial layers may comprise epitaxial structures, which may be provided, for example, within or on a surface region of the epitaxial layers or the wafer. For example, the substrate may comprise only epitaxial layers and may be without a wafer. For example, a wafer used for epitaxial growth may have been removed in previous process steps.In another example, a wafer may be at least partially present in the substrate, for example, on the backside of the semiconductor substrate, while one or more epitaxial layers are provided thereon on the frontside of the semiconductor substrate. Then, the semiconductor substrate to be provided with contacts may be the wafer on the backside thereof. For example, the semiconductor devices may be fabricated from semiconductor substrates, such as Si, SiC, GaN, or other III / V or II / VI semiconductor substrates, which are to be provided with metal contacts on the backside of the substrate. Although this document mostly refers to semiconductor devices and methods for contacting the backside semiconductor surface with metal nitride layers, it can typically be used to provide frontside and / or backside contacts in, for example, power MOSFETs, SiC-based diodes, or J-FETs.The terms "front" and "back" (also referred to as "rear") are used with reference to the orientation of the examples shown in the drawings section. Because components of embodiments can be positioned in several different orientations, the directional terminology is used for illustrative purposes only and should not be considered limiting in any way.

[0016] The metal nitride layers are provided as ohmic contact layers above the semiconductor substrates. In this document, the term "above" means that a layer is applied on the surface of a substrate or over one or more other structures or layers. Thus, the layer may be directly on the substrate or may extend directly onto another layer or element, or intervening layers or elements may also be present. In contrast, when a layer or element is referred to as being "directly on" or extending "directly onto" another layer or element, no intervening layers or elements are present.

[0017] The metal nitride layers are described here as layers, but they can be applied above the semiconductor substrate, for example, directly on the surface of the semiconductor substrate, as a continuous layer, or can be arranged as a structured layer. Structured layer in this context means that the metal nitride layer forms at least one interface region with the semiconductor substrate, i.e., is in direct contact with the semiconductor substrate surface in this at least one interface region. Accordingly, the structured metal nitride layer can form two or more interface regions in a structured manner, meaning that it has a specific shape or is applied at a specific distance, thereby forming a structure of metal contacts on, for example, the backside of a semiconductor substrate.

[0018] As previously described, the metal nitride layer is applied in such a way that it provides ohmic contacts between the surface of the semiconductor substrate and the metal nitride layer or optionally applied additional metal stacks above the metal nitride layer, thereby providing semiconductor devices with reliable contacts in a simple and cost-effective manner. Furthermore, the metal nitride layer is suitable for reducing the contact resistance to a value at least equivalent to or lower than that obtained with conventional nickel silicide layers.

[0019] One of the reasons for this rather low contact resistance of the metal nitride layer may be the specific nitrogen content distribution in the metal nitride layer, which is obtained by the manufacturing processes described below. It has been found that the nitrogen content in the metal nitride layer exhibits a maximum at or near the at least one interface region between the metal nitride layer and the surface of the semiconductor substrate. In some embodiments, the maximum is at the interface, while in other embodiments the maximum may be at a depth of a few atomic layers. This effect appears to be realistic due to the enrichment of nitrogen atoms or molecules at or near the interface with the semiconductor substrate.According to the concept described here, annealing the metal nitride layer apparently causes a diffusion of nitrogen atoms within the metal nitride layer, causing enrichment at or near the interface. Typically, injection of dopant atoms into the underlying semiconductor substrate has not been observed. Accordingly, the reliability of the low-contact-resistance ohmic contacts described here in the semiconductor devices is believed to be a direct result of the thermal annealing during the metallization procedure used, rather than an effect of nitrogen implantation within the semiconductor substrate. Therefore, the effect appears to be clearly distinct from implantation techniques commonly used for metallization.

[0020] According to some examples, the semiconductor substrate of the semiconductor device may comprise SiC-, GaN-, or Si-based substrates. The substrates may be silicon carbide, GaN, or Si workpieces to be processed. For example, the SiC-based semiconductor substrate may be a SiC-based wafer. Alternatively, the SiC-based semiconductor substrate may comprise a base wafer (a so-called "growth substrate" or a so-called "growth wafer") on which semiconductor layers are deposited, e.g., using an epitaxial process. At least one epitaxial layer may be adjacent to a front side of the semiconductor substrate. In optional process steps, a metal contact layer may be provided on the SiC-based semiconductor substrate. In this case, the SiC-based semiconductor substrate may be a processed wafer. Example processed wafers with a SiC-based substrate may include power MOSFETs or diodes or J-FETs.These SiC-based electronic components typically comprise an n-doped SiC substrate layer on the backside of the semiconductor substrate to be contacted with a metal contact layer. On the frontside of the semiconductor substrate, a p-doped semiconductor layer may be required at the interface between the semiconductor substrate and the metal contact layer for reliable ohmic contact. While an emphasis is placed on manufacturing methods for ohmic contacts in power MOSFETs or diode component parts, the embodiments and examples described herein are not intended to be limited to these specific electronic components. Instead, the methods can be used to manufacture ohmic contacts of any other electronic components based on a SiC-, GaN-, or Si-based substrate, for example, epitaxial layers contained in the SiC-, GaN-, or Si-based substrate.Furthermore, the term "substrate" may include processed wafers comprising some epitaxial layers in which the growth substrate has been at least partially removed before the backside contact can be created. Furthermore, the interface between the semiconductor substrate front and / or backside and the metal layer may be doped with other dopants. For example, n-doped layers on the frontside or p-doped layers on the backside may also be selected depending on the produced electronic device. Different doping concentrations may be used for each "n" or "p" doping type. Generally, these concentrations are identified, for example, as n- or p+. In this document, any doping type specified herein may have the same or different absolute concentration as the same type in another embodiment or example.

[0021] The semiconductor substrate and, if applicable, the epitaxial layers for these electronic devices are typically monocrystalline. Embodiments of monocrystalline semiconductor materials are mostly based on 4H-SiC or 6H-SiC substrates. Accordingly, as described above, the substrate may include device structures within the substrate. Before the contacts are provided by depositing metal nitride and optionally further metal layer stacks, further device structures may be produced within the base substrate. Furthermore, thickness reduction steps of the semiconductor substrate may be applied, if necessary, before the contacts are fabricated.

[0022] In some examples, the substrate may be a ground wafer or a substrate with a specially adapted surface roughness, since substrates with different roughness resulting from grinding processes of the substrate surface can improve the measured contact resistance values. A higher surface roughness, which can be created by grinding or thinning the substrate, can lead to more defects being present on the SiC surface. The higher number of defects caused by higher roughness can then be responsible for the lower contact resistance values ​​in the resulting ohmic contacts at the interface between the SiC substrate and the metal nitride layer. In particular, the higher number of defects can also lead to a higher number of docking sites for nitrogen on the SiC surface. The nitrogen can originate from the metal nitride film.This can ultimately reduce the resistance of an ohmic contact to SiC.

[0023] The higher number of defects, i.e. the higher surface roughness, can also be used to reduce the LTA energy required to form a good ohmic contact at the interface between the SiC substrate and the metal layer.

[0024] Accordingly, a higher roughness can reduce the LTA energy required to form a good ohmic contact in the subsequent annealing process. Therefore, adjusting the substrate surface roughness can provide a wider process window for the LTA process in production.

[0025] According to some examples, the semiconductor device may be based on a metal nitride layer comprising a metal component from one or more main group metals or transition metals. Exemplary main group metal nitrides may be selected from Si or Al nitrides. Suitable transition metal nitrides for the contact layers are based on any transition metal that forms stable nitrides and has ceramic properties. Exemplary transition metals may be selected from the group consisting of Ni (nickel), Ti (titanium), V (vanadium), Zr (zirconium), Nb (niobium), Mo (molybdenum), Hf (hafnium), Ta (tantalum), and W (tungsten). In particular, Ti, Si, Al, W, Ta, and Mo are preferably used as metal components for depositing a metal nitride layer above the semiconductor substrate. Silicon, as a Group 4 metalloid, falls under the definition of metal nitride in this application, even though the silicon nitrides are typically ceramics.Mixed metal nitrides are also suitable as nitrides with different stoichiometric proportions of metal and nitrogen. In embodiments, the metal nitride layer comprises Si3N4 or Al3N4. Titanium nitride (TiN) or titanium tungsten nitride (TiWN) are specific examples with R. on-values ​​and a body diode performance with low dependence on LTA energy during thermal laser annealing. They can be used to perform the previously described enrichment of nitrogen atoms within the interface region of the semiconductor substrate and the metal nitride layer, forming a maximum nitrogen content at or near the interface region. This enables a large process window for LTA, for example, if TiN or TiWN is used as the metal nitride for the ohmic contacts in semiconductor devices with a metal nitride contact layer. The contact resistance, measured using a transmission line method (TLM - transfer length method), reveals that the contact resistance with a TiN layer is approximately 14 to 15 mOhm*mm. 2 which is lower than current NiSi-based values ​​in common semiconductor devices (about 30 mOhm*mm 2 ) is.

[0026] According to some other embodiments of the semiconductor device, the metal nitride layer may be selected from other metal nitrides or dielectrics. Therefore, they may comprise dielectrics such as Si3N4 or Al3N4.

[0027] Some examples of semiconductor devices include a metal nitride layer, wherein the at least one nitrogen-enriched interface region is located near the interface between the metal nitride layer and the surface of the substrate. The interface region may extend into the metal nitride layer for no more than about 20 nm, in particular no more than about 15 nm, especially no more than about 10 nm, for example, between 5 and 15 nm.

[0028] According to at least some embodiments, the proportion of excess nitrogen in the TiN lattice within the metal nitride layer at the location of a nitrogen maximum is much higher than the proportion of excess nitrogen that can be achieved using a conventional implantation process. Excess nitrogen is the proportion of nitrogen that is diffused to the location of the maximum by the annealing process described herein. If the nitrogen content in the TiN layer is typically 50%, the nitrogen content at the location of the maximum is increased by 1% or more. In some examples, the total nitrogen content within the metal nitride layer in the region of the maximum content may be in the range of about 51 atomic % or more when measured for enrichment using TEM-EDX (elemental mapping), but may be much higher in other embodiments.In other words, using the methods described herein, the proportion of excess nitrogen can be enriched by a factor of at least 10, sometimes 100 or more, compared to conventional implantation methods. Accordingly, semiconductor devices as described herein exhibit improved contact resistance due to the high proportion of electron carriers near the interface.

[0029] According to at least some examples, the semiconductor device may comprise at least one interface region in contact with an additional doping region formed in the semiconductor substrate. Accordingly, the previously described novel concept of metal nitride ohmic contact layers with low contact resistance may be combined with dopant implantation. For example, on the wafer backside, i.e., the backside of the substrate, the deposition of scattering oxide or a photoresist for implantation is generally not easily possible due to glass support processes. Therefore, the metal layer may be deposited on the wafer first, and the implantation is performed through this metal layer. This enables the processing of the wafer, which will be described in more detail later with reference to the manufacturing processes. The dopants, e.g., nitrogen, that are introduced into the semiconductor substrate, e.g.,A SiC substrate, implanted at the same time as the nitrogen content in the metal nitride layer at or near the interface is enriched using thermal annealing, e.g., thermal laser annealing. Accordingly, the high nitrogen content within the metal nitride layer at or near the interface, together with the nitrogen or dopant atoms in the semiconductor substrate, are then responsible for improving, i.e., further reducing, the ohmic contact value through heavy doping at or near the interface. Accordingly, further improved ohmic contacts with low resistance values ​​can be achieved if an additional implantation region is provided within the semiconductor substrate. Furthermore, the additional implantations can improve stability during processing.Depending on the dopants, different properties can be achieved. These implantations can be provided at or near the interface between the metal nitride layer and the substrate. Suitable implantation depths (also known as the ion range peak) in the semiconductor substrate are about 50 nm or less, in particular 5 to 50 nm, especially about 5 to 30 nm, for example about 5 nm. In some embodiments, the implantation can also extend to some extent into the metal nitride layer, for example about 10 nm within the metal nitride layer. Preferably, the ion range peak is near the interface between the metal nitride layer and the semiconductor substrate, and its location can be suitably adjusted, for example, by the implantation energy used. The implantation energy depends, among other things, on the thickness of the metal layer.

[0030] Embodiments of the semiconductor devices may further comprise additional metallization structures above the metal nitride layer. These additional metallization structures may consist of the same or different metal components as the metals deposited in the metal nitride layer. Generally, one or more additional layers may be used to improve the contacts or provide better soldering properties to the metal contacts.

[0031] In some examples, the metal nitride layer and the additional metallization structures can be used to provide backside metallization of the semiconductor device. The resulting metal contacts have lower contact resistance values ​​and exhibit good electrical performance compared to conventional metal contacts.

[0032] The semiconductor devices described herein can be obtained by novel approaches for forming ohmic contacts on the wafer backside by using a non-critical material approach. According to one embodiment, the method for producing a semiconductor device comprises providing a semiconductor substrate, depositing a metal nitride layer above the semiconductor substrate, and thermally annealing at least the metal nitride layer. The thermal annealing can be performed such that nitrogen atoms or molecules from the metal nitride layer are enriched in the at least one interface region. The enrichment of nitrogen in the interface region results in the creation of a maximum of a nitrogen content in the metal nitride layer at or near the at least one interface region.It is assumed that during thermal annealing, a portion of the nitrogen from the metal nitride layer is driven into the interface and simultaneously activated. This may occur due to nitrogen binding to unsaturated bonds or damaged areas of SiC.

[0033] Thermal annealing is most likely performed using an LTA process. However, thermal annealing or thermal annealing through a light-absorbing layer and laser annealing can also be used.

[0034] In some examples, the annealing can be performed under a reactive atmosphere, such as NH3 or forming gas (N2 mixed with H2, e.g., approximately 5% H2 admixture), or a pure nitrogen atmosphere. The reactive atmosphere using nitrogen components promotes enhanced nitrogen enrichment near the interface. Other reactive nitrogen-based compounds can also be used.

[0035] As previously described, the metal nitride layer obtained by thermal annealing provides ohmic contacts between the surface of the semiconductor substrate and the metal nitride layer or the optionally applied additional metal stacks above the metal nitride layer, thereby providing semiconductor devices with reliable contacts in a simple and cost-effective manner. Furthermore, the metal nitride layer obtained in this way is suitable for reducing the contact resistance to a value equal to or lower than that obtained with conventional nickel silicide layers.

[0036] The specially adapted nitrogen content in the metal nitride layer, with a maximum at or near the at least one interface region between the metal nitride layer and the surface of the semiconductor substrate, appears to be responsible for the good contact resistances measured in semiconductor devices fabricated according to the methods described herein. In some examples, the maximum is at the interface, while in other embodiments the maximum may be at a depth of a few atomic layers. The effect appears to be realistic due to the enrichment of nitrogen atoms or molecules at or near the interface with the semiconductor substrate. According to the concept as described herein, thermal annealing of the metal nitride layer causes diffusion of nitrogen atoms within the metal nitride layer, thereby causing the enrichment at the interface.As explained previously, it is believed that due to the bonding of nitrogen to unsaturated bonds or damaged sites of SiC, an improvement in electrical performance can be achieved by reducing the electrical resistivity.

[0037] The method involves treating the surface of the semiconductor substrate with a grinding or thinning process prior to depositing the metal nitride layer. The roughness of the semiconductor substrate can be adjusted through these grinding or thinning processes. Accordingly, more defects can be present at the interface of the semiconductor substrate surface and, accordingly, at the interface between the semiconductor substrate and the metal nitride layer, which promotes the formation of a good ohmic contact. With a higher roughness, for example, the LTA energy can be reduced when the good ohmic contact is created in the annealing step. Therefore, the process can provide a wide process window for the LTA in the production of semiconductor devices with good ohmic contact.

[0038] Examples of thermal annealing processes include thermal laser annealing (LTA) with suitable energy densities depending on the prepared metal nitride systems. The R on - and body diode performance advantageously exhibits a low dependence on the LTA energy densities used. In addition, good R on -Values ​​a very wide process window for LTA if TiN is used as an ohmic contact in the previously described processes. Other annealing methods besides LTA can be used. Examples include thermal annealing through a light-absorbing layer and laser annealing.

[0039] It is believed that one reason for the good electrical performance of ohmic contacts with metal nitride layers above the semiconductor substrate is due to a reduced influence of byproducts typically generated during thermal annealing processes of silicide reactions. Silicide reactions typically generate carbon clusters or grains within the metal layer or at the interface of SiC / metal or silicon oxide particles, or NiSi bumps and other phenomena that reduce reliability are observed. The processes described here typically do not exhibit similar effects and are accordingly capable of producing reliable ohmic contacts using a wide process window during LTA processing.Surface roughness adjustment can also be used to specifically adjust the contact resistance and / or the LTA energy to be used during annealing. Therefore, the resulting semiconductor devices with ohmic metal nitride contacts are generally provided with mechanically stable backside metallizations that exhibit fewer delamination events and fewer cracks, even in high-temperature applications. Accordingly, they can be produced with high yields and good reliability. At the same time, the produced ohmic contacts exhibit good electrical performance.

[0040] In some examples, thermal annealing comprises heating the metal nitride layer and the surface regions of the semiconductor substrate at the at least one interface region. During thermal annealing, the nitrogen concentration at or near the interface with the semiconductor substrate increases up to a local maximum concentration within the metal nitride layer, also referred to herein as a "maximum," although higher nitrogen contents in the metal nitride layer may be possible. At the same time, dopants in the n-doped semiconductor substrate may be activated during thermal laser annealing, thereby increasing the dopant concentration near the interface with the metal nitride contact layer. At the same time, amorphous or non-crystalline regions may be annealed. Recrystallization processes improve the electrical performance of the metallization produced in these processes.

[0041] In some examples of the methods, the thermal annealing is performed such that the at least one interface region with enriched nitrogen content extends into the metal nitride layer for no more than about 20 nm, in particular no more than about 15 nm, for example, less than about 10 nm. It is advantageous for the maximum nitrogen content to be at or near the interface with the semiconductor substrate in order to increase electrical performance.

[0042] In some embodiments for the method, it may be preferable to additionally provide a doped region within the semiconductor substrate at or near the interface with the metal nitride layer provided thereabove. Therefore, some examples include an implantation step for implanting dopants through the metal nitride layer into the surface regions of the semiconductor substrate. For example, after thinning a wafer as the semiconductor substrate to a desired thickness by grinding or any other abrasive or non-abrasive process, a metal nitride layer may be deposited above the wafer, and dopants, such as nitrogen or phosphorus, may be implanted to increase the dopant concentration in the semiconductor substrate.During thermal annealing, for example, using LTA, the metal nitride layer forms a good ohmic contact by enriching a nitrogen content near the interface. At the same time, the dopants within the semiconductor substrate surface or near the interface are activated, thereby increasing the dopant concentration and electrical performance at the interface between the semiconductor substrate and the metal nitride contact layer. Exemplary depths of the implanted dopants are approximately 5 to 50 nm relative to the metal-substrate interface.

[0043] In further embodiments, the methods comprise depositing additional metallization structures above the metal nitride layer to complete a metal contact of semiconductor devices. Suitable additional metallization structures are described with reference to the semiconductor device. Accordingly, semiconductor devices with good electrical performance can be obtained.

[0044] The above-described embodiments will be further described by reference to the drawings, which show different steps of a method for producing a semiconductor device in Fig. 1 to 3 and an exemplary semiconductor device produced therewith, in Fig. Show 4.

[0045] Now with reference to Fig. 1, a semiconductor substrate 10, such as a silicon carbide substrate, is shown. Although this example is described with reference to a SiC substrate, any other suitable substrate may also be used. The silicon carbide substrate 10 in this example is an n-type doped 4H-SiC silicon carbide substrate, which may have been provided with epitaxial layers or structures on the front side thereof, which are not shown in the figures.

[0046] In this example, with reference to Fig. 2, the backside of the SiC substrate 10 is treated by chemical vapor deposition of a metal nitride layer 20 (e.g., a TiN layer deposition) above the SiC substrate surface. Other deposition methods, such as plasma vapor deposition (PVD) or atomic layer deposition (ALD), can also be used. At least in some parts of the semiconductor surface, the metal nitride layer 20 is in direct contact with the semiconductor substrate surface.

[0047] After the deposition of the metal nitride layer 20 above the SiC substrate 10, the stack of layers 10 and 20 is treated by thermal annealing, in this example by thermal laser annealing of at least the metal nitride layer 20 and surface portions of the SiC substrate 10.

[0048] After thermal annealing, for example by thermal laser annealing, the good ohmic contact performance obtained in the semiconductor device is believed to be achieved by changing the local electrical structure of the interface region 15, particularly in the region shown in Fig. 3. It has been observed through TEM micrographs and EDX mapping of thermally annealed structures that the nitrogen content in the interface region 15 exhibits a higher nitrogen content at or near the interface with the SiC substrate, or very close to the interface region 15, than in the metal nitride layer 20 above this interface region 15. Therefore, it is believed that thermal annealing causes an injection or enrichment of nitrogen atoms from the metal nitride layer into regions near the interface of the metal nitride layer and the SiC substrate. The mechanism is not yet clear, but it is believed that some of the metal nitride material in the metal nitride layer 20 is decomposed and rearrangements occur within the metal nitride lattice. The defects of the SiC surfaces may be advantageous locations where N from TiN can be bound during thermal annealing.This can be described as a quasi-epitaxial growth of metal nitride on the SiC at the interface between these two layers. The nitrogen atoms contained in the metal nitride layer can preferentially bind to defects in the SiC surfaces during thermal annealing. This increases the local doping of SiC.

[0049] In addition, a portion of the nitrogen atoms generated by the decomposition reactions diffuse to the SiC substrate surface, so that the nitrogen content is enriched near the interface region 15. Nitrogen clusters or nitrogen intercalations in the metal nitride lattice at the atomic level can occur in the interface region 15. The nitrogen atoms enriched in this interface region can act similarly to dopant atoms in the metal nitride layer. Due to outdiffusion, other parts of the metal nitride layer have lower nitrogen contents or higher metal concentrations than in the interface region 15.

[0050] The proportion of nitrogen in the interface region 15 obtained by this method is typically 10 times or more higher, preferably 100 times or more higher, than nitrogen proportions obtained by implantation methods known in the art. Furthermore, the examples showed that nitrogen injection into the SiC substrate layer was lower or could not be observed at all. Furthermore, in contrast to other thermal annealing processes of metal material layers deposited above SiC substrates, no metal silicide formation was observed in the experiments conducted. At least no measurable proportion of metal silicide was measured in the examples for the metal nitride contacts obtained using the method described here. Furthermore, the occurrence of carbon clusters, such as after silicide formation in silicide processes, was not observed, at least in some embodiments.Such clusters, if they were formed at all, may not have been detectable due to the low total carbon content in the metal nitride layer. In the case of TiN layers, titanium silicides or carbides are likely generated if some silicon or carbon from SiC is decomposed during thermal annealing.

[0051] Accordingly, this is like in Fig. The methods described in Figures 1 to 3 are suitable for manufacturing semiconductor devices with reliable ohmic contacts in a simple and cost-effective manner. At the same time, the method is suitable for eliminating or preventing the formation of byproducts, such as the formation of carbon clusters or graphite layers, in metallization layers for contacting SiC substrates or any other semiconductor substrate.

[0052] Now with reference to Fig. 4 shows an embodiment of a semiconductor device with a metal nitride layer as described in the Fig.1 to 3. The semiconductor substrate comprises a SiC substrate 10, a TiN layer 20, and interface regions 15 where the substrate and the metal nitride layers are in contact with each other. On the left side of the cross-section through this semiconductor device 100, the N2 content is shown. From this qualitative diagram, it can be concluded that the maximum N2 content lies within the interface regions 15, while the nitrogen content in the semiconductor substrate 10 and the metal nitride layer 20 is rather low. The diagram is merely a qualitative description of the concentration of nitrogen atoms within the cross-section of a semiconductor device 100, which can be obtained by one of the methods described here. In the case of additional nitrogen implantations, for example, further maxima or higher concentrations are also possible in the semiconductor substrate.Therefore, this graph is intended to explain the definition of maximum, rather than limiting this feature to this specific example as shown here.

[0053] As used herein, the terms "having," "containing," "including," "comprising," and the like are open-ended terms that indicate the presence of stated elements or features but do not exclude additional elements or features. The articles "a," "an," and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

[0054] It is understood that the features of the various embodiments described herein may be combined with one another unless specifically stated otherwise. Although specific embodiments have been illustrated and described herein, it will be understood by one of ordinary skill in the art that a variety of alternative and / or equivalent implementations may be substituted for the specific embodiments and examples shown and described without departing from the scope of the present disclosure. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this disclosure be limited only by the claims and the equivalents thereof.

Claims

[1] A semiconductor device (100) comprising a semiconductor substrate (10) and a metal nitride layer (20) above the semiconductor substrate (10), wherein the metal nitride layer (20) forms at least one interface region (15) with the semiconductor substrate (10), wherein the nitrogen content in the metal nitride layer (20) has a maximum at or at a depth of a few atomic layers from the at least one interface region (15), and the maximum is obtained by a method according to any one of claims 9 to 14. [2] The semiconductor device (100) of claim 1, wherein the semiconductor substrate comprises silicon carbide or GaN or silicon. [3] The semiconductor device (100) according to any one of claims 1 or 2, wherein the metal nitride layer (20) comprises a metal component of one or more main group metals or transition metals selected from the group consisting of Ti, Si, Al, W, Ta and Mo. [4] The semiconductor device (100) according to any one of claims 1 or 2, wherein the metal nitride layer (20) comprises Al3N4 or the ceramic Si3N4. [5] Semiconductor device (100) according to one of the preceding claims, wherein the at least one nitrogen enriched interface region (15) extends into the metal nitride layer (20) for not more than 20 nm. [6] Semiconductor device (100) according to one of the preceding claims, wherein the at least one interface region (15) is in contact with an additional doping region formed in the semiconductor substrate (10). [7] A semiconductor device (100) according to any one of the preceding claims, further comprising additional metallization structures above the metal nitride layer (20). [8] The semiconductor device (100) of claim 7, wherein the metal nitride layer (20) and the additional metallization structures provide a backside metallization of the semiconductor device (100). [9] A method of producing a semiconductor device (100), comprising: - providing a semiconductor substrate (10), - treating the surface of the semiconductor substrate (10) by means of a grinding or thinning process, - depositing a metal nitride layer (20) above the semiconductor substrate (10), thereby forming at least one interface region (15) with the semiconductor substrate (10), and - thermally annealing at least the metal nitride layer (20), wherein the thermal annealing is carried out in such a way that nitrogen atoms or molecules from the metal nitride layer (20) are enriched in the at least one interface region (15), whereby a maximum of a nitrogen content in the metal nitride layer (20) is produced at or at a depth of a few atomic layers from the at least one interface region (15). [10] The method of claim 9, wherein the thermal annealing comprises a thermal laser annealing process. [11] The method of any one of claims 9 to 10, wherein the thermal annealing comprises heating the metal nitride layer (20) and the surface regions of the semiconductor substrate (10) at the at least one interface region (15). [12] Method according to one of claims 9 to 11, wherein the at least one interface region (15) with enriched nitrogen content extends into the metal nitride layer (20) for not more than 20 nm. [13] The method of any one of claims 9 to 12, further comprising an implantation step of implanting dopants through the metal nitride layer (20) into the surface regions of the semiconductor substrate (10), wherein the depth of implanted dopants is 5 to 50 nm close to the metal-substrate interface. [14] The method of any one of claims 9 to 13, further comprising depositing additional metallization structures above the metal nitride layer (20).

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