Organic light-emitting display device and thin-film transistor array substrate

Abstract

Organic light-emitting display device comprising the following: a substrate (101) having a display area (AA) and a non-display area (NA); and at least one thin-film transistor (DT, ST) having a semiconductor pattern (311, 312) having a source region (311S, 312S) and a drain region (311D, 312D), wherein the source region (311S, 312S) and the drain region (311D, 312D) each have conductive regions (311b, 311c, 311e, 311f; 312b, 312c, 312e, 312f) and non-conductive regions (311a, 311d; 312a, 312d) arranged alternately on the substrate (101), wherein the at least one thin-film transistor (DT, ST) comprises: a gate electrode (314, 315) facing the semiconductor pattern (311, 312); and a source electrode (319S, 318S) and a drain electrode (319D, 318D) that are electrically connected to the source region (311S, 312S) and the drain region (311D, 312D), respectively, wherein the conductive regions (311b, 311c, 311e, 311f; 312b, 312c, 312e, 312f) comprise a first conductive region (311b, 311e; 312b, 312e) that contacts the source electrode (319S, 318S) or the drain electrode (319D, 318D), and a second conductive region (311c, 311f; 312c, 312f) that is arranged between the source electrode (319S, 318S) or the drain electrode (319D, 318D) and the gate electrode (314, 315), wherein the first conductive region (311b, 311e; 312b, 312e) is made conductive by being connected to ions were brought into contact, and wherein the second conductive area (311c, 311f; 312c, 312f) is made conductive by injecting ions into it.

Description

Field of invention

[0001] The present disclosure relates to an organic light-emitting display device and in particular to an organic light-emitting display device comprising hybrid thin-film transistors in which different types of semiconductor materials are used to form several thin-film transistors forming a pixel circuit section of a subpixel and several thin-film transistors forming a GIP circuit section, and which can reduce, for example minimize, the size of the thin-film transistors in order to realize a high-resolution display device. Discussion of the state of the art

[0002] Unlike a liquid crystal display device, which uses a backlight, an organic light-emitting display device, which uses a self-illuminating light-emitting element, features a thin profile and high image quality. Therefore, organic light-emitting displays are the focus of considerable attention in the field of displays.

[0003] Since it is particularly possible to form a light-emitting element on a flexible substrate, an organic light-emitting display device enables the creation of screens in various shapes, such as flexible and foldable screens. Furthermore, due to its thinness, an organic light-emitting display device is suitable for small electronic products such as smartwatches.

[0004] To be applied to a display device that frequently displays a still image, such as a smartwatch, a light-emitting display device is required that has a new type of pixel circuit section which can prevent the generation of a leakage current when displaying a still image.

[0005] A thin-film transistor has been proposed that uses an oxide semiconductor as the active layer to achieve improved leakage current blocking.

[0006] US 2021 / 0028314 A1 describes a TFT with an oxide semiconductor layer comprising a conductive region for source and drain electrodes, a channel region overlapping with a gate electrode, and a resistive region between the channel region and an adjacent conductive region.

[0007] US 2019 / 0164999 A1 describes an OLED device comprising an active transistor layer, a gate insulating layer, a gate electrode, and a connection pattern that is connected to the conductive layer and the active layer via contact holes.

[0008] US 2015 / 0187959 A1 describes an array substrate with a thin-film transistor in which gate and data lines define a pixel area, a light shield pattern is connected to a guide line, and an oxide semiconductor layer is placed on a buffer and inter-insulation layer. Summary of the invention

[0009] In a display device using hybrid thin-film transistors, different types of semiconductor layers are employed, such as a polycrystalline semiconductor layer and an oxide semiconductor layer. Therefore, the processes for forming the polycrystalline semiconductor layer and the oxide semiconductor layer are performed separately, complicating the manufacturing process. Furthermore, the polycrystalline semiconductor layer and the oxide semiconductor layer exhibit different properties with respect to chemical gases, further complicating the manufacturing process.

[0010] In particular, a polycrystalline semiconductor layer, compared to an oxide semiconductor layer, is characterized by the fact that charge carriers such as electrons or holes move at high speeds, and is therefore suitable for a driver thin-film transistor capable of high-speed operation. Accordingly, a polycrystalline semiconductor layer is typically used to form a driver thin-film transistor.

[0011] A driver thin-film transistor using a polycrystalline semiconductor layer, while operating at a relatively high speed, is disadvantageous for reproducing low grayscale values ​​due to a high current fluctuation rate resulting from current loads. Therefore, one objective of the present disclosure is to provide a driver thin-film transistor using an oxide semiconductor and to create a pixel circuit section in which the current fluctuation rate due to current loads is low and the s-factor is large. Furthermore, in line with the recent trend towards high-resolution display devices, another objective of the present disclosure is to provide a structure that can reduce (e.g., minimize) the size of multiple thin-film transistors arranged in a subpixel.

[0012] One or more of these problems are solved by the features of the independent claims. According to the invention, an organic light-emitting display device comprises a substrate having a display area and a non-display area, and at least one thin-film transistor having a semiconductor pattern comprising a source area and a drain area. Both the source area and the drain area comprise conductive and non-conductive areas arranged alternately on the substrate.

[0013] The semiconductor pattern can be an oxide semiconductor pattern.

[0014] According to the invention, the at least one thin-film transistor has a gate electrode that faces or overlaps the semiconductor pattern, and a source electrode and a drain electrode that are electrically connected to the source region and the drain region, respectively. The conductive regions comprise a first conductive region that contacts the source electrode or the drain electrode, and a second conductive region that is arranged between the source electrode or the drain electrode and the gate electrode.

[0015] According to the invention, the first conductive region is made conductive by bringing it into contact with ions, and the second conductive region is made conductive by injecting ions into it. The first conductive region can be made conductive by bringing the second source region and the second drain region into contact with foreign ions.

[0016] The gate electrode can be located in a layer above the source and drain electrodes. The source and drain electrodes can also be located on the same layer.

[0017] The gate electrode can be located on the same layer as the source and drain electrodes. The source and drain electrodes can also be located on the same layer.

[0018] The at least one thin-film transistor can comprise a driver thin-film transistor and / or at least one switching thin-film transistor.

[0019] The driver thin-film transistor can have a first light-blocking pattern located beneath the semiconductor pattern and connected to the source electrode. Alternatively, the driver thin-film transistor can have a first semiconductor pattern, a first gate electrode overlapping the first semiconductor pattern, and a first source electrode and a first drain electrode connected to the first semiconductor pattern.

[0020] The switching thin-film transistor can have a second semiconductor pattern, a second gate electrode overlapping with the second semiconductor pattern, and a second source electrode and a second drain electrode connected to the second semiconductor pattern. The first source electrode, the first drain electrode, the second source electrode, and the second drain electrode can be located on the same layer.

[0021] The first gate electrode and the second gate electrode can be located on the same layer. Alternatively, the first gate electrode and the second gate electrode can be located on a layer above the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode.

[0022] The first gate electrode and the second gate electrode can be located on the same layer as the first source electrode, the first drain electrode, the second source electrode and the second drain electrode.

[0023] The first and second gate electrodes can be located on different layers. The vertical distance between the first gate electrode and the first semiconductor pattern can be greater than the vertical distance between the second gate electrode and the second semiconductor pattern. A vertical direction can be understood as a direction perpendicular to the substrate and / or the display area. That is, the first gate electrode and the first semiconductor pattern can be further apart in a direction perpendicular to the display area than the second gate electrode and the second semiconductor pattern.

[0024] The switching thin-film transistor can have a second light-blocking pattern. The vertical distance between the second semiconductor pattern and the second light-blocking pattern can be greater than the vertical distance between the first semiconductor pattern and the first light-blocking pattern. That is, the second semiconductor pattern and the second light-blocking pattern can be further apart in a direction perpendicular to the display area than the first semiconductor pattern and the first light-blocking pattern. The second light-blocking pattern can be electrically connected to the second gate electrode.

[0025] The driver thin-film transistor can be located in the display area, and the switching thin-film transistor can be located in the display area and / or the non-display area.

[0026] A thin-film transistor array substrate according to the invention comprises at least one thin-film transistor with a semiconductor pattern comprising a source region, a drain region, and a channel region arranged between the source region and the drain region. Both the source region and the drain region comprise at least two conductive regions and a non-conductive region arranged between the at least two conductive regions.

[0027] The conductive areas and the non-conductive area can be arranged alternately in the source area and the drain area, respectively.

[0028] According to the invention, the conductive areas comprise a first conductive area spaced apart from the channel area and a second conductive area arranged adjacent to the channel area, wherein the first conductive area is made conductive by being brought into contact with ions, and wherein the second conductive area is made conductive by injecting ions into it.

[0029] The thin-film transistor array substrate according to the present disclosure may further comprise a source electrode and a drain electrode, each connected to the source region and the drain region, and a light-blocking pattern arranged below the semiconductor pattern and connected to the source electrode.

[0030] The semiconductor pattern can be an oxide semiconductor pattern.

[0031] The at least one thin-film transistor can be a driver thin-film transistor and / or a switching thin-film transistor. Brief description of the drawings

[0032] The accompanying drawings, which are included to provide a better understanding of the disclosure and which are incorporated into and form part of this application, illustrate embodiments of the disclosure and, together with the description, serve to explain the principle of the disclosure; they show: Fig. 1 a schematic view of a display device according to an embodiment of the present disclosure; Fig. 2 a circuit diagram showing a pixel circuit for controlling a pixel in the display device according to the embodiment of the present disclosure; Fig. 3 A cross-sectional view of a thin-film transistor arranged in a non-display area, and of a pixel circuit section and a section for light-emitting elements arranged in a pixel area, along a line II' in Fig. 1 according to the embodiment of the present disclosure; Fig. 4 a cross-sectional view showing a drive thin-film transistor and a switching thin-film transistor in the pixel area of Fig. 3 shows in detail; Fig. 5A and Fig. 5B a cross-sectional view or a top view showing part of one of the Fig. The 4 thin-film transistors shown are shown; Fig. 6 a cross-sectional view of a driver thin-film transistor and a switching thin-film transistor in a pixel area according to a further embodiment of the present disclosure; Fig. 7 a cross-sectional view of a control thin-film transistor and a switching thin-film transistor in a pixel area according to yet another embodiment of the present disclosure; Fig. 8A a cross-sectional view showing the relationship between parasitic capacitances present in the Fig. The 7 shown drive thin-film transistor is generated; Fig. 8B a circuit diagram of Fig. 8A; and Fig. 9A and Fig. 9B Cross-sectional views to illustrate main sections in a manufacturing process according to an embodiment of the present disclosure. Detailed description of the revelation

[0033] The advantages and features of the present disclosure and the methods for achieving them will become clear from the embodiments described in detail below with reference to the accompanying drawings. However, the present disclosure can be implemented in many different forms and should not be interpreted as being limited to the embodiments set forth herein. Rather, these embodiments are provided to ensure that this disclosure is thorough and complete and to fully convey its scope to those skilled in the art.

[0034] In the drawings illustrating the exemplary embodiments of the present disclosure, the shapes, sizes, ratios, angles, and numbers shown are given as examples and are therefore not limited to the disclosure of the present invention. Throughout this entire description, the same reference numerals denote the same components. Furthermore, in the following description of the present disclosure, a detailed description of known functions and configurations included herein is omitted if this could obscure the subject matter of the present disclosure.

[0035] The terms "include," "consist of," and / or "have" used in this description do not preclude the presence or addition of other elements, unless used in conjunction with the term "only." Singular forms are intended to include plural forms unless the context clearly indicates otherwise.

[0036] When interpreting components included in the various embodiments of the present disclosure, the components are interpreted as containing a defect area, even if there is no explicit description of it.

[0037] When describing the various embodiments of the present disclosure, if a positional relationship between two parts is described using terms such as "on", "above", "below", "next to", or the like, one or more other parts may be located between the two parts unless the term "directly" or "closely" is used.

[0038] Spatially relative terms such as "under," "below," "above," "lower," and "upper" can be used here to describe the relationship of one element or component to another, as illustrated in the figures. It is understood that, in addition to the orientation shown in the figures, these spatially relative terms are intended to encompass different orientations of the device in use or operation. For example, if the device in the figures is inverted, elements described as "under" or "below" other elements would then be oriented "above" the other elements. The exemplary term "below" or "below" can therefore encompass both an orientation from above and from below. Likewise, the exemplary term "above" or "upper" can encompass both an orientation from above and from below.

[0039] When describing the various embodiments of the present disclosure, if, for example, the temporal relationship between two actions is described using terms such as "after", "subsequent", "next", "before" or the like, the actions may not occur sequentially unless the term "immediately" or "directly" is used.

[0040] It is understood that, although the terms "first", "second", etc. may be used here to describe different elements, these elements are not intended to be limited by these terms. These terms are used merely to distinguish one element from another. Therefore, in the present description, an element designated as "first" may be the same as an element designated as "second" without exceeding the technical scope of this disclosure, unless otherwise specified.

[0041] The term "at least one" is to be understood as encompassing all possible combinations that can be proposed from one or more relevant elements. For example, the meaning of "at least one from a first element, a second element, or a third element" can be one from the first element, the second element, or the third element, respectively, and can also include all possible combinations that can be proposed from two or more elements of the first element, the second element, and the third element.

[0042] The respective features of the various embodiments of the present disclosure can be partially or completely coupled and combined, and various technical combinations and operating modes thereof are possible. These different embodiments can be carried out independently of one another or in conjunction with one another.

[0043] It should be noted that when assigning reference numerals to the elements of the drawings, identical or similar elements are designated with the same reference numerals even if they are shown in different drawings.

[0044] In the embodiments described in this disclosure, a source electrode and a drain electrode are distinguished for the sake of simplicity. However, the source electrode and the drain electrode are interchangeable. The source electrode can be the drain electrode, and the drain electrode can be the source electrode. Furthermore, the source electrode in one embodiment can be the drain electrode in another embodiment, and the drain electrode in one embodiment can be the source electrode in yet another embodiment.

[0045] In one or more embodiments of the present disclosure, for the sake of simplicity, a source region is distinguished from a source electrode, and a drain region is distinguished from a drain electrode. However, embodiments of the present disclosure are not limited to this. For example, a source region may be a source electrode, and a drain region may be a drain electrode. Furthermore, a source region may be a drain electrode, and a drain region may be a source electrode.

[0046] The respective features of the various embodiments of the present disclosure can be partially or completely coupled and combined with one another and can be interlocked and operated in various technical ways, as is fully understandable to average persons skilled in the art, and the embodiments can be carried out independently of one another or in combination with one another.

[0047] In the following, various embodiments of the present disclosure are described in detail with reference to the accompanying drawings.

[0048] Fig. Figure 1 is a top view of a display device 100 according to an embodiment of the present disclosure.

[0049] A display panel 102 comprises a display area AA and a non-display area NA adjacent to display area AA, which are arranged in a substrate 101. For example, the substrate 101 can be made of a flexible plastic material so that it is bendable. For example, the substrate 101 is made of polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polycarbonate (PC), polyethersulfone (PES), polyacrylate (PAR), polysulfone (PSF), or cycloolefin copolymer (COC). However, glass is not excluded as a substrate material.

[0050] A subpixel in the display area AA features a thin-film transistor that uses an oxide semiconductor material as the active layer.

[0051] At least one of a data control unit 104 and one of a gate control unit 103 can be arranged in the non-display area NA. Furthermore, the non-display area NA can also have a bending area BA in which the substrate 101 can be bent.

[0052] The gate driver unit 103 can be formed directly on the substrate 101 using a thin-film transistor that employs a polycrystalline semiconductor material as the active layer. Alternatively, the gate driver unit 103 can comprise a thin-film transistor that employs a polycrystalline semiconductor material as the active layer and a thin-film transistor that employs an oxide semiconductor material as the active layer.

[0053] The thin-film transistor with an oxide semiconductor layer and the thin-film transistor with a polycrystalline semiconductor layer have a high electron mobility in a channel and are therefore able to exhibit high resolution and be driven with low power.

[0054] The AA display area can contain multiple data lines and multiple gate lines. For example, the multiple data lines can be arranged in rows or columns, and the multiple gate lines can be arranged in columns or rows. Additionally, subpixels PX can be arranged in areas defined by the data lines and the gate lines.

[0055] The gate control unit 103, which includes a gate drive circuit, can be located in the non-display area NA. The gate drive circuit of the gate control unit 103 sequentially supplies a sampling signal to the multiple gate lines GL, thereby sequentially addressing the respective pixel rows in the display area. Here, the gate drive circuit can also be referred to as a sampling drive circuit. Furthermore, a pixel row refers to a row formed by pixels connected to a gate line.

[0056] The gate drive circuit can consist of a thin-film transistor with a polycrystalline semiconductor layer, a thin-film transistor with an oxide semiconductor layer, or both a thin-film transistor with a polycrystalline semiconductor layer and a thin-film transistor with an oxide semiconductor layer. If the same semiconductor material is used in the thin-film transistors located in the non-display region NA and the display region AA, the thin-film transistors can be manufactured simultaneously using the same process.

[0057] The gate control circuit can include a shift register and a level converter.

[0058] In the display device according to the embodiment of the present disclosure, the gate control circuit can be implemented as a gate-in-board (GIP) type and can be arranged directly on the substrate 101.

[0059] The gate control unit 103, which includes the gate control circuit, sequentially supplies a sampling signal with an on voltage or an off voltage to the multiple gate lines.

[0060] The display device 100 according to the embodiment of the present disclosure may further comprise a data drive circuit. When a specific gate line is opened by the gate drive unit 103, which includes the gate drive circuit, the data drive circuit converts image data into an analog data voltage (for example, data voltage Vdata, as described in Fig. 2 is shown) and supplies the analog data voltage to the multiple data lines.

[0061] The multiple gate lines GL arranged on substrate 101 can have multiple scanning lines and multiple emission control lines. These multiple scanning lines and emission control lines are wires that transmit different types of gate signals (scanning signals and emission control signals) to gate nodes of different types of transistors (scanning transistors and emission control transistors).

[0062] The gate control unit 103, which includes the gate control circuit, can be a sampling control circuit that receives sampling signals (for example, sampling signals Scan1 [n], Scan2 [n], Scan3 [n] and Scan3 [n+1], as described in Fig. 2 are shown) outputs to several sampling lines, which are gate lines GL of one type, and an emission control circuit that outputs emission control signals (for example, an emission control signal EM, as shown in Fig. 2 is shown) outputs to several emission control lines, which are gate lines GL of a different type.

[0063] The data lines DL can be arranged so that they run through the bending area BA. Different data lines DL can be arranged so that they connect to a data contact point PAD (in Fig. (1 not shown) are connected.

[0064] The bending area BA can be an area in which the substrate 101 can be bent. The substrate 101 can be held in a flat state in any area other than the bending area BA.

[0065] Fig. Figure 2 is a pixel circuit diagram of a subpixel according to an embodiment of the present disclosure. An exemplary pixel circuit diagram is given in which seven thin-film transistors T2, T3, T4, T5, T6, T7, and D-TFT and a single storage capacitor Cst are provided. One of the seven thin-film transistors (e.g., D-TFT) can be a driver thin-film transistor, and the remaining ones can be switching thin-film transistors for internal compensation. As shown in Figure 2, the D-TFT is a driver thin-film transistor. Fig. As shown in Figure 2, an anode of a light-emitting element OLED is electrically connected to the thin-film transistor T6, and a cathode of the light-emitting element OLED is connected to a low-power supply voltage V. SSELelectrically connected. One electrode of the storage capacitor Cst is electrically connected to a gate electrode of the thin-film transistor D-TFT, and the other electrode of the storage capacitor Cst is connected to a high-power supply voltage V. DDEL electrically connected. Here, Vin is a voltage for resetting the thin-film transistor D-TFT and VAR is a voltage for resetting the anode of the light-emitting element OLED.

[0066] The following description of the embodiment of the present disclosure is given under the assumption that a driver thin-film transistor D-TFT uses an oxide semiconductor pattern as its active layer and that a T3 thin-film transistor, arranged adjacent to the driver thin-film transistor D-TFT, uses an oxide semiconductor pattern as its active layer. Furthermore, at least one of the remaining switching thin-film transistors may use a polycrystalline semiconductor pattern as its active layer for internal compensation. However, the present disclosure is not limited to the one in Fig. The example shown in Figure 2 is limited and is also applicable to internal compensation circuits that have any number of different configurations. For example, all thin-film transistors contained in the subpixel's pixel circuitry can be designed to use an oxide semiconductor as the active layer. Furthermore, the thin-film transistor forming the gate drive circuit section can also be configured to use an oxide semiconductor as the active layer.

[0067] In the following, an organic light-emitting display device according to a first embodiment of the present disclosure is described with reference to Fig. 3 to 5B described.

[0068] Fig. Figure 3 is a cross-sectional view of a configuration comprising a first gate-driver thin-film transistor GT located in the non-display area NA, specifically in the gate-driver unit, and using a polycrystalline semiconductor pattern as the active layer, and further comprising a single drive thin-film transistor DT, a single switching thin-film transistor ST, and a single storage capacitor Cst located in the subpixel PX. Fig. 4 is a cross-sectional view showing the Fig. Figure 3 shows the control thin-film transistor DT and switching thin-film transistor ST in more detail. Fig. 5A is a cross-sectional view of the in Fig. 4 thin-film switching transistors ST shown and Fig. 5B is a top view of components of the in Fig. 4 shown switching thin-film transistor ST.

[0069] In short, a subpixel PX comprises a pixel circuit section 370, which is arranged on the substrate 101, and a section for light-emitting elements 380, which is electrically connected to the pixel circuit section 370. The pixel circuit section 370 and the section for light-emitting elements 380 are electrically isolated by planarization layers PLN1 and PLN2.

[0070] Here, pixel circuit section 370 refers to an assembly section comprising a drive thin-film transistor DT, a switching thin-film transistor ST, and a storage capacitor Cst for driving a subpixel PX. Furthermore, section 380 for light-emitting elements refers to an assembly section comprising an anode 323, a cathode 327, and a light-emitting layer 325, which is arranged between the anode 323 and the cathode 327 to emit light.

[0071] Although the pixel circuit section 370 is exemplary in Fig. Figure 3 shows a single drive thin-film transistor DT, a single switching thin-film transistor ST and a single storage capacitor Cst, but the present disclosure is not limited to this.

[0072] In particular, in one embodiment of the present disclosure, each of the following uses a control thin-film transistor DT and at least one switching thin-film transistor ST: an oxide semiconductor pattern as the active layer.

[0073] A thin-film transistor using an oxide semiconductor material as the active layer exhibits improved leakage current blocking and relatively low manufacturing costs compared to a thin-film transistor using a polycrystalline semiconductor material as the active layer. Therefore, to reduce energy consumption and manufacturing costs, an oxide semiconductor material is used in one embodiment of the present disclosure to produce not only a drive thin-film transistor but also at least one switching thin-film transistor.

[0074] An oxide semiconductor can consist of an oxide of a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti), or a combination of a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti) and an oxide thereof. In particular, an oxide semiconductor can contain zinc oxide (ZnO), zinc-tin oxide (ZTO), zinc-indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), or indium zinc-tin oxide (IZTO).

[0075] In the pixel circuit section that forms a subpixel, an oxide semiconductor material can be used to form all thin-film transistors, or to form at least one switching thin-film transistor.

[0076] It is difficult to ensure the reliability of a thin-film transistor using an oxide semiconductor material, whereas a thin-film transistor using a polycrystalline semiconductor material exhibits high operating speed and improved reliability. Therefore, the in Fig. 3 is described under the assumption that an oxide semiconductor material is used to fabricate one of the switching thin-film transistors and the drive thin-film transistor DT, and a polycrystalline semiconductor material is used to fabricate the thin-film transistors that form the gate drive unit. However, the present disclosure is not limited to the one in Fig. The embodiment shown in Figure 1 is limited. That is, all thin-film transistors forming the subpixel can be designed to use an oxide semiconductor as the active layer, and all thin-film transistors forming the gate driver can be designed to use an oxide semiconductor as the active layer. Alternatively, thin-film transistors using an oxide semiconductor as the active layer and thin-film transistors using a polycrystalline semiconductor as the active layer can be combined to form the gate driver.

[0077] One embodiment of the present disclosure aims to reduce (for example, minimize) the size of the thin-film transistors that are the main components of the subpixel, in accordance with the recent trend towards high-resolution display devices where the number of subpixels arranged in each unit area is relatively large. To reduce (for example, minimize) the size of the thin-film transistor, the most important aspect is to reduce the size of a semiconductor pattern, including a channel area.

[0078] Reducing the size of the semiconductor pattern means reducing the size of conductive areas, which can be a channel area, a source area, and a drain area that make up the semiconductor pattern.

[0079] However, if the size of a channel region of a semiconductor pattern, particularly an oxide semiconductor pattern, is reduced, the threshold voltage Vth becomes negative, undesirably limiting the operation of a thin-film transistor. Furthermore, if the size of a channel region of the driving thin-film transistor DT, which uses an oxide semiconductor pattern as its active layer, is reduced, the s-factor value decreases, thus reducing the drive voltage range of the driving thin-film transistor DT.

[0080] Therefore, the present disclosure proposes a thin-film transistor that uses an oxide semiconductor pattern as the active layer and can achieve high resolution while preventing the conversion of the Vth value to a negative value and increasing the s-factor value.

[0081] A substrate 101 can be structured as a multilayer substrate in which an organic film and an inorganic film are stacked alternately. For example, the substrate 101 can be formed by alternating stacking of an organic film such as polyimide and an inorganic film such as silicon dioxide (SiO2).

[0082] A lower buffer layer 301 is formed on the substrate 101. The lower buffer layer 301 serves to block the ingress of moisture or similar substances from the outside. The lower buffer layer 301 can be formed by stacking silicon dioxide films (SiO2 films) in several layers.

[0083] A second buffer layer (not shown) can also be formed on the lower buffer layer 301 to more securely protect thin-film transistors arranged in the pixel circuit section 370 from moisture.

[0084] A first thin-film transistor GT is formed on substrate 101 in the non-display region NA. The first thin-film transistor can use a polycrystalline semiconductor pattern as the active layer. The first thin-film transistor GT comprises a first polycrystalline semiconductor pattern 303, which has a channel through which electrons or holes move, a first gate electrode 306, a first source electrode 317S, and a first drain electrode 317D.

[0085] The first polycrystalline semiconductor pattern 303 is formed from a polycrystalline semiconductor material. The first polycrystalline semiconductor pattern 303 comprises a first channel region 303C, which is arranged in its center, and furthermore a first source region 303S and a first drain region 303D, which are arranged with the first channel region 303C between them.

[0086] The first source region 303s and the first drain region 303d are conductive regions obtained by doping an intrinsic polycrystalline semiconductor pattern with a predetermined concentration of foreign ions of group V or group III such as phosphorus (P) or boron (B).

[0087] The first channel region 303c maintains the intrinsic state of the polycrystalline semiconductor material and creates a route along which electrons or holes can move.

[0088] The first thin-film transistor GT comprises a first gate electrode 306, which overlaps with the first channel region 303C of the first polycrystalline semiconductor pattern 303. A first gate insulating layer 302 is arranged between the first gate electrode 306 and the first polycrystalline semiconductor pattern 303.

[0089] According to one embodiment of the present disclosure, the first thin-film transistor GT is of a top-gate type in which the first gate electrode 306 is arranged above the first polycrystalline semiconductor structure 303. Accordingly, a first storage capacitor electrode 305 and a second light-blocking pattern 304, formed from a first gate electrode material, can be formed by a single masking process, thereby reducing the number of masking processes.

[0090] The first gate electrode 306 consists of a metallic material. For example, the first gate electrode 306 can take the form of a single layer or multiple layers of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or an alloy thereof. However, the present disclosure is not limited to this.

[0091] A first interlayer insulating layer 307 is deposited on the first gate electrode 306. The first interlayer insulating layer 307 can be made of silicon nitride (SiNx). In particular, the first interlayer insulating layer 307 made of silicon nitride (SiNx) can contain hydrogen particles. If, after forming the first channel region 303C and depositing the first interlayer insulating layer 307 on it, a heat treatment process is carried out, the hydrogen particles contained in the first interlayer insulating layer 307 penetrate the first source region 303S and the first drain region 303D, thereby making the polycrystalline semiconductor material conductive. This can be referred to as a hydrogenation process, which is a process in which source and drain regions are made conductive by a contact method.

[0092] The first thin-film transistor GT can further comprise an upper buffer layer 310 and a second gate insulating layer 313, which are formed sequentially on the first intermediate insulating layer 307. The first source electrode 317S and the first drain electrode 317D can be formed on the second gate insulating layer 313 and are each connected to the first source region 303s and the first drain region 303d, respectively.

[0093] The upper buffer layer 310 insulates the first polycrystalline semiconductor pattern 303 from a first oxide semiconductor pattern 311 of the drive thin-film transistor DT, which is formed from an oxide semiconductor material, and a second oxide semiconductor pattern 312 of the first switching thin-film transistor ST, which is formed from an oxide semiconductor material. Furthermore, the upper buffer layer 310 provides a base on which the first oxide semiconductor pattern 311 and the second oxide semiconductor pattern 312 are formed.

[0094] The second gate insulating layer 313 is an insulating layer that covers the first oxide semiconductor pattern 311 of the drive thin-film transistor DT and the second oxide semiconductor pattern 312 of the first switching thin-film transistor ST. Since the second gate insulating layer 313 is formed on the first oxide semiconductor pattern 311 and the second oxide semiconductor pattern 312, the second gate insulating layer 313 can be formed as an inorganic film that does not contain hydrogen particles.

[0095] Both the first source electrode 317s and the first drain electrode 317d can take the form of a single layer or multiple layers of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), or an alloy thereof. However, the present disclosure is not limited to these possibilities.

[0096] The control thin-film transistor DT is formed on the upper buffer layer 310.

[0097] According to one embodiment of the present disclosure, the control thin-film transistor DT has the first oxide semiconductor pattern 311.

[0098] In a conventional driver thin-film transistor, a polycrystalline semiconductor pattern is used as the active layer, which is advantageous for high-speed operation. However, the conventional driver thin-film transistor with the polycrystalline semiconductor pattern has the problem that a leakage current is generated in an off-state, thus consuming a large amount of energy. Therefore, the embodiment of the present disclosure proposes a driver thin-film transistor DT that uses an oxide semiconductor pattern as the active layer, which is advantageous with regard to preventing the generation of a leakage current.

[0099] In the case of a thin-film transistor using an oxide semiconductor pattern as the active layer, the current fluctuation value relative to a unit voltage fluctuation value is large due to the properties of the oxide semiconductor material, and therefore defects frequently occur in a low-gray area where precise current control is required. Therefore, the embodiment of the present disclosure provides a drive thin-film transistor in which a current fluctuation in an active layer is relatively insensitive to a fluctuation in the value of a voltage applied to a gate electrode. Furthermore, the embodiment of the present disclosure provides a drive thin-film transistor that has a relatively small channel area and a relatively high s-factor value to achieve high resolution.

[0100] With reference to Fig. 4 , Fig. 5A and Fig. 5B the drive thin-film transistor DT comprises a first oxide semiconductor pattern 311 formed on the upper buffer layer 310, and further comprises a second source electrode 319S and a second drain electrode 319D electrically connected to the first oxide semiconductor structure 311, and a second gate electrode 314 overlapping the first oxide semiconductor structure 311.

[0101] The second gate insulating layer 313 is positioned between the first oxide semiconductor pattern 311 and both the second source electrode 319S and the second drain electrode 319D. That is, the second gate insulating layer 313 covers the first oxide semiconductor pattern 311, and the second source electrode 319S and the second drain electrode 319D are located on the second gate insulating layer 313.

[0102] Furthermore, in one embodiment of the present disclosure, the second gate electrode 314 is formed on a second interlayer insulating layer 316, which covers the second source electrode 319S and the second drain electrode 319D and overlaps with the first oxide semiconductor pattern 311. Therefore, the second gate insulating layer 313 and the second interlayer insulating layer 316 are arranged between the second gate electrode 314 and the first oxide semiconductor pattern 311. Furthermore, the second gate electrode 314 is arranged on an insulating layer located on the second source electrode 319S and the second drain electrode 319D.

[0103] The first oxide semiconductor pattern 311 comprises a second channel region 311CH through which charge carriers move, and further comprises a second source region 311S and a second drain region 311D, which are arranged with the second channel region 311CH in between.

[0104] The second channel region 311CH is a region of the first oxide semiconductor pattern 311 that overlaps with the second gate electrode 314. Therefore, to reduce the size of the driving thin-film transistor DT, it is necessary to reduce the width of the second channel region 311CH by reducing the trace width of the second gate electrode 314.

[0105] The second source region 311S is provided with several conductive regions 311b and 311c, which are made conductive by the injection of foreign ions, and the second drain region 311D is provided with several conductive regions 311f and 311e, which are also made conductive by the injection of foreign ions. Furthermore, non-conductive regions 311a and 311d, into which no foreign ions are injected, are arranged between the conductive regions 311b and 311c and between the conductive regions 311f and 311e, respectively.

[0106] The conductive and non-conductive regions can be arranged alternately. It should be noted that a "non-conductive region" can refer to a region with a conductivity lower than that of the conductive regions shown here. For example, the non-conductive region could be an undoped intrinsic region.

[0107] In particular, the second source region 311s can be configured such that the non-conductive region 311a, the first conductive region 311b, the non-conductive region 311a, and the second conductive region 311c are arranged successively adjacent to one another. Similarly, the second drain region 311d can be configured such that the non-conductive region 311d, the first conductive region 311e, the non-conductive region 311d, and the second conductive region 311f are arranged successively adjacent to one another. Furthermore, the second conductive regions 311c and 311f are arranged adjacent to the second channel region 311CH.

[0108] The non-conductive regions 311a and 311d, which are contained in the second source region 311S and the second drain region 311D, serve as channel regions and thus have the effect of significantly increasing the length of the second channel region 311CH.

[0109] Since the non-conductive regions 311a and 311d contained in the second source region 311S and the second drain region 311D serve as channel regions in the driver thin-film transistor DT according to the embodiment of the present disclosure, it may be possible to realize a driver thin-film transistor DT with a smaller size by reducing the length of the second channel region 311CH.

[0110] With reference to Fig. 5B, the first conductive region 311b of the second source region 311S can be a region in contact with the second source electrode 319S. The first conductive region 311e of the second drain region 311D can be a region in contact with the second drain electrode 319D. The areas of the first conductive regions 311b and 311e can each be larger than the contact area between the second source electrode 319s and the second source region 311s, and the contact area between the second drain electrode 319d and the second drain region 311d. The reason for this is that the first conductive regions 311b and 311e are made conductive by bringing the second source region 311S and the second drain region 311D into contact with foreign ions, whereby at this time the foreign ions diffuse into certain sections of the second source region 311S and the second drain region 311D.As a result, the area areas of the first conductive regions 311b and 311e can each be larger than the contact area between the second source electrode 319s and the second source region 311s and the contact area between the second drain electrode 319D and the second drain region 311D.

[0111] The following describes a process for forming the first conductive areas 311b and 311e according to the embodiment of the present disclosure with reference to Fig. 9A is described in more detail.

[0112] The first oxide semiconductor pattern 311 is formed on the upper buffer layer 310, and then the second gate insulating layer 313, which electrically insulates the first oxide semiconductor pattern 311, is deposited on top of it. When the first oxide semiconductor pattern 311 comes into contact with hydrogen particles, oxygen vacancies contained in the first oxide semiconductor pattern 311 combine with the hydrogen particles, thus making the first oxide semiconductor pattern 311 conductive. Therefore, the second gate insulating layer 313 can be made of silicon dioxide (SiO2), which does not contain hydrogen particles.

[0113] A fifth contact hole CH5 and a sixth contact hole CH6 are formed in the second gate insulating layer 313 to expose the second source region 311S and the second drain region 311D, respectively.

[0114] In addition to the fifth contact hole CH5 and the sixth contact hole CH6, a seventh contact hole CH7, which exposes the upper surface of a first light-blocking pattern 308 located below the first oxide semiconductor pattern 311 to shield the first oxide semiconductor pattern 311 from light, a third and fourth contact hole CH3 and CH4, which expose a section of the third source region 312S and a section of the third drain region 312D of the second oxide semiconductor pattern 312 respectively, and a first and second contact hole CH1 and CH2, which expose a section of the first source region 303S and a section of the first drain region 303D of the first thin-film transistor GT located in the non-display region NA, are formed simultaneously.In this case, hydrogen particles are generated in a first intermediate insulating layer 302, which is formed on the first polycrystalline semiconductor pattern 303 and contains hydrogen particles, and in a second upper buffer sublayer 310b, which is formed on the first light-blocking pattern 308 and contains hydrogen particles. The generated hydrogen particles come into contact with the first oxide semiconductor pattern 311, thereby forming the first conductive regions 311b and 311e.

[0115] The second conductive region 311c of the second source region 311s can be the section of the second source region 311s located between the second gate electrode 314 and the second source electrode 319s. Furthermore, the second conductive region 311f of the second drain region 311D can be the section of the second drain region 311D located between the second gate electrode 314 and the second drain electrode 319D. Therefore, one end of the second source electrode 319S and one end of the second drain electrode 319D can be spaced apart from the respective ends of the second gate electrode 314.

[0116] The following describes a process for forming the second leading areas 311c and 311f with reference to Fig. 9B described.

[0117] After the second source electrode 319S and the second drain electrode 319D have been formed, a second intermediate insulating layer 316 is formed to cover the second source electrode 319S and the second drain electrode 319D. The second gate electrode 314 is formed on the second intermediate insulating layer 316.

[0118] The second gate electrode 314 is arranged to overlap with the first oxide semiconductor pattern 311, and the overlapping area of ​​the first oxide semiconductor pattern 311 becomes the second channel area 311CH.

[0119] As it is in Fig. As shown in Figure 5B, the second gate electrode 314 and the second source electrode 319S are spaced apart by a predetermined distance. Furthermore, as shown in Fig. As shown in Figure 5B, the second gate electrode 314 and the second drain electrode 319D are spaced apart by a predetermined distance. Foreign ions, for example, group III or group V ions such as boron (B) or phosphorus (P), are injected by ion implantation. At this point, the second gate electrode 314, the second source electrode 319S, and the second drain electrode 319D act as a mask for the injected ions, thereby forming the second conducting regions 311c and 311f. Therefore, unlike the first conducting regions 311b and 311e, the second conducting regions 311c and 311f are formed by an ion implantation process.

[0120] Furthermore, the control thin-film transistor DT also includes a first light-blocking pattern 308 which is inserted into the upper buffer layer 310 such that it overlaps with the first oxide semiconductor pattern 311.

[0121] Essentially, the first light-blocking pattern 308 can be inserted into the upper buffer layer 310. In one embodiment of the present disclosure, several upper buffer sublayers are provided. That is, a second upper buffer sublayer 310b and a third upper buffer sublayer 310c can be stacked successively in the upper buffer layer 310. Alternatively, a first upper buffer sublayer (in Fig. 3 not shown), a second upper buffer sublayer 310b and a third upper buffer sublayer 310c stacked one after the other.

[0122] With reference to Fig. 3 The first light-blocking pattern 308 is arranged on the first intermediate insulating layer 307. Additionally, the second upper buffer sublayer 310b completely covers the top surface of the first light-blocking pattern 308, and the third upper buffer sublayer 310c is formed on the second upper buffer sublayer 310b.

[0123] The first upper buffer sublayer and the third upper buffer sublayer 310c can be formed from silicon dioxide (SiO2).

[0124] The first upper buffer sublayer and the third upper buffer sublayer 310c consist of silicon dioxide (SiO2) which does not contain hydrogen particles, thus protecting the oxide semiconductor pattern whose reliability can be degraded due to the ingress of hydrogen particles during a heat treatment process.

[0125] The second upper buffer sublayer 310b can be made of silicon nitride (SiNx), which has an excellent ability to trap hydrogen particles. The second upper buffer sublayer 310b can be formed on a section of the first upper buffer sublayer such that it covers both the top surface and the side face of the first light-blocking pattern 308, thus completely sealing the first light-blocking pattern 308. Alternatively, the second upper buffer sublayer 310b can be formed on the entire surface of the first upper buffer sublayer on which the first light-blocking pattern 308 is formed. Silicon nitride (SiNx) has a better ability to trap hydrogen particles than silicon dioxide (SiO2).This means that when a hydrogenation process is carried out to introduce hydrogen particles into the first polycrystalline semiconductor pattern 303 of the first thin-film transistor GT, the second upper buffer sublayer 310b, which contains silicon nitride, traps hydrogen particles generated in the first interlayer insulating layer 307, thereby protecting the oxide semiconductor patterns formed thereon from the hydrogen particles. If hydrogen particles penetrate the oxide semiconductor pattern, a problem arises in which the oxide semiconductors exhibit different threshold voltages or channel conductivities depending on their formation positions.

[0126] In particular, it is important to ensure the reliability of the driver thin-film transistor, as the driver thin-film transistor directly contributes to the operation of the light-emitting element.

[0127] Since the second upper buffer sublayer 310b is designed to cover the first light-blocking pattern 308, it may be possible in the embodiment of the present disclosure to prevent a deterioration of the reliability of the driving thin-film transistor DT due to hydrogen particles.

[0128] Furthermore, in the embodiment of the present disclosure, the first light-blocking pattern 308 can be configured as a metal layer containing a titanium (Ti) material that has an excellent ability to trap hydrogen particles. For example, the metal layer can be a single layer of titanium, multiple layers of molybdenum (Mo) and titanium (Ti), or an alloy of molybdenum (Mo) and titanium (Ti). However, the present disclosure is not limited to these, and any other metal layer containing titanium (Ti) can be used.

[0129] Titanium (Ti) traps hydrogen particles that diffuse into the upper buffer layer 310, preventing the hydrogen particles from reaching the first oxide semiconductor pattern 311. Therefore, in the drive thin-film transistor DT according to the embodiment of the present disclosure, the first light-blocking pattern 308 is formed as a layer of metal such as titanium with the ability to trap hydrogen particles and is covered with a silicon nitride layer (SiNx layer) with the ability to trap hydrogen particles, thus mitigating the problem where the reliability of the oxide semiconductor pattern is degraded by hydrogen particles.

[0130] The second upper buffer sublayer 310b, which contains silicon nitride (SiNx), can selectively cover only the first light-blocking pattern 308.

[0131] The second upper buffer sublayer 310b is formed from a material different from that of the first upper buffer sublayer. Specifically, the second upper buffer sublayer 310b is formed as a silicon nitride film (SiNx film). If the second upper buffer sublayer 310b is deposited over the entire surface of the display area, film delamination may occur. To address this issue, the second upper buffer sublayer 310b can be selectively formed only on the necessary section, i.e., only at the location where the first light-blocking pattern 308 is formed.

[0132] The first light-blocking pattern 308 and the second upper buffer sublayer 310b are, from a functional perspective, preferably configured vertically below the first oxide semiconductor pattern 311 such that they overlap with the first oxide semiconductor pattern 311. Furthermore, the first light-blocking pattern 308 can be configured to be larger than the first oxide semiconductor pattern 311 in order to completely overlap with it.

[0133] Meanwhile, the second source electrode 319S of the control thin-film transistor DT can be electrically connected to the first light-blocking pattern 308.

[0134] As described above, when the first light-blocking pattern 308 is inserted into the upper buffer layer 310 and the second source electrode 319s is electrically connected to the first light-blocking pattern 308, the following additional effect can be achieved.

[0135] This is done with reference to the Fig. 8A and Fig. 8B described.

[0136] Fig. 8A is a cross-sectional view of the drive thin-film transistor DT under the in Fig. 3 components shown. Fig. 8B is a circuit diagram showing the relationship between the parasitic capacitance generated in the driving thin-film transistor DT and a voltage applied to it.

[0137] With reference to Fig. Since the second source region 311S and the second drain region 311D are made conductive, 8A becomes a parasitic capacitance C. act within the first oxide semiconductor pattern 311, a parasitic capacitance C is generated. gi a parasitic capacitance C is generated between the second gate electrode 314 and the first oxide semiconductor pattern 311. bufbetween the first light-blocking pattern 308, which is electrically connected to the second source electrode 319S, and the first oxide semiconductor pattern 311.

[0138] The first oxide semiconductor pattern 311 and the first light-blocking pattern 308 are electrically connected via the second source electrode 319S, thus connecting the parasitic capacitance Cact and the parasitic capacitance Cbuf in parallel and the parasitic capacitance Cact and the parasitic capacitance Cgi in series. Furthermore, when a gate voltage of V is applied, the following condition is met. gat (ΔV gat ) is applied to the second gate electrode 314, the effective voltage V eff (ΔV), which is actually applied to the first oxide semiconductor pattern 311, the following equation 1. ΔV=Cgi / (Cgi+Cact+Cbuf)×ΔVgat

[0139] Accordingly, the effective voltage applied to the channel of the first oxide semiconductor pattern 311 is inversely proportional to the parasitic capacitance C. buf and thus the effective voltage applied to the first oxide semiconductor pattern 311 can be adjusted by changing the parasitic capacitance C buf be adapted.

[0140] That is, if the first light-blocking pattern 308 is arranged close to the first oxide semiconductor pattern 311 to reduce the parasitic capacitance C buf To increase the current, the actual value of the current flowing through the first oxide semiconductor pattern 311 may be reduced.

[0141] The reduction of the RMS value of the current flowing through the first oxide semiconductor pattern 311 means that the range within which it is possible to drive the thin-film transistor DT using the actual voltage V applied to the second gate electrode 314 gat to control, is being expanded.

[0142] The effective voltage V eff can be determined by a ratio of the parasitic capacity C buf and the parasitic capacity C gi to be adapted. Therefore, in the Fig. In the embodiment shown in section 3, since the first light-blocking pattern 308 is arranged relatively close to the first oxide semiconductor pattern 311, the parasitic capacitance C buf greater than the parasitic capacity C gi This expands the range of grayscale values ​​within which the driver thin-film transistor DT can perform control. As a result, the light-emitting element can be precisely controlled even at low grayscale values, thus potentially solving a problem of uneven luminance that frequently occurs at low grayscale values.

[0143] The first thin-film transistor ST comprises a second oxide semiconductor pattern 312 formed on the upper buffer layer 310, a second gate insulating layer 313 covering the second oxide semiconductor pattern 312, a third source electrode and drain electrode 318S and 318D formed on the second gate insulating layer 313, a second intermediate insulating layer 316 formed on the third source electrode and drain electrode 318S and 318D, and a third gate electrode 315 formed on the second intermediate insulating layer 316.

[0144] The first switching thin-film transistor ST according to an embodiment of the present disclosure has a configuration that is generally similar to that of the drive thin-film transistor DT. However, the first switching thin-film transistor ST is smaller than the drive thin-film transistor DT. For example, the drive thin-film transistor DT may have a channel length of 7 µm, and the first switching thin-film transistor ST may have a channel length of 3 µm.

[0145] If the channel size of the switching thin-film transistor ST decreases, the amount of energy consumed decreases. If the components of the present disclosure, i.e., the source region and the drain region, are designed such that conductive and non-conductive regions are arranged alternately, the effective length of the channel of the switching thin-film transistor ST can increase, although the actual size of the channel remains constant. Therefore, if the embodiment of the present disclosure is designed to consume the same amount of energy as a conventional device, it may be possible to reduce the channel length.

[0146] The second oxide semiconductor pattern 312 includes a third channel region 312CH through which charge carriers move, and further includes a third source region 312S and a third drain region 312D, which are arranged with the third channel region 312CH in between.

[0147] The third channel region 312CH is a region of the second oxide semiconductor pattern 312 that overlaps with the third gate electrode 315. Therefore, to reduce the size of the first switching thin-film transistor ST, it is necessary to reduce the width of the third channel region 312CH by reducing the trace width of the third gate electrode 315.

[0148] The third source region 312S is provided with several conductive regions 312b and 312c, which are made conductive by the injection of foreign ions, and the third drain region 312D is provided with several conductive regions 312f and 312e, which are also made conductive by the injection of foreign ions. Furthermore, non-conductive regions 312a and 312d, into which no foreign ions are injected, are arranged between the conductive regions 312b and 312c and between the conductive regions 312f and 312e, respectively.

[0149] The conductive and non-conductive areas can be arranged alternately.

[0150] In particular, the third source region 312s can be configured such that the non-conductive region 312a, the third conductive region 312b, the non-conductive region 312a, and the fourth conductive region 312c are arranged successively adjacent to one another. Similarly, the third drain region 312d can be configured such that the non-conductive region 312d, the third conductive region 312e, the non-conductive region 312d, and the fourth conductive region 312f are arranged successively adjacent to one another. Furthermore, the fourth conductive regions 312c and 312f are arranged adjacent to the third channel region 312CH.

[0151] The non-conductive regions 312a and 312d, which are contained in the third source region 312S and the third drain region 312D, serve as channel regions and thus exhibit an effect of a substantial increase in the length of the third channel region 312CH.

[0152] Since the non-conductive regions 312a and 312d, which are contained in the third source region 312S and the third drain region 312D, serve as channel regions, it may therefore be possible in the first switching thin-film transistor ST according to the embodiment of the present disclosure to realize a first switching thin-film transistor ST with a smaller size by reducing the length of the third channel region 312CH.

[0153] The configuration of the drive thin-film transistor DT, which is in Fig. The configuration shown in 5B is essentially the same as that of the first switching thin-film transistor ST.

[0154] The first switching thin-film transistor ST may further comprise a second light-blocking pattern 304, which is arranged below the second oxide semiconductor pattern 312 such that it overlaps with it. In particular, the second light-blocking pattern 304 may be made of the same material as the first gate electrode 306 and may be formed on the upper surface of the first gate insulating layer 302. The second light-blocking pattern 304 may not be a required component. That is, in some cases, the second light-blocking pattern 304 may be omitted in the first switching thin-film transistor ST.

[0155] Alternatively, the second light-blocking pattern 304 can be formed on the same layer and from the same material as a second storage capacitor electrode 309, instead of being formed on the same layer and from the same material as the first gate electrode. That is, if a subpixel PX is equipped with multiple switching thin-film transistors, the multiple switching thin-film transistors can each be equipped with second light-blocking patterns 304 in different layers, thus increasing design freedom.

[0156] Although the second light-blocking pattern 304 in Fig. Since the third gate electrode 315 is not shown to be electrically connected to the third gate electrode 315, the second light-blocking pattern 304 can be electrically connected to the third gate electrode 315 to form a dual gate. Because the first switching thin-film transistor ST has a dual-gate structure, it may be possible to control the current flowing through the third channel area 312C more precisely, reduce the overall size of the display device, and realize a high-resolution display device.

[0157] The second oxide semiconductor pattern 312 consists of an oxide semiconductor material and includes a third channel region 312CH, which retains the intrinsic state of the oxide semiconductor material instead of being doped with foreign substances, and a third source region 312s and a third drain region 312D, in which conductive regions into which foreign substances are injected and non-conductive regions into which no foreign substances are injected are combined.

[0158] Similar to the first source electrode and drain electrode 317S and 317D and the second source electrode and drain electrode 319S and 319D, the third source electrode 318S and the third drain electrode 318D can each take the form of a single layer or multiple layers consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu) or an alloy thereof.

[0159] The third source electrode and drain electrode 318S and 318D are thus formed on the second gate insulating layer 313 simultaneously with and from the same material as the first source electrode and drain electrode 317S and 317D and the second source electrode and drain electrode 319S and 319D, making it possible to reduce the number of mask processes.

[0160] With reference to Fig. 3 The pixel circuit section 370 according to the embodiment of the present disclosure further comprises the storage capacitor Cst.

[0161] The storage capacitor Cst stores a data voltage that is applied to it via the data lines for a specific period of time, and then delivers the data voltage to the light-emitting element.

[0162] The storage capacitor Cst comprises two corresponding electrodes and a dielectric arranged between them. The storage capacitor Cst includes a first storage capacitor electrode 305, which is made of the same material as the first gate electrode 306 and is arranged on the same layer, and a second storage capacitor electrode 309, which is made of the same material as the first gate electrode 306 and is arranged on the same layer as the first light-blocking pattern 308.

[0163] The first intermediate layer insulating layer 307 is arranged between the first storage capacitor electrode 305 and the second storage capacitor electrode 309.

[0164] The second storage capacitor electrode 309 of the storage capacitor Cst can be electrically connected to the second source electrode 319S.

[0165] Next, an organic light-emitting display device according to a second embodiment of the present disclosure is described with reference to Fig. 6 described. The components of the second embodiment of the present disclosure are the same as those of the first embodiment, with the exception of the second gate electrode 314 and the third gate electrode 315.

[0166] With reference to Fig. In the second embodiment, the second gate electrode 314 and the third gate electrode 315 are formed on the same layer as the second source electrode 319S and the second drain electrode 319D. The second gate electrode 314 is arranged between the second source electrode 319S and the second drain electrode 319D. The third source electrode 318S and the third drain electrode 318D are arranged on the same layer as the second gate electrode 314 and the third gate electrode 315.

[0167] The second gate electrode 314 and the third gate electrode 315 are formed simultaneously and from the same material. However, the second gate electrode 314 and the third gate electrode 315 can be formed from the same material as the second source electrode 319S and the third source electrode 318S, or from other materials.

[0168] Since the second gate electrode 314, the second source electrode 319S, and the third source electrode 3185 are arranged on the same layer, a gate line 338, which applies a gate voltage to the second gate electrode 314, and a data line (not shown), which applies a source voltage to the second source electrode 319S and the third source electrode 318S, must be arranged in different layers. Gate lines and data lines are arranged to cross to define subpixels and must therefore be formed in different layers to prevent a short circuit from occurring when the gate lines and data lines cross. Therefore, in the second embodiment of the present disclosure, which is described in Fig. As shown in Figure 6, the gate conductor 338 is arranged on the second intermediate layer insulating layer 316 and can be connected to the second gate electrode 314 and the third gate electrode 315 through contact holes CHG.

[0169] In the case where the gate line 338 is formed on the second intermediate insulating layer 316, the gate line 338 can be covered with a third intermediate insulating layer 317 to electrically insulate the gate line 338 from the outside.

[0170] In the second embodiment, the upper buffer layer 310 is represented by a three-layer structure. That is, the upper buffer layer 310 can be configured such that the first upper buffer sublayer 310a, the second upper buffer sublayer 310b, and the third upper buffer sublayer 310c are stacked sequentially. In particular, the second upper buffer sublayer 310b can contain silicon nitride (SiNx), which has an excellent ability to trap hydrogen particles. The first upper buffer sublayer 310a and the third upper buffer sublayer 310c can be silicon oxide layers (SiO2 layers) that do not contain hydrogen particles.

[0171] The first light-blocking pattern 308 is arranged on the second upper buffer sublayer 310b.

[0172] Although the upper buffer layer 310 in the second embodiment is described as having a structure in which three upper buffer sublayers are stacked, this structure of the upper buffer layer 310 is also applicable to the first embodiment.

[0173] Next, a third embodiment of the present disclosure is described with reference to Fig. 7 described.

[0174] The third embodiment is the same as the first embodiment, except for the positions of the second gate electrode 314, the third gate electrode 315 and the first light-blocking pattern 308.

[0175] As described above, with reference to equation 1 and Fig. 8A takes the value of C bufto, when the distance (for example, a vertical distance in a direction perpendicular to a surface of the substrate 101) from the first oxide semiconductor pattern 311 to the first light-blocking pattern 308 decreases, and the value of the effective voltage V eff (ΔV) decreases. ΔV=Cgi / (Cgi+Cact+Cbuf)×ΔVgat

[0176] If the distance (for example, a vertical distance in a direction perpendicular to the surface of the substrate 101) from the first oxide semiconductor structure 311 to the second gate electrode 314 increases, the value of C decreases gi from and the value of the effective voltage V eff decreases. That is, when the value of C decreases buf increases and the value of C gi as the value of V decreases eff decrease significantly. The reduction in the value of V effThis means increasing the voltage range that can actually be applied to the gate electrode to control it. In other words, the s-factor value of the driving thin-film transistor DT can increase.

[0177] The first switching thin-film transistor ST must have a high operating speed. To increase the operating speed of the first switching thin-film transistor ST, it is necessary to reduce the distance (for example, a vertical distance in a direction perpendicular to the surface of the substrate 101) between the second oxide semiconductor pattern 312 and the third gate electrode 315. Therefore, in the third embodiment of the present disclosure, the second gate electrode 314 is arranged on the second intermediate insulating layer 316, the third gate electrode 315 is arranged on the second gate insulating layer 313, and the first light-blocking pattern 308 is arranged on the second upper buffer sublayer 310b. As a result, the s-factor value of the drive thin-film transistor DT and the operating speed of the first switching thin-film transistor ST increase, thereby realizing the highly efficient pixel circuit section of the subpixel.

[0178] With reference to Fig. 3. A first planarization layer PLN1 and a second planarization layer PLN2 can be sequentially formed on the pixel circuit section 370 to planarize the upper end of the pixel circuit section 370. The section for light-emitting elements 380 comprises a first electrode 323, which is an anode, a second electrode 327, which is a cathode corresponding to the first electrode 323, and a light-emitting layer 325, which is arranged between the first electrode 323 and the second electrode 327. The first electrode 323 is formed in each subpixel.

[0179] The light-emitting element section 380 is connected to the pixel circuit section 370 via a connecting electrode 321 formed on the first planarization layer PLN1. In particular, the first electrode 323 of the light-emitting element section 380 and the second drain electrode 319D of the driver thin-film transistor DT, which forms the pixel circuit section 370, are connected to each other via the connecting electrode 321.

[0180] The first electrode 323 is connected to the connecting electrode 321, which is exposed through a contact hole CH9 formed through the second planarization layer PLN2. Furthermore, the connecting electrode 321 is connected to the second drain electrode 319D, which is exposed through a contact hole CH8 formed through the first planarization layer PLN1.

[0181] The first electrode 323 can be configured in a multilayer structure comprising a transparent conductive film and an opaque conductive film with high reflection efficiency. The transparent conductive film can be made of a material with a relatively high work function, such as indium tin oxide (ITO) or indium zinc oxide (IZO), and the opaque conductive film can be configured in a single-layer or multilayer structure containing Al, Ag, Cu, Pb, Mo, Ti, or an alloy thereof. For example, the first electrode 323 can be configured in a structure such that a transparent conductive film, an opaque conductive film, and a transparent conductive film are stacked sequentially, or such that a transparent conductive film and an opaque conductive film are stacked sequentially.

[0182] The light-emitting layer 325 is formed by stacking a hole-related layer, an organic light-emitting layer and an electron-related layer on the first electrode 323 either in that order or in reverse order.

[0183] A bank layer 324 is a pixel-defining film that exposes the first electrode 323 of each subpixel. The bank layer 324 can be made of an opaque material (e.g., black material) to prevent optical interference between adjacent subpixels. In this case, the bank layer 324 comprises a light-blocking material, which includes a color pigment, organic black, or carbon. Furthermore, a spacer 326 can be arranged on the bank layer 324.

[0184] The second electrode 327, which is the cathode, is formed on the upper surface and the side faces of the light-emitting layer 325 such that it faces the first electrode 323, with the light-emitting layer 325 positioned between them. The second electrode 327 can be formed in one piece over the entire surface of the active area. In the case where the second electrode 327 is applied to an organic light-emitting display device of the upward emission type, the second electrode 327 can be formed as a transparent conductive film, for example, made of indium tin oxide (ITO) or indium zinc oxide (IZO).

[0185] An encapsulation section 390 to prevent the ingress of moisture can also be arranged on the second electrode 327.

[0186] The encapsulation section 390 can comprise a first inorganic encapsulation layer 328a, a second organic encapsulation layer 328b and a third inorganic encapsulation layer 328c, stacked sequentially.

[0187] The first inorganic encapsulation layer 328a and the third inorganic encapsulation layer 328c can be formed from an inorganic material such as silicon dioxide (SiOx). The second organic encapsulation layer 328b can be formed from an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0188] As can be seen from the foregoing description, in an organic light-emitting display device according to some embodiments of the present disclosure, a drive thin-film transistor and a switching thin-film transistor have an oxide semiconductor pattern, thereby reducing power consumption. Additionally, a thin-film transistor is provided that can operate effectively at low grayscale values. Furthermore, since a source region and a drain region each have conductive and non-conductive areas, it may be possible to achieve an effect of increasing (e.g., substantially increasing) the length of a channel. Accordingly, the present disclosure is applicable to a high-resolution organic light-emitting display device in which the number of pixels arranged in each unit area is relatively large.

Claims

[1] Organic light-emitting display device comprising: a substrate (101) having a display area (AA) and a non-display area (NA); and at least one thin-film transistor (DT, ST) having a semiconductor pattern (311, 312) having a source region (311S, 312S) and a drain region (311D, 312D), wherein the source region (311S, 312S) and the drain region (311D, 312D) each have conductive regions (311b, 311c, 311e, 311f; 312b, 312c, 312e, 312f) and non-conductive regions (311a, 311d; 312a, 312d) arranged alternately on the substrate (101), wherein the at least one thin-film transistor (DT, ST) comprises: a gate electrode (314, 315) facing the semiconductor pattern (311, 312); and a source electrode (319S, 318S) and a drain electrode (319D, 318D) that are electrically connected to the source region (311S, 312S) and the drain region (311D, 312D), respectively, wherein the conductive regions (311b, 311c, 311e, 311f; 312b, 312c, 312e, 312f) comprise a first conductive region (311b, 311e; 312b, 312e) that contacts the source electrode (319S, 318S) or the drain electrode (319D, 318D), and a second conductive region (311c, 311f; 312c, 312f) that is arranged between the source electrode (319S, 318S) or the drain electrode (319D, 318D) and the gate electrode (314, 315), wherein the first conductive region (311b, 311e; 312b, 312e) is made conductive by being connected to ions were brought into contact, and wherein the second conductive area (311c, 311f; 312c, 312f) is made conductive by injecting ions into it. [2] Organic light-emitting display device according to claim 1, wherein the semiconductor pattern (311, 312) is an oxide semiconductor pattern. [3] Organic light-emitting display device according to claim 1 or 2, wherein the gate electrode (314, 315) is arranged on a layer that is further away from the substrate (101) than a layer on which the source electrode (319S, 318S) and the drain electrode (319D, 318D) are arranged, or the gate electrode (314, 315) is arranged on the same layer as the source electrode (319S, 318S) and the drain electrode (319D, 318D). [4] Organic light-emitting display device according to claim 1, 2 or 3, wherein the at least one thin-film transistor (DT, ST) comprises a drive thin-film transistor (DT), wherein the drive thin-film transistor (DT) comprises: a first semiconductor pattern (311); a first gate electrode (314) facing the first semiconductor pattern (311); and a first source electrode (319S) and a first drain electrode (319D), each connected to the first semiconductor pattern (311). [5] Organic light-emitting display device according to claim 4, wherein the at least one thin-film transistor (DT, ST) comprises a switching thin-film transistor (ST), wherein the switching thin-film transistor (ST) comprises: a second semiconductor pattern (312); a second gate electrode (315) facing the second semiconductor pattern (312); and a second source electrode (318S) and a second drain electrode (318D), each connected to the second semiconductor pattern (312), and wherein the first source electrode (319S), the first drain electrode (319D), the second source electrode (318S) and the second drain electrode (318D) are arranged on the same layer. [6] Organic light-emitting display device according to claim 5, wherein the first gate electrode (314) and the second gate electrode (315) are arranged on the same layer which is further away from the substrate (101) than a layer in which the first source electrode (319S), the first drain electrode (319D), the second source electrode (318S) and the second drain electrode (318D) are arranged. [7] Organic light-emitting display device according to claim 5, wherein the first gate electrode (314) and the second gate electrode (315) are arranged on the same layer as the first source electrode (319S), the first drain electrode (319D), the second source electrode (318S) and the second drain electrode (318D). [8] Organic light-emitting display device according to claim 5, wherein the first gate electrode (314) and the second gate electrode (315) are arranged on different layers, and wherein a vertical distance between the first gate electrode (314) and the first semiconductor pattern (311) is longer than a vertical distance between the second gate electrode (315) and the second semiconductor pattern (312). [9] Organic light-emitting display device according to claim 8, wherein the driver thin-film transistor (DT) has a first light-blocking pattern (308) arranged below the first semiconductor pattern (311) and connected to the first source electrode (319S), and the switching thin-film transistor (ST) has a second light-blocking pattern (304), and wherein a vertical distance between the second semiconductor pattern (312) and the second light-blocking pattern (304) is longer than a vertical distance between the first semiconductor pattern (311) and the first light-blocking pattern (308). [10] Organic light-emitting display device according to any one of claims 5 to 9, wherein the control thin-film transistor (DT) is arranged in the display area (AA), and / or wherein the switching thin-film transistor (ST) is arranged in the display area (AA) and / or the non-display area (NA). [11] Thin-film transistor assembly substrate comprising: at least one thin-film transistor (ST, DT) having a semiconductor pattern (311, 312) wherein the semiconductor pattern (311, 312) has a source region (311S, 312S), a drain region (311D, 312D) and a channel region (311CH, 312CH) arranged between the source region (311S, 312S) and the drain region (311D, 312D), wherein the source region (311S, 312S) and the drain region (311D, 312D) each have at least two conductive regions (311b, 311c, 311e, 311f; 312b, 312c, 312e, 312f) and a non-conductive region (311a, 311d; 312a, 312d) which is arranged between adjacent conductive regions (311b, 311c, 311e, 311f; 312b, 312c, 312e, 312f), wherein the at least two conductive areas (311b, 311c, 311e, 311f; 312b, 312c, 312e, 312f) comprise a first conductive area (311b, 311e; 312b, 312e) spaced apart from the channel area (311CH, 312CH) and a second conductive area (311c, 311f; 312c, 312f) arranged adjacent to the channel area (311CH, 312CH), wherein the first conductive area (311b, 311e; 312b, 312e) is made conductive by being brought into contact with ions, and wherein the second conductive area (311c, 311f; 312c, 312f) is made conductive by being injected with ions. [12] Thin-film transistor array substrate according to claim 11, wherein the conductive regions (311b, 311c, 311e, 311f; 312b, 312c, 312e, 312f) and the non-conductive region (311a, 311d; 312a, 312d) are arranged alternately in the source region (311S, 312S) and the drain region (311D, 312D). [13] Thin-film transistor mounting substrate according to claim 11 or 12, further comprising: a source electrode (319S, 318S) and a drain electrode (319D, 318D) connected to the source region (311S, 312S) and the drain region (311D, 312D), respectively; and a light-blocking pattern (308) arranged between the semiconductor pattern (311, 312) and the substrate (101), wherein the light-blocking pattern (308) is connected to the source electrode (319S, 318S). [14] Thin-film transistor array substrate according to any one of claims 11 to 13, wherein the at least one thin-film transistor (DT, ST) is a drive thin-film transistor (DT) and / or a switching thin-film transistor (ST). [15] Organic light-emitting display device comprising the thin-film transistor array substrate according to any one of claims 11 to 14.

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