Semiconductor package structure

Abstract

Semiconductor package structure (500; 700), comprising: a first redistribution layer (102); a first semiconductor die (108) arranged above the first redistribution layer (102) and having a first via (110) with a first width; a second via (116) adjacent to the first semiconductor die (108) and with a second width that is larger than the first width; a molding material (118) that surrounds the first semiconductor die (108) and the second via (116); a second semiconductor die (120) which is arranged above the mold material (118) and electrically connected to the first via (110) and the second via (116); a second redistribution layer (124) arranged above the second semiconductor die (120); and an interposer (302) located between the first redistribution layer (102) and the second semiconductor die (120) is arranged and has a deep trench capacitor (600).

Description

BACKGROUND OF THE INVENTION Field of Invention

[0001] The present invention relates to semiconductor packaging technology and in particular to a semiconductor package structure. Description of the state of the art

[0002] A semiconductor package structure can not only protect a semiconductor die from environmental contaminants, but can also provide an electrical connection between the semiconductor die packaged within it and a substrate, such as a printed circuit board (PCB).

[0003] Although existing semiconductor package structures have generally been adequate, they are not satisfactory in every respect. For example, as semiconductor dies acquire more and more functions, the costs and effort involved in manufacturing the semiconductor package structures also increase. Therefore, further improvements to semiconductor package structures are necessary.

[0004] Semiconductor package structures with multiple vias and semiconductor dies are known from DE 10 2020 112 959 A1, DE 10 2016 100 523 A1, US 2012 / 0056316 A1, and US 2015 / 0303174 A1. Vias of different widths are described in US 2020 / 0328161 A1 and US 2021 / 0057362 A1. CN 113363162 A discloses a semiconductor package structure with a deep-trench capacitor. BRIEF SUMMARY OF THE INVENTION

[0005] One aspect of the invention relates to a semiconductor package structure according to claim 1.

[0006] Another aspect of the invention relates to a semiconductor package structure according to claim.

[0007] Preferred embodiments of the invention are specified in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present invention can be better understood by reading the following detailed description and the following examples with reference to the accompanying drawings, in which: Fig. 1 a cross-sectional view of an exemplary semiconductor package structure according to unclaimed examples; Fig. 2 a cross-sectional view of an exemplary semiconductor package structure according to unclaimed examples; Fig. 3 a cross-sectional view of an exemplary semiconductor package structure according to unclaimed examples; Fig. 4 is a cross-sectional view of an exemplary semiconductor package structure according to unclaimed examples; Fig. 5 is a cross-sectional view of an exemplary semiconductor package structure according to some embodiments; Fig. 6 is a cross-sectional view of a section of an exemplary semiconductor package structure according to some embodiments; Fig. 7 is a cross-sectional view of an exemplary semiconductor package structure according to some embodiments; Fig. 8 is a cross-sectional view of an exemplary semiconductor package structure according to unclaimed examples; Fig. 9 is a cross-sectional view of an exemplary semiconductor package structure according to some embodiments; Fig. Figure 10 shows a cross-sectional view of an exemplary semiconductor package structure according to some unclaimed examples; and Fig. Figure 11 shows a cross-sectional view of an exemplary semiconductor package structure according to some embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0009] The following description serves to explain the general principles of the invention and should not be understood in a limiting sense. The scope of the invention is best determined by reference to the accompanying claims.

[0010] The present invention is described with reference to certain embodiments and drawings, but the invention is not limited thereto and is only restricted by the claims. The described drawings are schematic only and not limiting. In the drawings, the size of some elements may be exaggerated for descriptive purposes and may not be shown to scale. The dimensions and relative dimensions do not correspond to the actual dimensions in the embodiment of the invention.

[0011] Additional elements can be added based on the embodiments described below. For example, the description of “forming a first element on a second element” may include embodiments in which the first element is in direct contact with the second element, and may also include embodiments in which additional elements are arranged between the first element and the second element, so that the first element and the second element are not in direct contact.

[0012] The spatially relative descriptions of the first and second elements may change when the structure is operated or used in different orientations. Furthermore, the present invention may repeat reference numerals and / or letters in the various embodiments. This repetition serves for simplicity and clarity and does not in itself imply any relationship between the different described embodiments.

[0013] A semiconductor package structure according to some embodiments of the present invention is described. The semiconductor package structure comprises semiconductor die subdivisions. In particular, the semiconductor package structure according to the present invention replaces one large semiconductor die with two or more semiconductor dies, thus reducing manufacturing costs and effort and improving yield and performance.

[0014] Fig. Figure 1 is a cross-sectional view of a semiconductor package structure 100 according to unclaimed embodiments. Additional features can be added to the semiconductor package structure 100. Some of the features described below can be substituted or omitted for different embodiments. To simplify the illustration, only a portion of the semiconductor package structure 100 is shown.

[0015] As in Fig. As shown in Figure 1, the semiconductor package structure 100, according to some embodiments, has a first redistribution layer 102 on a front side and a second redistribution layer 124 on a back side, opposite the front side. Therefore, the first redistribution layer 102 can also be referred to as the front-side redistribution layer, and the second redistribution layer 124 can also be referred to as the back-side redistribution layer.

[0016] The first redistribution layer 102 and the second redistribution layer 124 can each comprise one or more conductive layers arranged within one or more passivation layers. The conductive layers can be made of conductive material, such as copper, aluminum, tungsten, the like, an alloy thereof, or a combination thereof. The passivation layers can comprise a polymer layer made of polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), epoxy, or the like, or a combination thereof. Alternatively, the passivation layers can comprise a dielectric layer made of silicon oxide, silicon nitride, silicon oxynitride, or the like, or a combination thereof.

[0017] As in Fig. As shown in Figure 1, the first redistribution layer 102, according to some embodiments, has more conductive and passivation layers than the second redistribution layer 124. The first redistribution layer 102 may be thicker than the second redistribution layer 124, but the present invention is not limited to this. For example, the second redistribution layer 124 may be thicker or substantially the same thickness as the first redistribution layer 102.

[0018] As in Fig. As shown in Figure 1, the semiconductor package structure 100, according to some embodiments, has a plurality of bump structures 104 arranged below the first redistribution layer 102 and electrically connected to it. The bump structures 104 can be micro-bumps, flip-chip (C4) bumps, solder balls, ball grid array (BGA) balls, or the like, or a combination thereof. The bump structures 104 can be made of conductive material, for example, copper, aluminum, tungsten, or the like, an alloy thereof, or a combination thereof.

[0019] As in Fig. As shown in Figure 1, the semiconductor package structure 100, according to some embodiments, includes a capacitor 106 which is arranged below the first redistribution layer 102 and electrically connected to the first redistribution layer 102. The capacitor 106 can be an integrated passive device (IPD) for improving electrical properties. The capacitor 106 can be arranged between the conductive terminals 104.

[0020] As in Fig. As shown in Figure 1, the semiconductor package structure 100, according to some embodiments, comprises a first semiconductor die 108 arranged above the first redistribution layer 102, and a second semiconductor die 120 arranged above the first semiconductor die 108. The first semiconductor die 108 can also be referred to as the lower semiconductor die, and the second semiconductor die 120 can also be referred to as the upper semiconductor die.

[0021] In some embodiments, the first semiconductor die 108 and the second semiconductor die 120 each independently comprise a system-on-a-chip (SoC) die, a logic device, a memory device, a radio frequency (RF) device, the like, or a combination thereof. For example, the first semiconductor die 108 and the second semiconductor die 120 can each independently comprise a microcontroller (MCU) die, a microprocessor unit (MPU) die, a power management integrated circuit (PMIC) die, a GPS (global position system) device, an accelerated processing unit (APU) die, a central processing unit (CPU) die, a graphics processing unit (GPU) die, an input / output (I / O) die, a dynamic random access memory (DRAM) controller, static random access memory (SRAM), high bandwidth memory (HBM), the like, or any combination thereof.

[0022] The size of the second semiconductor die 120 can be larger than the size of the first semiconductor die 108. The first semiconductor die 108 and the second semiconductor die 120 can comprise semiconductor dies manufactured at different nodes. For example, the first semiconductor die 108 can contain SRAM manufactured at a mature node, and the second semiconductor die 120 can contain a SoC manufactured at an advanced node.

[0023] In comparison to a semiconductor die possessing all required functions, the present invention uses semiconductor die subdivisions (for example, the first semiconductor die 108 and the second semiconductor die 120), each of which possesses some of the required functions. As a result, manufacturing costs and effort can be reduced, and yield and performance improved. Furthermore, thermal behavior can be improved because thermal coupling is avoided.

[0024] In some embodiments, the semiconductor package structure 100 also includes one or more passive components (not shown) adjacent to the first semiconductor die 108 or the second semiconductor die 120, for example resistors, capacitors, inductors, the like or a combination thereof.

[0025] As in Fig. As shown in Figure 1, the first semiconductor die 108, according to some embodiments, has one or more embedded vias 110 that electrically connect the second semiconductor die 120 to the first redistribution layer 102. The vias 110 can be made of conductive material, for example, copper, aluminum, tungsten, the like, an alloy thereof, or a combination thereof. The vias 110 can extend from a first surface to a second surface of the first semiconductor die 108, which is opposite the first surface.

[0026] As in Fig. As shown in Figure 1, the semiconductor package structure 100 according to some embodiments of the present invention has a plurality of bump structures 112 arranged between the first semiconductor die 108 and the second semiconductor die 120. The bump structures 112 can electrically connect the vias 110 to the second semiconductor die 120.

[0027] The bump structures 112 can have microbumps, flip-chip (C4) bumps, solder balls, ball grid array (BGA) balls, or the like, or a combination thereof. The bump structures 112 can be formed from conductive material, for example, copper, aluminum, tungsten, or the like, an alloy thereof, or a combination thereof. The first semiconductor die 108 can be bonded to the second semiconductor die 120 by any suitable bonding techniques, such as microbump bonding, direct hybrid bonding, or the like.

[0028] As in Fig. As shown in Figure 1, the semiconductor package structure 100 according to some embodiments of the present invention comprises an underfill material 114 that surrounds the bump structures 112 to provide structural support. The underfill material 114 can be made of a polymer such as epoxy. The underfill material 114 can be dispensed by capillary action and then cured by any suitable curing process.

[0029] As in Fig. As shown in Figure 1, the semiconductor package structure 100, according to some embodiments, has one or more vias 116 arranged above the first redistribution layer 102 and adjacent to the first semiconductor die 108. The vias 116 can be electrically connected to the first redistribution layer 102. The vias 116 can be made of conductive material, for example, copper, aluminum, tungsten, the like, an alloy thereof, or a combination thereof. The second semiconductor die 120 can be electrically connected to the capacitor 106 via the bump structures 112, the vias 110, the vias 116, and the first redistribution layer 102.

[0030] In some embodiments, the vias 116 have a width greater than the width of the vias 110. The width of the vias 110 and 116 can be measured in a direction substantially parallel to the top surface of the first redistribution layer 102. In some embodiments, the width of the vias 110 can be from 2 µm to 18 µm, and the width of the vias 116 can be from 40 µm to 80 µm.

[0031] As in Fig. As shown in Figure 1, the semiconductor package structure 100, according to some embodiments, has a molding material 118 arranged above the first redistribution layer 102. The molding material 118 can be made of a non-conductive material such as a moldable polymer, an epoxy, a resin, or the like, or a combination thereof. As shown in Figure 1, the semiconductor package structure 100 has a molding material 118 arranged above the first redistribution layer 102. The molding material 118 can be made of a non-conductive material such as a moldable polymer, an epoxy, a resin, or the like, or a combination thereof. Fig. As shown in Figure 1, the side walls of the molding material 118 can be essentially coplanar with the side walls of the first redistribution layer 102 and the second redistribution layer 124.

[0032] The molding material 118 can surround the first semiconductor die 108 and the vias 116 and can abut the sidewalls of the first semiconductor die 108. The molding material 118 can protect the first semiconductor die 108 and the vias 116 from the environment, thus preventing these components from being damaged by, for example, voltages, chemicals and / or moisture.

[0033] Fig. Figure 2 is a cross-sectional view of a semiconductor package structure 200 according to unclaimed embodiments. It should be noted that the semiconductor package structure 200 has the same or similar components as those in Figure 2. Fig. The semiconductor package structure shown in Figure 1 can have 100 components, and for the sake of simplicity, these components are not described again in detail. In the following embodiments, a redistribution layer connects semiconductor dies.

[0034] As in Fig. As shown in Figure 2, the semiconductor package structure 200, according to some embodiments, has a third redistribution layer 126 arranged between the first semiconductor die 108 and the second semiconductor die 120. The sidewalls of the third redistribution layer 126 can be substantially coplanar with the sidewalls of the mold material 118. The third redistribution layer 126 can resemble the first redistribution layer 102 or the second redistribution layer 124 and is not repeated. The second semiconductor die 120 can be electrically connected to the capacitor 106 via the third redistribution layer 126, the vias 110, the vias 116, and the first redistribution layer 102.

[0035] Fig. Figure 3 is a cross-sectional view of a semiconductor package structure 300 according to unclaimed embodiments. It should be noted that the semiconductor package structure 300 has the same or similar components as those in Figure 3. Fig. The semiconductor package structure 100 shown in Figure 1 can have several components, and for the sake of simplicity, these components are not described again in detail. In the following embodiments, the semiconductor package structure 300 has an additional semiconductor die.

[0036] As in Fig. As shown in Figure 3, the semiconductor package structure 300, according to some embodiments, has a third semiconductor die 202, which is arranged between the first redistribution layer 102 and the second semiconductor die 120 and adjacent to the vias 116. The third semiconductor die 202 may be surrounded by the form material 118. The third semiconductor die 202 may resemble the first semiconductor die 202 and is not repeated.

[0037] As in Fig. As shown in Figure 3, the first semiconductor die 108 and the third semiconductor die 202 are arranged on opposite sides of the vias 116, but the present invention is not limited thereto. The number and configuration of the semiconductor dies are shown only by way of example. For instance, the first semiconductor die 108 and the third semiconductor die 202 can be arranged on the same side of the vias 116. In some embodiments, the first semiconductor die 108 and the third semiconductor die 202 can be stacked vertically between the second semiconductor die 120 and the first redistribution layer 102. Alternatively, in some further embodiments, the semiconductor package structure 100 has more than two semiconductor dies between the second semiconductor die 120 and the first redistribution layer 102.

[0038] As in Fig. As shown in Figure 3, the third semiconductor die 202, according to some embodiments, has one or more embedded vias 204 that electrically connect the second semiconductor die 120 to the first redistribution layer 102. The vias 204 can be made of conductive material, for example, copper, aluminum, tungsten, the like, an alloy thereof, or a combination thereof. The vias 204 can extend from a first surface of the third semiconductor die 202 to a second surface of the third semiconductor die 202 that faces the first surface.

[0039] In some embodiments, the vias 204 have a width that is smaller than the width of the vias 116. The width of the vias 204 can be greater, less, or substantially equal to the width of the vias 110 in the first semiconductor die 108. The width of the vias 204 can be measured in a direction that is substantially parallel to the top surface of the first redistribution layer 102. In some embodiments, the width of the vias 204 can be from 2 µm to 18 µm.

[0040] As in Fig. As shown in Figure 3, both the first semiconductor die 108 and the third semiconductor die 202 have the vias, but the present invention is not limited thereto. The number and configuration of the vias are shown only as examples. For instance, the first semiconductor die 108 may have the vias 110, and the third semiconductor die 202 need not have the vias 204.

[0041] As in Fig. As shown in Figure 3, the semiconductor package structure 300, according to some embodiments of the present invention, comprises a plurality of bump structures 206 between the second semiconductor die 120 and the third semiconductor die 202, and an underfill material 208 surrounding the bump structures 206. The bump structures 206 can electrically connect the vias 204 to the second semiconductor die 120. The second semiconductor die 120 can be electrically connected to the capacitor 106 via the bump structures 112, the vias 110, the bump structures 206, the vias 204, the vias 116, and the first redistribution layer 102. The bump structures 206 can resemble the bump structures 112, and the underfill material 208 can resemble the underfill material 114, and these are not repeated.

[0042] Fig. Figure 4 is a cross-sectional view of a semiconductor package structure 400 according to unclaimed embodiments. It should be noted that the semiconductor package structure 400 has the same or similar components as those described in Figure 4. Fig. The semiconductor package structure shown in Figure 3 can have 300 components, and for the sake of simplicity, these components will not be described again in detail. In the following embodiments, a redistribution layer connects semiconductor dies.

[0043] As in Fig. As shown in Figure 4, the semiconductor package structure 400, according to some embodiments, has a third redistribution layer 126 arranged between the first semiconductor die 108 and the second semiconductor die 120. The third redistribution layer 126 may resemble the first redistribution layer 102 or the second redistribution layer 124 and is not repeated. The second semiconductor die 120 may be electrically connected to the capacitor 106 via the third redistribution layer 126, the vias 110, the vias 204, the vias 116, and the first redistribution layer 102.

[0044] Fig. Figure 5 is a cross-sectional view of a semiconductor package structure 500 according to some embodiments of the invention. It should be noted that the semiconductor package structure 500 has the same or similar components as those described in Figure 5. Fig. The semiconductor package structure 100 shown in Figure 1 can have several components, and for the sake of simplicity, these components will not be described again in detail. In the following embodiments, the semiconductor package structure 500 has an interposer containing a deep-trench capacitor.

[0045] As in Fig. As shown in Figure 5, the semiconductor package structure 500, according to some embodiments, has an interposer 302 located between the first redistribution layer 102 and the second semiconductor die 120, and adjacent to the first semiconductor die 108 and the third semiconductor die 202. The interposer 302 may be surrounded by the mold material 118. Since the material of the interposer 302 has a higher thermal conductivity than the material of the mold material 118, replacing a portion of the mold material 118 with the interposer 302 may increase the heat dissipation efficiency of the semiconductor package structure 500.

[0046] As in Fig. As shown in Figure 5, the interposer 302, according to some embodiments, has one or more vias 304 which are electrically connected to the first redistribution layer 102. The vias 304 can be made of conductive material, for example, copper, aluminum, tungsten, the like, an alloy thereof, or a combination thereof. The vias 304 can extend from a first surface of the interposer 302 to a second surface of the interposer 302, which is opposite the first surface.

[0047] In some embodiments, the vias 304 have a width greater than the width of the vias 110 in the first semiconductor die 108 and greater than the width of the vias 204 in the third semiconductor die 202. The width of the vias 304 can be measured in a direction substantially parallel to the top surface of the first redistribution layer 102. In some embodiments, the width of the vias 304 can be from 40 µm to 80 µm.

[0048] As in Fig. As shown in Figure 5, the interposer 302, according to some embodiments, includes a deep trench capacitor 600. The deep trench capacitor 600 can be arranged on a front or a rear side of the interposer 302. In contrast to a capacitor arranged under the first redistribution layer 102 (such as the one shown in Figure 5), the deep trench capacitor 600 can be located on a front or a rear side of the interposer 302. Fig. (Capacitor 106 shown in Figure 1) allows the deep trench capacitor 600 to be positioned closer to the second semiconductor die 120. This further improves its electrical properties. Additionally, more bump structures 104 can be arranged for electrical interconnection. The deep trench capacitor 600 is described with reference to Fig. 6 described.

[0049] Fig. Figure 6 is a cross-sectional view of a section of the semiconductor package structure according to some embodiments of the present invention. Some of the in Fig. The 6 components shown can be found in some components of the in Fig. The semiconductor package structure shown in section 5 resembles 500, and for the sake of simplicity these components are not described again in detail.

[0050] As in Fig. As shown in Figure 6, the trench capacitor 600, according to some embodiments of the present invention, comprises a semiconductor substrate 602. The semiconductor substrate 602 can be made of semiconductor materials, for example silicon, germanium, a III-V semiconductor material, the like, or a combination thereof. The semiconductor substrate 602 can be doped (e.g., using p- or n-type dopants) and can have a first conductivity type.

[0051] According to some embodiments of the present invention, the deep trench capacitor 600 has a conductive region 604 in the semiconductor substrate 602. The conductive region 604 can be heavily doped (e.g., using p- or n-type dopants) and can have a second conductivity type that differs from the first conductivity type. For example, the first conductivity type can be the n-type and the second conductivity type can be the p-type.

[0052] As in Fig. As shown in Figure 6, the deep trench capacitor 600, according to some embodiments of the present invention, has alternating dielectric layers 606, 608 and conductive layers 610, 612 in the conductive region 604. The dielectric layers 606 and 608 can each be formed independently of one another from high-k dielectrics such as aluminum oxide. The conductive layers 610 and 612 can each be formed independently of one another from conductive materials such as polysilicon.

[0053] As in Fig. As shown in Figure 6, the trench capacitor 600, according to some embodiments of the present invention, has a connecting structure 614 arranged above the conductive area 604. The connecting structure 614 can be electrically connected to the conductive area 604 and the conductive layers 610 and 612. The connecting structure 614 can be made of conductive material, for example, copper, aluminum, tungsten, the like, an alloy thereof, or a combination thereof.

[0054] With renewed reference to Fig. According to some embodiments of the present invention, the semiconductor package structure 500 comprises several bump structures 306 arranged between the interposer 302 and the second semiconductor die 120, and an underfill material 308 surrounding the bump structures 306. The bump structures 306 can electrically connect the vias 304 and the deep-ditch capacitor 600 to the second semiconductor die 120. The bump structures 306 can resemble the bump structures 112, and the underfill material 308 can resemble the underfill material 114, and these are not repeated.

[0055] Although two semiconductor dies (the first semiconductor die 108 and the third semiconductor die 202) are located under the second semiconductor die 120 in Fig. The present invention is not limited to those shown in Figure 5. For example, in some embodiments, the semiconductor package structure 500 need not include the third semiconductor die 202. Alternatively, in some further embodiments, the third semiconductor die 202 can be connected by one or more vias (such as those shown in Figure 5). Fig. The vias shown in 116) are replaced.

[0056] Fig. Figure 7 is a cross-sectional view of a semiconductor package structure 700 according to some embodiments of the invention. It should be noted that the semiconductor package structure 700 has the same or similar components as those described in Figure 7. Fig. The semiconductor package structure shown in Figure 5 can have 500 components, and for the sake of simplicity, these components will not be described again in detail. In the following embodiments, a redistribution layer connects semiconductor dies and a deep-trench capacitor.

[0057] As in Fig. As shown in Figure 7, the semiconductor package structure 700, according to some embodiments, has a third redistribution layer 126 arranged between the interposer 302 and the second semiconductor die 120. The third redistribution layer 126 may resemble the first redistribution layer 102 or the second redistribution layer 124 and is not repeated. The second semiconductor die 120 may be electrically connected to the trench capacitor 600 via the third redistribution layer 126.

[0058] Fig. Figure 8 is a cross-sectional view of a semiconductor package structure 800 according to unclaimed embodiments. It should be noted that the semiconductor package structure 800 has the same or similar components as those in Figure 8. Fig. The semiconductor package structure shown in Figure 1 can have 100 components, and for the sake of simplicity, these components will not be described again in detail. In the following embodiments, one or more vias are arranged between the lower semiconductor die and the rear-side redistribution layer.

[0059] As in Fig. As shown in Figure 8, the semiconductor package structure 800, according to some embodiments, has one or more vias 130 arranged directly above the first semiconductor die 108. The vias 130 can electrically connect the first semiconductor die 108 to the second redistribution layer 124 and improve the data exchange of the first semiconductor die 108. The vias 130 can be made of conductive material, for example, copper, aluminum, tungsten, the like, an alloy thereof, or a combination thereof.

[0060] The size of the first semiconductor die 108 can be smaller, larger, or substantially the same as the size of the second semiconductor die 120. The second semiconductor die 120 can be arranged over a first section of the first semiconductor die 108, and the vias 130 can be arranged over a second section of the first semiconductor die 108. In particular, the first semiconductor die 108 and the second semiconductor die 120 can partially overlap (i.e., be offset relative to each other), thus avoiding thermal coupling.

[0061] In some embodiments, the vias 130 have a width greater than the width of the vias 110 in the first semiconductor die 108. The width of the vias 130 can be greater, less, or substantially equal to the width of the vias 116. The width of the vias 130 can be measured in a direction substantially parallel to the top surface of the first redistribution layer 102. In some embodiments, the width of the vias 130 can be from 40 µm to 80 µm.

[0062] The vias 110 in the first semiconductor die 108 can be located directly beneath the second semiconductor die 120. In some embodiments, the vias 110 can be located in the first section of the first semiconductor die 108 and need not be located in the second section of the first semiconductor die 108, as shown in Fig. Figure 8 shows that in some further embodiments, the vias 110 can be arranged in both the first and second sections of the first semiconductor die 108. That is, the vias 110 can be arranged directly beneath both the second semiconductor die 120 and the vias 130.

[0063] As in Fig. As shown in Figure 8, the semiconductor package structure 800, according to some embodiments, has a molding material 118 arranged between the first redistribution layer 102 and the second redistribution layer 124. The molding material 118 can be made of a non-conductive material such as a moldable polymer, an epoxy, a resin, or the like, or a combination thereof. The molding material 118 can surround the first semiconductor die 108, the vias 116, the second semiconductor die 120, and the vias 130 to prevent these components from being damaged, for example, by stress, chemicals, and / or moisture.

[0064] Fig. Figure 9 is a cross-sectional view of a semiconductor package structure 900 according to some embodiments of the invention. It should be noted that the semiconductor package structure 900 has the same or similar components as those described in Figure 9. Fig. Figure 8 shows a semiconductor package structure 800, and for the sake of simplicity, these components will not be described again in detail. In the following embodiments, a redistribution layer connects semiconductor dies and vias.

[0065] As in Fig. As shown in Figure 9, the semiconductor package structure 900, according to some embodiments, has a third redistribution layer 126, which is arranged between the second semiconductor die 120 and the vias 116 and between the first semiconductor die 108 and the vias 130. The third redistribution layer 126 may resemble the first redistribution layer 102 or the second redistribution layer 124 and is not repeated.

[0066] As in Fig. As shown in Figure 9, the semiconductor package structure 900, according to some embodiments, has a molded material 118 arranged between the first redistribution layer 102 and the second redistribution layer 124. The third redistribution layer 126 can divide the molded material 118 into two sections. One section of the molded material 118 can surround the first semiconductor die 108 and the vias 116, and another section of the molded material 118 can surround the second semiconductor die 120 and the vias 130.

[0067] Fig. Figure 10 is a cross-sectional view of a semiconductor package structure 1000 according to unclaimed embodiments. It should be noted that the semiconductor package structure 1000 has the same or similar components as those in Figure 10. Fig. The semiconductor package structure shown in Figure 1 can have 100 components, and for the sake of simplicity, these components will not be described again in detail. In the following embodiments, one or more vias are arranged between the vias and the rear-side redistribution layer.

[0068] As in Fig. As shown in Figure 10, the semiconductor package structure 1000, according to some embodiments, has one or more vias 130 arranged directly above the vias 116. The vias 130 can electrically connect the vias 116 to the second redistribution layer 124 and improve the data exchange of the first semiconductor die 108.

[0069] In some embodiments, the vias 130 have a width greater than the width of the vias 110 in the first semiconductor die 108. The width of the vias 130 can be greater, less, or substantially equal to the width of the vias 116. The width of the vias 130 can be measured in a direction substantially parallel to the top surface of the first redistribution layer 102. In some embodiments, the width of the vias 130 can be from 40 µm to 80 µm.

[0070] As in Fig. As shown in Figure 10, the semiconductor package structure 1000, according to some embodiments, has a molding material 118 arranged between the first redistribution layer 102 and the second redistribution layer 124. The molding material 118 can be made of a non-conductive material such as a moldable polymer, an epoxy, a resin, or the like, or a combination thereof. The molding material 118 can surround the first semiconductor die 108, the vias 116, the second semiconductor die 120, and the vias 130 to prevent these components from being damaged, for example, by stresses, chemicals, and / or moisture.

[0071] Fig. Figure 11 is a cross-sectional view of a semiconductor package structure 1100 according to some unclaimed examples. It should be noted that the semiconductor package structure 1100 has the same or similar components as those in Fig. Figure 10 shows a semiconductor package structure that can have 1000 components, and for the sake of simplicity, these components are not described again in detail. In the following embodiments, a redistribution layer connects semiconductor dies and vias.

[0072] As in Fig. As shown in Figure 11, the semiconductor package structure 1100, according to some embodiments, has a third redistribution layer 126, which is arranged between the first semiconductor die 108 and the second semiconductor die 120 and between the vias 116 and 130. The third redistribution layer 126 may resemble the first redistribution layer 102 or the second redistribution layer 124 and is not repeated.

[0073] As in Fig.As shown in Figure 11, the semiconductor package structure 1100, according to some embodiments, has a mold material 118 arranged between the first redistribution layer 102 and the second redistribution layer 124. The third redistribution layer 126 can divide the mold material 118 into two sections. One section of the mold material 118 can surround the first semiconductor die 108, the third semiconductor die 202 (if present), and the vias 116, and another section of the mold material 118 can surround the second semiconductor die 120 and the vias 130.

[0074] In summary, a semiconductor package structure features semiconductor die subdivisions (for example, multiple vertically stacked semiconductor dies) instead of one large semiconductor die. This reduces manufacturing costs and effort, and improves yield and performance. Furthermore, thermal behavior can be improved by avoiding thermal coupling.

[0075] In some embodiments, the semiconductor package structure includes a deep-trench capacitor located between an upper semiconductor die and a front-side redistribution layer. Compared to a capacitor located beneath the front-side redistribution layer, the deep-trench capacitor is positioned closer to the upper semiconductor die, thus further improving the electrical properties. Additional bump structures can also be arranged beneath the front-side redistribution layer for electrical interconnection.

Claims

[1] Semiconductor package structure (500; 700), comprising: a first redistribution layer (102); a first semiconductor die (108) disposed over the first redistribution layer (102) and having a first via (110) with a first width; a second via (116) adjacent to the first semiconductor die (108) and having a second width greater than the first width; a molding material (118) surrounding the first semiconductor die (108) and the second via (116); a second semiconductor die (120) disposed over the mold material (118) and electrically connected to the first via (110) and the second via (116); a second redistribution layer (124) disposed over the second semiconductor die (120); and an interposer (302) arranged between the first redistribution layer (102) and the second semiconductor die (120) and has a deep trench capacitor (600). [2] The semiconductor package structure of claim 1, wherein the first width is 2 µm to 18 µm, and wherein the second width is 40 µm to 80 µm. [3] The semiconductor package structure (500) of claim 1, further comprising a bump structure (112) connecting the first semiconductor die (108) and the second semiconductor die (120), the semiconductor package structure preferably further comprising a third semiconductor die (202) surrounded by the mold material (118), the third semiconductor die (202) having a third via (130) having a third width that is smaller than the second width. [4] The semiconductor package structure (700) of claim 1 or 2, further comprising a third redistribution layer (126) disposed between the first semiconductor die (108) and the second semiconductor die (120) and electrically connecting the second semiconductor die (120) to the first via (110) and the second via (116), the semiconductor package structure preferably further comprising a third semiconductor die (202) surrounded by the mold material (118), the third semiconductor die (202) having a third via (130) having a third width that is smaller than the second width. [5] The semiconductor package structure (500; 700) of claim 1 or 2, wherein the interposer (302) comprises the second via (116) and / or wherein the semiconductor package structure further comprises a third redistribution layer (126) disposed between the interposer (302) and the second semiconductor die (120) and electrically connecting the second semiconductor die (120) to the deep trench capacitor (600). [6] The semiconductor package structure of claim 1 or 2, further comprising a third via (130) disposed directly above the second via (116) and having a third width greater than the first width, the semiconductor package structure preferably further comprising a third redistribution layer (126) disposed between the first semiconductor die (108) and the second semiconductor die (120) and electrically connected to the second semiconductor die (120), the first via (110), the second via (116) and the third via (130). [7] The semiconductor package structure of claim 1 or 2, further comprising a third via (130) disposed directly above the first semiconductor die (108) and having a third width greater than the first width, wherein the semiconductor package structure preferably further comprises a third redistribution layer (126) disposed between the second semiconductor die (120) and the second via (116) and between the first semiconductor die (108) and the third via (130). [8] Semiconductor package structure (900; 1100), comprising: a first redistribution layer (102); a first semiconductor die (108) disposed over the first redistribution layer (102) and having a first via (110); a second via (116) adjacent to the first semiconductor die (108); a second semiconductor die (120) disposed over a first portion of the first semiconductor die (108) and electrically connected to the first via (110) and the second via (116); a third via (130) disposed over a second portion of the first semiconductor die (108); a second redistribution layer (124) disposed over the second semiconductor die (120) and electrically connected to the third via (130); and a third redistribution layer (126) disposed between the first semiconductor die (108) and the second semiconductor die (120); a first molding material (118) surrounding the first semiconductor die (108) and the second via (116); and a second molding material (118) surrounding the second semiconductor die (120) and the third via (130). [9] The semiconductor package structure of claim 8, wherein the first via (110) is arranged in the first portion of the first semiconductor die (108), and / or wherein the semiconductor package structure preferably further comprises a molding material (118) surrounding the first semiconductor die (108), the second semiconductor die (120), the second via (116) and the third via (130). [10] The semiconductor package structure of claim 8 or 9, wherein the third via (130) electrically connects the third redistribution layer (126) to the second redistribution layer (124).

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