CONDUCTIVE ELEMENTS WITH UNLOCKED LIMIT AREA FOR DIE PLACEMENT IN FLIP-CHIP PACKAGES, SEMICONDUCER PACKAGES AND METHOD FOR MAKING A SEMICONDUCER PACKAGE

Abstract

Semiconductor package, which includes the following: a semiconductor die (500) with a device side; a conductive layer (503) that is coupled to the device side; a conductive column (508) coupled to the conductive layer (303, 503), wherein the conductive column (508) has an upper part (508b) and a base part (508a), the base part (508a) having a wider diameter than the upper part (508b); a polyimide layer (510) coupled to the conductive layer (503) and surrounding the conductive column (508); a solder layer (512) coupled to the conductive column (508), wherein the polyimide layer (510) does not extend between an upper surface (511) of the conductive column (508) and the solder layer (512); and a conductive connection (513) coupled to the solder layer (512) and exposed on a surface of the semiconductor housing, wherein the device side of the semiconductor die (500) faces the conductive connection (513).

Description

BACKGROUND

[0001] Flip-chip encapsulation is a method for connecting semiconductor devices, such as integrated circuit (IC) dies and microelectromechanical systems (MEMS), to an external circuit assembly using solder pads deposited on die pads. The solder pads are deposited on the top side of a semiconductor wafer during wafer processing. To mount the chip to an external circuit assembly, such as a printed circuit board or another chip, the wafer is flipped so that its top side is facing down. The flipped wafer is then oriented so that conductive pads on the wafer align with matching pads on the external circuit or a printed circuit board. Solder on the contact pads is remelted to complete the connection between the devices.The contact mounds are conductive elements that electrically and mechanically couple device areas of the dies through metal redistribution layers, polyimide layers, passivation layers, die pads, etc. US 2021 / 0 134 750 A1 discloses a semiconductor package comprising a semiconductor chip with an active surface, a conductive layer bonded to the active surface, and a polyimide layer bonded to the conductive layer. DE 10 2016 118 385 A1 further discloses an interconnect structure, an LED module, and a method. In addition, US 2019 / 0 019 772 A1 discloses a method for forming semiconductor structures. SUMMARY

[0002] The invention is defined by the features of the independent claims. Embodiments thereof are found in the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Having thus described the invention in general terms, reference is now made to the accompanying drawings, whereby the following applies: Fig. Figure 1 is a cross-sectional view of a state-of-the-art flip chip with an example solder joint. Fig. Figure 2 is a flowchart of a method for forming column contact hillocks with an unobstructed perpendicular interface area according to a non-essential embodiment. Fig. Figures 3A-H are a series of non-essential cross-sectional views illustrating the steps in the formation of column contact mounds with an inclined upper surface using the process from Fig. 2 illustrate. Fig. Figure 4 is a flowchart of a method for forming column contact hillocks with an unobstructed perpendicular interface area according to an embodiment. Fig. 5A-H are a series of cross-sectional views showing the steps involved in forming column contact mounds with a foot section using the process from Fig. 4 illustrate. DETAILED DESCRIPTION

[0004] The present revelation is described with reference to the attached figures. The figures are not drawn to scale and are provided solely for illustrative purposes. Some aspects of the revelation are described below with reference to exemplary applications. It is understood that numerous specific details, relationships, and procedures are presented to provide an understanding of the revelation. The present revelation is not limited by the illustrated sequence of actions or events, since some actions may occur in different sequences and / or concurrently with other actions or events. Furthermore, not all illustrated actions or events are necessary to implement a methodology according to the present revelation.

[0005] In the drawings, identical reference numerals consistently refer to the same elements, and the various features are not necessarily drawn to scale. Corresponding numbers and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. In the following discussion and in the claims, the terms "including," "includes," "featuring," "shows," "with," or variations thereof are intended to be inclusive in a manner similar to the term "comprising" and should accordingly be interpreted as "including, but not limited to"... Furthermore, the terms "coupled," "couple," or "couples" are intended to include an indirect or direct electrical or mechanical connection or combinations thereof.For example, if a first device is electrically coupled to or connected with a second device, this connection may be made by a direct electrical connection or by an indirect electrical connection via one or more intervening devices and / or connections. Terms such as "above," "below," "front," "back," "over," "above," "below," "below," and the like may be used in this disclosure. These terms should not be interpreted as limiting the position or orientation of a structure or element, but should be used to provide a spatial relationship between structures or elements.

[0006] In flip-chip encapsulation, products use a solder alloy to bond metallic pillars or posts, formed on a semiconductor die, to a conductor frame. Typically, the posts are copper (Cu), and the conductor frame is copper. In one example, manufacturing costs can be reduced by eliminating a typical sputtering and etching process step and by applying a passivation layer, such as a polyimide (PI) layer, after the posts are created. Although solder bonding provides a good connection between the copper posts and a copper conductor frame, there are potential problems with the quality and reliability of solder joints if a passivation layer is applied after the posts are created and not removed before solder is applied to the posts. For example, the PI layer may overlap with the top of the post if a typical post design is used.This PI overlap can reduce the interface surface area between the solder and the post by, for example, covering an outer edge of the post's top surface, thus leaving a smaller area on the post's top surface exposed for bonding to the solder. As used here, the term interface area refers to an exposed area on one feature designed for bonding to another. By reducing the interface surface area, the bond between the solder and the post may be subject to higher stress due to its smaller connection, which is detrimental to the enclosure's lifetime and may reduce the enclosure's electronic performance.

[0007] An exemplary process for producing a flip-chip device is disclosed here. The process eliminates PI overlap by modifying the post structure on the semiconductor wafer. In one configuration, a mushroom-shaped post is created by applying a photoresist thickness less than the target post height. As used here, the term mushroom-shaped refers to a structure with a columnar base and a wider circular top, such as an umbrella-shaped cap. In another configuration, a foot is created on the post by modifying photoresist process parameters. The foot represents a broad base portion of the post. In one example, the foot has inclined sides that ramp down from the post to a contact layer.These configurations create structures that prevent the PI layer from overlapping with the post, which then prevents a reduction of an interface surface area between the post and the plumb line.

[0008] Fig. Figure 1 is a cross-sectional view of a prior art flip chip 100 with an exemplary solder joint. A metal layer can be deposited and then patterned at each contact area of ​​a semiconductor die 101 to form a metallized contact area 102. The area 102 is referred to as a copper-over-anything (COA) layer. A metallic post 103 is formed in contact with the metallized contact area 102. The post 103 has an upper surface 103a, which serves as the area for the post 103 to bond to the solder ball 105. The solder ball 105 can be placed on either the post 103 or on a conductor frame 106 and then heated to form a solder bond between the interface area 104 of the post 103 and the conductor frame 106 using, for example, a thermosonic or remelting process.

[0009] Before the solder ball 105 is applied to the post 103, a PI passivation layer 107 is applied over the semiconductor die 101 and the contact area 102. The PI layer 107 also surrounds the post 103, and using existing designs, a portion 107a of the PI layer 103 typically overlaps at least a portion of the top surface 103a on the post 103. As a result, the interface area 104 between the post 103 and the solder ball 105 is smaller than the total top surface 103a of the post 103. The solder ball 105 forms a layer between the post 103 and the conductor frame 106. Because the interface area 104 is narrower than the available post surface 103a, the current carrying capacity through the post 103 to or from a circuit arrangement on the die 101 may be limited.Because the post-plumb interface is narrower than otherwise possible, there may also be a tendency for cracks to form between the ladder frame 106 and the post 103 due to, for example, thermal cycling.

[0010] Fig. Figure 2 is a flowchart illustrating the main steps of a method 200 for forming column contact hillocks with an unblocked solder interface area according to an exemplary semiconductor package not essential to the invention. Fig. Figures 3A-H are a series of non-essential cross-sectional views illustrating the steps in the formation of the column contact mounds using the process from Fig. 2 illustrate.

[0011] Steps 201 and 202 are in Fig. Figure 3A illustrates a small portion of a semiconductor die 300. It is understood that the semiconductor die 300 can extend to the left and right, thus incorporating various circuit arrangements and multiple contact regions. The semiconductor die 300 comprises a semiconductor wafer 301, such as a silicon wafer. A contact region 302 has been formed on one device side of the semiconductor wafer 301. A COA layer 303 has been deposited to form a metallic feature that is in contact with the contact region 302. The contact region 302 can be a nucleation layer for contact with the COA layer 303. The COA layer 303 can be deposited, for example, by sputtering. A photoresist layer 304 is deposited over the COA layer 303. The photoresist 304 can be a positive or negative photoresist.

[0012] Method 200 further includes exposing and developing the photoresist layer to create a recess 305. In an example, as in Fig. As illustrated in Figure 3B, the recess 305 can be inclined or funnel-shaped. In other examples, the recess 305 can have relatively straight vertical sides. How Fig. Figure 3B shows that the photoresist layer 304 was structured, exposed, and developed to define the recess 305. An upper region 305a of the recess 305 can be wider near the upper surface 306 of the photoresist layer 304 than a lower region 305b of the recess 305 near the COA layer 303.

[0013] Method 200 further comprises plating a conductive column in the developed area of ​​the photoresist layer 204. For example, as in Fig. Figure 3C shows a conductive pillar 307 formed in the recess 305 using a plating technique, such as electroplating or electroless plating. As used here, the term "conductive pillar" refers to a conductor track or via that provides an electrical connection between a semiconductor wafer or integrated circuit die and other components. The conductive pillar may also be referred to as a post or contact mound and may be formed by copper, solder, or some other interconnect structure. No restriction to any particular structure of the conductive pillar is intended or should be implied. The plating operation fills the opening 305 in the photoresist 304 with a material to form a pillar 307.The conductive column 307 has a base part 308 formed in the recess 305 and an upper part 309 formed above the upper surface 306 of the photoresist 304. The upper part 309 can be formed by overplating, resulting in the column 307 having a mushroom shape. As used here, the term "mushroom shape" refers to a generally vertical structure with a distinct upper and lower part, such that the radius of the upper part is larger than the radius of the lower part. In some examples, the sidewalls of the upper and lower parts may be inclined or curved, in which case average, median, or maximum radii of the upper and lower parts can be compared to identify that the upper part is larger than the lower part.In some examples, the upper and lower parts of the structure are formed from a single material and / or during the same process. A rim or lip 309a of the upper part 309 overlaps the photoresist 304 and extends away from the base part 308. The relative radius of the base part 308 to the radius of the upper part 309, and therefore the length of the lip 309a, depends on the amount of over-cladding performed and can vary as a design choice. In one example, the upper surface 310 of the column 307 has a curved or domed shape as a result of the over-cladding. The length of the lip 309a and the curvature of the upper surface can be chosen as a design choice based on the materials used to form the conductive column 307, the photoresist layer 304 and the PI layer 311, in order to minimize the amount of the PI layer 311 covering the upper surface 310.

[0014] Method 200 further comprises removing the photoresist layer 205 to expose a mushroom-shaped conductive column with a dome-shaped upper surface. As described in Fig. As shown in 3D, the photoresist layer 304 was removed to leave the conductive column 307 attached to the COA layer 303. In one example, a wet cleaning process is used to remove and etch the photoresist layer 304. Method 200 further includes the application of a PI layer 206. As shown in Fig. As shown in Figure 3E, the PI layer 311 was deposited onto the semiconductor wafer 301 and the COA layer 303. The PI layer 311 is deposited and structured over the entire device such that the PI layer is removed from the top surface 310 of the conductive column 307. The PI layer 311 surrounds the base portion 308 of the column 307 and may include a region 311a of PI built up around the column 307. The dome shape of the top surface 310 on the column 307 causes the PI layer 311 to flow off the column 307. As a result, a larger surface area on the top surface 310 is exposed than on existing column designs.

[0015] Method 200 involves placing (e.g., dropping) a conductive element onto the conductive column 207. For example, in Fig. 3F positions a conductive element 312 (e.g., solder) on the upper surface 310 of the conductive column 307. In some configurations, a flux adhesion material may be applied to the upper surface 310 before the conductive element 312 is placed on the column 307. In some cases, the conductive element 312 is a solder ball placed using a stencil-and-brush technique or a cyclone technique. In some examples, the conductive element 312 is a spherical conductive material. In some examples, the conductive element 312 is a shape other than a sphere, e.g., a rectangular prism, another type of prism, or any other suitable shape. The conductive element 312 in these cases may be suitably dimensioned. The method 200 further includes remelting the conductive element 208. Fig. 3G represents the remelted conductive element 312. The domed upper surface 310 reduces the tendency for the PI layer 311 to remain on the surface of the column 307. Compared to existing designs, this increases the interface area between the column 307 and the remelted conductive element 312, thereby increasing the wettable surface area of ​​the conductive element 312 during remelting.

[0016] Process 200 then includes singulating the wafer (e.g., using a sawing technique) to produce a die 209, which contains the in Fig. The 3G depicted structures are included. Method 200 further includes flipping and attaching the structure from Fig. 3G on a conductive connection 210. Fig. 3H displays the structure Fig. 3G is shown, which is turned upside down and attached to a conductive terminal 313, which may be part of a conductor frame. The attachment can be achieved, for example, by remelting the conductive element to form a conductive layer 312, such as a solder layer. The method 200 also includes applying a potting compound 211, such as an epoxy or other encapsulating agent. As in Fig. As shown in 3H, the potting compound 314 covers the conductive terminal 313, the semiconductor wafer 301, the conductive column 307, the conductive element 312 and the other structures.

[0017] Fig. Figure 4 is a flowchart illustrating the main steps of an alternative method 400 for forming column contact hillocks with an unblocked solder interface area according to one embodiment. Fig. 5A-H are a series of cross-sectional views showing the steps in the formation of column contact mounds using the process from Fig. 4 illustrate.

[0018] Steps 401 and 402 are in Fig. Figure 5A illustrates a small portion of a semiconductor die 500. It is understood that the die 500 can extend to the left and right, thus incorporating various circuit arrangements and multiple contact areas. The semiconductor die 500 comprises a semiconductor wafer 501, such as a silicon wafer. A contact area 502 has been formed on one device side of the semiconductor wafer 501. A COA layer 503 has been deposited to form a metallic feature that is in contact with the contact area 502. For example, the contact area 502 can be a nucleation layer for contact with the COA layer 503. The COA layer 503 can be deposited, for example, by sputtering. A photoresist layer 504 is deposited over the COA layer 503. The photoresist 504 can be a positive or negative photoresist.

[0019] Method 400 further includes exposing and developing the photoresist layer to create an aperture 505. How Fig. As shown in Figure 5B, the photoresist layer 504 was structured, exposed, and developed to define the aperture 505. A lower region, or foot region, 505a of the aperture 505 is formed above the COA layer 503. The foot region 505a is wider than an upper region 505b of the aperture 505. The foot region 505a has inclined sidewalls 506 that extend from the COA layer 503 to sidewalls 507 of the upper region 505b. In some examples, the sidewalls 506 of the foot region 505a extend for less than half the height of the aperture 505, so that the foot region 505a is shorter than the upper region 505b. The sidewalls 507 of the upper region 505b may be inclined outwards, as shown in Figure 5B. Fig. 5B is shown. In other examples, the side walls 507 of the upper region may have a generally vertical orientation. The relative width of the base region 505a to the upper region 505b may vary as a design choice.

[0020] Method 400 further comprises plating a conductive column in the developed area of ​​the photoresist layer 404. For example, as in Fig. Figure 5C shows a conductive column 508 formed in the aperture 505 using a plating technique, such as electroplating or electroless plating. The plating operation fills the apertures 505 in the photoresist 504 with a material to form a column 508. In some examples, the conductive column 508 is produced using copper. The conductive column 508 has a base 508a, which is formed in the base region 505a of the aperture 505, and an upper 508b, which is formed in the upper region 505b of the aperture 505. The base 508a and the upper 508b take the shape of the base region 505a and the upper region 505b, respectively. The foot area 508a has a sloping surface 509 extending from the upper area 505b towards the COA layer 503.

[0021] Method 400 further comprises removing the photoresist layer 405 to expose a conductive column with a wide base. As in Fig. As shown in Figure 5D, the photoresist layer 504 was removed to leave the conductive column 508 attached to the COA layer 503. In one example, a wet cleaning process is used to remove and etch the photoresist layer 504. Method 400 further includes the application of a PI layer 406. As shown in Fig. As shown in Figure 5E, the PI layer 510 was deposited onto the semiconductor wafer 501 and the COA layer 503. The PI layer 510 is deposited and patterned across the entire device, such that the PI layer is removed from the top surface 511 of the conductive column 508. During the deposition of the PI layer 510, the inclined surface 509 of the base 508a prevents the PI layer 510 from flowing over the top surface 511 of the conductive column 508. As a result, a larger surface area on the top surface 511 is exposed than on existing column designs.

[0022] Method 400 involves placing (e.g., dropping) a conductive element onto the conductive column 407. For example, in Fig. In Method 400, a conductive element 512 (e.g., solder) is positioned on the upper surface 511 of the conductive column 508. In some configurations, a flux adhesion material may be applied to the upper surface 511 before the conductive element 512 is placed on the column 508. In some cases, the conductive element 512 is a solder ball, which is placed using a stencil-and-brush technique or a cyclone technique. In some examples, the conductive element 512 is a spherical conductive material. In some examples, the conductive element 512 is a shape other than a sphere, e.g., a rectangular prism, another type of prism, or any other suitable shape. The conductive element 512 in these cases may be suitably dimensioned. Method 400 further includes remelting the conductive element 408. Fig. 5G represents the remelted conductive element 512. The base 508a creates a lower tendency for the PI layer 510 to cover the surface 511 of the column 508, thus increasing the interface area between the column 508 and the remelted conductive element 512 and increasing the wettable surface area of ​​the conductive element 512 during remelting.

[0023] The process 400 then includes singulating the wafer (e.g., using a sawing technique) to produce a die 409, which contains the in Fig. The 5G depicted structures are included. Procedure 400 further includes flipping and attaching the structure made of Fig. 5G on a conductive connection 410. For example, Fig. 5H the structure made of Fig. 5G, which is turned upside down and attached (e.g., by remelting the conductive element to form a conductive layer 512, such as a solder layer) to a conductive terminal 513, which may be part of a conductor frame. Method 400 also includes applying a potting compound, such as an epoxy or other encapsulating agent, 411. As in Fig. As shown in Figure 5H, the potting compound 514 covers the conductive terminal 503, the semiconductor wafer 501, the conductive column 508, the conductive element (solder) 512 and the other structures.

[0024] An exemplary semiconductor package includes a semiconductor die with a fixture side featuring a conductive layer coupled to the fixture side. A conductive pillar is coupled to the conductive layer. The conductive pillar has a top portion and a base portion. The top portion has a wider diameter than the base portion, so that a lip on the underside of the top portion extends away from the base portion. A polyimide layer is coupled to the conductive layer and surrounds the conductive pillar. A solder layer is coupled to the conductive pillar. The polyimide layer does not extend between a top surface of the conductive pillar and the solder layer. A conductive termination, such as a wire frame, is coupled to the solder layer and is exposed to a surface of the semiconductor package. The fixture side of the semiconductor die faces the conductive termination.The conductive column can be copper. The conductive column can have a mushroom shape. The upper surface of the conductive column can have a convex or dome shape. The upper part of the conductive column extends further away from the device side of the semiconductor die than the polyimide layer.

[0025] Another example of a semiconductor package includes a semiconductor die with a fixture side. A conductive layer is coupled to the fixture side. A conductive pillar is coupled to the conductive layer. The conductive pillar has a top portion and a base portion. The base portion has a wider diameter than the top portion. A polyimide layer is coupled to the conductive layer and surrounds the conductive pillar. A solder layer is coupled to the conductive pillar. The polyimide layer does not extend between a top surface of the conductive pillar and the solder layer. A conductive termination, such as a wire frame, is coupled to the solder layer and is exposed to a surface of the semiconductor package. The fixture side of the semiconductor die faces the conductive termination. The conductive pillar can be copper.The base of the conductive column may have inclined sides extending from the upper part towards the conductive layer. The upper surface of the conductive column may have a convex or dome-shaped form. The upper surface of the conductive column extends further away from the device side of the semiconductor die than the polyimide layer.

[0026] An exemplary method for fabricating a semiconductor package comprises the following steps: providing a semiconductor wafer with a device side, forming a conductive layer above the device side, forming a conductive column above the conductive layer, wherein the conductive column has a base portion and an upper portion, one of which is wider than the other. The exemplary method further comprises forming a polyimide layer adjacent to and surrounding the conductive column, and positioning a conductive element on the conductive column, wherein the polyimide layer does not extend between an upper surface of the conductive column and the conductive element.The exemplary process further includes remelting the conductive element, singulating the semiconductor wafer to produce a die with the conductive layer, conductive column, polyimide layer, and remelted conductive element, coupling the remelted conductive element to a conductive terminal using a remelting technique, thereby producing a solder layer that couples the conductive column to the conductive terminal, and encapsulating the die, conductive column, solder layer, and conductive terminal in a potting compound, with the conductive terminal exposed on a surface of the potting compound. The conductive element can be copper. In one example, the upper part of the conductive column can have a wider diameter than the base part, giving the conductive column a mushroom shape.In another example, the base of the conductive column may have a wider diameter than the top, and inclined sides on the base may extend from the top to the conductive layer. The formation of the polyimide layer may involve preventing it from extending over the top surface of the conductive column due to the shape of the top. Alternatively, the formation of the polyimide layer may involve preventing it from extending over the top surface of the conductive column due to the shape of the bottom.

Claims

[1] Semiconductor package comprising the following: a semiconductor die (500) with a device side; a conductive layer (503) that is coupled to the device side; a conductive column (508) coupled to the conductive layer (303, 503), wherein the conductive column (508) has an upper part (508b) and a base part (508a), the base part (508a) having a wider diameter than the upper part (508b); a polyimide layer (510) coupled to the conductive layer (503) and surrounding the conductive column (508); a solder layer (512) coupled to the conductive column (508), wherein the polyimide layer (510) does not extend between an upper surface (511) of the conductive column (508) and the solder layer (512); and a conductive connection (513) coupled to the solder layer (512) and exposed on a surface of the semiconductor housing, wherein the device side of the semiconductor die (500) faces the conductive connection (513). [2] Semiconductor housing according to claim 1, wherein the conductive column (508) comprises copper. [3] Semiconductor housing according to claim 1, wherein the base part (508a) of the conductive column (508) has inclined sides (509) extending from the upper part (508b) to the conductive layer (503). [4] Semiconductor housing according to claim 1, wherein the upper surface (511) of the conductive column (508) has a convex shape. [5] Semiconductor housing according to claim 1, wherein the upper surface (511) of the conductive column (508) extends further away from the device side of the semiconductor die (500) than the polyimide layer (510). [6] Semiconductor housing according to claim 1, wherein the conductive connection (513) is part of a conductor frame. [7] Method (400) for manufacturing a semiconductor package comprising the following: Providing (401) a semiconductor wafer (501) with a device side; Forming a conductive layer (503) above the device side; Forming a conductive column (508) above the conductive layer (503), wherein the conductive column (508) has a base part (508a) and an upper part (508b), wherein the base part (508a) has a wider diameter than the upper part (508b); Forming (406) a polyimide layer (510) adjacent to the conductive layer (503) and surrounding the conductive column (508); Positioning (407) a conductive element (512) on the conductive column (508), wherein the polyimide layer (510) does not extend between an upper surface (511) of the conductive column (508) and the conductive element (512); Remelting (408) of the conductive element (512); singulating (409) the semiconductor wafer (501) to produce a die (500) with the conductive layer (503), the conductive column (508), the polyimide layer (510) and the remelted conductive element (512); Coupling (410) the remelted conductive element (512) with a conductive terminal (513) using a remelting technique, thereby producing a solder layer that couples the conductive column (508) to the conductive terminal (513); and Covering (411) the die (500), the conductive column (508), the solder layer (512) and the conductive connection (513) in a potting compound (514), wherein the conductive connection (513) is exposed on a surface of the potting compound (514). [8] Method according to claim 7, wherein the conductive element (512) comprises copper. [9] Method according to claim 7, wherein the base part (508a) of the conductive column (508) has inclined sides (509) extending from the upper part (508b) to the conductive layer (503). [10] Method according to claim 7, wherein forming the polyimide layer (510) comprises preventing the polyimide layer (510) from extending over the upper surface (511) of the conductive column (508) due to the shape of the upper part (508b) of the conductive column (508). [11] Method according to claim 7, wherein forming (406) the polyimide layer (510) comprises preventing the polyimide layer (510) from extending over the upper surface (511) of the conductive column (508) due to the shape of the lower part of the conductive column (508).

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