Semiconductor device and method for forming this

Abstract

Device comprising: a first semiconductor fin (54) extending from a substrate (50), a second semiconductor fin (54) extending from the substrate (50), a hybrid fin (66) above the substrate (50), the hybrid fin (66) being arranged between the first semiconductor fin (54) and the second semiconductor fin (54), the hybrid fin (66) having an internal oxide section (112A) extending downward from an upper surface of the hybrid fin (66), a first insulating region (68B) between the second semiconductor fin (54), the first semiconductor fin (54), and the hybrid fin (66), the hybrid fin (66) extending over an upper surface of the first insulating region (68B), a high-k gated dielectric (112B) over side walls of the hybrid fin (66), side walls of the first semiconductor fin (54), and side walls of the second semiconductor fin (54), a gate electrode (114) on the high-k gate dielectric (112B),and source / drain regions (98) on the first semiconductor fin (54) on opposite sides of the gate electrode (114), wherein the first semiconductor fin (54) has an interface oxide layer (112A) between side walls of the first semiconductor fin (54) and the high-k gate dielectric (112B), wherein the oxide inner section (112A) of the hybrid fin (66) is silicon-richer than the interface oxide layer (112A), wherein the oxide inner section (112A) of the hybrid fin (66) has a silicon-to-oxygen ratio in the range of 1:1 to 1:1.5, and the interface oxide layer (112A) on the first semiconductor fin (54) has a silicon-to-oxygen ratio in the range of 1:1.5 to 1:2.

Description

PRIORITY CLAIM AND CROSS-REFERENCE

[0001] This application claims priority over preliminary US application No. 63 / 268,871, which was filed on March 4, 2022, and is incorporated herein by reference. BACKGROUND

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers onto a semiconductor substrate, and by lithography to structure the various material layers and form circuit components and elements.

[0003] The semiconductor industry is constantly improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, thus enabling more components to be integrated into a given area. However, reducing the smallest feature sizes brings additional problems to light that must be addressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of this disclosure are best understood from the detailed description below, when read together with the accompanying figures. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 shows an example of field-effect transistors (FinFETs) according to some embodiments. Fig. 2 to Fig. Figure 19 shows views of intermediate stages in the fabrication of FinFETs according to some embodiments. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments, or examples, for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, forming a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements, so that the first and second elements may not be in direct contact. Furthermore, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition is done for the sake of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed.

[0006] Furthermore, terms relating to spatial relativity, such as "below," "under," "lower," "above," "upper," and the like, may be used herein to facilitate description and to describe the relationship of one element or feature to another element or feature (or other elements or features), as illustrated in the figures. The terms relating to spatial relativity are intended to encompass various orientations of the device used or operated in addition to the orientation illustrated in the figures. The device may be oriented in a different way (rotated by 90 degrees or otherwise), and the terms relating to spatial relativity used herein may be interpreted accordingly.

[0007] According to various embodiments, hybrid fins are formed adjacent to and between semiconductor fins. The hybrid fins have seams that are filled using a silicon precursor impregnation process and an oxidation process. These processes simultaneously form the interface layer(s) beneath the exchange gate structures, so no additional processing is required to fill the seams of the hybrid fins. Filling the seams of the hybrid fins prevents conductive material from subsequently formed source / drain and / or gate contacts from forming in the seams. Preventing conductive material from source / drain and / or gate contacts from forming in the seams prevents source / drains and gates from being short-circuited across the seams. The manufacturing yield of the devices can be improved in this way.

[0008] Fig. Figure 1 shows an example of field-effect transistors (FinFETs) according to some embodiments. Fig. Figure 1 is a three-dimensional view in which some elements of the FinFETs have been omitted for clarity. The FinFETs have semiconductor fins 54 extending from a substrate 50 (e.g., a semiconductor substrate), with the semiconductor fins 54 acting as channel regions 58 for the FinFETs. Insulation regions 68, such as STI (shallow trench insulation) regions, are arranged between adjacent semiconductor fins 54, which may extend over adjacent insulation regions 68 and protrude from the space between them. Although the insulation regions 68 are described / represented as being separate from the substrate 50, the term "substrate," as used here, can refer exclusively to the semiconductor substrate or to a combination of the semiconductor substrate and the insulation regions.Although the lower sections of the semiconductor fins 54 are depicted as being individual materials extending through the substrate 50, the lower sections of the semiconductor fins 54 and / or the substrate 50 may also comprise a single material or multiple materials. In this context, the semiconductor fins 54 refer to the section extending from the space between the adjacent isolation regions 68.

[0009] Gate dielectrics 112 are located along side walls and above the upper surfaces of the semiconductor fins 54. Gate electrodes 114 are located above the gate dielectrics 112. Epitaxial source / drain regions 98 are arranged on opposite sides of the semiconductor fins 54 with respect to the gate dielectrics 112 and the gate electrodes 114. The epitaxial source / drain regions 98 can be shared by different semiconductor fins 54. For example, adjacent epitaxial source / drain regions 98 can be electrically connected, such as by joining the epitaxial source / drain regions 98 through epitaxial growth, or by coupling the epitaxial source / drain regions 98 with the same source / drain contact.

[0010] Fig. Figure 1 further shows reference cross-sections that are used in later figures. Cross-section AA' extends along a longitudinal axis of a gate electrode 114. Cross-section BB' is perpendicular to cross-section AA' and runs along a longitudinal axis of a semiconductor fin 54 and, for example, in the direction of current flow between the epitaxial source / drain regions 98 of a FinFET. Cross-section CC' is parallel to cross-section AA' and extends through the epitaxial source / drain regions 98 of the FinFETs. For clarity, subsequent figures refer to these reference cross-sections.

[0011] Some embodiments discussed here are in the context of FinFETs designed using a gate-last process. In other embodiments, a gate-first process can be used. Furthermore, some embodiments consider aspects used in planar devices, such as planar FETs.

[0012] Fig. 2 to Fig. Figure 19 shows views of intermediate stages in the fabrication of FinFETs according to some embodiments. Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9A, Fig. 10A, Fig. 11A, Fig. 12A, Fig. 13A, Fig. 14A, Fig. 15A, Fig. 16A, Fig. 17A, Fig. 18A and Fig. Figure 19 shows cross-sectional views along a similar cross-section to the reference cross-section AA' in Fig. 1. Fig. 9B, Fig. 10B, Fig. 11B, Fig. 12B, Fig. 13B, Fig. 14B, Fig. 15B, Fig. 16B, Fig. 17B and Fig. 18B are cross-sectional views shown along a similar cross-section to the reference cross-section BB' in Fig. 1. Fig. 9C, Fig. 10C, Fig. 11C, Fig. 12C, Fig. 13C, Fig. 14C, Fig. 15C, Fig. 16C, Fig. 17C and Fig. 18C are cross-sectional views shown along a similar cross-section to the reference cross-section CC' in Fig. 1.

[0013] In Fig. 2. A substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, an SOI substrate (semiconductor on an insulator), or the like, which may be doped (e.g., with a p- or n-type impurity) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. In general, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide layer (BOX layer), a silicon oxide layer, or the like. The insulating layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multilayer or gradient substrate, may also be used.In some embodiments, the semiconductor material of substrate 50 may contain: silicon; germanium; a compound semiconductor comprising silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor comprising silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide, combinations thereof, or the like.

[0014] The substrate 50 has an n-region 50N and a p-region 50P. The n-region 50N can be used to form n-type devices, such as NMOS transistors, e.g., n-FinFETs, and the p-region 50P can be used to form p-type devices, such as PMOS transistors, e.g., p-FinFETs. The n-region 50N can be physically separated from the p-region 50P (not shown separately), and any number of device elements (e.g., other active devices, doped regions, isolation structures, etc.) can be placed between the n-region 50N and the p-region 50P. Although one n-area 50N and one p-area 50P are shown, any number of n-areas 50N and p-areas 50P can be provided.

[0015] In Fig. 3. Fin structures 52 are formed in the substrate 50. The fin structures 52 have semiconductor fins 54, which are semiconductor bridges. The fin structures 52 can be formed in the substrate 50 by etching grooves 56 in the substrate 50. The etching can be any suitable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. The etching process can be anisotropic.

[0016] The fin structures 52 can be structured using any suitable method. For example, the fin structures 52 can be structured using one or more photolithographic processes, including dual or multiple structuring processes. In general, dual or multiple structuring processes combine photolithographic and self-aligning processes, making it possible to create structures with, for example, smaller pitches than would otherwise be achievable using a single direct photolithographic process. For example, in one embodiment, a sacrificial layer is formed over a substrate and structured using a photolithographic process. Spacers are formed along the structured sacrificial layer using a self-aligning process.The sacrificial layer is then removed, and the remaining spacers can then be used as masks 60 for structuring the fin structures 52. In some embodiments, the masks 60 (or another layer) can remain on the fin structures 52.

[0017] In the illustrated embodiment, the fin structures 52 each have two semiconductor fins 54. However, the fin structures 52 can each have any number of semiconductor fins 54, such as one, two, three, or more semiconductor fins 54. Furthermore, different fin structures 52 can have different numbers of semiconductor fins 54. For example, fin structures 52 in a first region of a die (e.g., a core logic region) can have a first number of semiconductor fins 54, and semiconductor fins 52 in a second region of the die (e.g., an input / output region) can have a second number of semiconductor fins 54, the second number being different from the first.

[0018] The grooves 56 can have different widths. In some embodiments, a first subset of the grooves 56A has a smaller width than a second subset of the grooves 56B. The grooves 56A separate the semiconductor fins 54 of respective fin structures 52, and the grooves 56B separate the fin structures 52 from each other. The semiconductor fins 54 of respective fin structures 52 are spaced closer together than the fin structures 52 are spaced apart. In some embodiments, the semiconductor fins 54 of respective fin structures 52 are spaced apart by a distance D1 in the range of 5 nm to 100 nm, the fin structures 52 are spaced apart by a distance D2 in the range of 20 nm to 200 nm, and the distance D2 is greater than the distance D1.The grooves 56 can be formed with different widths by structuring the masks 60 with elements spaced apart by different distances corresponding to the different widths of the grooves 56. The widths of the grooves 56 define the width of the semiconductor fins 54 (also referred to as the critical dimension of the semiconductor fins 54). In some embodiments, the semiconductor fins 54 have a critical dimension in the range of 5 nm to 30 nm.

[0019] In some embodiments, the grooves 56 have different depths. For example, grooves 56A may have a shallower depth than grooves 56B. The grooves 56 can be formed as a result of structure-loading effects during etching of the grooves 56 to different depths, the structure-loading effects being caused by the fact that the structure of the masks 60 has elements spaced apart by different distances. The depths of the grooves 56 define the height of the semiconductor fins 54. In some embodiments, the semiconductor fins 54 have a height in the range of 10 nm to 100 nm.

[0020] In Fig. 4. One or more layers of an insulating material 62 are formed for insulating regions above the substrate 50 and between adjacent semiconductor fins 54. The insulating material 62 can contain an oxide, such as silicon oxide, a nitride, such as silicon nitride, the like, or a combination thereof, and can be formed by chemical vapor deposition (CVD), high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD), atomic layer deposition (ALD), the like, or a combination thereof. Other insulating materials formed by any suitable process can be used. In the illustrated embodiment, the insulating material 62 has a liner 62A on surfaces of the substrate 50 and the semiconductor fins 54 and a filler material 62B on the liner 62A.The liner 62A can be amorphous silicon, silicon oxide, silicon nitride, or the like, deposited by a conformal deposition process, such as ALD, and the filler material 62B can be silicon oxide grown by a conformal growth process, such as FCVD. In another embodiment, a single layer of the insulating material 62 is formed. An annealing process can be carried out after the insulating material has been formed. The annealing process can be carried out in a hydrogen- or oxygen-containing environment. The liner 62A can be oxidized by the annealing process so that, after annealing, the liner 62A is a material similar to the filler material 62B. In one embodiment, the insulating material 62 is formed such that excess insulating material 62 covers the semiconductor fins 54.

[0021] The thickness of the insulating material 62 is controlled such that the insulating material 62 does not fill the entirety of the trenches 56. In some embodiments, the insulating material 62 is deposited to a thickness T1 in the range of 5 nm to 30 nm. The distances D1, D2 (see Fig. 3) and the thickness T1 are controlled such that the insulating material 62 fills the trenches 56A without filling the trenches 56B. For example, the distributed volume of the insulating material 62 may be sufficient to completely fill (or overfill) the trenches 56A, but may be insufficient to completely fill the trenches 56B. Therefore, the insulating material 62 in the trenches 56B does not completely fill the trenches 56B, but instead conformally lines the surfaces of the substrate 50 and the sidewalls of the semiconductor fins 54 that define the trenches 56B.

[0022] In the illustrated embodiment, the side walls of the semiconductor fins 54 and the insulating material 62 are arranged such that they form right angles with the upper surfaces of the substrate 50 and the insulating material 62, respectively. In other embodiments, contouring can occur during the structuring of the semiconductor fins 54 and the deposition of the insulating material 62. Accordingly, rounded surfaces can connect the side walls of the semiconductor fins 54 with the upper surfaces of the substrate 50, and rounded surfaces can connect the side walls of the insulating material 62 with the upper surfaces of the insulating material 62.

[0023] In Fig. 5. One or more dielectric layers 64 are formed on the insulating material 62. The dielectric layer(s) 64 fill (and may overfill) the remaining sections of the trenches 56B that are not filled (e.g., not covered) by the insulating material 62. In some embodiments, the dielectric layer(s) 64 merge in the trenches 56B and form seams or cavities 64A in the trenches 56B. The seams 64A may have a width W1 in the range of 1 to 3 nm. The dielectric layer(s) 64 may be formed from one or more dielectric materials. Suitable dielectric materials include nitrides (e.g. silicon nitride), oxides (e.g. tantalum oxide, aluminum oxide, zirconium oxide, hafnium oxide, etc.), carbides (e.g. silicon carbonitride, silicon oxicarbonate, etc.), combinations thereof, or the like, which can be deposited using ALD, CVD, or the like.Other insulating materials formed by any suitable process may be used. Furthermore, the dielectric layer(s) 64 may be formed from a low-k dielectric material (e.g., a dielectric material having a k-value less than approximately 3.5), from a high-k dielectric material (e.g., a dielectric material having a k-value greater than approximately 7.0), or from multiple layers thereof. The dielectric layer(s) 64 is formed from a material exhibiting high etch selectivity with respect to the etching of the insulating material 62. In some embodiments, the dielectric layer(s) 64 contains silicon nitride formed by ALD.

[0024] In Fig. 6. A removal process is applied to the dielectric layer(s) 64 and the insulating material 62 to remove excess sections of the dielectric layer(s) 64 and the insulating material 62 above the semiconductor fins 54 (e.g., outside the grooves 56), thereby forming hybrid fins 66 having the seams or cavities 66A on the insulating material 62. In some embodiments, a planarization process, such as chemical-mechanical polishing (CMP), a back-etching process, combinations thereof, or the like, may be used. After the removal process, the dielectric layer(s) 64 has (have) sections left in the grooves 56B (forming the hybrid fins 66). After the planarization process, the upper surfaces of the hybrid fins 66, the insulating material 62 and the semiconductor fins 54 are coplanar (within process variations), so that they are at the same height.The hybrid fins 66 are arranged between and adjacent to the fin structures 52. In some embodiments, the seams 66A of the hybrid fins 66 have a depth D4 in the range of 60 m to 70 nm after the planarization process. The hybrid fins 66 can also be referred to below as “dielectric fins”.

[0025] In Fig. 7. The insulating material 62 is recessed to form STI regions 68. The insulating material 62 is recessed such that upper sections of the semiconductor fins 54 and the hybrid fins 66 protrude over adjacent STI regions 68 and from the space between them. Furthermore, the upper surfaces of the STI regions 68 can be flat, as shown, convex, concave (such as a bulge), or a combination thereof. The upper surfaces of the STI regions 68 can be formed flat, convex, and / or concave by means of a suitable etching process. The STI regions 68 can be recessed using a suitable etching process, such as one that is selective with respect to the insulating material(s) 62.As will be described in more detail below, the etching process selectively etches the insulating material(s) 62 at a faster rate than the materials of the semiconductor fins 54 and the hybrid fins 66. The semiconductor fins 54 and the hybrid fins 66 can therefore be protected from damage during the formation of the STI regions 68. Timed etching processes can be used to stop the etching of the insulating material 62 after the STI regions 68 have reached a desired height. In some embodiments, the STI regions 68 have a height in the range of 10 nm to 100 nm. The STI regions 68 contain the remaining sections of the insulating material 62 in the grooves 56.

[0026] As mentioned above, trenches 56B are deeper than trenches 56A. Consequently, the STI regions 68 have different heights. In particular, a first subset of STI regions 68A has a lower height than a second subset of STI regions 68B. STI regions 68A are located in trenches 56A and between and within the semiconductor fins 54 of respective fin structures 52 and can be referred to as "inner STI regions." STI regions 68B are located in trenches 56B and between adjacent fin structures 52 and around the hybrid fins 66 (e.g., between the semiconductor fins 54 and the hybrid fins 66) and can be referred to as "outer STI regions." Since the trenches 56B are deeper than the trenches 56A, the lower surfaces of the STI areas 68B are located further away from the upper surfaces of the semiconductor fins 54 and the hybrid fins 66 than the lower surfaces of the STI areas 68A.In some embodiments, the lower surfaces of the STI areas 68B are arranged further away from the upper surfaces of the semiconductor fins 54 and the hybrid fins 66 by the distance D3 (described above) than the lower surfaces of the STI areas 68A.

[0027] The formation of the STI regions 68 reshapes sections of the trenches 56A, 56B. The reshaped sections of trenches 56A are located between respective pairs of semiconductor fins 54, and the reshaped sections of trenches 56B are located between respective pairs of a semiconductor fin 54 and a hybrid fin 66. The distances D1, D2 (see Fig. 3) and the thickness T1 (see Fig. 4) are controlled such that the reshaped sections of the trenches 56A are wider than the reshaped sections of the trenches 56B. In some embodiments, the reshaped sections of the trenches 56A have a width W1 in the range of 10 nm to 30 nm, the reshaped sections of the trenches 56B have a width W2 in the range of 5 nm to 20 nm, and the width W1 is greater than the width W2.

[0028] The insulating material 62 can be recessed to varying degrees as a result of structure-loading effects during the recessing process. These structure-loading effects are caused by the fact that the reshaped sections of the trenches 56A and 56B have different widths. In some embodiments, the etching of the insulating material 62 is carried out with etching parameters (e.g., temperature, pressure, and duration) that exacerbate the structure-loading effects. As a result of these effects, the sections of insulating material 62 in the trenches 56A are recessed to a greater extent (e.g., to a greater depth) than the sections in the trenches 56B. Consequently, the upper surfaces of the STI areas 68B are positioned further away from the substrate 50 than the upper surfaces of the STI areas 68A. In other words, STI areas 68B extend over STI areas 68A with respect to substrate 50.In some embodiments, the upper surfaces of the STI areas 68B are arranged a distance D5 in the range of 2 nm to 10 nm further away from the substrate 50 than the upper surfaces of the STI areas 68A.

[0029] In some embodiments where the insulating material 62 contains silicon dioxide, the insulating material 62 is removed by a dry etching process using hydrofluoric acid (HF) and ammonia (NH3). Each STI region 68B extends along three sides (e.g., the side walls and the bottom surface) of a hybrid fin 66. In particular, a first section of an STI region 68B is located between a hybrid fin 66 and a first fin structure 52, a second section of the STI region 68B is located between the hybrid fin 66 and a second fin structure 52, and a third section of the STI region 68B is located below the hybrid fin 66.

[0030] The for Fig. 2 to Fig. The process described in Figure 7 is merely an example of how the semiconductor fins 54, the hybrid fins 66, and the STI regions 68 can be formed. In some embodiments, the semiconductor fins 54 and / or the hybrid fins 66 can be formed using a mask and an epitaxial growth process. For example, a dielectric layer can be formed over a top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures can be epitaxially grown in some of the trenches, insulating structures can be deposited in others of the trenches, and the dielectric layer can be (in a similar manner to that described for Fig. (described in section 7) are recessed so that the epitaxial structures protrude from the dielectric layer to form the semiconductor fins 54, and the insulating structures protrude from the dielectric layer to form the hybrid fins 66. In some embodiments where epitaxial structures are grown epitaxially, the epitaxially grown materials can be doped in situ during growth, which can avoid prior and / or subsequent implantations, although in situ and implantation doping can be used together.

[0031] Furthermore, it can be advantageous to epitaxially grow a material in the n-region 50N that differs from the material in the p-region 50P. In various embodiments, upper sections of the semiconductor fins 54 can be made of silicon germanium (Si₂). x Ge 1-x, where x can be in the range of 0 to 1), silicon carbide, pure or essentially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For example, the available materials for forming a III-V compound semiconductor include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, and the like.

[0032] Furthermore, suitable wells (not shown separately) can be formed in the semiconductor fins 54 and / or the substrate 50. The wells can have a conductivity type opposite to that of source / drain regions subsequently formed in each of the n-region 50N and the p-region 50P. In some embodiments, a p-well is formed in the n-region 50N, and an n-well is formed in the p-region 50P. In some embodiments, a p-well or an n-well is formed in both the n-region 50N and the p-region 50P.

[0033] In embodiments with different trough types, various implantation steps for the n-region 50N and the p-region 50P can be achieved using a mask (not shown separately), such as a photoresist. For example, a photoresist can be formed over the semiconductor fins 54, the hybrid fins 66, and the STI regions 68 in the n-region 50N. The photoresist is patterned to expose the p-region 50P. The photoresist can be formed using a rotational coating technique and can be patterned using suitable photolithographic techniques. After the photoresist has been patterned, n-impurity implantation is performed in the p-region 50P, and the photoresist can act as a mask to essentially prevent n-impurities from being implanted into the n-region 50N.The n-impermites can be phosphorus, arsenic, antimony, or the like, which enter the area at concentrations in the range of 10. 13 cm -3 up to 10 14 cm -3 The photoresist is implanted. After implantation, it is removed, for example using any suitable ashing process.

[0034] Before or after the implantation of the p-region 50P, a mask (not shown separately), such as a photoresist, is formed over the semiconductor fins 54, the hybrid fins 66, and the STI regions 68 in the p-region 50P. The photoresist is patterned to expose the n-region 50N. The photoresist can be formed using a rotational coating technique and can be patterned using suitable photolithographic techniques. After the photoresist has been patterned, p-impurity implantation can be performed in the n-region 50N, and the photoresist can act as a mask to essentially prevent p-impurities from being implanted into the p-region 50P. The p-impurities can be boron, boron fluoride, indium, or the like, which are introduced into the region up to a concentration in the range of 10 13 cm -3 up to 10 14 cm -3The photoresist is implanted. After implantation, it is removed, for example using any suitable ashing process.

[0035] Following the implantation of the n-region 50N and the p-region 50P, annealing can be performed to repair implantation damage and activate the implanted p- and / or n-impurities. In some embodiments where epitaxial structures are grown epitaxially for the semiconductor fins 54, the grown materials can be doped in situ during growth, which can avoid implantation, although in situ and implantation doping can be used together.

[0036] In Fig. In embodiment 8, a dummy dielectric layer 72 is formed on the semiconductor fins 54, the hybrid fins 66, and within the seams 66A of the hybrid fins 66. The dummy dielectric layer 72 can be formed from a dielectric material, such as silicon oxide, silicon nitride, a combination thereof, or the like, deposited or thermally grown by suitable techniques, such as ALD, in-situ vapor growth (ISSG), rapid thermal oxidation (RTO), or the like. The dummy dielectric layer 72 can fill or substantially fill the seams 66A of the hybrid fins 66. The dummy dielectric layer 72 can also have, or be described as, an interface layer or an interface oxide layer. In some embodiments, the dummy dielectric layer 72 has a thickness in the range of 1 nm to 10 nm.A dummy gate layer 74 is formed over the dummy dielectric layer 72, and a mask layer 76 is formed over the dummy gate layer 74. The dummy gate layer 74 can be deposited over the dummy dielectric layer 72 and then planarized, for example, using a CMP. The dummy gate layer 74 can be made of a conductive or non-conductive material, such as amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), a metal, a metal nitride, a metal silicide, a metal oxide, or the like, which can be deposited using physical vapor deposition (PVD), CVD, or the like. The dummy gate layer 74 can be formed from a material(s) that has a high etch selectivity towards the etching of insulating materials, e.g. the STI regions 68 and / or the dummy dielectric layer 72.The mask layer 76 can be deposited over the dummy gate layer 74. The mask layer 76 can be formed from a dielectric material, such as silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 74 and a single mask layer 76 are formed over the n-region 50N and the p-region 50P. In the illustrated embodiment, the dummy dielectric layer 72 covers the semiconductor fins 54, the hybrid fins 66, and the STI regions 68, such that the dummy dielectric layer 72 extends over the STI regions 68 and between the dummy gate layer 74 and the STI regions 68. In another embodiment, the dummy dielectric layer 72 covers only the semiconductor fins 54.

[0037] Fig. 9A to Fig. 18C shows various additional steps in the manufacture of devices of the embodiments. Fig. 9A to Fig. Figure 18C shows elements in either the n-region 50N or the p-region 50P. For example, the structures shown may be applicable to both the n-region 50N and the p-region 50P. Differences (if any) between the structures of the n-region 50N and the p-region 50P are explained in the description accompanying each figure.

[0038] In Fig. 9A to Fig. In 9C, the mask layer 76 is structured using suitable photolithographic and etching techniques to form masks 86. The structure of the masks 86 is then transferred to the dummy gate layer 74 using any suitable etching technique to form dummy gates 84. The structure of the masks 86 can optionally be further transferred to the dummy dielectric layer 72 using any suitable etching technique to form dummy dielectrics 82. The dummy gates 84 cover respective channel regions 58 of the semiconductor fins 54. The structure of the masks 86 can be used to physically separate adjacent dummy gates 84. The dummy gates 84 can have longitudinal directions that are substantially perpendicular (within process variations) to the longitudinal directions of the semiconductor fins 54. The masks 86 can be removed during the structuring of the dummy gate 84, or can be removed during subsequent processing.

[0039] Gatespacers 92 are formed over the semiconductor fins 54, on exposed sidewalls of the masks 86 (if present), the dummy gates 84, and the dummy dielectrics 82. The gatespacers 92 can be formed by conformal deposition of one or more dielectric materials and subsequent etching of the dielectric material(s). Suitable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, or the like, which can be formed by a conformal deposition process such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), or the like. Other insulating materials formed by any suitable process may be used.Any suitable etching process, such as dry etching, wet etching, the like, or a combination thereof, can be performed to structure the dielectric material(s). The etching can be anisotropic. The dielectric material(s), when etched, has sections that remain on the sidewalls of the dummy gates 84 (forming the gatespacers 92). In some embodiments, the etching used to form the gatespacers 82 is adjusted such that the dielectric material(s) also has sections that remain on the sidewalls of the semiconductor fins 54 (forming fin spacers 94). After etching, the fin spacers 94 (if present) and the gatespacers 92 can have flat sidewalls (as shown) or can have curved sidewalls (not shown separately).

[0040] The fin spacers 94 have inner fin spacers 94N (which are arranged between the semiconductor fins 54 of an identical fin structure 52, see Fig. 8) and outer fin spacers 94O (arranged between the semiconductor fins 54 and the hybrid fins 66). In the illustrated embodiments, the inner fin spacers 94N are separated after structuring, so that the STI regions 68A are exposed. In another embodiment, the inner fin spacers 94N are not completely separated, so that sections of the dielectric material(s) for the spacers remain over the STI regions 68A. Since the STI regions 68A have a smaller height than the STI regions 68B, the inner fin spacers 94N also have a greater height than the outer fin spacers 94O.

[0041] Furthermore, implantations can be performed to form lightly doped source / drain regions (LDD regions) (not shown separately). In embodiments with different device types, similar to the implantations described above for the wells, a mask (not shown separately), such as a photoresist, can be formed over the n-region 50N while the p-region 50P is exposed, and impurities of a suitable type (e.g., p-types) can be implanted into the semiconductor fins 54 exposed in the p-region 50P. The mask can then be removed. Subsequently, a mask (not shown separately), such as a photoresist, can be formed over the p-region 50P while the n-region 50N is exposed, and impurities of a suitable type (e.g., n-types) can be implanted into the semiconductor fins 54 exposed in the n-region 50N. The mask can then be removed.The n-impurities can be any of the n-impurities described above, and the p-impurities can be any of the p-impurities described above. During implantation, the channel regions 58 remain covered with the dummy gates 84, so that the channel regions 58 remain substantially free of the impurity implanted to form the LDD regions. The LDD regions can have a concentration of impurities in the range of 10. 15 cm -3 up to about 10 19 cm -3 exhibit. Tempering can be used to repair implant damage and to activate the implanted impurities.

[0042] It should be noted that the preceding disclosure generally describes a process for forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, a different sequence of steps may be used, additional spacers may be formed and removed, and / or the like. Furthermore, the n-devices and the p-devices may be formed using different structures and steps.

[0043] In Fig. 10A to Fig. In step 10C, source / drain recesses 96 are formed in the semiconductor fins 54. In the illustrated embodiment, the source / drain recesses 96 extend into the semiconductor fins 54. The source / drain recesses 96 can also extend into the substrate 50. In various embodiments, the source / drain recesses 96 can extend to an upper surface of the substrate 50 without etching the substrate 50; the semiconductor fins 54 can be etched such that lower surfaces of the source / drain recesses 96 are arranged below the upper surfaces of the STI regions 68; or the like. The source / drain recesses 96 can be formed by etching the semiconductor fins 54 using an anisotropic etching process, such as RIE, NBE, or the like. The etching process selectively etches the material(s) of the semiconductor fins 54 at a faster rate than the materials of the hybrid fins 66 and the STI areas 68.The gate spacers 92 and the dummy gates 84 together mask sections of the semiconductor fins 54 during the etching processes used to form the source / drain recesses 96. Timed etching processes can be used to stop the etching of the source / drain recesses 96 after they have reached a desired depth. The fin spacers 94 (if present) can be etched during or after the etching of the source / drain recesses 96, thus reducing their height. The size and dimensions of the source / drain regions subsequently formed in the source / drain recesses 96 can be controlled by adjusting the height of the fin spacers 94. The hybrid fins 66 are not recessed and remain between the fin structures 52, and the source / drain recesses 96 are etched.

[0044] In Fig. 11A to Fig. In 11C, epitaxial source / drain regions 98 are formed in the source / drain recesses 96. The epitaxial source / drain regions 98 are thus formed in the semiconductor fins 54 such that each dummy gate 84 (and corresponding channel region 58) is located between respective adjacent pairs of epitaxial source / drain regions 98. The epitaxial source / drain regions 98 are therefore adjacent to the channel regions 58. In some embodiments, gate spacers 92 are used to separate the epitaxial source / drain regions 98 from the dummy gates 84 by a suitable lateral distance, so that the epitaxial source / drain regions 98 do not short-circuit with subsequently formed gates of the resulting FinFETs. A material from the epitaxial source / drain areas 98 can be selected to exert tension in the respective channel areas 58, thereby improving performance.

[0045] The epitaxial source / drain regions 98 in the n-region 50N can be formed by masking the p-region 50P. Then, the epitaxial source / drain regions 98 in the n-region 50N are epitaxially grown in the source / drain recesses 96 in the n-region 50N. The epitaxial source / drain regions 98 can comprise any suitable material appropriate for n-type devices. For example, if the semiconductor fins 54 are silicon, the epitaxial source / drain regions 98 in the n-region 50N can comprise materials that exert a tensile stress on the channel regions 58, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like. The epitaxial source / drain areas 98 in the n-area 50N can be referred to as “n-source / drain areas”.The epitaxial source / drain regions 98 in the n-region 50N can have surfaces that are raised from the respective surfaces of the semiconductor fins 54 and can have rhombic surfaces.

[0046] The epitaxial source / drain regions 98 in the p-region 50P can be formed by masking the n-region 50N. The epitaxial source / drain regions 98 in the p-region 50P are then epitaxially grown in the source / drain recesses 96 in the p-region 50P. The epitaxial source / drain regions 98 can comprise any suitable material appropriate for p-type devices. For example, if the semiconductor fins 54 are silicon, the epitaxial source / drain regions 98 in the p-region 50P can comprise materials that exert a compressive stress on the channel regions 58, such as silicon germanium, boron-doped silicon germanium, germanium, germanium-tin, or the like. The epitaxial source / drain regions 98 in the p-region 50P can be referred to as “p-source / drain regions”.The epitaxial source / drain regions 98 in the p-region 50P can have surfaces that are raised from the respective surfaces of the semiconductor fins 54 and can have rhombic surfaces.

[0047] Impurities can be implanted into the epitaxial source / drain regions 98 and / or the semiconductor fins 54 to form source / drain regions, similar to the process described above for forming LDD regions, followed by annealing. The source / drain regions can contain an impurity concentration in the range of 10 19 cm- 3 up to 10 21 cm- 3 exhibit. The n- and p-impurities for source / drain regions can be any of the impurities described above. In some embodiments, the epitaxial source / drain regions 98 can be doped in situ during growth.

[0048] The epitaxial source / drain regions 98 can have one or more semiconductor material layers. For example, the epitaxial source / drain regions 98 can each have a liner layer 98A, a main layer 98B, and a termination layer 98C (or, more generally, a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer). Any number of semiconductor material layers can be used for the epitaxial source / drain regions 98. In embodiments in which the epitaxial source / drain regions 98 have three semiconductor material layers, the liner layers 98A can be grown in the source / drain recesses 96, the main layers 98B can be grown on the liner layers 98A, and the termination layers 98C can be grown on the main layers 98B.The liner layers 98A, the main layers 98B, and the termination layers 98C can be formed from different semiconductor materials and can be doped to different impurity concentrations. In some embodiments, the main layers 98B have a higher concentration of impurities than the termination layers 98C, and the termination layers 98C have a higher concentration of impurities than the liner layers 98A. Forming the liner layers 98A with a lower concentration of impurities than the main layers 98B can increase adhesion in the source / drain recesses 96, and forming the termination layers 98C with a lower concentration of impurities than the main layers 98B can reduce the diffusion of dopants from the main layers 98B during subsequent processing.

[0049] As a result of the epitaxial processes used to form the epitaxial source / drain regions 98, the upper surfaces of the epitaxial source / drain regions exhibit rhombic surfaces that extend laterally outwards beyond the sidewalls of the semiconductor fins 54. In some embodiments, these rhombic surfaces cause adjacent epitaxial source / drain regions 98 to merge, as described by Fig. Figure 11C illustrates this. However, the hybrid fins 66 (where present) block lateral epitaxial growth to prevent some of the epitaxial source / drain regions 98 from merging. For example, the hybrid fins 66 may form at cell boundaries to separate the epitaxial source / drain regions 98 of adjacent cells. Therefore, some of the epitaxial source / drain regions 98 are separated by the hybrid fins 66. The epitaxial source / drain regions 98 may contact the sidewalls of the hybrid fins 66. In the illustrated embodiments, the fin spacers 94 are configured to cover a portion of the sidewalls of the semiconductor fins 54 that extends over the STI regions 68, thereby inhibiting epitaxial growth.In another embodiment, the spacer used to form the gatespacers 92 is set in such a way as not to form the fin spacers 94, so that the epitaxial source / drain areas 98 are allowed to extend to the surfaces of the STI areas 68.

[0050] The fin spacers 94 can retain their relative heights after the fin spacers 94 have been removed (for Fig. 10A to Fig. 10C described) and the epitaxial source / drain areas 98 have grown up (for Fig. 11A to Fig. (described in Section 11C), so that the inner fin spacers 94N continue to have a greater height than the outer fin spacers 94O. Accordingly, the outer fin spacers 94O above the STI regions 68B (between the hybrid fins 66 and the semiconductor fins 54) have a first height, the inner fin spacers 94N above the STI regions 68A (between the semiconductor fins 54) have a second height, and the second height is greater than the first height. In some embodiments, the inner fin spacers 94N and the outer fin spacers 94O have a height in the range of 5 nm to 50 nm.

[0051] In Fig. 12A to Fig. In step 12C, a first dielectric intermediate layer (ILD) 104 is deposited over the epitaxial source / drain regions 98, the gate spacers 92, the masks 86 (if present) or the dummy gates 84, and the hybrid fins 66. The first ILD 104 can be formed from a dielectric material that can be deposited by any suitable process, such as CVD, plasma-enhanced CVD (PECVD), FCVD, or the like. Suitable dielectric materials may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed by any suitable process may be used.

[0052] In some embodiments, a contact etch stop layer (CESL) 102 is formed between the first ILD 104 and the epitaxial source / drain regions 98, the gate spacers 92, the masks 86 (if present) or the dummy gates 84, and the hybrid fins 66. In some embodiments, the CESL 102 fills the seams 66A of the hybrid fins 66 adjacent to the source / drain regions 98 (see, e.g., Figure 1). Fig. 12C) or it essentially fills them. The CESL 102 can be formed from a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, which exhibits high etch selectivity with respect to the etching of the first ILD 104. The CESL 102 can be formed using any method, such as CVD, ALD, or the like.

[0053] In Fig. 13A to Fig. In 13C, a removal process is performed to flatten the upper surfaces of the first ILD 104 with the upper surfaces of the gatespacers 92 and the masks 86 (if present) or the dummy gates 84. In some embodiments, a planarization process, such as chemical-mechanical polishing (CMP), a back-etching process, combinations thereof, or the like, may be used. The planarization process may also remove the masks 86 on the dummy gates 84 and sections of the gatespacers 92 along the sidewalls of the masks 86. After the planarization process, the upper surfaces of the first ILD 104, the CESL 102, the gatespacers 92, and the masks 86 (if present) or the dummy gates 84 are coplanar (within process variations), so that they are at the same level. Accordingly, the upper surfaces of the masks 86 (if present) or the dummy gates 84 are exposed by the first ILD 104.In the illustrated embodiment, the masks 86 remain, and the planarization process flattens the upper surfaces of the first ILD 104 with the upper surfaces of the masks 86.

[0054] In Fig. 14A to Fig. In 14C, the masks 86 (if present), the dummy gates 84, and the dummy dielectrics 82 are removed in an etching process, forming recesses 106. The removal process removes the dummy dielectrics 82 from the seams 66A of the hybrid fins 66, which were exposed by removing the dummy gates 84. In some embodiments, the dummy dielectrics 82 are removed from the recesses 106 in a first region of a die (e.g., a core logic region) and remain in recesses 106 in a second region of the die (e.g., an input / output region). In some embodiments, the dummy gates 84 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process which uses a reaction gas(es) that selectively etches (etches) the material of the dummy gates 84 at a faster rate than the materials of the first ILD 104 and the gate spacer 92.During removal, the dummy dielectrics 82 can be used as etch stop layers when the dummy gates 84 are etched. The dummy dielectrics 82 can then be removed after the dummy gates 84 have been removed. In some embodiments, the dummy dielectrics 82 are removed by an anisotropic etching process. Each recess 106 exposes and / or lies above a channel region 58 of a respective semiconductor fin 54. The recesses 106 also expose the hybrid fins 66 and the seams 66A of the hybrid fins 66.

[0055] In Fig. 15A to Fig. In 16C, gate dielectrics 112 and gate electrodes 114 are formed for exchange gates. Each corresponding pair of a gate dielectric 112 and a gate electrode 114 can be collectively referred to as a “gate structure”. Each gate structure extends along side walls and an upper surface of a channel region 58 of the semiconductor fins 54. Some of the gate structures extend further along side walls and an upper surface of a hybrid fin 66.

[0056] The gate dielectrics 112 have two or more gate dielectric layers 112A and 112B arranged in the recesses 106, such as on the top surfaces and sidewalls of the semiconductor fins 54, on the top surfaces and sidewalls of the hybrid fins 66, and on sidewalls of the gate spacers 92. The gate dielectric layer 112A can be described as an interface layer and may comprise an oxide, such as silicon oxide or a metal oxide, a silicate, such as a metal silicate, combinations thereof, multiple layers thereof, or the like. The gate dielectric layer 112A is formed such that it fills or substantially fills the seams 66A in the hybrid fins 66. The gate dielectric layer 112A is formed in the seams 66A by first impregnating the structure in a silicon precursor, followed by an oxidation process. In some embodiments, the silicon precursor contains SiH4, Si2H6, LTO 52 0 (C6H 17NSi), SAM 24 (C8H 22 N2Si), the like, or a combination thereof. In some embodiments, the silicon precursor impregnation process is carried out at a temperature in the range of 350 °C to 490 °C, for a duration in the range of 10 minutes to 30 minutes, and at a silicon precursor to carrier gas ratio in the range of 5:1 to 10:1, wherein the carrier gas contains N2, H2, or the like. Performing the silicon precursor impregnation under process conditions in these ranges, followed by an oxidation process, provides a sufficiently thin film (e.g., less than 10 Å), and the length, width, and height of the trench design between semiconductor fins 54 and hybrid fins 66 of the overall wafer structure are not affected.

[0057] In some embodiments, the oxidation process is an O3 oxidation process. The gate dielectric layer 112A within the seams 66A of the hybrid fins 66 can have a different material composition than the gate dielectric layer 112A on the semiconductor fins 54. In some embodiments, the gate dielectric layer 112A within the seams 66A is richer in silicon than the gate dielectric layer 112A outside the seams 66A. For example, the gate dielectric layer 112A within the seams 66A of the hybrid fins 66 can have a silicon-to-oxygen (Si:O) ratio in the range of 1:1 to 1:1.5, and the gate dielectric layer 112A on the semiconductor fins 54 can have a Si:O ratio in the range of 1:1.5 to 1:2.

[0058] Fig. 19 shows a structure at a similar stage of processing as Fig. 15A according to some embodiments. The training steps and processes of this structure are similar to those described in the other embodiments, and the descriptions are not repeated here. In Fig. 19 The gate dielectric layer 112A is located within the seams 66A and on the channel regions 58 of the semiconductor fins 54. In some embodiments, the gate dielectric layer 112A is not formed on an outer side wall of the hybrid fins 66, as shown in Fig. 19 shown.

[0059] Filling the seams 66A of the hybrid fins 66 with the interface layer 112A prevents the formation of conductive material from subsequently formed source / drain and / or gate contacts in the seams 66A. Preventing the formation of conductive material from source / drain and / or gate contacts in the seams 66A prevents the source / drains and gates from being short-circuited to each other via the seams 66A. The manufacturing yield of the devices can be improved in this way. Furthermore, by simultaneously forming the interface layer(s) under the exchange gate structures and filling the seams 66A, no additional processing is required to fill the seams of the hybrid fins.

[0060] After the gate dielectric layer 112A has formed, the gate dielectric layer 112B is formed. The gate dielectric layer 112B can contain a high-k dielectric material, such as a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The dielectric material(s) of the gate dielectric layer 112B can be formed by molecular beam deposition (MBD), aluminum lithography (ALD), photochemical electron vapor deposition (PECVD), or the like. The gate dielectric layer 112B is not formed within the seams 66A, as the seams 66A have already been filled by the gate dielectric layer 112A. In embodiments in which sections of the dummy dielectrics 82 remain in the recesses 106, the gate dielectric layer 112 comprises a material of the dummy dielectrics 82 (e.g. silicon oxide).Although a two-layer gate dielectric layer 112 is shown, the gate dielectric layers 112 can have any number of interface layers and any number of main layers.

[0061] In Fig. 16A to Fig. In Figure 16C, the gate electrodes 114, comprising one or more gate electrode layers, are arranged over the gate dielectrics 112, which fill the remaining portions of the recesses 106. The gate electrodes 114 can comprise a metal-containing material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, tungsten, cobalt, ruthenium, aluminum, combinations thereof, multiple layers thereof, or the like. Although single-layer gate electrodes 114 are shown, the gate electrodes 114 can comprise any number of work-function setting layers, any number of barrier layers, any number of adhesive layers, and a filler material.

[0062] As an example of gate structure formation, one or more gate dielectric layers can be deposited in the recesses 106. The gate dielectric layer(s) can also be deposited on the upper surfaces of the first ILD 104, the CESL 102, and the gate spacer 92. Subsequently, one or more gate electrode layers can be deposited on the gate dielectric layer(s) 112. A removal process can then be performed to remove the excess portions of the gate dielectric layer(s) and the gate electrode layer(s), which are located above the upper surfaces of the first ILD 104, the CESL 102, and the gate spacer 92. After the removal process, the gate dielectric layer(s) will have portions remaining in the recesses 106 (thus forming the gate dielectrics 112).After the removal process, the gate electrode layer(s) exhibit sections that were left in the recesses 106 (forming the gate electrodes 114). In some embodiments, a planarization process, such as chemical-mechanical polishing (CMP), a re-etching process, combinations thereof, or the like, may be used. After the planarization process, the upper surfaces of the gate spacer 92, the CESL 102, the first ILD 104, the gate dielectrics 112A and 112B, and the gate electrodes 114 are coplanar (within process variations), so that they are at the same level.

[0063] The formation of the gate dielectrics 112A and 112B in the n-region 50N and the p-region 50P can take place simultaneously, so that the gate dielectrics 112A and 112B in each region are formed from the same material(s), and the formation of the gate electrodes 114 can take place simultaneously, so that the gate electrodes 114 in each region are formed from the same material(s). In some embodiments, the gate dielectrics 112A and 112B in each region can be formed using different processes, so that the gate dielectrics 112A and 112B can contain different materials and / or have different numbers of layers, and / or the gate electrodes 114 can be formed in each region using different processes, so that the gate electrodes 114 can contain different materials and / or have different numbers of layers.Different masking steps can be used to mask and expose suitable areas when different processes are used.

[0064] In Fig. 17A to Fig. In embodiment 17C, a second ILD 124 is deposited over the gate spacers 92, the CESL 102, the first ILD 104, the gate dielectrics 112A and 112B, and the gate electrodes 114. In some embodiments, the second ILD 124 is a flowable film formed using a flowable CVD process. In other embodiments, the second ILD 124 is formed from a dielectric material, such as PSG, BSG, BPSG, USG, or the like, which can be deposited using any suitable process, such as CVD, PECVD, or the like.

[0065] Optionally, prior to the formation of the second ILD 124, gate masks 116 are formed over the gate structures (which include the gate dielectrics 112 and the gate electrodes 114). As an example of how the gate masks 116 are formed, the gate structures and, optionally, the gate spacers 92 can be recessed using any suitable etching process. One or more dielectric materials can be formed in the recesses and on the upper surfaces of the CESL 102 and the first ILD 104. Suitable dielectric materials include silicon nitride, silicon carbonitride, silicon oxynitride, silicon oxycarbonitride, or the like, which can be formed using a conformal deposition process such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), or the like.Other insulating materials formed by any suitable process may be used. A removal process is performed to remove the excess sections of the dielectric material(s), the excess sections being located above the upper surfaces of CESL 102 and the first ILD 104, thereby forming the gate masks 116. After the removal process, the dielectric material(s) has sections left in the recesses (thus forming the gate masks 116). In some embodiments, a planarization process, such as chemical-mechanical polishing (CMP), a back-etching process, combinations thereof, or the like, may be used.After the planarization process, the upper surfaces of the CESL 102, the first ILD 104, and the gate masks 116 are coplanar (within process variations), meaning they are at the same level. Gate contacts are then formed such that they penetrate the gate masks 116 to contact the upper surfaces of the gate electrodes 114.

[0066] In some embodiments, an etch stop layer (ESL) 122 is formed between the second ILD 124 and the gate spacers 92, the CESL 102, the first ILD 104 and the gate masks 116 (if present), or the gate dielectrics 112A and 112B and the gate electrodes 114. The ESL 122 can contain a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, which exhibits high etch selectivity with respect to the etching of the second ILD 124.

[0067] In Fig. 18A to Fig.In 18C, gate contacts 132 and source / drain contacts 134 are configured such that they contact the gate electrodes 114 and the epitaxial source / drain regions 98, respectively. The gate contacts 132 are physically and electrically coupled to the gate electrodes 114. The source / drain contacts 134 are physically and electrically coupled to the epitaxial source / drain regions 98.

[0068] As an example of forming the gate contacts 132 and the source / drain contacts 134, openings for the gate contacts 132 are formed by the second ILD 124, the ESL 122, and the gate masks 116, and openings for the source / drain contacts 134 are formed by the second ILD 124, the ESL 122, the first ILD 104, and the CESL 102. The openings can be formed using suitable photolithographic and etching techniques. A liner (not shown separately), such as a diffusion barrier, an adhesive layer, or the like, and a conductive material are formed in the openings. The liner can contain titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material can be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as a CMP, can be carried out to remove excess material from a surface of the second ILD 124.The remaining liner and the conductive material form the gate contacts 132 and the source / drain contacts 134 in the openings. The gate contacts 132 and the source / drain contacts 134 can be formed in different processes or they can be formed in the same process. Although shown as being formed in the same cross-sections, it is understood that each of the gate contacts 132 and the source / drain contacts 134 can be formed in different cross-sections, which can prevent short-circuiting of the contacts.

[0069] Optionally, metal-semiconductor alloy regions 136 are formed at the interfaces between the epitaxial source / drain regions 98 and the source / drain contacts 134. The metal-semiconductor alloy regions 136 can be silicide regions formed from a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), germanide regions formed from a metal germanide (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), silicon germanide regions formed from both a metal silicide and a metal germanide, or the like. The metal-semiconductor alloy regions 136 can be formed upstream of the source / drain contact material(s) 134 by depositing a metal in the openings for the source / drain contacts 134 and then performing a thermal annealing process. The metal can be any metal capable of bonding with the semiconductor materials (e.g.,Silicon, silicon germanium, germanium, etc.) of the epitaxial source / drain regions 98 to react to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or their alloys. The metal can be deposited using a deposition process such as ALD, CVD, PVD, or the like. After the thermal annealing process, a cleaning process, such as wet cleaning, can be performed to remove any residual metal from the source / drain contact openings 134, such as from surfaces of the metal-semiconductor alloy regions 136. The source / drain contact material(s) 134 can then be formed on the metal-semiconductor alloy regions 136.

[0070] Embodiments can offer advantages. Filling the seams 66A of the hybrid fins 66 with the interface layer 112A prevents the formation of conductive material from subsequently formed source / drain and / or gate contacts in the seams 66A. Preventing the formation of conductive material from source / drain and / or gate contacts in the seams 66A prevents the source / drains and gates from being short-circuited to each other via the seams 66A. The manufacturing yield of the devices can be improved in this way. In some embodiments, the seams 66A are filled using a silicon precursor impregnation process and an oxidation process. These processes simultaneously form the interface layer(s) beneath the exchange gate structures, so no additional processing is required to fill the seams of the hybrid fins.

[0071] The disclosed FinFET embodiments could also be applied to nanostructured devices, such as nanostructured field-effect transistors (e.g., nanofoil, nanowire, gate-all-around field-effect transistors, or the like) (NSFETs). In one NSFET embodiment, the fins are replaced by nanostructures formed by structuring a stack of alternating layers of channel layers and sacrificial layers. Dummy gate structures and source / drain regions are formed in a similar manner to the embodiments described above. After the dummy gate structures are removed, the sacrificial layers can be partially or completely removed in channel regions.The exchange gate structures are formed in a similar manner to those described above. The exchange gate structures can partially or completely fill openings left by the removal of the sacrificial layers, and they can partially or completely surround the channel layers in the channel regions of the NSFET devices. ILDs and contacts to the exchange gate structures and the source / drain regions can be formed in a similar manner to those described above.

[0072] Furthermore, the FinFET / NSFET devices can be interconnected via metallization layers in a superimposed interconnect structure to form integrated circuits. This superimposed interconnect structure can be formed in a back-end-of-line (BEOL) process, in which the metallization layers are connected to the gate contacts 132 and the source / drain contacts 134. Additional elements, such as passive devices, memory (e.g., magnetoresistive random-access memory (MRAM), resistive random-access memory (RRAM), phase-change random-access memory (PCRAM), etc.), or the like, can be integrated into the interconnect structure during the BEOL process.

[0073] One embodiment comprises a device comprising: a first semiconductor fin extending from a substrate, a second semiconductor fin extending from the substrate, a hybrid fin above the substrate, wherein the hybrid fin is arranged between the first semiconductor fin and the second semiconductor fin, and wherein the hybrid fin has an internal oxide section extending downwards from an upper surface of the hybrid fin.The device also includes: a first isolation region between the second semiconductor fin, the first semiconductor fin and the hybrid fin, wherein the hybrid fin extends over an upper surface of the first isolation region, a high-k dielectric over side walls of the hybrid fin, side walls of the first semiconductor fin, and side walls of the second semiconductor fin, a gate electrode on the high-k gate dielectric, and source / drain regions on the first semiconductor fin on opposite sides of the gate electrode.

[0074] Embodiments may include one or more of the following features: a device in which the upper surfaces of the hybrid fin, the first semiconductor fin, and the second semiconductor fin are at the same level. The first semiconductor fin has an interfacial oxide layer between the side walls of the first semiconductor fin and the high-k gated dielectric. The inner oxide section of the hybrid fin is richer in silicon than the interfacial oxide layer. The hybrid fin contains silicon nitride, tantalum oxide, aluminum oxide, zirconium oxide, hafnium oxide, silicon carbonitride, silicon oxicarbonate, or a combination thereof. The device further comprises: a third semiconductor fin adjacent to the second semiconductor fin; a second insulating region between the second semiconductor fin and the third semiconductor fin, wherein an upper surface of the first insulating region is located further from the substrate than an upper surface of the second insulating region.A lower surface of the first isolation region is positioned further away from upper surfaces of the hybrid fin, the first semiconductor fin, and the second semiconductor fin than a lower surface of the second isolation region.

[0075] One embodiment comprises a method comprising: forming a first semiconductor fin and a second semiconductor fin extending from a substrate; forming an insulating material around the first semiconductor fin and the second semiconductor fin, wherein a first section of the insulating material is arranged between the first semiconductor fin and the second semiconductor fin; the method further comprises forming a hybrid fin on the first section of the insulating material, the hybrid fin having a seam therein; the method further comprises recessing the first section of the insulating material to form a first insulating region; and the method further comprises forming a dummy gate structure over the first semiconductor fin, the hybrid fin, and the second semiconductor fin.The process also includes forming source / drain regions on the first and second semiconductor fins on opposite sides of the dummy gate structure. The process also includes removing the dummy gate structure to form a gate trench. The process further includes forming a first gate dielectric layer on the first semiconductor fin, the hybrid fin, and the second semiconductor fin in the gate trench, with the first gate dielectric layer filling the seam in the hybrid fin. The process further includes forming a second gate dielectric layer on top of the first gate dielectric layer in the gate trench. The process further includes forming a gate electrode layer on top of the second gate dielectric layer in the gate trench.

[0076] Embodiments may include one or more of the following features. The method for forming the hybrid fin comprises: depositing a dielectric layer on the insulating material between the first semiconductor fin and the second semiconductor fin, unoccupied by the insulating material; and removing a portion of the dielectric layer. Removing the portion of the dielectric layer comprises planarizing the dielectric layer, the insulating material, the first semiconductor fin, and the second semiconductor fin, such that the upper surfaces of the hybrid fin, the first semiconductor fin, and the second semiconductor fin are at the same level.Forming the first gate dielectric layer involves performing a silicon precursor impregnation process in the gate groove, followed by an oxidation process in the gate groove. After the oxidation process, the first gate dielectric layer is formed in the gate groove and at the hybrid fin seam. The first gate dielectric layer contains silicon oxide, and the second gate dielectric layer is a high-k layer. The first gate dielectric layer at the hybrid fin seam is richer in silicon than the first gate dielectric layer on the first semiconductor fin. The hybrid fin contains silicon nitride, tantalum oxide, aluminum oxide, zirconium oxide, hafnium oxide, silicon carbonitride, silicon oxia carbonitride, or a combination thereof.The method further comprises: forming an etch stop layer over the source / drain regions and the hybrid fin, wherein the etch stop layer fills a section of the seam in the hybrid fin outside the gate trench; forming a dielectric intermediate layer over the etch stop layer. The method further comprises forming conductive contacts through the dielectric intermediate layer and the etch stop layer to the source / drain regions, wherein the conductive contacts are electrically connected to the source / drain regions.

[0077] One embodiment comprises a method comprising forming a first semiconductor fin extending from a substrate. The method further comprises forming an insulating material around the first semiconductor fin. The method further comprises depositing a dielectric layer on the insulating material around the first semiconductor fin. The method further comprises removing a portion of the dielectric layer to form a dielectric fin, wherein the dielectric fin has a seam therein. The method further comprises recessing the insulating material, wherein, after the recession of the insulating material, the dielectric fin extends over an upper surface of the insulating material. The method further comprises forming a dummy gate structure over the first semiconductor fin, the dielectric fin, and the recessed insulating material.The process also includes forming source / drain regions on the semiconductor fin on opposite sides of the dummy gate structure. The process also includes removing the dummy gate structure to form a gate trench. The process also includes performing a silicon precursor impregnation process in the gate trench. Following the silicon precursor impregnation process, the process also includes performing an oxidation process in the gate trench to form an interface layer on the first semiconductor fin and the dielectric fin in the gate trench, with the interface layer filling the seam in the dielectric fin. The process also includes forming a high-k gate dielectric layer on the interface layer in the gate trench. The process also includes forming a gate electrode layer on the high-k gate dielectric layer in the gate trench.

[0078] Embodiments may include one or more of the following features. A method in which the interface layer in the seam of the dielectric fin is richer in silicon than the interface layer on the first semiconductor fin. The high-k gated dielectric layer is not located in the seam of the dielectric fin. Removing the section of the dielectric layer includes planarizing the dielectric layer, the insulating material, and the first semiconductor fin, such that the upper surfaces of the dielectric fin and the first semiconductor fin are at the same level.

[0079] The foregoing outlines features of several embodiments so that a person skilled in the art can better understand the aspects of the present disclosure. A person skilled in the art should recognize that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to accomplish the same tasks and / or achieve the same advantages as the embodiments presented herein. A person skilled in the art should also understand that such equivalent embodiments do not deviate from the inventive concept and scope of the present disclosure, and that they can make various changes, substitutions, and modifications here without deviating from the inventive concept and scope of the present disclosure. QUOTES INCLUDED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 63268871

[0001]

Claims

[1] Device comprising: a first semiconductor fin extending from a substrate, a second semiconductor fin extending from the substrate, a hybrid fin above the substrate, wherein the hybrid fin is arranged between the first semiconductor fin and the second semiconductor fin, wherein the hybrid fin has an oxide inner section extending downwards from an upper surface of the hybrid fin, a first isolation region between the second semiconductor fin, the first semiconductor fin, and the hybrid fin, wherein the hybrid fin extends over an upper surface of the first isolation region, a high-k gated dielectric across sidewalls of the hybrid fin, sidewalls of the first semiconductor fin, and sidewalls of the second semiconductor fin, a gate electrode on the high-k gate dielectric, and Source / drain regions on the first semiconductor fin on opposite sides of the gate electrode. [2] Device according to claim 1, wherein the upper surfaces of the hybrid fin, the first semiconductor fin and the second semiconductor fin are at the same level. [3] Device according to claim 1 or 2, wherein the first semiconductor fin has an interface oxide layer between side walls of the first semiconductor fin and the high-k gated dielectric. [4] Device according to claim 3, wherein the oxide inner section of the hybrid fin is richer in silicon than the interface oxide layer. [5] Device according to any of the preceding claims, wherein the hybrid fin contains silicon nitride, tantalum oxide, aluminium oxide, zirconium oxide, hafnium oxide, silicon carbonitride, silicon oxicarbonate, or a combination thereof. [6] Device according to one of the preceding claims, further comprising: a third semiconductor fin adjacent to the second semiconductor fin, and a second isolation region between the second semiconductor fin and the third semiconductor fin, wherein an upper surface of the first isolation region is located further away from the substrate than an upper surface of the second isolation region. [7] Device according to claim 6, wherein a lower surface of the first isolation region is arranged further away from upper surfaces of the hybrid fin, the first semiconductor fin and the second semiconductor fin than a lower surface of the second isolation region. [8] Procedures, comprehensive: Forming a first semiconductor fin and a second semiconductor fin extending from a substrate, Forming an insulating material around the first semiconductor fin and the second semiconductor fin, wherein a first section of the insulating material is arranged between the first semiconductor fin and the second semiconductor fin, Forming a hybrid fin on the first section of the insulation material, wherein the hybrid fin has a seam in it, Leaving out the first section of insulation material to form an initial insulation area, Forming a dummy gate structure over the first semiconductor fin, the hybrid fin, and the second semiconductor fin, Formation of source / drain regions on the first semiconductor fin and the second semiconductor fin on opposite sides of the dummy gate structure, Removing the dummy gate structure to create a gate trench, Forming a first gate dielectric layer on the first semiconductor fin, the hybrid fin and the second semiconductor fin in the gate groove, wherein the first gate dielectric layer fills the seam in the hybrid fin, Formation of a second gate dielectric layer on top of the first gate dielectric layer in the gate groove, and Formation of a gate electrode layer on the second gate dielectric layer in the gate groove. [9] Method according to claim 8, wherein forming the hybrid fin comprises: Deposition of a dielectric layer on the insulating material between the first semiconductor fin and the second semiconductor fin, unoccupied by the insulating material, and Removing a section of the dielectric layer. [10] Method according to claim 9, wherein the removal of the section of the dielectric layer comprises: Planarizing the dielectric layer, the insulating material, the first semiconductor fin, and the second semiconductor fin, wherein the upper surfaces of the hybrid fin, the first semiconductor fin, and the second semiconductor fin are at the same level. [11] Method according to any one of the preceding claims 8 to 10, wherein forming the first gate dielectric layer comprises: Performing a silicon precursor impregnation process in the gate trench, and After performing the silicon precursor impregnation process, an oxidation process is carried out in the gate groove, whereby after the oxidation process the first gate dielectric layer is formed in the gate groove and in the seam of the hybrid fin. [12] Method according to any one of the preceding claims 8 to 11, wherein the first gate dielectric layer contains silicon oxide, and wherein the second gate dielectric layer comprises a high-k layer. [13] Method according to claim 12, wherein the first gate dielectric layer in the seam of the hybrid fin is richer in silicon than the first gate dielectric layer on the first semiconductor fin. [14] Method according to any one of the preceding claims 8 to 13, wherein the hybrid fin comprises silicon nitride, tantalum oxide, aluminium oxide, zirconium oxide, hafnium oxide, silicon carbonitride, silicon oxicarbonate, or a combination thereof. [15] Method according to any one of the preceding claims 8 to 14, further comprising: Forming an etch stop layer over the source / drain areas and the hybrid fin, with the etch stop layer filling a section of the seam in the hybrid fin outside the gate trench, and Formation of a dielectric intermediate layer above the etch stop layer. [16] The method of claim 15, further comprising: Forming conductive contacts through the dielectric intermediate layer and the etch stop layer to the source / drain regions, wherein the conductive contacts are electrically connected to the source / drain regions. [17] Procedures, including: Formation of a first semiconductor fin extending from a substrate, Formation of an insulating material around the first semiconductor fin, Deposition of a dielectric layer on the insulating material around the first semiconductor fin, and Removing a section of the dielectric layer to form a dielectric fin, wherein the dielectric fin has a seam in it, Recess of the insulating material, wherein after the recess of the insulating material the dielectric fin extends over an upper surface of the insulating material, Forming a dummy gate structure over the first semiconductor fin, the dielectric fin and the recessed insulating material, Formation of source / drain regions on the first semiconductor fin on opposite sides of the dummy gate structure, Removing the dummy gate structure to create a gate trench, Performing a silicon precursor impregnation process in the gate trench, and After performing the silicon precursor impregnation process, an oxidation process is carried out in the gate groove to form an interface layer on the first semiconductor fin and the dielectric fin in the gate groove, with the interface layer filling the seam in the dielectric fin. Formation of a high-k gate dielectric layer on the interface layer in the gate groove, and Formation of a gate electrode layer on the high-k gate dielectric layer in the gate groove. [18] Method according to claim 17, wherein the interface layer in the seam of the dielectric fin is richer in silicon than the interface layer on the first semiconductor fin. [19] Method according to claim 17 or 18, wherein the high-k gated dielectric layer is not located in the seam of the dielectric fin. [20] Method according to any one of the preceding claims 17 to 19, comprising removing the section of the dielectric layer: Planarizing the dielectric layer, the insulating material, and the first semiconductor fin, with the upper surfaces of the dielectric fin and the first semiconductor fin being at the same level.