PROFILE CONTROL FOR INSULATION STRUCTURES IN SEMICONDUCTOR DEVICES AND ASSOCIATED SEMICONDUCTOR DEVICES

Abstract

Procedure, comprehensive: Establishing a fin structure (106N, 106P) on a substrate (104); Fabricating a superlattice structure (423, 425) with first and second nanostructured layers (124, 126, 424, 426) arranged in an alternating configuration on the fin structure (106N, 106P); Deposition, in a first deposition process, of an oxide coating such that it encloses the superlattice structure (423, 425) and the fin structure (106N, 106P); Establishing a dopant source coating (108B, 508B, 608B) on the oxide coating; Deposition of an oxide filler layer on the dopant source coating (108B, 508B, 608B) in a second deposition process that is different from the first deposition process; Performing a doping process to produce a doped oxide coating and a doped oxide filler layer; Removal of portions of the doped oxide coating, the doped oxide filler layer, and the dopant source coating (108B, 508B, 608B) from sidewalls of the superlattice structure (423, 425); and fabricating, on the fin structure (106N, 106P), a gate structure (112, 112N, 112P) such that it encloses the first nanostructured layers (124, 126, 424, 426), wherein the production of the dopant source coating (108B, 508B, 608B) includes carrying out a nitration process on the oxide coating; The production of the dopant source coating (108B, 508B, 608B) involves converting an upper part of the oxide coating into a nitride coating.

Description

background

[0001] Advances in semiconductor technology have led to a growing demand for higher storage capacity, faster processing systems, increased performance, and lower costs. To meet these demands, the semiconductor industry continues to miniaturize the dimensions of semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), which include planar MOSFETs and fin field-effect transistors (FinFETs). This miniaturization has increased the complexity of semiconductor manufacturing processes.

[0002] DE 10 2017 117 984 A1 describes a process comprising the following steps: etching a semiconductor substrate to create trenches, wherein a portion of the semiconductor substrate between the trenches is a semiconductor strip; and depositing a dielectric dose layer on the sidewalls of the semiconductor strip. The dielectric dose layer is doped with an n- or p-type dopant. The remaining portions of the trenches are filled with a dielectric material. Planarization is performed on the dielectric material. The remaining portions of the dielectric dose layer and the dielectric material form STI regions (STI: shallow trench insulation). Heat treatment is performed to diffuse the dopant in the dielectric dose layer into the semiconductor strip.

[0003] US 2018 / 0145131A1 discloses FinFET structures and methods for their fabrication.

[0004] The invention is defined in the claims. Brief description of the drawings

[0005] Aspects of the present revelation can best be understood by referring to the following detailed description in conjunction with the accompanying drawings. The Fig. Figures 1A to 1E show isometric section and top-down views of a semiconductor device with insulation structures according to some embodiments. Fig. Figure 1F shows properties of an insulation structure according to some embodiments. Fig. Figure 2A shows an isometric representation of another semiconductor device with insulation structures according to some embodiments. Fig. 2B shows properties of another insulation structure according to some embodiments. Fig. Figure 3 is a flowchart of a method for manufacturing a semiconductor device with insulating structures according to some embodiments. The Fig. Figures 4, 5A and 5B, 5E to 5G, 6A to 6D, 8 to 13 and 14A to 19D show isometric section and top-down views of a semiconductor device with insulation structures at various stages of its manufacturing process according to some embodiments. The Fig. 5C, Fig. 5D and Fig. Figure 6E shows properties of different insulation structures at various stages of their manufacturing process according to some embodiments. The Fig. 7A, Fig. 7B and Fig. Figure 7E shows isometric representations of another semiconductor device with insulation structures at various stages of its manufacturing process according to some embodiments. The Fig. 7C and Fig. Figure 7D shows properties of another insulation structure at various stages of its manufacturing process according to some embodiments.

[0006] The following are explanatory embodiments described with reference to the accompanying drawings. In the drawings, similar reference numerals generally denote identical, functionally similar, and / or structurally similar elements. The discussion of elements with the same designations applies to each of these elements unless otherwise stated. Detailed description

[0007] The disclosure below provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the fabrication of a first element above or on top of a second element in the description below may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, such that the first and second elements are not in direct contact. Here, the fabrication of a first element on top of a second element means that the first element is fabricated in direct contact with the second element.Furthermore, reference numbers and / or letters may be repeated in the various examples in this disclosure. This repetition serves the purpose of simplicity and clarity and does not in itself imply any relationship between the various embodiments and / or configurations discussed.

[0008] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of one element or structural element to one or more other elements or structural elements depicted in the figures. These spatially relative terms are intended to encompass orientations of the device in use or operation beyond the orientation shown in the figures. The device may be oriented differently (rotated by 90° or in a different orientation), and the spatially relative descriptors used here can be interpreted accordingly.

[0009] It should be noted that in the patent description, references to "an embodiment," "an exemplary embodiment," "exemplary," etc., mean that the described embodiment may have a certain element, structure, or property, but that not every embodiment necessarily has to have that particular element, structure, or property. Furthermore, these phrases need not necessarily refer to the same embodiment. If a particular element, structure, or property is described in connection with an embodiment, a person skilled in the art should know how that particular element, structure, or property is to be realized in connection with other embodiments, regardless of whether it is explicitly described.

[0010] It should be clear that the phraseology or terminology used here serves to describe and not to restrict, so that the phraseology or terminology of the present patent specification should be interpreted by those skilled in the art in light of the principles.

[0011] In some embodiments, the terms "approximately" and "essentially" may indicate a value of a given quantity that varies within 5% of the value (e.g., by ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values ​​are merely examples and are not intended to be limiting. The terms "approximately" and "essentially" may refer to a percentage of the values ​​that would be interpreted by those skilled in the art in light of the principles used herein.

[0012] The fin structures revealed here can be structured using a suitable process. For example, the fin structures can be structured using one or more photolithography processes, such as dual or multiple structuring processes. Dual or multiple structuring processes can combine photolithography and self-aligning processes, enabling the creation of structures with, for example, pitches smaller than those achievable with a single direct photolithography process. For instance, a sacrificial layer is produced over a substrate and then structured using a photolithography process. Spacers are produced along the structured sacrificial layer using a self-aligning process. Subsequently, the sacrificial layer is removed, and the remaining spacers can then be used to structure the fin structures.

[0013] This disclosure provides exemplary structures of semiconductor devices (e.g., GAA-FETs) with doped STI structures (STI: shallow trench insulation) and exemplary methods for their fabrication. In some embodiments, the doped STI structure may comprise a doped coating, a dopant source coating, and a doped filler layer. In some embodiments, the fabrication of the doped STI structure may include producing a stack with a coating, a dopant source coating, and a filler layer at an etch rate higher than that of the coating. The fabrication of the doped STI structure may further include doping the coating and the filler layer by annealing the stack to implant a dopant material from the dopant source coating into the coating and the filler layer.Doping the coating and the filler layer reduces the etch rate difference between them and / or modifies their etch rates to be essentially equal. This improves the uniformity of the etched surface profiles of the doped STI structure. The more uniform surface profiles of the doped STI structures result in improved linear profiles of structures subsequently fabricated on the doped STI structure, thus preventing or reducing manufacturing defects in the later fabricated structures.

[0014] In some embodiments, the dopant source coating may have a nitride layer [e.g., silicon dioxide nitride (SiON) or silicon nitride (SiN)], and the doped coating and the doped filler layer may contain nitrogen dopants. In some embodiments, the concentration of nitrogen atoms in the dopant source coating may decrease to a range of about 0 atomic percent to about 5 atomic percent after the annealing process, or from a range of about 5 atomic percent to about 20 atomic percent. In some embodiments, the doped filler layer may have a concentration of nitrogen dopants of about 1 atomic percent to about 5 atomic percent. The concentration of nitrogen dopants in the doped filler layer is higher than the concentration of nitrogen dopants in the doped coating.

[0015] Fig. Figure 1A shows an isometric representation of a semiconductor device 100 with an NFET 102N and a PFET 102P according to some embodiments. Fig. Figures 1B to 1D show sectional views of the semiconductor device 100 along lines A-A, B-B and C-C. Fig. 1A to 1E according to some embodiments. Fig. 1E is a top-down view of the semiconductor device 100 along lines D - D of the Fig. 1A to 1D according to some embodiments. The Fig. Figures 1B to 1E show representations of the semiconductor device 100 with further structures, which for the sake of simplicity are shown in Fig. 1A are not shown. The discussion of elements with the same designations applies to each of these elements unless otherwise stated.

[0016] In the Fig. The semiconductor device 100 can have the following features, from 1A to 1E: (I) a substrate 104; (II) fin structures 106N and 106P arranged on the substrate 104; (III) doped STI structures 108 arranged on the substrate 104 and adjacent to the fin structures 106N and 106P; (IV) source / drain (S / D) regions 110N and 110P arranged on the fin structures 106N and 106P, respectively; (V) gate structures 112; (VI) gate spacers 114; (VII) isolation structures 116 arranged on the doped STI structures 108; (VIII) barrier layers 118 arranged on the isolation structures 116; (IX) an etch stop layer (ESL) 120; (X) an interlayer dielectric layer (ILD layer) 122; (XI) stacks of nanostructured channel regions 124 arranged on the fin structure 106N; (XII) stacks of nanostructured channel regions 126 arranged on the fin structure 106P; and (XIII) internal spacers 115.The term “nanostructured” as used here defines a structure, layer, and / or region having a horizontal dimension (e.g., along an x- and / or y-axis) and / or a vertical dimension (e.g., along a z-axis) that is smaller than approximately 100 nm and is, for example, approximately 90 nm, approximately 50 nm, or approximately 10 nm, or has other values ​​smaller than 100 nm. In some embodiments, the nanostructured channel regions 124 and / or 126 may have the form of nanolayers, nanowires, or nanorods, or other suitable nanostructured shapes.

[0017] In some embodiments, the substrate 104 can be a semiconductor material, such as silicon, germanium (Ge), silicon germanium (SiGe), a silicon-on-insulator (SOI) structure, or a combination thereof. Furthermore, the substrate 104 can be doped with p-type dopants (e.g., boron, indium, aluminum, or gallium) or n-type dopants (e.g., phosphorus or arsenic). In some embodiments, the fin structures 106N and 106P can contain a material similar to the substrate 104 and can extend along the x-axis.

[0018] In some embodiments, each of the STI structures 108 may comprise: a doped coating 108A arranged on the substrate 104 and along sidewalls of the fin structures 106N and 106P; a dopant source coating 108B arranged on the doped coating 108A; and a doped filler layer 108C arranged on the dopant source coating 108B. In some embodiments, the doped coating 108A and the doped filler layer 108C may comprise an insulating oxide layer containing dopants, and the dopant source coating 108B may comprise an insulating compound of the dopant material. In some embodiments, the doped coating 108A and the doped filler layer 108C may contain the same type of dopants. In some embodiments, the insulating oxide layer can be a silicon oxide layer (SiO2) or another suitable insulating oxide layer.In some embodiments, the doped coating 108A, the dopant source coating 108B and the doped filler layer 108C can each contain a semiconductor element that is similar to or different from each other.

[0019] In some embodiments, the doped coating 108A and the doped filler layer 108C can each be an insulating oxide layer with nitrogen dopants, and the dopant source coating 108B can be a nitride layer, such as a SiN layer, a SiON layer, or another suitable nitride layer. In some embodiments, the doped coating 108A, the dopant source coating 108B, and the doped filler layer 108C can each exhibit a concentration profile of nitrogen atoms with a peak concentration C2 along lines E - E of the Fig. 1A, Fig. 1D and Fig. 1E have, as in Fig. Figure 1F shows that the concentration of nitrogen atoms in the doped filler layer 108C can be higher than that in the doped coating 108A and the dopant source coating 108B, as shown in Fig. Fig. 1F is shown.

[0020] In some embodiments, the type and concentration profile of dopants in the doped coating 108A and the doped filler layer 108C (e.g. in Fig. (1F shown) and the material of the dopant source coating 108B (e.g., SiN or SiON) is selected such that substantially equal etch rates are achieved for the doped coating 108A, the dopant source coating 108B, and the doped filler layer 108C, or an etch rate difference of less than about 1 nm / s is achieved between the doped coating 108A, the dopant source coating 108B, and the doped filler layer 108C. These etch rates for the doped coating 108A, the dopant source coating 108B, and the doped filler layer 108C can facilitate the fabrication of doped STI structures 108 with substantially planar top-side profiles. The substantially planar top-side profiles of the doped STI structures 108 can facilitate the subsequent fabrication of structures (e.g., cladding layers 838, which are in Fig. 8 are shown) on the doped STI structures 108 with improved linear sidewall profiles. The subsequently produced structures with improved linear sidewall profiles can facilitate manufacturing defects in the subsequent production of S / D areas 110N and 110P and gate structures 112, which are later produced with reference to the Fig. 8 to 13 and 14A to 19D are described, prevent or reduce.

[0021] In Fig. In some embodiments, the peak concentration C2 of nitrogen atoms in 1F can be equal to or less than about 5 atomic percent. In some embodiments, the concentration of nitrogen atoms in the doped coating 108A can be about 0.1 atomic percent to about 4 atomic percent. In some embodiments, the concentration of nitrogen atoms in the doped filler layer 108C can be about 1 atomic percent to about 5 atomic percent. Below these concentrations of nitrogen atoms in the doped coating 108A and the doped filler layer 108C, substantially equal etch rates cannot be achieved for the doped coating 108A and the doped filler layer 108C.However, at higher concentrations of nitrogen atoms than the aforementioned concentrations in the doped coating 108A, the dopant source coating 108B and the doped filler layer 108C, the nitrogen atoms can introduce immobile charges into the doped coating 108A, which can cause a current loss in the substrate 104.

[0022] In some embodiments, the doped coating 108A can have a thickness T1 of approximately 2 nm to approximately 10 nm. If the thickness T1 is less than 2 nm, the nitrogen atoms from the dopant source coating 108B can introduce immobile charges into the doped coating 108A, which can cause a current loss in the substrate 104. Furthermore, with a thickness T1 of less than 2 nm, the fin structures 106N and 106P cannot be adequately protected against thermal damage during subsequent tempering and / or deposition processes. Conversely, if the thickness T1 is greater than 10 nm, the processing time for the doped coating 108A increases, and thus the manufacturing costs for the device increase. In some embodiments, the dopant source coating 108B can have a thickness T2 of approximately 1 nm to approximately 6 nm.If the thickness T2 is less than 1 nm, the dopant source layer 108B cannot provide sufficient concentrations of nitrogen atoms to achieve substantially equal etch rates for the doped layer 108A and the doped filler layer 108C. Conversely, if the thickness T2 is greater than 6 nm, nitrogen atoms from the dopant source layer 108B can introduce immobile charges into the doped layer 108A, which can cause a current loss in the substrate 104.

[0023] In the Fig. In some embodiments, S / D regions 1A to 1C and 1E may contain an epitaxially grown semiconductor material, such as Si, and n-type dopants, such as phosphorus and other suitable n-type dopants. In some embodiments, S / D regions 110P may contain an epitaxially grown semiconductor material, such as Si and SiGe, and p-type dopants, such as boron and other suitable p-type dopants.

[0024] In the Fig. 1B, Fig. 1D and Fig. In some embodiments, nanostructured channel regions 124 and 126 of 1E may contain semiconductor materials similar to or different from those of the substrate 104. In some embodiments, the nanostructured channel regions 124 and 126 may contain: Si, SiAs, silicon phosphide (SiP), SiC, SiCP, SiGe, silicon germanium boron (SiGeB), germanium boron (GeB), silicon germanium tin boron (SiGeSnB), a III-V semiconductor compound, or other suitable semiconductor materials. Although the nanostructured channel regions 124 and 126 are shown with rectangular cross-sections, they may also have cross-sections with other geometric shapes (e.g., circular, elliptical, triangular, or polygonal shapes).

[0025] In the Fig. 1A, Fig. 1B, Fig. 1D and Fig. In some embodiments, each of the gate structures 112 can comprise a gate structure 112N enclosing nanostructured channel regions 124 and a gate structure 112P enclosing nanostructured channel regions 126, for which reason the gate structures 112 can be referred to as “gate-all-around structures” (“GAA structures”) or “horizontal gate-all-around structures” (“HGAA structures”). The portions of the gate structures 112N and 112P enclosing the nanostructured channel regions 124 and 126 can be electrically isolated from adjacent S / D regions 110N and 110P by internal spacers 115. In some embodiments, the semiconductor device 100 can be a FinFET and can have fin regions (not shown) instead of the nanostructured channel regions 124 and 126.

[0026] In some embodiments, the gate structures 112N and 112P of each gate structure 112 may comprise: (I) oxide interface layers (IL layers) 128N and 128P arranged on the nanostructured channel regions 124 and 126, respectively; (II) dielectric high-k gate layers (HK gate layers) 130N and 130P arranged on the ILD layers 128N and 128P, respectively; (III) exit work metal layers (WFM layers) 132N and 132P arranged on the dielectric HK gate layers 130N and 130P, respectively; and (IV) gate metal filler layers 134 arranged on the WFM layers 132N and 132P. In some embodiments, the gate structures 112N and 112P of each gate structure 112 can have a common gate metal filler layer 134. In some embodiments, the WFM layers 132N and 132P can contain different materials.In some embodiments, the IL layers 128N and 128P and the dielectric HK gate layers 130N and 130P may contain materials that are similar or different from each other.

[0027] In some embodiments, the IL layers 128N and 128P can be silicon oxide (SiO2) or silicon germanium oxide (SiGeO2). x ) or germanium oxide (GeO x) and they can have a thickness of about 0.5 nm to about 2 nm. In some embodiments, the dielectric HK gate layers 130N and 130P can contain a high-k dielectric material, such as hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), and zirconium silicate (ZrSiO2), and they can have a thickness of about 0.5 nm to about 4 nm. Within these thickness ranges for the IL layers 128N and 128P and the dielectric HK gate layers 130N and 130P, adequate electrical separation can be provided between the gate structures 112N and the nanostructured channel regions 124 and between the gate structures 112P and the nanostructured channel regions 126 without affecting the device size and manufacturing costs.

[0028] In some embodiments, the WFM layers 132N may contain: titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), Al-doped Ti, Al-doped TiN, Al-doped Ta, Al-doped TaN, other suitable Al-doped materials or combinations thereof. In some embodiments, the WFM layers 132P may contain: largely Al-free (e.g., without Al) Ti-based or Ta-based nitrides or nitride alloys, such as titanium nitride (TiN), titanium silicon nitride (TiSiN), a titanium-gold alloy (Ti-Au alloy), a titanium-copper alloy (Ti-Cu alloy), tantalum nitride (TaN), titanium silicon nitride (TaSiN), a tantalum-gold alloy (Ta-Au alloy), a tantalum-copper alloy (Ta-Cu alloy), or a combination thereof.In some embodiments, the gate metal filling layers 134 may contain a suitable conductive material, such as tungsten (W), Ti, silver (Ag), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), Al, iridium (Ir), nickel (Ni), metal alloys or a combination thereof.

[0029] In some embodiments, the gate spacers 114, the internal spacers 115, the ESL 120 and the ILD layer 122 may contain an insulating material such as SiO2, SiN, silicon carbon nitride (SiCN), silicon oxide carbonitride (SiOCN) and silicon germanium oxide.

[0030] In some embodiments, the insulating structures 116 can electrically isolate the S / D regions 110N and 110P from each other and electrically isolate the gate structures 112N and 112P from each other. The insulating structures 116 can also prevent the fusion of epitaxially grown semiconductor materials of the S / D regions 110N and 110P during the formation of the S / D regions 110N and 110P. In some embodiments, the insulating structures 116 can comprise an insulating coating 116A and an insulating filler layer 116B. In some embodiments, the insulating coating 116A and the insulating filler layer 116B can contain SiO2, SiN, silicon carbon nitride (SiCN), silicon oxide carbonitride (SiOCN), or silicon germanium oxide.In some embodiments, sidewalls of the insulation structures 116 can be manufactured such that they are substantially aligned with sidewalls of the doped filler layer 108C in order to prevent or minimize etching of the doped filler layer 108C during the generation of the S / D regions 110N and 110P, as explained in more detail below.

[0031] In some embodiments, barrier layers 118 can prevent etching of the insulating structures 116 during the generation of the S / D regions 110N and 110P, as will be explained in more detail later. In some embodiments, the barrier layers 118 can be rare-earth metal oxide layers containing a rare-earth metal such as hafnium (Hf), lanthanum (La), indium (In), rhodium (Rh), palladium (Pd), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), or a combination thereof. The concentration of the rare-earth metal atoms in the rare-earth metal oxide layer can be approximately 1 × 10 20 atoms / cm² 3 up to about 3 × 10 22 atoms / cm² 3 If the concentration is lower than approximately 1 × 10 20 atoms / cm² 3If the barrier layers 118 cannot adequately protect the insulating structures 116 against etching during the generation of the S / D regions 110N and 110P, the manufacturing costs for the device increase if the concentration is higher than approximately 3 × 10⁻⁶. 22 atoms / cm² 3 is.

[0032] Fig. Figure 2A shows an isometric representation of a semiconductor device 200 with an NFET 102N and a PFET 102P according to some embodiments. The discussion of the semiconductor device 100 also applies to the semiconductor device 200, with the exception of doped STI structures 208 of the semiconductor device 200. In some embodiments, representations of the semiconductor device 200 along lines A' - A', B' - B', C' - C' and D' - D' may differ from those of the Fig. 1B to 1E are similar, with the exception of the doped STI structures 208. In some embodiments, the doped STI structures 208 can be a two-layer structure with a nitrogen-based coating 208A and a doped filler layer 208B instead of the three-layer structure of the doped STI structure 108.

[0033] In some embodiments, the nitrogen-based coating 208A can be an insulating nitride layer, and the doped filler layer 208B can be an insulating oxide layer with nitrogen dopants. In some embodiments, the insulating nitride layer can be a SiN, SiON, or other suitable insulating nitride layer, and the insulating oxide layer can be a SiO2 layer or another suitable insulating oxide layer. In some embodiments, the nitrogen-based coating 208A and the doped filler layer 208B can each contain a semiconductor element that is similar or different from each other.

[0034] In some embodiments, the nitrogen-based coating 208A and the doped filler layer 208B can exhibit concentration profiles 208C or 208D of nitrogen atoms with a peak concentration C6 along a line E' - E' of Fig. 2A, as shown in Fig. Fig. 2B is shown. The concentration of nitrogen atoms in the doped filler layer 208B (e.g., concentration profile 208C) can be essentially equal to the concentration of nitrogen atoms in the nitrogen-based coating 208A, or the concentration of nitrogen atoms in the doped filler layer 208B (e.g., concentration profile 208D) can be greater than the concentration of nitrogen atoms in the nitrogen-based coating 208A. In some embodiments, the type and concentration profile of dopants in the doped filler layer 208B (e.g., in 2B) can be varied. Fig. 2B) and the material of the nitrogen-based coating 208A (e.g., SiN or SiON) is selected such that substantially equal etch rates are achieved for the nitrogen-based coating 208A and the doped filler layer 208B, or an etch rate difference of less than about 1 nm / s is achieved between the nitrogen-based coating 208A and the doped filler layer 208B. These etch rates for the doped coating 208A and the doped filler layer 208B can facilitate the fabrication of doped STI structures 208 with substantially planar top surface profiles. Similar to the doped STI structures 108, the substantially planar top surface profiles of the doped STI structures 208 can facilitate the subsequent fabrication of structures (e.g., cladding layers 838, which are in Fig. 8 are shown) on the doped STI structures 208 with improved linear sidewall profiles.

[0035] In Fig. In some embodiments, the peak concentration C6 of nitrogen atoms in 2B can be equal to or less than approximately 5 atomic percent. In some embodiments, the concentration of nitrogen atoms in the nitrogen-based coating 208A and the doped filler layer 208B can be approximately 1 atomic percent to approximately 5 atomic percent. Below these concentrations of nitrogen atoms in the nitrogen-based coating 208A and the doped filler layer 208B, substantially equal etch rates cannot be achieved for the nitrogen-based coating 208A and the doped filler layer 208B. Conversely, at concentrations of nitrogen atoms higher than those mentioned above, the nitrogen atoms can introduce immobile charges into the nitrogen-based coating 208A, which can cause a current loss in the substrate 104.In some embodiments, sidewalls of insulation structures 116 can be manufactured such that they are substantially aligned with sidewalls of the doped filler layer 208B (not shown) in order to prevent or minimize etching of the doped filler layer 208B during the generation of the S / D regions 110N and 110P.

[0036] In Fig. In some embodiments, the nitrogen-based coating 208A can have a thickness T3 of approximately 2 nm to approximately 10 nm. If the thickness T3 is less than 2 nm, the nitrogen-based coating 208A cannot adequately protect the fin structures 106N and 106P against thermal damage during subsequent annealing and / or deposition processes. Furthermore, with a thickness T3 of less than 2 nm, an adequate concentration of dopants for the doped filler layer 208B cannot be provided. Conversely, if the thickness T3 is greater than 10 nm, nitrogen atoms can introduce immobile charges into the nitrogen-based coating 208A, which can cause a current loss in the substrate 104.

[0037] Fig. Figure 3 is a flowchart of an exemplary method 300 for manufacturing the semiconductor devices 100 and 200 according to some embodiments. For explanation, the following are shown in Fig. The 3 operations specified are described using the exemplary procedure for manufacturing semiconductor devices 100 and 200, which are described in the Fig. 4, 5A - 5G, 6A - 6D, 7A - 7E, 8 - 13 and 14A - 19D are shown. Fig. Figures 4, 5A, 5B, 5E, 6A to 6D and 8 to 13 are isometric representations of semiconductor devices 100 at various stages of fabrication according to some embodiments. Fig. 7A, Fig. 7B and Fig. Figure 7E are isometric representations of semiconductor devices 200 at various stages of fabrication according to some embodiments. Fig. 14A to 19A are sectional views of semiconductor devices 100 along lines A - A of the Fig. 1A and 1C to 1E at various manufacturing stages according to some embodiments. The Fig. Figures 14B to 19B are sectional views of semiconductor devices 100 along lines B - B of the Fig. 1A, Fig. 1B and Fig. 1E at various manufacturing stages according to some embodiments. The Fig. Figures 14C to 19C are sectional views of semiconductor devices 100 along lines C - C of the Fig. 1A, Fig. 1B and Fig. 1E at various manufacturing stages according to some embodiments. The Fig. 14D to 19D are top-down views of semiconductor devices 100 along lines D - D of the Fig. 1A to 1D at various manufacturing stages according to some embodiments. Depending on specific applications, operations may be performed in a different sequence or not at all. It should be noted that semiconductor devices 100 or 200 may not be fabricated using Method 300. It is therefore understood that further processes may be required before, during, and after Method 300, and that some other processes may only be briefly described here. Elements in the Fig. 4, 5A - 5G, 6A - 6D, 7A - 7E, 8 - 13 and 14A - 19D with the same designations as elements in the Fig. 1A to 1F have been described above.

[0038] In Fig. In one operation, 305 superlattice structures are fabricated on fin structures on a substrate. As in Fig. As shown in Figure 4, for example, superlattice structures 423 and 425 are fabricated on the fin structures 106N and 106P, respectively. In some embodiments, a superlattice structure 423 can contain epitaxially grown nanostructured layers 124 and 425 arranged in an alternating configuration, and a superlattice structure 425 can contain epitaxially grown nanostructured layers 126 and 426 arranged in an alternating configuration. In some embodiments, the nanostructured layers 124 and 126 can contain Si without a significant amount of Ge (e.g., without Ge), and the nanostructured layers 424 and 426 can contain SiGe. The nanostructured layers 424 and 426 are also referred to as sacrificial layers 424 and 426. During subsequent processing, the sacrificial layers 424 and 426 can be replaced in a gate replacement process to produce parts of the gate structures 112N and 112P, respectively.

[0039] In some embodiments, a stack of masking layers 436A to 436D can be fabricated on each of the superlattice structures 423 and 425. In some embodiments, masking layer 436A can contain a material similar to that of nanostructured layer 424; masking layer 436B can contain a material similar to that of nanostructured layer 124; masking layer 436C can be an oxide layer; and masking layer 436D can be a nitride layer.

[0040] In Fig. In one operation, 310 doped STI structures are fabricated on the substrate and adjacent to the fin structures. For example, doped STI structures 108 can be fabricated on substrate 104 and adjacent to fin structures 106N and 106P, as described in the Fig. 5A to 5G or the Fig. Sections 6A to 6E are explained.

[0041] In the Fig. In some embodiments, 5A to 5G, the fabrication of the doped STI structures 108 may comprise the following sequential operations: (I) Deposition of an undoped coating 508A onto the structure of Fig. 4, as in Fig. 5A is shown; (II) Deposition of a doped source coating 508B on the undoped coating 508A, as shown in Fig. 5A is shown; (III) Deposition of an undoped filler layer 508C on the dopant source coating 508B, as shown in Fig. 5A is shown; (IV) Performing a tempering process on the structure of Fig. 5A, to produce a doped coating 108A, a dopant source coating 108B and a doped filler layer 108C, as in Fig. 5B is shown; and (V) performing an etching process on the doped coating 108A, the dopant source coating 108B and the doped filler layer 108C to produce doped STI structures 108 as shown in Fig. 5E is shown.

[0042] In some embodiments, the deposition of the undoped coating 508A may involve the deposition of an undoped oxide layer (e.g., an undoped SiO2 layer) with a thickness of about 2 nm to about 10 nm in an ALD process (ALD: atomic layer deposition) or a non-flowing CVD process (CVD: chemical vapor deposition) at a temperature of about 25 °C to about 1000 °C, a pressure of about 133 Pa to about 2000 Pa (about 1 Torr to about 15 Torr) and an RF power (HF: radio frequency) of about 10 W to about 500 W. In some embodiments, the deposition of the dopant source coating 508B may include the deposition of a nitride layer (e.g., a SiON or SiN layer) with a thickness of about 1 nm to about 6 nm in an ALD process or a non-flowable CVD process at a temperature of about 400 °C to about 700 °C, a pressure of about 133 Pa to about 2000 Pa (about 1 Torr to about 15 Torr), and an RF power of about 10 W to about 200 W.In some embodiments, the deposition of the undoped filler layer 508C may include the deposition of an undoped free-flowing oxide layer (e.g., an undoped free-flowing SiO2 layer) in a free-flowing CVD process at a temperature of about 25 °C to about 200 °C and a pressure of about 133 Pa to about 2000 Pa (about 1 Torr to about 15 Torr).

[0043] In some embodiments, performing the tempering process may involve performing a wet tempering process on the structure of Fig. 5A in an environment with steam, oxygen, and nitrogen at a temperature of approximately 200°C to approximately 600°C, a pressure of approximately 133 Pa to approximately 101,000 Pa (approximately 1 Torr to approximately 760 Torr), and for a duration of approximately 0.5 min to approximately 300 min. In some embodiments, the tempering process may involve performing a dry tempering process on the structure of Fig. 5A comprises an etching process carried out in a nitrogen environment at a temperature of approximately 500°C to approximately 700°C, a pressure of approximately 133 Pa to approximately 101,000 Pa (approximately 1 Torr to approximately 760 Torr), and for a duration of approximately 0.5 min to approximately 120 min. In some embodiments, the etching process may include a dry etching process in an etching gas mixture of hydrogen fluoride (HF), ammonia (NH3), nitrogen trifluoride (NF3), and hydrogen at a temperature of approximately 25°C to approximately 200°C and an HF power of approximately 10 W to approximately 100 W.

[0044] In some embodiments, the undoped coating 508A, the dopant source coating 508B and the undoped filler layer 508C can, prior to the tempering process, exhibit a nitrogen atom concentration profile with a nitrogen peak concentration C1 of approximately 5 atomic % to approximately 20 atomic % along a line F - F of Fig. 5A have, as in Fig. 5C is shown. In some embodiments, the doped coating 108A, the dopant source coating 108B and the doped filler layer 108C can exhibit a nitrogen atom concentration profile after the annealing process, with a nitrogen peak concentration C2 of about 5 atomic % or less than 5 atomic % along a line F - F of Fig. 5B have, as in Fig. 5D is shown. The discussion of Fig. 1F also applies to Fig. 5D unless otherwise specified.

[0045] How the nitrogen concentration profiles in the Fig. 5C and Fig. As shown in Figure 5D, during the tempering process, nitrogen atoms diffuse from the dopant source coating 508B into the undoped coating 508A and the undoped filler layer 508C, transforming them into the doped coating 108A, the dopant source coating 108B, and the doped filler layer 108C, respectively. The tempering process can be described as a doping process. During the tempering process, the concentration of nitrogen atoms is increased from approximately 0 atomic percent in the undoped coating 508A and the undoped filler layer 508C to approximately 5 atomic percent or less, in order to produce the doped coating 108A and the doped filler layer 108C. In contrast, the concentration of nitrogen atoms in the dopant source coating 508B is reduced in order to produce a dopant source coating 108B with a concentration of nitrogen atoms of less than about 5 atomic %.In some embodiments, the peak concentration of nitrogen atoms in the doped filler layer 108C is higher than the peak concentrations of nitrogen atoms in the doped coating 108A and / or the dopant source coating 108B, as shown in . Fig. 5D is shown.

[0046] The density of the undoped coating 508A is higher than that of the undoped filler layer 508C, which has a flowable oxide layer. Therefore, the etch rate of the undoped filler layer 508C is higher than that of the undoped coating 508A. Doping the undoped filler layer 508C with nitrogen atoms can densify the flowable oxide layer of the undoped filler layer 508C. This densification of the flowable oxide layer results in a non-flowable oxide layer in the doped filler layer 508C, with an etch rate that is lower than that of the undoped filler layer 508C. Through the tempering process, the unequal etch rates of the undoped coating 508A, the dopant source coating 508B and the undoped filler layer 508C can be modified so that essentially equal etch rates are achieved for the doped coating 108A, the dopant source coating 108B and the doped filler layer 108C.In some embodiments, the etch rate difference between the undoped coating 508A, the dopant-source coating 508B, and the undoped filler layer 508C can be reduced to less than approximately 1 nm / s in the doped coating 108A, the dopant-source coating 108B, and the doped filler layer 108C by the tempering process. Due to the substantially equal etch rates and / or the low etch rate difference between the doped coating 108A, the dopant-source coating 108B, and the doped filler layer 108C, doped STI structures 108 with substantially planar top-side profiles can be produced, as shown in [reference]. Fig. Figure 5F shows an enlarged sectional view of area 501 of Fig. 5E is. In some embodiments, the doped STI structures 108 can be fabricated with top-top profiles having a height difference H1 of less than about 2 nm between a top-top edge and a top-top center along an axis of symmetry G, as in Fig. 5G is shown, which is a further enlarged cross-sectional view of area 501 of Fig. 5E is. The top surface profiles of the doped STI structures 108 in the Fig. 5F and Fig. 5G can enable the later production of structures (e.g., the one in Fig. 8 mantle layers shown 838 and / or the one in Fig. 9 insulation structures shown 116) on the doped STI structures 108 with improved linear sidewall profiles facilitate.

[0047] Without the doping process, STI structures could have top-top profiles with raised top-top edges 108s and a height difference of more than about 2 nm between the top-top edges 108s and the top-top center along the symmetry axis G, as shown in the Fig. 5F and Fig. 5G is shown. These top edges 108s can form sidewall profiles of the cladding layers 838 and the insulation structures 116, which are less linear, resulting in a cladding layer residue 838r (which is in the Fig. 14B and Fig. (as shown in Figure 14D) remains in S / D openings 1410N and 1410P. This residual cladding layer 838r can lead to manufacturing defects in the production of the S / D areas 110N and 110P, the internal spacers 115 and / or the gate structures 112, as will be explained later.

[0048] With a nitrogen peak concentration C1 of approximately 5 atomic percent to approximately 20 atomic percent, the doped coating 108A and the doped filler layer 108C can be adequately produced without introducing immobile charges into the doped coating 108A. If the nitrogen peak concentration C1 is lower than approximately 5 atomic percent, the dopant source coating 508B cannot provide sufficient concentrations of nitrogen atoms to produce the doped coating 108A and the doped filler layer 108C with sufficiently equal etch rates. Conversely, if the nitrogen peak concentration C1 is higher than approximately 20 atomic percent, the nitrogen atoms can introduce immobile charges into the doped coating 108A, which can cause a current loss in the substrate 104.

[0049] In the Fig. In some embodiments, the fabrication of the doped STI structures 108 in 6A to 6E may comprise the following sequential operations: (I) Depositing an undoped coating 608A onto the structure of Fig. 4, as in Fig. 6A is shown; (II) Performing a nitration process on the structure of Fig. 6A with ammonia or nitrogen gas 640 to convert an upper part of the undoped coating 608A into a doped source coating 608B, as in Fig. 6B is shown; (III) Deposition of an undoped filler layer 608C on the dopant source coating 608B, as shown in Fig. 6C is shown; (IV) Performing a tempering process on the structure of Fig. 6C, to produce a doped coating 108A, a dopant source coating 108B and a doped filler layer 108C, as in Fig. 6D is shown; and (V) performing an etching process on the doped coating 108A, the dopant source coating 108B and the doped filler layer 108C to produce doped STI structures 108 as shown in Fig. Figure 5E is shown. In some embodiments, the masking layers 436C and 436D can also be etched during the etching process. The discussion of the undoped coating 508A, the dopant source coating 508B, and the undoped filler layer 508C also applies to the undoped coating 608A, the dopant source coating 608B, and the undoped filler layer 608C.

[0050] The deposition processes for the undoped coating 608A and the undoped filler layer 608C can be similar to those for the undoped coating 508A and the undoped filler layer 508C. In some embodiments, performing the nitriding process can be a thermal nitriding process on the structure of Fig. 6A in an environment with ammonia or nitrogen gas 640 at a temperature of about 700 °C to about 1000 °C, a pressure of about 133 Pa to about 101,000 Pa (about 1 Torr to about 760 Torr) and for a duration of about 0.5 min to about 60 min. In some embodiments, the nitriding process may involve performing a plasma nitriding process on the structure of Fig. 6A in an environment with ammonia or nitrogen gas 640 at a temperature of approximately 250 °C to approximately 1000 °C, a pressure of approximately 133 Pa to approximately 101,000 Pa (approximately 1 Torr to approximately 760 Torr), an RF power of approximately 10 W to approximately 15,000 W, and for a duration of approximately 0.5 min to approximately 60 min. The tempering process, which is applied to the structure of Fig. The process carried out at 6C may be similar to the tempering process used in the structure of Fig. 5A is carried out.

[0051] In some embodiments, the undoped coating 608A, the dopant source coating 608B, and the undoped filler layer 608C can, prior to the tempering process, exhibit a nitrogen atom concentration profile with a nitrogen peak concentration C3 of approximately 5 atomic % to approximately 20 atomic % along a line J - J of Fig. 6C have, as in Fig. Figure 6E is shown. In some embodiments, the doped coating 108A, the dopant source coating 108B, and the doped filler layer 108C can exhibit a nitrogen atom concentration profile along a line J - J after the annealing process. Fig. 6D has something similar to what is in Fig. 5D is shown.

[0052] In some embodiments, doped STI structures 208 can be produced on the substrate 104 and adjacent to the fin structures 106N and 106P instead of the doped STI structures 108, as described with reference to the Fig. 7A to 7E. In some embodiments, the fabrication of the doped STI structures 208 may comprise the following sequential operations: (I) Deposition of a nitrogen-based coating 708A onto the structure of Fig. 4, as in Fig. 7A is shown; (II) Deposition of an undoped filler layer 708B on the nitrogen-based coating 708A, as shown in Fig. 7A is shown; (III) Performing a tempering process on the structure of Fig. 7A, to produce a nitrogen-based coating 208A and a doped filler layer 208B, as in Fig. 7B is shown; and (IV) performing an etching process on the nitrogen-based coating 208A and the doped filler layer 208B to produce doped STI structures 208 as shown in Fig. 7E is shown.

[0053] In some embodiments, the deposition of the nitrogen-based coating 708A may involve the deposition of a nitride layer (e.g., a SiON or SiN layer) in an ALD process or a non-flowing CVD process using a Si precursor (e.g., dichlorosilane or hexachlorosilane), an oxygen precursor, and a nitrogen precursor (e.g., NH3 or N2) at a temperature of about 400 °C to about 700 °C and an RF power of about 10 W to about 100 W. In some embodiments, the deposition of the undoped filler layer 708B may involve the deposition of an undoped free-flowing oxide layer (e.g., an undoped free-flowing SiO2 layer) in a free-flowing CVD process at a temperature of about 25 °C to about 200 °C and a pressure of about 133 Pa to about 2000 Pa (about 1 Torr to about 15 Torr). The tempering process, which is based on the structure of Fig. The process carried out at 6C may be similar to the tempering process used in the structure of Fig. 5A is carried out. The etching process, which is performed on the structure of Fig. 7B, which is carried out, may be similar to the etching process used on the structure of Fig. 5B is carried out.

[0054] In some embodiments, the nitrogen-based coating 708A and the undoped filler layer 708B can exhibit nitrogen atom concentration profiles 708C or 708D prior to the tempering process, with a nitrogen peak concentration C3 of approximately 5 atomic % to approximately 20 atomic % along a line K - K of Fig. 7A have, as in Fig. Figure 7C is shown. In some embodiments, the nitrogen-based coating 208A and the doped filler layer 208B can exhibit nitrogen atom concentration profiles after the tempering process, with a nitrogen peak concentration C4 of about 5 atomic % or less than 5 atomic % along a line K - K of Fig. 7B have, as in Fig. 7D is shown. The discussion of Fig. 2B also applies to Fig. 7D, unless otherwise specified.

[0055] How the nitrogen concentration profiles in the Fig. 7C and Fig. As shown in Figure 7D, during the tempering process, nitrogen atoms diffuse from the nitrogen-based coating 708A into the undoped filler layer 708B, converting it into the nitrogen-based coating 208A or the doped filler layer 208B. The tempering process can be described as a doping process. During the tempering process, the concentration of nitrogen atoms in the undoped filler layer 708B is increased from approximately 0 atomic percent to approximately 5 atomic percent or less to produce the doped filler layer 208B. Conversely, the concentration of nitrogen atoms in the nitrogen-based coating 708A is decreased to produce the nitrogen-based coating 208A with a nitrogen concentration of less than approximately 5 atomic percent.

[0056] The density of the nitrogen-based coating 708A is higher than that of the undoped filler layer 708B, which has a flowable oxide layer. Therefore, the etch rate of the undoped filler layer 708B is higher than that of the nitrogen-based coating 708A. Doping the undoped filler layer 708B with nitrogen atoms densifies the flowable oxide layer of the undoped filler layer 708B. This densification of the flowable oxide layer results in a non-flowable oxide layer in the doped filler layer 708B, with an etch rate that is lower than that of the undoped filler layer 708B. The tempering process allows the unequal etch rates of the nitrogen-based coating 708A and the undoped filler layer 708B to be modified so that essentially equal etch rates are achieved for the nitrogen-based coating 208A and the doped filler layer 208B.In some embodiments, the etch rate difference between the nitrogen-based coating 708A and the undoped filler layer 708B can be reduced to less than approximately 1 nm / s in the nitrogen-based coating 708A and the doped filler layer 208B by the tempering process. Due to the substantially equal etch rates and / or the low etch rate difference between the nitrogen-based coating 708A and the doped filler layer 208B, doped STI structures 208 with substantially planar top surface profiles can be produced.

[0057] In Fig. In one operation, 315 mantle layers are produced such that they enclose the superlattice structures. For example, 838 mantle layers are produced such that they enclose the superlattice structures 423 and 425, as shown in Fig. Figure 8 shows the fabrication of the cladding layers 838, which may include: (I) depositing a layer of a material (e.g., SiGe) similar to that of the nanostructured layers 424 in a CVD process using precursors such as monogerman (GeH4) and disilane (Si2H6) onto the structure of Fig. 5E; and (II) performing an etching process on the deposited material layer to alter the structure of Fig. 8 to produce.

[0058] The essentially planar top surface profiles of the doped STI structures 108 form mantle layers 838 with essentially linear sidewall profiles, as in Fig. 8 is shown. If, however, no STI structures 108 are used, the STI structures would have raised top edges 108s, as explained above, and the mantle layers could have nonlinear sidewall profiles, such as the one shown in Fig. 8 sidewall profiles 838s shown. These nonlinear sidewall profiles 838s can lead to a residual shell layer 838r (which is in the Fig. 14B and Fig. 14D) remains, which can then lead to manufacturing defects in the production of the S / D areas 110N and 110P, the internal spacers 115 and / or the gate structures 112, as will be explained later.

[0059] In Fig. In one operation, 320 isolation structures are fabricated on the doped STI structures. As in Fig. As shown in Figure 9, for example, insulating structures 116 are fabricated on the doped STI structures 108. The fabrication of the insulating structure 116 can include the following sequential operations: (I) Deposition of an insulating coating 116A on the structure of Fig. 8; (II) Depositing an insulating filler layer 116B onto the insulating coating 116A; and (III) Performing a CMP process (CMP: chemical-mechanical polishing) on ​​the insulating coating 116A, the insulating filler layer 116B, and the sheathing layers 838 to substantially coplanarize the top surfaces of the insulating coating 116A, the insulating filler layer 116B, and the sheathing layers 838, as described in Fig. 9 is shown.

[0060] In Fig. In one operation, 325 barrier layers are produced on the insulation structures. For example, with reference to the Fig. 10 and Fig. As outlined in Figure 11, barrier layers 118 are fabricated on the insulating structures 116. The fabrication of the barrier layers 118 can include the following sequential operations: (I) Performing an etching process on the insulating structures 116 to create the structure of Fig. 10 to produce; (II) Deposition of a rare earth metal oxide layer (not shown) on the structure of Fig. 10; and (III) performing a CMP process on the rare earth metal oxide layer to substantially coplanarize the top surfaces of the barrier layers 118 and the shell layers 838, as described in Fig. 11 is shown.

[0061] In Fig. In one operation, 330 polysilicon structures are fabricated on the barrier layers, the mantle layers, and the superlattice structures. For example, with reference to the Fig. 12 and Fig. As outlined in Figure 13, polysilicon structures 1312 are fabricated on the barrier layers 118, the cladding layers 838, and the superlattice structures 423 and 425. The fabrication of the polysilicon structures 1312 may include the following sequential operations: (I) Performing an etching process on the structure of Fig. 10, to remove the masking layers 436A and 436B, as in Fig. 12 shown; (II) Deposition of a polysilicon layer (not shown) on the structure of Fig. 12; and (III) performing a structuring process (e.g. a lithography process) on the polysilicon layer to produce the polysilicon structures 1312 as in Fig. Figure 13 shows that in some embodiments, hard mask layers 1336A and 1336B can be produced during the fabrication of the polysilicon structures 1312. In some embodiments, gate spacers 114 can be produced after the fabrication of the polysilicon structures 1312, as shown in Figure 13. Fig. 14A is shown.

[0062] In Fig. In one operation, 335 S / D areas are generated on the fin structures. For example, with reference to the Fig. As outlined in Figures 14A to 16D, S / D regions 110N and 110P are generated on the fin structures 106N and 106P, respectively. The generation of the S / D regions 110N and 110P may include the following sequential operations: (I) Generating S / D openings 1410N and 1410P, as shown in the Fig. 14A, Fig. 14B and Fig. 14D (however, not in the section view of Fig. 14C); and (II) epitaxial growth of semiconductor materials in the S / D openings 1410N and 1410P, as shown in the Fig. 16A, Fig. 16B and Fig. 16D is shown. The generation of the S / D openings 1410N and 1410P can involve etching portions of the superlattice structures 423 and 425 and the cladding layers 838 that are not covered by the gate spacers 114 and the polysilicon structures 1312. Areas 1401, which are shown in Fig. 14D shown, can be covered by the gate spacers 114 and the polysilicon structures 1312.

[0063] In some embodiments, which are in the Fig. As shown in Figures 15A to 15D, internal spacers 115 can be produced between operations (I) and (II) of the manufacturing process for the S / D ranges 110N and 110P.

[0064] The Fig. 14B and Fig. Figure 14D shows shell layer residues 838r that may remain after the creation of the S / D openings 1410N and 1410P due to the nonlinear sidewall profiles 838s of shell layers formed on undoped STI structures with raised top edges 108s (as explained above), if the doped STI structures 108 are not used. The existing shell layer residues 838r can lead to manufacturing defects, such as gaps between the insulating pads 116A and the internal spacers 115, between the insulating pads 116A and the S / D areas 110N, and / or between the insulating pads 116A and the S / D areas 110P. These gaps can then lead to further manufacturing defects during the fabrication of the gate structures 112 in an operation 345.For example, a gate metal filler layer 134 can be deposited in these gaps and cause an electrical short circuit between the S / D areas 110N and 110P and the gate structures 112.

[0065] In some embodiments, after the S / D regions 110N and 110P have been produced, ESLs 120 and ILD layers 122 can be manufactured, as shown in the Fig. 17A to 17D are shown. Areas 1701, which are in Fig. The layers shown in 17D can be covered by the ESLs 120 and the ILD layers 122.

[0066] In Fig. In one operation, 340 gate openings are created. For example, in the Fig. 18A, Fig. 18C and Fig. 18D (but not in the section view of Fig. As shown in Figure 18B), gate openings 1812 are generated around the nanostructured channel regions 124 and 126. The generation of the gate openings 1812 can involve etching the polysilicon structures 1312, the nanostructured layers 424 and 426, and parts of the sheath layers 838 beneath the polysilicon structures 1312. Fig. 18B shows a sectional view along a line B - B of Fig. 18D.

[0067] In Fig. In one operation, 345 gate structures are produced in the gate openings. For example, in the Fig. 19A, Fig. 19C and Fig. 19D (but not in the sectional view of Fig. As shown in Figure 19B), gate structures 112 are fabricated in the gate openings 1812. The fabrication of the gate structures 112 can include the following sequential operations: (I) fabrication of IL layers 128N and 128P on the nanostructured layers 124 and 126, respectively, as shown in the Fig. 19A, Fig. 19C and Fig. 19D is shown; (II) Deposition of dielectric HK gate layers 130N and 130P on the IL layers 128N and 128P respectively, as shown in the Fig. 19A, Fig. 19C and Fig. 19D is shown; (III) Deposition of WFM layers 132N and 132P on the dielectric HK gate layers 130N and 130P respectively, as shown in the Fig. 19A, Fig. 19C and Fig. 19D shown; (IV) Deposition of a gate metal filler layer 134 on the WFM layers 132N and 132P, as shown in the Fig. 19A, Fig. 19C and Fig. 19D; and (V) performing a CMP process to substantially coplanarize the top surfaces of the ILD layers 122, the dielectric HK gate layers 130N and 130P, the WFM layers 132N and 132P, and the gate metal filler layer 134, as shown in the Fig. 19A, Fig. 19C and Fig. 19D is shown. Fig. 19B shows a sectional view along a line B - B of Fig. 19D.

[0068] In some embodiments, operations 315 to 345 can be performed on the structure of Fig. 7E will be carried out to manufacture a semiconductor device 200.

[0069] In the present disclosure, exemplary structures of semiconductor devices (e.g., the GAA-FETs 102N and 102P) with doped STI structures (e.g., the doped STI structures 108 and 208) and exemplary methods (e.g., method 300) for their fabrication are provided. In some embodiments, the doped STI structure may comprise a doped coating (e.g., the doped coating 108A), a dopant source coating (e.g., the dopant source coating 108B), and a doped filler layer (e.g., the doped filler layer 108C). In some embodiments, the fabrication of the doped STI structure may include fabricating a stack with a coating, a dopant source coating, and a filler layer at a higher etch rate than the etch rate of the coating.The fabrication of the doped STI structure can further involve doping the coating and infill layer by annealing the stack to implant dopant material from the dopant source coating into the coating and infill layer. Doping the coating and infill layer can reduce the etch rate difference between the coating and infill layer, and / or modify the etch rates of the coating and infill layer to be essentially equal. This improves the uniformity of the etched surface profiles of the doped STI structure. The improved uniformity of these surface profiles leads to improved linear profiles of structures subsequently fabricated on the doped STI structure, thereby preventing or reducing manufacturing defects in the later fabricated structures.

[0070] In some embodiments, the dopant source coating may have a nitride layer [e.g., silicon dioxide nitride (SiON) or silicon nitride (SiN)], and the doped coating and the doped filler layer may contain nitrogen dopants. In some embodiments, the concentration of nitrogen atoms in the dopant source coating may decrease to a range of about 0 atomic percent to about 5 atomic percent after the annealing process, or from a range of about 5 atomic percent to about 20 atomic percent. In some embodiments, the doped filler layer may have a concentration of nitrogen dopants of about 1 atomic percent to about 5 atomic percent. The concentration of nitrogen dopants in the doped filler layer is higher than the concentration of nitrogen dopants in the doped coating.

[0071] In some embodiments, a method comprises the following: fabricating a fin structure on a substrate; fabricating a superlattice structure with first and second nanostructured layers arranged in an alternating configuration on the fin structure; depositing, in a first deposition process, an oxide coating such that it encloses the superlattice structure and the fin structure; fabricating a dopant source coating on the oxide coating; depositing an oxide filler layer on the dopant source coating in a second deposition process different from the first deposition process; performing a doping process to fabricate a doped oxide coating and a doped oxide filler layer; removing portions of the doped oxide coating, the doped oxide filler layer, and the dopant source coating from the sidewalls of the superlattice structure;and fabricating a gate structure on the fin structure such that it encloses the first nanostructured layers.

[0072] In some embodiments, a method comprises the following: fabricating a fin structure on a substrate; fabricating a superlattice structure with first and second nanostructured layers arranged in an alternating configuration on the fin structure; fabricating a dopant source coating on the superlattice structure and the fin structure in a first deposition process; fabricating a doped filler layer on the dopant source coating in a second deposition process different from the first deposition process; removing portions of the dopant source coating and the doped filler layer from the sidewalls of the superlattice structure; and fabricating a gate structure on the fin structure such that it encloses the first nanostructured layers.

[0073] In some embodiments, a semiconductor device comprises: a substrate; a fin structure on the substrate; a stack of nanostructured layers arranged on a first part of the fin structure; a source / drain region arranged on a second part of the fin structure; a gate structure enclosing each of the nanostructured layers; and an isolation structure arranged on the substrate and adjacent to the fin structure, wherein the isolation structure comprises a doped oxide coating, a nitride coating, and a doped oxide filler layer.

Claims

[1] Procedure, encompassing: Establishing a fin structure (106N, 106P) on a substrate (104); Fabricating a superlattice structure (423, 425) with first and second nanostructured layers (124, 126, 424, 426) arranged in an alternating configuration on the fin structure (106N, 106P); Deposition, in a first deposition process, of an oxide coating such that it encloses the superlattice structure (423, 425) and the fin structure (106N, 106P); Establishing a dopant source coating (108B, 508B, 608B) on the oxide coating; Deposition of an oxide filler layer on the dopant source coating (108B, 508B, 608B) in a second deposition process that is different from the first deposition process; Performing a doping process to produce a doped oxide coating and a doped oxide filler layer; Removal of portions of the doped oxide coating, the doped oxide filler layer, and the dopant source coating (108B, 508B, 608B) from sidewalls of the superlattice structure (423, 425); and fabricating, on the fin structure (106N, 106P), a gate structure (112, 112N, 112P) such that it encloses the first nanostructured layers (124, 126, 424, 426), wherein the production of the dopant source coating (108B, 508B, 608B) includes carrying out a nitration process on the oxide coating; The production of the dopant source coating (108B, 508B, 608B) involves converting an upper part of the oxide coating into a nitride coating. [2] Method according to claim 1, wherein the nitration process is carried out with ammonia or nitrogen gas. [3] Method according to claim 1 or 2, wherein carrying out the nitration process comprises carrying out a thermal nitration process in an environment containing ammonia or nitrogen gas (640) at a temperature of about 700 °C to about 1000 °C, a pressure of about 133 Pa to about 101,000 Pa and for a duration of about 0.5 min to about 60 min. [4] Method according to claim 1 or 2, wherein carrying out the nitration process comprises carrying out a plasma nitration process in an environment containing ammonia or nitrogen gas (640) at a temperature of about 250 °C to about 1000 °C, a pressure of about 133 Pa to about 101,000 Pa, an RF power of about 10 W to about 15,000 W and for a duration of about 0.5 min to about 60 min. [5] Procedure, comprehensive: Establishing a fin structure (106N, 106P) on a substrate (104); Fabricating a superlattice structure (423, 425) with first and second nanostructured layers (124, 126, 424, 426) arranged in an alternating configuration on the fin structure (106N, 106P); Deposition, in a first deposition process, of an oxide coating such that it encloses the superlattice structure (423, 425) and the fin structure (106N, 106P); Establishing a dopant source coating (108B, 508B, 608B) on the oxide coating; Deposition of an oxide filler layer on the dopant source coating (108B, 508B, 608B) in a second deposition process that is different from the first deposition process; Performing a doping process to produce a doped oxide coating and a doped oxide filler layer; Removal of portions of the doped oxide coating, the doped oxide filler layer, and the dopant source coating (108B, 508B, 608B) from sidewalls of the superlattice structure (423, 425); and fabricating, on the fin structure (106N, 106P), a gate structure (112, 112N, 112P) such that it encloses the first nanostructured layers (124, 126, 424, 426), wherein The doping process includes implanting the oxide coating with a first doping concentration and implanting the oxide filler layer with a second doping concentration that is higher than the first doping concentration; and / or The doping process includes implanting the oxide coating and oxide filler layer with nitrogen atoms from the dopant source coating (108B, 508B, 608B); and / or The doping process involves increasing the concentration of nitrogen atoms in the oxide coating and oxide filler layer and decreasing the concentration of nitrogen atoms in the dopant source coating (108B, 508B, 608B). [6] Method according to any of the preceding claims, wherein the production of the dopant source coating (108B, 508B, 608B) comprises depositing the dopant source coating (108B, 508B, 608B) on the oxide coating. [7] Method according to any of the preceding claims, wherein carrying out the doping process comprises carrying out a tempering process on the oxide coating, the dopant source coating (108B, 508B, 608B) and the oxide filler layer. [8] Method according to one of the preceding claims, which, after removing parts of the doped oxide coating, the doped oxide filler layer and the dopant source coating (108B, 508B, 608B) from the side walls of the superlattice structure (423, 425), further comprises producing a sheath layer (838) on the side walls of the superlattice structure (423, 425). [9] Method according to any of the preceding claims, further comprising producing an isolation structure (116) on the doped oxide filling layer. [10] Method according to any of the preceding claims, further comprising replacing a part of the superlattice structure (423, 425) with a source / drain region. [11] Method according to any of the preceding claims, wherein the production of the gate structure (112, 112N, 112P) comprises removing the second nanostructured layers (124, 126, 424, 426). [12] Procedures, including: Establishing a fin structure (106N, 106P) on a substrate (104); Fabricating a superlattice structure (423, 425) with first and second nanostructured layers (124, 126, 424, 426) arranged in an alternating configuration on the fin structure (106N, 106P); Formation of a dopant source coating (108B, 508B, 608B) on the superlattice structure (423, 425) and the fin structure (106N, 106P) in a first deposition process; Producing a doped filler layer (108C, 208B) on the dopant source coating (108B, 508B, 608B) in a second deposition process that is different from the first deposition process; Removal of portions of the dopant source coating (108B, 508B, 608B) and the doped filler layer (108C, 208B) from sidewalls of the superlattice structure (423, 425); and Fabricating a gate structure (112, 112N, 112P) on the fin structure (106N, 106P) such that it encloses the first nanostructured layers (124, 126, 424, 426); wherein fabricating the doped filler layer comprises: Deposition of an oxide filler layer on the dopant source coating (108B, 508B, 608B) in a flowable deposition process; and Implanting nitrogen atoms from the dopant source coating (108B, 508B, 608B) into the oxide filler layer. [13] Method according to claim 12, wherein the production of the dopant source coating (108B, 508B, 608B) comprises depositing a nitride layer on the superlattice structure (423, 425) and the fin structure (106N, 106P) in a non-flowable deposition process. [14] Method according to claim 12 or 13, wherein producing the doped filler layer comprises: Deposition of an undoped oxide filler layer on the dopant source coating (108B, 508B, 608B) in a flowable deposition process; and Performing a tempering process on the undoped oxide fill layer and the dopant source coating (108B, 508B, 608B). [15] Semiconductor device with: a substrate (104); a fin structure (106N, 106P) on the substrate (104); a stack of nanostructured layers (124, 126, 424, 426) arranged on a first part of the fin structure (106N, 106P); a source / drain area located on a second part of the fin structure (106N, 106P); a gate structure (112, 112N, 112P) that encloses each of the nanostructured layers (124, 126, 424, 426); and an insulation structure (116) arranged on the substrate (104) and adjacent to the fin structure (106N, 106P), wherein the insulation structure (116) has a doped oxide coating, a nitride coating and a doped oxide filler layer; wherein The doped oxide coating and the doped oxide filler layer contain nitrogen dopants. [16] Semiconductor device according to claim 15, wherein the doped oxide filler layer has a first doping concentration and the doped oxide coating has a second doping concentration which is different from the first doping concentration. [17] Semiconductor device according to one of claims 15 to 16, further comprising a second insulation structure arranged on the insulation structure (116) and substantially aligned with the doped oxide filler layer.

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