A semiconductor device and a manufacturing method thereof

Abstract

This invention discloses a semiconductor device and its manufacturing method, relating to the field of semiconductor technology, to improve the yield and performance of P-type gate-around transistors (GOTMTs). The semiconductor device includes a semiconductor substrate and a P-type GOTMT formed on the semiconductor substrate. The P-type GOTMT includes a channel region having at least one nanostructure layer. Each nanostructure layer includes a first material portion, a second material portion, and a third material portion, all made of germanium-silicon. The germanium content in the second material portion is greater than the germanium content in the first and third material portions, respectively, and the germanium content in the third material portion is greater than the germanium content in the first material portion. The second material portions are located on both sides of the first material portion along its thickness direction, and the third material portions are located on both sides of the first material portion along its width direction. The manufacturing method of the semiconductor device is used to manufacture the above-described semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a semiconductor device and its manufacturing method. Background Technology

[0002] Gate-around transistors (GOT) include a gate stack structure formed not only on the top and sidewalls of the channel but also on the bottom of the channel. Therefore, compared to planar transistors and fin field-effect transistors, GOT has advantages such as higher gate control capability. Furthermore, for P-type GOT transistors, using high-mobility semiconductor materials such as germanium-silicon or germanium to fabricate the channel region can improve the hole mobility of the P-type GOT transistor.

[0003] However, the P-type gate-around transistors formed using existing manufacturing methods have low yields and poor performance. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device and a method for manufacturing the same, which improves the yield of P-type gate-around transistors and enhances their performance.

[0005] To achieve the above objectives, the present invention provides a semiconductor device comprising: a semiconductor substrate and a P-type gate-around transistor formed on the semiconductor substrate. The channel region of the P-type gate-around transistor includes at least one nanostructure layer. Each nanostructure layer includes a first material portion, a second material portion, and a third material portion, all made of germanium-silicon. The germanium content in the second material portion is greater than the germanium content in the first and third material portions, respectively, and the germanium content in the third material portion is greater than the germanium content in the first material portion. The second material portions are located on both sides of the first material portion along its thickness direction, and the third material portions are located on both sides of the first material portion along its width direction. The thickness direction of the first material portion is parallel to the thickness direction of the semiconductor substrate, and the width direction of the first material portion is parallel to the width direction of the gate stack structure included in the P-type gate-around transistor.

[0006] With the above technical solution, the P-type gate-around transistor formed on the semiconductor substrate in the semiconductor device provided by the present invention includes a channel region having at least one nanostructure. Furthermore, each nanostructure includes a first material portion, a second material portion, and a third material portion, all made of germanium-silicon. Therefore, since germanium-silicon has a higher hole mobility than silicon, when the channel region of the P-type gate-around transistor includes the first, second, and third material portions, it is beneficial to improve the hole mobility of the P-type gate-around transistor, thereby improving its operating performance.

[0007] Furthermore, among the first, second, and third material portions, the second and third material portions, which have a relatively higher germanium content, cover the outer periphery of the first material portion, which has a relatively lower germanium content. In the actual manufacturing process of the P-type gate-around transistor of this invention, when removing the sacrificial layer of silicon material located between the bottom nanostructure of the P-type gate-around transistor and the semiconductor substrate (or between adjacent nanostructures when the P-type gate-around transistor includes at least two nanostructures), the material difference between the second and third material portions, which have a relatively higher germanium content, and the sacrificial layer of silicon material is relatively large. Therefore, the etchant is less likely to damage the nanostructure of the P-type gate-around transistor. This improves the etching selectivity between the nanostructure, which contains high-mobility germanium-silicon materials, and the sacrificial layer of silicon material, thereby improving the yield of the channel region of the P-type gate-around transistor.

[0008] Secondly, compared to the

[100] crystal orientation, the

[110] crystal orientation has a higher hole mobility. Therefore, placing the third material section with a relatively high germanium content on both sides of the first material section along the width direction can further improve the operating performance of the P-type gate ring transistor. Furthermore, compared to the second material section, the third material section has a relatively low germanium content, which can reduce the interface state density of the third material section. Simultaneously, among the first, second, and third material sections, the second material section, with the highest germanium content, is located on both sides of the first material section along the thickness direction. This can increase the hole mobility in the

[100] crystal orientation of the nanostructure, reduce the difference between the hole mobility in the

[100] and

[110] crystal orientations of the nanostructure, and facilitate a higher hole mobility in all regions along the circumferential direction of the nanostructure, thereby further improving the operating performance of the P-type gate ring transistor.

[0009] Secondly, the present invention also provides a method for manufacturing a semiconductor device, the method comprising: first, providing a semiconductor substrate; next, forming a P-type gate-around transistor on the semiconductor substrate. The channel region of the P-type gate-around transistor includes at least one nanostructure layer. Each nanostructure layer includes a first material portion, a second material portion, and a third material portion, all made of germanium-silicon. The germanium content in the material of the second material portion is greater than the germanium content in the materials of the first and third material portions, respectively, and the germanium content in the material of the third material portion is greater than the germanium content in the material of the first material portion. The second material portions are located on both sides of the first material portion along the thickness direction, and the third material portions are located on both sides of the first material portion along the width direction. The thickness direction of the first material portion is parallel to the thickness direction of the semiconductor substrate, and the width direction of the first material portion is parallel to the width direction of the gate stack structure included in the P-type gate-around transistor.

[0010] The beneficial effects of the second aspect and its various implementations in this invention can be found in the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here. Attached Figure Description

[0011] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings:

[0012] Figure 1 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 1 ;

[0013] Figure 2 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 2 ;

[0014] Figure 3 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 3 ;

[0015] Figure 4 A schematic diagram of the semiconductor device during the manufacturing process provided in the embodiments of the present invention. Figure 4 ;

[0016] Figure 5 A longitudinal cross-sectional view along the length of the first fin of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 5 ;

[0017] Figure 6 A longitudinal cross-sectional view along the length of the first fin of the semiconductor device provided in the embodiment of the present invention during the manufacturing process. Figure 6 ;

[0018] Figure 7 Part (1) is a longitudinal cross-sectional view of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process, along the length of the second fin and at the second fin. Figure 7 ; Figure 7 Part (2) is a longitudinal cross-sectional view of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process, along the length of the first fin and at the first fin. Figure 8 ;

[0019] Figure 8 Part (1) is a longitudinal cross-sectional view of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process, along the length of the second fin and at the second fin. Figure 9 ; Figure 8Part (2) is a longitudinal cross-sectional view of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process, along the length of the first fin and at the first fin. Figure 10 ;

[0020] Figure 9 Part (1) is a longitudinal cross-sectional view of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process, along the length of the second fin and at the second fin. Figure 10 one; Figure 9 Part (2) is a longitudinal cross-sectional view of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process, along the length of the first fin and at the first fin. Figure 10 two;

[0021] Figure 10 Part (1) is a longitudinal cross-sectional view of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process, along the length of the second fin and at the second fin. Figure 10 three; Figure 10 Part (2) is a longitudinal cross-sectional view of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process, along the length of the first fin and at the first fin. Figure 10 Four;

[0022] Figure 11 Part (1) is a longitudinal cross-sectional view of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process, along the length of the second fin and at the second fin. Figure 10 five; Figure 11 Part (2) is a longitudinal cross-sectional view of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process, along the length of the first fin and at the first fin. Figure 10 six;

[0023] Figure 12 A longitudinal cross-sectional view of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process, along the width direction of the first fin. Figure 10 seven;

[0024] Figure 13 A longitudinal cross-sectional view of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process, along the width direction of the first fin. Figure 10 eight;

[0025] Figure 14 A longitudinal cross-sectional view of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process, along the width direction of the first fin. Figure 10 Nine;

[0026] Figure 15 A longitudinal cross-sectional view of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process, along the width direction of the first fin. Figure 2 ten;

[0027] Figure 16 A longitudinal cross-sectional view of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process, along the width direction of the first fin. Figure 2 eleven;

[0028] Figure 17 A longitudinal cross-sectional view of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process, along the width direction of the first fin. Figure 2 twelve;

[0029] Figure 18 A longitudinal cross-sectional view of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process, along the width direction of the first fin. Figure 2 Thirteen;

[0030] Figure 19 A longitudinal cross-sectional view of the structure of the semiconductor device provided in the embodiment of the present invention during the manufacturing process, along the width direction of the first fin. Figure 2 fourteen.

[0031] Reference numerals: 11 Semiconductor substrate, 12 Boron heavily doped region, 13 Intrinsic silicon material layer, 14 Stacked material layer, 15 First fin structure, 16 Second fin structure, 17 Shallow trench isolation structure, 18 First fin, 19 Sacrificial layer, 20 Semiconductor stack, 21 First semiconductor layer, 22 Second semiconductor layer, 23 Third semiconductor layer, 24 Second fin, 25 Mask layer, 26 Sacrificial gate, 27 Gate sidewall, 28 Inner sidewall, 29 Source region, 30 Drain region, 31 Interlayer dielectric layer, 32 Intrinsic silicon layer, 33 First material portion, 34 Second material portion, 35 Third material portion, 36 Oxide layer, 37 Silicon protection portion, 38 Nanostructure, 39 Gate stacked structure. Detailed Implementation

[0032] Embodiments of the present disclosure will now be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the disclosure. Furthermore, descriptions of well-known structures and technologies are omitted in the following description to avoid unnecessarily obscuring the concepts of the present disclosure.

[0033] The accompanying drawings illustrate various structural schematics according to embodiments of the present disclosure. These drawings are not to scale, and some details have been enlarged for clarity, and some details may have been omitted. The shapes of the various regions and layers shown in the drawings, as well as their relative sizes and positional relationships, are merely exemplary and may deviate from reality due to manufacturing tolerances or technical limitations. Furthermore, those skilled in the art can design regions / layers with different shapes, sizes, and relative positions as needed.

[0034] In the context of this disclosure, when a layer / element is referred to as being "on top of" another layer / element, the layer / element may be directly on top of the other layer / element, or there may be an intermediate layer / element between them. Additionally, if a layer / element is "on top of" another layer / element in one orientation, then when the orientation is reversed, the layer / element may be "below" the other layer / element. To make the technical problems, technical solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0035] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. "Several" means one or more, unless otherwise explicitly specified.

[0036] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0037] A gate-around transistor (GMT) includes a gate stack structure formed not only on the top and sidewalls of the channel but also on the bottom of the channel. Therefore, compared to planar transistors and fin field-effect transistors, GMTs have advantages such as higher gate control capability. However, the crystal orientation of the channel in existing GMTs is typically

[100] . In this case, the channel of the GMT is conducive to electron transport but not to hole transport. Therefore, since the channel carriers of a P-type transistor are holes, applying a GMT with a

[100] oriented channel to the aforementioned P-type transistor is not conducive to improving the hole mobility of the P-type transistor. In this case, the channel region of the P-type GMT can be manufactured using high-mobility semiconductor materials such as germanium-silicon or germanium to improve the hole mobility of the P-type GMT.

[0038] However, P-type gate-around transistors fabricated using existing methods exhibit low yields and poor performance. Specifically, in actual manufacturing processes, the germanium content in the channel layer of the germanium-silicon high-mobility material formed on the silicon sacrificial layer is typically relatively low to reduce lattice mismatch and improve the lattice quality of the germanium-silicon high-mobility material channel layer. Existing manufacturing methods can only achieve high selectivity etching of the germanium-silicon high-mobility material sacrificial layer relative to the silicon channel layer, but struggle to achieve high selectivity etching of the silicon sacrificial layer relative to the relatively low-germanium-content germanium-silicon high-mobility material channel layer (e.g., an etching selectivity ratio greater than or equal to 100:1). This results in significant manufacturing difficulties for P-type gate-around transistors with channel materials including germanium-silicon high-mobility materials, leading to low yields and hindering further performance improvements.

[0039] To address the aforementioned technical problems, embodiments of the present invention provide a semiconductor device and a method for manufacturing the same. In the semiconductor device provided by these embodiments, a P-type gate-around transistor formed on a semiconductor substrate includes a channel region having at least one nanostructure layer. Each nanostructure layer includes a first material portion, a second material portion, and a third material portion, all made of germanium-silicon. Furthermore, the germanium content in the second material portion is greater than the germanium content in the first and third material portions, respectively, and the germanium content in the third material portion is greater than the germanium content in the first material portion. Simultaneously, the second material portions are located on both sides of the first material portion along its thickness direction, and the third material portions are located on both sides of the first material portion along its width direction, thereby improving the yield and operating performance of the P-type gate-around transistor.

[0040] Firstly, such as Figure 19As shown, the semiconductor device provided in this embodiment of the invention includes a semiconductor substrate 11 and a P-type gate-around transistor formed on the semiconductor substrate 11. The channel region of the P-type gate-around transistor includes at least one nanostructure 38. Each nanostructure 38 includes a first material portion 33, a second material portion 34, and a third material portion 35, all made of germanium-silicon. The germanium content in the material of the second material portion 34 is greater than the germanium content in the materials of the first material portion 33 and the third material portion 35, respectively, and the germanium content in the material of the third material portion 35 is greater than the germanium content in the material of the first material portion 33. The second material portion 34 is located on both sides of the first material portion 33 along the thickness direction, and the third material portion 35 is located on both sides of the first material portion 33 along the width direction. The thickness direction of the first material portion 33 is parallel to the thickness direction of the semiconductor substrate 11, and the width direction of the first material portion 33 is parallel to the width direction of the gate stack structure 39 included in the P-type gate-around transistor.

[0041] Specifically, the aforementioned semiconductor substrate can be a silicon substrate or a silicon-on-insulator (SOI) or other semiconductor substrates on which no structure is formed.

[0042] Alternatively, a semiconductor substrate with certain structures can be formed on the semiconductor substrate. Specifically, the structures formed on the semiconductor substrate can be determined according to the actual application scenario, and are not specifically limited here. For example, when the semiconductor device provided in the embodiments of the present invention is applied to a second or higher layer of semiconductor devices in an integrated circuit, the semiconductor substrate includes a semiconductor substrate, at least one layer of semiconductor devices located below the semiconductor device provided in the embodiments of the present invention, and an interlayer dielectric layer that isolates different layers of semiconductor devices.

[0043] Structurally, the aforementioned P-type gate-around transistor can include a source region, a drain region, a channel region, and a gate stack structure. The channel region of the P-type gate-around transistor is located between the source and drain regions. The gate stack structure of the P-type gate-around transistor surrounds the outer periphery of the channel region, each layer having a nanostructure. The nanostructure of the P-type gate-around transistor may have only one nanostructure layer. Alternatively, as... Figure 19 As shown, the channel region of the P-type gate-around transistor may include at least two nanostructures 38 spaced apart along the thickness direction of the semiconductor substrate 11. Additionally, the gate stack structure 39 of the P-type gate-around transistor may include a gate dielectric layer surrounding each nanostructure 38 and a gate electrode formed on the gate dielectric layer.

[0044] In terms of device type, a P-type gate ring transistor can be a junctionless gate ring transistor, meaning that the conductivity types of the source and drain regions of a P-type gate ring transistor are the same as those of the channel region; or a P-type gate ring transistor can be a junction gate ring transistor, meaning that the conductivity types of the source and drain regions of a P-type gate ring transistor are opposite to those of the channel region.

[0045] In terms of materials, the source and drain regions of a P-type gate-around transistor can be made of semiconductor materials such as silicon, silicon-germanium, or germanium. The gate dielectric layer of a P-type gate-around transistor can be made of dielectric materials such as HfO2, ZrO2, TiO2, or Al2O3. The gate material of a P-type gate-around transistor can be conductive materials such as TiN, TaN, or TiSiN.

[0046] As for the materials of each nanostructure layer included in the P-type gate ring transistor, the specific germanium content in the materials of the first material section, the second material section and the third material section can be determined according to actual needs, as long as the germanium content in the material of the second material section is greater than the germanium content in the materials of the first material section and the third material section, and the germanium content in the material of the third material section is greater than the germanium content in the material of the first material section.

[0047] For example, the germanium content in the material of the first material section can be greater than or equal to 10% and less than or equal to 30%. For instance, the germanium content in the material of the first material section can be 10%, 15%, 20%, 25%, or 30%. In this case, such as... Figures 12 to 14As shown, the first material portion 33 is obtained by performing a concentrated oxidation process on a portion of the first semiconductor layer 21. The first material portion 33 is the middle portion of the remaining first semiconductor layer 21 along its width after the concentrated oxidation process, while the third material portion 35 is the two side edge portions of the remaining first semiconductor layer 21 along its width after the concentrated oxidation process. Furthermore, the germanium content in the material of the first material portion 33 is approximately the same as the germanium content in the material of the first semiconductor layer 21. Based on this, the germanium content in the material of the first material portion 33 is within the aforementioned range. This prevents a situation where a low germanium content in the material of the first material portion 33 leads to a low germanium content in the material of the first semiconductor layer 21 used to manufacture both the first material portion 33 and the third material portion 35, resulting in a lower improvement in the germanium content of the material of the third material portion 35 after a certain period of concentrated oxidation. This facilitates increasing the etching selectivity between the third material portion 35 and the third semiconductor layer 23, further improving the yield of the P-type gate-around transistor. Simultaneously, it can prevent the extended concentration oxidation process time for obtaining a third material section 35 with a higher germanium content from causing the obtained nanostructure size to fail to meet operational requirements, thereby further improving the yield of the P-type gate ring transistor. Furthermore, by ensuring the germanium content in the first material section 33 is within the aforementioned range, it can prevent a higher germanium content in the first semiconductor layer 21 due to a higher germanium content in the first material section 33, which would result in a greater degree of lattice mismatch in the formed first semiconductor layer 21, thus improving the formation quality of the channel region included in the P-type gate ring transistor.

[0048] For example, the germanium content in the material of the third material section can be greater than or equal to 30% and less than or equal to 50%. For instance, the germanium content in the material of the third material section can be 30%, 35%, 40%, 45%, or 50%, etc. The beneficial effects in this case can be referred to the preceding text, and will not be repeated here.

[0049] For example, the germanium content in the material of the second material section can be greater than or equal to 35% and less than or equal to 70%. For instance, the germanium content in the material of the second material section can be 35%, 40%, 50%, 60%, or 70%, etc. The beneficial effects in this case are similar to the beneficial effects of the germanium content in the material of the third material section being greater than or equal to 30% and less than or equal to 50% as described above, and will not be repeated here.

[0050] For example, the germanium content in the material of the first material section can be 20%, the germanium content in the material of the second material section can be 60%, and the germanium content in the material of the third material section can be 40%.

[0051] In terms of thickness, the embodiments of the present invention do not specifically limit the thickness of the second material portion and the third material portion.

[0052] For example, the thickness of the second material portion and / or the third material portion can be greater than or equal to 0.5 nm and less than or equal to 1 nm. For example, the thickness of the second material portion can be 0.5 nm, 0.6 nm, 0.7 nm, 0.8 nm, 0.9 nm, or 1 nm, etc. For example, the thickness of the third material portion can be 0.5 nm, 0.6 nm, 0.7 nm, 0.8 nm, 0.9 nm, or 1 nm, etc. In this case, the thickness of the second material portion within the above range can prevent the improvement in hole mobility in the P-type gate ring transistor from being too small, and prevent the etchant used to etch the remaining third semiconductor layer in the first fin from causing damage to the nanostructures included in the P-type gate ring transistor. In addition, it can also prevent the nanostructures included in the P-type gate ring transistor from not meeting the requirements due to the longer concentration oxidation process of the remaining first fins caused by the thickness of the second material portion, thereby further improving the yield of the P-type gate ring transistor. Furthermore, the beneficial effects of the thickness of the third material section within the aforementioned range can be referred to the analysis of the beneficial effects of the thickness of the second material section within the aforementioned range described above, and will not be repeated here.

[0053] Specifically, such as Figure 19 As shown, the thickness of the second material section 34 can be the same as or different from the thickness of the third material section 35.

[0054] In one example, such as Figure 19 As shown, in each nanostructure 38 of the channel region of the aforementioned P-type gate-ring transistor, the surface of the second material portion 34 along the width direction of the first material portion 33 is recessed inward relative to the surface of the third material portion 35 away from the first material portion 33. Based on this, in practical applications, the germanium content in the material of the second semiconductor layer used to manufacture the second material portion 34 is higher than the germanium content in the material of the first semiconductor layer used to manufacture the first material portion 33 and the third material portion 35. Therefore, when the remaining first fin is subjected to concentrated oxidation treatment, the oxidation rate of the remaining second semiconductor layer with a relatively higher germanium content is greater, while the oxidation rate of the remaining first semiconductor layer with a relatively lower germanium content is smaller. Therefore, in the same nanostructure 38, the surface of the second material portion 34 formed based on the aforementioned second semiconductor layer and first semiconductor layer is recessed inward relative to the surface of the third material portion 35 away from the first material portion 33 along the width direction of the first material portion 33. At this time, as... Figure 19 As shown, each nanostructure 38 of the P-type gate ring transistor has an inwardly recessed chamfered structure, which can improve the problem of electric field concentration at the four corners of the conventional rectangular cross-section nanostructure 38 to a certain extent, and further improve the working performance of the P-type gate ring transistor.

[0055] The distance by which the surface of the second material part is recessed inward relative to the surface of the third material part away from the first material part along the width direction can be determined based on the difference in germanium content in the materials of the first semiconductor layer and the second semiconductor layer, as well as the processing conditions of the concentrated oxidation treatment during the actual manufacturing process. No specific limitation is made here.

[0056] For example, such as Figure 19 As shown, the distance by which the surface of the second material portion 34 is recessed inward relative to the surface of the third material portion 35 away from the first material portion 33 along the width direction can be greater than 0 and less than or equal to 1 nm. For example, the above distance can be 0.3 nm, 0.5 nm, 0.7 nm, 0.9 nm, or 1 nm, etc.

[0057] In one example, such as Figure 19 As shown, in the channel region of the aforementioned P-type gate-around transistor, each nanostructure 38 may further include a silicon protection portion 37. This silicon protection portion 37 covers the outer periphery of the second material portion 34 and the third material portion 35. In this case, as... Figure 15 As shown, after removing the remaining third semiconductor layer and the remaining sacrificial layer in the first fin, the silicon protection portion 37 can be formed to improve the problem of deteriorated interface states between the nanostructure 38 and the gate dielectric layer due to the high germanium content in the materials of the second material portion 34 and the third material portion 35, thereby further improving the yield and operating performance of the P-type gate ring transistor.

[0058] Specifically, the thickness of the aforementioned silicon protective portion can be determined according to actual needs, as long as it can be applied to the semiconductor device provided in the embodiments of the present invention.

[0059] In some cases, such as Figure 11 Part (2) and Figure 19 As shown, the P-type gate-around transistor may further include a gate sidewall 27, an inner sidewall 28, and an interlayer dielectric layer 31. The gate sidewall 27 of the P-type gate-around transistor is located at least on both sides of the gate stack structure 39 along its length, suppressing leakage current. The inner sidewall 28 of the P-type gate-around transistor is located between the gate stack structure 39 and the source region 29, and between the gate stack structure 39 and the drain region 30, limiting the length of the gate stack structure 39 and helping to reduce parasitic capacitance between the gate and source regions 29, and between the gate and drain regions 30. The interlayer dielectric layer 31 of the P-type gate-around transistor covers the semiconductor substrate 11, and the top of the interlayer dielectric layer 31 is flush with the top of the gate stack structure 39. Specifically, the materials of the gate sidewall 27, inner sidewall 28, and interlayer dielectric layer 31 can be insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride.

[0060] In one example, such as Figure 19 As shown, the semiconductor device may further include N-type gate-around transistors (GMT-AOTs), with N-type and P-type GMT-AOTs spaced apart on the semiconductor substrate 11 along a direction parallel to the surface of the substrate 11. Furthermore, the material of the channel region included in the N-type GMT-AOT is different from at least a portion of the material of the channel region included in the P-type GMT-AOT. The nanostructures 38 in each layer of the channel region included in the N-type GMT-AOT and the nanostructures 38 in the channel region included in the P-type GMT-AOT are staggered along the thickness direction of the semiconductor substrate 11.

[0061] Specifically, the aforementioned N-type gate-around transistor may include a source region, a drain region, at least one nanostructure layer, and a gate stack structure. The relative positions of the structures within the N-type gate-around transistor can be referenced to the relative positions of the structures in the previously described P-type gate-around transistor. Furthermore, the materials of the source region, drain region, and gate stack structure within the N-type gate-around transistor can be referenced to the materials of the source region, drain region, and gate stack structure within the previously described P-type gate-around transistor, and will not be repeated here.

[0062] Furthermore, in N-type gate-around transistors, the nanostructures in each layer of the channel region are staggered with the nanostructures of the same number of layers in the channel region of P-type gate-around transistors along the thickness direction of the semiconductor substrate. For example: Figure 19 As shown, the first, second, and third nanostructures 38 in the channel region of the N-type gate-around transistor are staggered with the first, second, and third nanostructures 38 in the channel region of the P-type gate-around transistor along the thickness direction of the semiconductor substrate 11. In this case, during actual manufacturing, the third semiconductor layer used to manufacture the nanostructures 38 of the N-type gate-around transistor and the stacked layers of the first and second semiconductor layers used to manufacture the nanostructures 38 of the P-type gate-around transistor can serve as sacrificial layers and channel layers respectively, thus simultaneously forming both N-type and P-type gate-around transistors on the semiconductor substrate 11. This improves the manufacturing efficiency of the semiconductor device and reduces its manufacturing cost.

[0063] As for the material of the channel region included in the N-type gate ring transistor, it can be a semiconductor material such as silicon or germanium silicon with low germanium concentration.

[0064] As for the device type of the N-type gate ring transistor, it can be a junctionless gate ring transistor or a junction gate ring transistor.

[0065] In one example, such as Figure 19As shown, in the case where the semiconductor device includes a P-type gate-around transistor and an N-type gate-around transistor, the portion of the semiconductor substrate 11 below the channel region of the P-type gate-around transistor includes a heavily boron-doped region 12, the top of which contacts a portion of the gate stack structure 39 of the P-type gate-around transistor. Furthermore, the semiconductor device also includes an intrinsic silicon layer 32 located between the semiconductor substrate 11 and the channel region of the N-type gate-around transistor. The thickness of the intrinsic silicon layer 32 is greater than or equal to the thickness of the gate stack structure 39 of the P-type gate-around transistor. In this case, the intrinsic silicon layer 32 located between the semiconductor substrate 11 and the channel region of the N-type gate-around transistor can isolate the gate stack structure 39 of the N-type gate-around transistor from the semiconductor substrate 11, suppressing leakage current. Additionally, in actual manufacturing processes, when fabricating the N-type gate-around transistor on the semiconductor substrate 11, the P-type gate-around transistor is fabricated simultaneously to improve manufacturing efficiency. Based on this, when the semiconductor device also includes an intrinsic silicon layer 32 located between the semiconductor substrate 11 and the channel region included in the N-type gate ring transistor, during the manufacturing process of the P-type gate ring transistor, a corresponding intrinsic silicon layer 32 (i.e., the sacrificial layer hereinafter) is also formed on the portion of the semiconductor substrate 11 corresponding to the channel region included in the P-type gate ring transistor. Figures 14 to 19 As shown, the presence of the intrinsic silicon layer 32 ensures that the nanostructure 38 of the P-type gate-around transistor can be properly released, and that the gate stack structure 39 can surround the outer periphery of the nanostructure 38, thereby improving the yield of the P-type gate-around transistor. Furthermore, after the portion of the semiconductor substrate 11 located below the channel region of the P-type gate-around transistor is heavily boron-doped, the etching rate of the etchant on this portion of the semiconductor substrate 11 is reduced, or even the etchant does not affect this portion of the semiconductor substrate 11 located below the channel region of the P-type gate-around transistor. This prevents the portion of the semiconductor substrate 11 located below the channel region of the P-type gate-around transistor from being over-etched during the release of the nanostructure 38, thus improving the yield of the semiconductor device.

[0066] Specifically, the boron doping concentration in the aforementioned heavily boron-doped region can be determined based on the actual application scenario, and is not specifically limited here. For example, the boron doping concentration in the heavily boron-doped region can be greater than or equal to 1E18cm⁻¹. -3 And less than or equal to 5E20cm -3 .

[0067] In one example, such as Figure 19 As shown, the semiconductor device provided in this embodiment of the invention may further include a shallow trench isolation structure 17 formed on the semiconductor substrate 11 to isolate different active regions of the semiconductor substrate 11 and suppress leakage current. The thickness and material of the shallow trench isolation structure 17 can be determined according to actual needs, as long as it can be applied to the semiconductor device provided in this embodiment of the invention.

[0068] When the above technical solution is adopted, such as Figure 19 As shown, in the semiconductor device provided by this embodiment of the invention, the P-type gate-around transistor formed on the semiconductor substrate 11 includes a channel region having at least one nanostructure 38. Furthermore, each nanostructure 38 includes a first material portion 33, a second material portion 34, and a third material portion 35, all made of germanium-silicon. Based on this, since germanium-silicon material has a higher mobility than silicon, when the channel region of the P-type gate-around transistor includes the first material portion 33, the second material portion 34, and the third material portion 35, all made of germanium-silicon, it is beneficial to improve the hole mobility of the P-type gate-around transistor, thereby improving its operating performance. Additionally, as... Figures 1 to 19 As shown, among the first material section 33, the second material section 34, and the third material section 35, the second material section 34 and the third material section 35, which have a relatively high germanium content, cover the outer periphery of the first material section 33, which has a relatively low germanium content. In the actual manufacturing process of the P-type gate-around transistor in this embodiment, when removing the sacrificial layer 19 of silicon material located between the bottom nanostructure 38 of the P-type gate-around transistor and the semiconductor substrate 11 (when the P-type gate-around transistor includes at least two nanostructures 38, it also includes the nanostructures 38 located between two adjacent layers of the P-type gate-around transistor) using an etchant, because the material difference between the second material section 34 and the third material section 35, which have a relatively high germanium content, and the sacrificial layer 19 of silicon material is relatively large, the etchant is unlikely to damage the nanostructures 38 of the P-type gate-around transistor. This improves the etching selectivity between the nanostructures 38, which contain high-mobility germanium-silicon materials, and the sacrificial layer 19 of silicon material, thus improving the yield of the channel region included in the P-type gate-around transistor. Secondly, compared to the

[100] crystal orientation, the

[110] crystal orientation has a higher hole mobility. Therefore, by placing the third material portion 35, which has a relatively high germanium content, on both sides of the first material portion 33 along the width direction, the operating performance of the P-type gate ring transistor can be further improved. Furthermore, compared to the second material portion 34, the germanium content in the material of the third material portion 35 is relatively low, which can reduce the interface state density of the third material portion 35. At the same time, among the first material portion 33, the second material portion 34, and the third material portion 35, the second material portion 34, which has the highest germanium content, is located on both sides of the first material portion 33 along the thickness direction. This can improve the hole mobility of the

[100] crystal orientation in the nanostructure 38, reduce the difference between the hole mobility of the

[100] crystal orientation and the

[110] crystal orientation in the nanostructure 38, and facilitate the formation of a high hole mobility in each region along the circumference of the nanostructure 38, thereby further improving the operating performance of the P-type gate ring transistor.

[0069] Secondly, embodiments of the present invention provide a method for manufacturing a semiconductor device. The following will describe a method based on... Figures 1 to 19 The illustrated perspective view or cross-sectional view describes the manufacturing process. Specifically, the method for manufacturing this semiconductor device includes the following steps:

[0070] First, a semiconductor substrate is provided. The specific structure and materials of this semiconductor substrate can be referred to in the previous text, and will not be repeated here.

[0071] Next, as Figure 19 As shown, a P-type gate-around transistor is formed on a semiconductor substrate 11. The channel region of the P-type gate-around transistor includes at least one nanostructure 38. Each nanostructure 38 includes a first material portion 33, a second material portion 34, and a third material portion 35, all made of germanium-silicon. The germanium content in the material of the second material portion 34 is greater than that in the materials of the first material portion 33 and the third material portion 35, respectively, and the germanium content in the material of the third material portion 35 is greater than that in the material of the first material portion 33. The second material portion 34 is located on both sides of the first material portion 33 along the thickness direction, and the third material portion 35 is located on both sides of the first material portion 33 along the width direction. The thickness direction of the first material portion 33 is parallel to the thickness direction of the semiconductor substrate 11, and the width direction of the first material portion 33 is parallel to the width direction of the gate stack structure 39 included in the P-type gate-around transistor.

[0072] For details regarding the specific structure and materials of the aforementioned P-type gate-around transistor, please refer to the previous text; they will not be repeated here.

[0073] For example, forming a P-type gate-around transistor on a semiconductor substrate may include the following steps:

[0074] like Figure 4 As shown, at least a first fin 18 is formed on a semiconductor substrate 11. Along the thickness direction of the semiconductor substrate 11, the first fin 18 encloses a sacrificial layer 19 and at least one semiconductor stack 20 located on the sacrificial layer 19. Each semiconductor stack 20 includes a first semiconductor layer 21, a second semiconductor layer 22, and a third semiconductor layer 23. The second semiconductor layer 22 is located on both sides of the first semiconductor layer 21 along the thickness direction, and the third semiconductor layer 23 is located on the stacked first semiconductor layer 21 and second semiconductor layer 22. The materials of the first semiconductor layer 21 and the second semiconductor layer 22 are both germanium-silicon, and the germanium content in the material of the second semiconductor layer 22 is greater than the germanium content in the material of the first semiconductor layer 21. The materials of the sacrificial layer 19 and the third semiconductor layer 23 are different from those of the first semiconductor layer 21 and the second semiconductor layer 22.

[0075] Specifically, the first semiconductor layer is used to manufacture the first and third material portions in the P-type gate-around transistor. Therefore, the germanium content in the first semiconductor layer can be determined based on the requirements for the germanium content in the first and third material portions in the actual application scenario. Similarly, the second semiconductor layer is used to manufacture the second material portion in the P-type gate-around transistor. Therefore, the germanium content in the second semiconductor layer can be determined based on the requirements for the germanium content in the second material portion in the actual application scenario.

[0076] The material of the third semiconductor layer can be any semiconductor material different from the materials of the first and second semiconductor layers, as long as it can be applied to the manufacturing method of the semiconductor device provided in the embodiments of the present invention.

[0077] For example, if the manufactured semiconductor device further includes N-type ring-gate transistors spaced apart from the P-type ring-gate transistors along a direction parallel to the surface of the semiconductor substrate, and the manufacturing method further includes forming the N-type ring-gate transistors on the semiconductor substrate, the third semiconductor layer can be used to manufacture the nanostructures included in the N-type ring-gate transistors. In this case, the material of the third semiconductor layer is the same as the material of the nanostructures included in the N-type ring-gate transistors. For example, the material of the third semiconductor layer can be silicon.

[0078] Regarding the sacrificial layer, its material can be any semiconductor material different from the materials of the first and second semiconductor layers, as long as it can be applied to the manufacturing method of the semiconductor device provided in this embodiment of the invention. The material of the sacrificial layer can be the same as or different from the material of the third semiconductor layer. When the material of the sacrificial layer is the same as the material of the third semiconductor layer, the same etchant can be used to simultaneously remove the remaining sacrificial layer and the third semiconductor layer in the first fin, improving manufacturing efficiency while reducing the difficulty of releasing the nanostructures included in the P-type gate-ring transistor.

[0079] In the actual manufacturing process, such as Figure 2 As shown, a multilayer material layer 14 covering the semiconductor substrate 11 can be formed using processes such as epitaxy. This multilayer material layer 14 is used to fabricate the semiconductor multilayer 20 in the first fin. Next, as... Figure 3 As shown, photolithography and etching processes can be used to pattern at least the stacked material layers and a portion of the semiconductor substrate 11 to form at least a first fin structure 15 on the semiconductor substrate 11. The etching depth of the semiconductor substrate 11 can be determined based on the specific structure of the manufactured semiconductor device. Next, as... Figure 4As shown, a shallow trench isolation structure 17 covering the semiconductor substrate 11 can be formed using processes such as deposition and etching. In this case, the portion of the first fin structure 15 exposed outside the shallow trench isolation structure 17 is the first fin portion 18. The top height of the shallow trench isolation structure 17 is less than the bottom height of the sacrificial layer 19; the portion located below the remaining stacked material layers and exposed outside the shallow trench isolation structure 17 is the sacrificial layer 19.

[0080] Specifically, the aforementioned stacked material layer can be formed directly on the semiconductor substrate. Alternatively, if the manufactured semiconductor device also includes an N-type gate-around transistor, and the gate stack structure of the N-type gate-around transistor has an intrinsic silicon layer between it and the semiconductor substrate, and the portion of the semiconductor substrate below the channel region of the P-type gate-around transistor is a heavily boron-doped region, the aforementioned stacked material layer can be formed beforehand, such as... Figure 1 As shown, using processes such as ion implantation, at least the portion of the semiconductor substrate 11 located below the channel region included in the P-type gate ring transistor is subjected to heavy boron doping to form a boron-doped region 12; then, as... Figure 2 As shown, an intrinsic silicon material layer 13 is formed on the semiconductor substrate 11 using processes such as epitaxy. In this case, as... Figure 3 As shown, the multilayer material layer, the intrinsic silicon material layer, and a portion of the semiconductor substrate 11 need to be patterned. After patterning, a first fin structure 15 and a second fin structure 16 with identical structures are formed on the semiconductor substrate 11. Simultaneously, as... Figure 4 As shown, after the shallow trench isolation structure 17 is formed, the portion of the second fin structure 16 exposed outside the shallow trench isolation structure 17 is the second fin portion 24. Furthermore, the second fin portion 24 has the same structure as the first fin portion 18.

[0081] Regarding the etching depth of the semiconductor substrate during the patterning process, without the aforementioned intrinsic silicon material layer, the etching depth of the semiconductor substrate is greater than or equal to the sum of the thicknesses of the shallow trench isolation structure and the sacrificial layer. However, with the aforementioned intrinsic silicon material layer formed, the etching depth of the semiconductor substrate only needs to be greater than or equal to the thickness of the shallow trench isolation structure to ensure that the gate stack structure included in the P-type ring gate transistor can properly surround the outer periphery of the underlying nanostructure.

[0082] Regarding the specific structure of the sacrificial layer, as mentioned above, in the absence of the aforementioned intrinsic silicon material layer, the portion below the remaining stacked material layers of the semiconductor substrate and exposed outside the shallow trench isolation structure constitutes the sacrificial layer, which is integrally formed with the semiconductor substrate. However, in the presence of the aforementioned intrinsic silicon material layer, the portion below the remaining stacked material layers of the intrinsic silicon material layer and exposed outside the shallow trench isolation structure constitutes the sacrificial layer.

[0083] After at least the first fin mentioned above has been formed, such as Figure 5 As shown, a mask layer 25 is formed that spans at least a portion of the first fin 18.

[0084] Specifically, the structure and material of the mask layer can be determined according to the actual application scenario, as long as it has a masking function. For example, the mask layer can be a photoresist mask layer. Another example is... Figure 5 As shown, the mask layer 25 may include a sacrificial gate 26 and gate sidewalls 27 located at least on both sides of the sacrificial gate 26 along the length direction.

[0085] Specifically, the formation process of the mask layer can be determined based on its structure and material. For example, taking a mask layer consisting of a sacrificial gate and gate sidewalls as an example, a deposition process can be used to form a material layer covering the already formed structure; then, the material layer is sequentially planarized and patterned to obtain the sacrificial gate. Next, a deposition process is used to form sidewall material covering the already formed structure, and then processes such as dry etching are used to remove the portion of the sidewall material covering the sacrificial gate sidewalls to obtain the gate sidewalls.

[0086] The specific formation range of the mask layer can be determined based on the structure of the manufactured semiconductor device. Specifically, when the semiconductor device includes only a P-type gate-around transistor, the mask layer only spans the portion of the first fin used to manufacture the P-type gate-around transistor. However, when the semiconductor device includes both an N-type gate-around transistor and a P-type gate-around transistor, the mask layer spans the portion of the first fin used to manufacture the P-type gate-around transistor and the portion of the second fin used to manufacture the N-type gate-around transistor.

[0087] Next, as Figure 6 As shown, dry etching or wet etching processes can be used to remove the portion of the first fin exposed outside the mask layer 25.

[0088] Next, in the case where the manufactured P-type gate-around transistor also includes inner sidewalls, such as Figure 7 As shown in section (2), dry etching or wet etching processes can be used to laterally etch the remaining third semiconductor layer 23 and the remaining sacrificial layer 19 along their length edges. Then, as... Figure 8 As shown in section (2), processes such as deposition and etching can be used to form inner sidewalls 28 that fill the remaining portions of each third semiconductor layer 23 and the remaining portions of the sacrificial layer 19 along both sides of the length direction. The material of the inner sidewalls 28 can be referred to above.

[0089] It should be noted that if the manufactured P-type gate ring transistor does not include the aforementioned inner sidewall, then the aforementioned inner sidewall formation operation is not required.

[0090] Next, as Figure 9 As shown in part (2), epitaxial processes can be used to form the source region 29 and drain region 30 of the P-type ring gate transistor on both sides of the remaining first fin along the length direction.

[0091] Next, as Figure 10 As shown in section (2), an interlayer dielectric layer 31 covering the semiconductor substrate 11 can be formed by processes such as deposition and chemical mechanical polishing. The top of the interlayer dielectric layer 31 is flush with the top of the mask layer 25, and the material of the interlayer dielectric layer 31 can be silicon oxide or silicon nitride.

[0092] Next, as Figure 11 Part (2) of the text, and Figure 12 As shown, at least part of the mask layer is removed.

[0093] Specifically, dry etching or wet etching processes can be used to completely remove the portion of the mask layer covering the remaining first fin. Alternatively, if the mask layer also includes a sacrificial gate and gate sidewalls, such as... Figure 11 Part (2) of the text, and Figure 12 As shown, it is only necessary to remove the portion of the sacrificial gate that covers the remaining first fin.

[0094] Next, as Figure 13 As shown, the remaining first fin is subjected to a concentrated oxidation process to form a first material portion 33 in the middle portion of each remaining first semiconductor layer along the width direction, to form a third material portion 35 in the two side edge portions of each remaining first semiconductor layer along the width direction, and to form a corresponding second material portion 34 in each remaining second semiconductor layer.

[0095] Specifically, the processing conditions for the concentrated oxidation treatment can be determined based on the materials of the first and second semiconductor layers, the materials and thicknesses of the first, second, and second material sections, and the actual application scenario; no specific limitations are made here. Additionally, as... Figure 13 As shown, an oxide layer 36 is formed on the outer periphery of the remaining first fin after the above-mentioned concentration and oxidation treatment.

[0096] Next, as Figure 14 As shown, processes such as wet etching can be used to remove the oxide layer formed on the outer periphery of the remaining first fin after concentrated oxidation treatment.

[0097] Next, as Figure 15 As shown, wet etching and dry etching processes can be used to remove the remaining third semiconductor layer and sacrificial layer in each of the first fins to obtain the nanostructure 38 included in the P-type gate ring transistor.

[0098] It should be noted that, as Figure 16As shown, in the case where each nanostructure 38 in the manufactured P-type gate ring transistor also includes a silicon protection portion 37, after removing the remaining third semiconductor layer and sacrificial layer in the first fin, it is necessary to use epitaxial processes to form the silicon protection portion 37 surrounding the second material portion 34 and the third material portion 35 in order to obtain the nanostructure 38 included in the P-type gate ring transistor.

[0099] Next, as Figure 17 As shown, atomic layer deposition and other processes can be used to form a gate stack structure 39 surrounding each nanostructure layer 38 included in the P-type gate ring transistor. The specific structure and materials of this gate stack structure 39 can be referred to the preceding text.

[0100] It should be noted that when the manufactured semiconductor device also includes an N-type gate ring transistor and the above-mentioned second fin is formed on the semiconductor substrate, the inner wall, source region, drain region and gate stack structure of the P-type gate ring transistor need to be formed under the masking effect of the corresponding mask layer, and the above-mentioned concentration oxidation process needs to be performed under the masking effect of the corresponding mask layer; the corresponding mask layer covers the area of ​​the semiconductor substrate where the N-type gate ring transistor is formed.

[0101] Furthermore, when the manufactured semiconductor device also includes an N-type gate-around transistor, after forming a mask layer spanning a portion of the first fin and a portion of the second fin, and before removing at least a portion of the mask layer, the semiconductor device manufacturing method further includes the step of: Figure 6 As shown, wet etching or dry etching processes are used to remove the portion of the second fin exposed outside the mask layer 25. Next, as... Figure 9 As shown in part (1), using epitaxial processes, the source region 29 and drain region 30 of the N-type ring gate transistor are formed only on both sides of the remaining second fin along the length direction.

[0102] Of course, in the case where the manufactured N-type gate-around transistor also includes inner sidewalls, after removing the portion of the second fin exposed outside the mask layer, as... Figure 7 As shown in part (1), dry etching or wet etching processes can be used to selectively etch only the remaining first semiconductor layer 21 and the remaining second semiconductor layer 22 in the second fin. Then, as... Figure 8As shown in part (1), processes such as deposition and etching can be used to form inner sidewalls 28 only on both sides along the length direction of the remaining portions of each first semiconductor layer 21 and each second semiconductor layer 22 in the second fin. Because the germanium content in the materials of the first semiconductor layer 21 and the second semiconductor layer 22 is different, when forming the notch for filling the inner sidewall 28 of the N-type gate ring transistor using an etchant, the etching rate of the remaining first semiconductor layer 21 in the second fin is less than the etching rate of the remaining second semiconductor layer 22. Based on this, the inner sidewall of the inner sidewall 28 of the N-type gate ring transistor is recessed inwards relative to the edge portion along its own thickness direction at the middle portion.

[0103] In addition, after forming the source and drain regions of the N-type gate ring transistor, such as Figure 10 As shown in portions (1) and (2), an interlayer dielectric layer 31 can be formed covering the region of the semiconductor substrate 11 where the N-type gate ring transistor is formed. The top of this interlayer dielectric layer 31 is flush with the top of the mask layer 25. Then, as... Figure 18 As shown, at least a portion of the mask layer, as well as the remaining portions of each first semiconductor layer and each second semiconductor layer in the second fin, can be removed to obtain the nanostructure 38 included in the N-type gate ring transistor. Then, as... Figure 19 As shown, atomic layer deposition and other processes can be used to form a gate stack structure 39 surrounding each nanostructure 38 included in the N-type ring gate transistor.

[0104] It should also be noted that, in the semiconductor device manufacturing method provided in the embodiments of the present invention, when the semiconductor device further includes an N-type gate ring transistor, the inner wall, source region, drain region, and nanostructure of the P-type gate ring transistor may be formed first under the masking effect of the corresponding mask layer, and then the corresponding structure of the N-type gate ring transistor may be formed; alternatively, the inner wall, source region, drain region, and nanostructure of the N-type gate ring transistor may be formed first under the masking effect of the corresponding mask layer, and then the corresponding structure of the P-type gate ring transistor may be formed.

[0105] The beneficial effects of the second aspect and its various implementations in the embodiments of the present invention can be referred to the analysis of the beneficial effects of the first aspect and its various implementations, and will not be repeated here.

[0106] The above description does not provide detailed explanations of the technical aspects of each layer's patterning, etching, etc. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to form the same structure, those skilled in the art can also design methods that are not entirely identical to those described above. Additionally, although various embodiments have been described above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination.

[0107] The embodiments of this disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure. The scope of this disclosure is defined by the appended claims and their equivalents. Various substitutions and modifications can be made by those skilled in the art without departing from the scope of this disclosure, and all such substitutions and modifications should fall within the scope of this disclosure.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor substrate and a P-type gate-ring transistor formed on the semiconductor substrate; wherein... The P-type gate-around transistor includes a channel region having at least one nanostructure; each nanostructure includes a first material portion, a second material portion, and a third material portion, all made of germanium-silicon; the germanium content in the second material portion is greater than the germanium content in the first material portion and the third material portion, respectively, and the germanium content in the third material portion is greater than the germanium content in the first material portion; the second material portion is located on both sides of the first material portion along the thickness direction, and the third material portion is located on both sides of the first material portion along the width direction; the thickness direction of the first material portion is parallel to the thickness direction of the semiconductor substrate, and the width direction of the first material portion is parallel to the width direction of the gate stack structure included in the P-type gate-around transistor.

2. The semiconductor device according to claim 1, characterized in that, The thickness of the second material portion and / or the third material portion is greater than or equal to 0.5 nm and less than or equal to 1 nm; and / or, The second material portion and the third material portion have the same thickness.

3. The semiconductor device according to claim 1, characterized in that, The germanium content in the material of the third material section is greater than or equal to 30% and less than or equal to 50%; and / or, The germanium content in the material of the second material section is greater than or equal to 35% and less than or equal to 70%.

4. The semiconductor device according to claim 1, characterized in that, In each layer of the nanostructure included in the channel region of the P-type gate ring transistor, the surface of the second material portion along the width direction of the first material portion is recessed inward relative to the surface of the third material portion that is away from the first material portion.

5. The semiconductor device according to claim 4, characterized in that, The distance by which the surface of the second material portion is recessed inward relative to the surface of the third material portion away from the first material portion is greater than 0 and less than or equal to 1 nm.

6. The semiconductor device according to claim 1, characterized in that, The P-type gate-ring transistor includes a channel region in which each nanostructure layer further includes a silicon protection portion; the silicon protection portion covers the outer periphery of the second material portion and the third material portion.

7. The semiconductor device according to claim 1, characterized in that, The semiconductor device further includes an N-type gate ring transistor, wherein the N-type gate ring transistor and the P-type gate ring transistor are spaced apart on the semiconductor substrate along a direction parallel to the surface of the semiconductor substrate; The material of the channel region of the N-type gate ring transistor is different from at least a portion of the material of the channel region of the P-type gate ring transistor; the nanostructures in each layer of the channel region of the N-type gate ring transistor and the nanostructures in the same number of layers of the channel region of the P-type gate ring transistor are staggered along the thickness direction of the semiconductor substrate.

8. The semiconductor device according to claim 7, characterized in that, The portion of the semiconductor substrate located below the channel region of the P-type gate ring transistor includes a heavily boron-doped region, and the top of the heavily boron-doped region is in contact with a portion of the gate stack structure of the P-type gate ring transistor. The semiconductor device further includes an intrinsic silicon layer located between the semiconductor substrate and the channel region included in the N-type gate ring transistor; the thickness of the intrinsic silicon layer is greater than or equal to the thickness of the gate stack structure included in the P-type gate ring transistor.

9. A method for manufacturing a semiconductor device, characterized in that, include: Provide a semiconductor substrate; A P-type gate-around transistor is formed on the semiconductor substrate; wherein the channel region of the P-type gate-around transistor has at least one layer of nanostructure; each nanostructure includes a first material portion, a second material portion, and a third material portion, all made of germanium-silicon; the germanium content in the second material portion is greater than the germanium content in the first material portion and the third material portion, respectively, and the germanium content in the third material portion is greater than the germanium content in the first material portion; the second material portion is located on both sides of the first material portion along the thickness direction, and the third material portion is located on both sides of the first material portion along the width direction; the thickness direction of the first material portion is parallel to the thickness direction of the semiconductor substrate, and the width direction of the first material portion is parallel to the width direction of the gate stack structure included in the P-type gate-around transistor.

10. The method for manufacturing a semiconductor device according to claim 9, characterized in that, The formation of a P-type gate-ring transistor on the semiconductor substrate includes: At least a first fin is formed on a semiconductor substrate; along the thickness direction of the semiconductor substrate, the first fin is surrounded by a sacrificial layer and at least one semiconductor stack layer located on the sacrificial layer; each semiconductor stack layer includes a first semiconductor layer, a second semiconductor layer, and a third semiconductor layer; the second semiconductor layer is located on both sides of the first semiconductor layer along the thickness direction, and the third semiconductor layer is located on the stacked first and second semiconductor layers; the materials of the first semiconductor layer and the second semiconductor layer are both germanium-silicon, and the germanium content in the material of the second semiconductor layer is greater than the germanium content in the material of the first semiconductor layer; the materials of the sacrificial layer and the third semiconductor layer are different from those of the first semiconductor layer and the second semiconductor layer; A mask layer is formed that spans at least a portion of the first fin. Remove the portion of the first fin exposed outside the mask layer; and form the source and drain regions of the P-type gate ring transistor on both sides of the remaining first fin along the length direction; At least a portion of the mask layer is removed; and the remaining first fin is subjected to a concentrated oxidation treatment so that the middle portion of each remaining first semiconductor layer along the width direction forms the first material portion, the two side edge portions of each remaining first semiconductor layer along the width direction form the third material portion, and each remaining second semiconductor layer forms the corresponding second material portion. Remove the oxide layer formed on the outer periphery of the remaining first fin after the concentrated oxidation treatment; Remove the remaining third semiconductor layer and sacrificial layer in each of the first fins to obtain the nanostructure included in the P-type gate ring transistor; A gate stack structure is formed around the periphery of each nanostructure layer included in the P-type ring gate transistor.

11. The method for manufacturing a semiconductor device according to claim 10, characterized in that, After providing a semiconductor substrate, the method for manufacturing the semiconductor device further includes: forming an N-type gate ring transistor on the semiconductor substrate; the N-type gate ring transistor and the P-type gate ring transistor are spaced apart along a direction parallel to the surface of the semiconductor substrate.

12. The method for manufacturing a semiconductor device according to claim 11, characterized in that, The method of forming at least a first fin on a semiconductor substrate includes: forming a first fin and a second fin with the same structure on a semiconductor substrate; The formation of a mask layer that spans at least a portion of the first fin includes: forming the mask layer that spans a portion of the first fin and a portion of the second fin; After forming the mask layer spanning a portion of the first fin and a portion of the second fin, and before removing at least a portion of the mask layer, the method of manufacturing the semiconductor device further includes: removing the portion of the second fin exposed outside the mask layer; and forming the source and drain regions of the N-type gate ring transistor only on both sides of the remaining second fin along its length direction. After removing at least a portion of the mask layer, the method for manufacturing the semiconductor device further includes: removing the remaining first semiconductor layer and the remaining second semiconductor layer in each of the second fins to obtain the nanostructure included in the N-type gate ring transistor; A gate stack structure is formed around the periphery of each nanostructure layer included in the N-type ring gate transistor.

13. A method for manufacturing a semiconductor device according to any one of claims 10 to 12, characterized in that, The process of forming at least a first fin on a semiconductor substrate includes: Forming a multilayer material layer covering the semiconductor substrate; At least the stacked material layer and a portion of the semiconductor substrate are patterned to form at least a first fin structure on the semiconductor substrate; A shallow trench isolation structure is formed covering the semiconductor substrate; the portion of the first fin structure exposed outside the shallow trench isolation structure is the first fin; the top height of the shallow trench isolation structure is less than the bottom height of the sacrificial layer, and the portion located below the remaining stacked material layers and exposed outside the shallow trench isolation structure is the sacrificial layer.

14. The method for manufacturing a semiconductor device according to claim 13, characterized in that, The sacrificial layer is integrally formed with the semiconductor substrate; or, After providing a semiconductor substrate, and before forming a multilayer material covering the semiconductor substrate, the method for manufacturing the semiconductor device further includes: At least the portion of the semiconductor substrate located below the channel region included in the P-type gate ring transistor is subjected to heavy boron doping to form a heavy boron doped region; An intrinsic silicon material layer is formed covering the semiconductor substrate; The patterning process of at least the stacked material layer and a portion of the semiconductor substrate includes: patterning the stacked material layer, the intrinsic silicon material layer, and a portion of the semiconductor substrate; the remaining intrinsic silicon material layer after the patterning process forms the sacrificial layer.

15. A method for manufacturing a semiconductor device according to any one of claims 10 to 12, characterized in that, The mask layer includes a sacrificial gate and gate sidewalls; the gate sidewalls are formed at least on both sides of the sacrificial layer along its length. The removal of at least a portion of the mask layer includes: removing the sacrificial gate.

16. A method for manufacturing a semiconductor device according to any one of claims 10 to 12, characterized in that, After removing the remaining third semiconductor layer and sacrificial layer from the first fin, and before forming the gate stack structure surrounding the periphery of each nanostructure included in the P-type ring gate transistor, the method for manufacturing the semiconductor device further includes: A silicon protective portion is formed around the outer periphery of the second material portion and the third material portion to obtain the nanostructure included in the P-type gate ring transistor.

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