Semiconductor component and method for its production

Abstract

Semiconductor component, including: a first substrate (11); a first insulator (13) provided on the first substrate (11); a first pad (17) provided in the first isolator (13); a second insulator (21) provided on top of the first insulator (13); a second pad (22) provided in the second insulator (21) is arranged on the first pad (17) and is in contact with the first pad (17); a third pad (29) provided in the second insulator (21) and arranged above the second pad (22); a third insulator (31) provided on top of the second insulator (21); and a fourth pad (32) provided in the third insulator (31), is arranged on the third pad (29) and is in contact with the third pad (29), wherein the shape of the first pad (17) and the second pad (22) is the same in plan view and the shape of the third pad (29) and the fourth pad (32) is the same in plan view, and the shape of the third and fourth pads in top view differs from the shape of the first and second pads in top view.

Description

SPECIALIZATION

[0001] The embodiments described herein relate to a semiconductor device and a method for its manufacture. BACKGROUND

[0002] In a case where a semiconductor device is manufactured by bonding three or more substrates using interlayer dielectrics, the problem arises of how bond islands can be formed in the interlayer dielectrics.

[0003] US 2021 / 0074675A1 describes a semiconductor device comprising a first wafer, a first wiring layer, a first insulating layer, a first electrode, a second wafer, a second wiring layer, a second insulating layer, a second electrode, and a first layer. The first electrode comprises a first surface, a second surface, a third surface, and a fourth surface. The second electrode comprises a fifth surface, a sixth surface, a seventh surface, a second side surface, and an eighth surface. The first layer is located between the fourth surface and a portion of the first insulating layer surrounding the fourth surface and is oriented in the first direction away from the third surface.

[0004] US 2021 / 0090987A1 describes a semiconductor device in which a capacitive MIM element can be formed without process damage, and a method for fabricating the semiconductor device. In this semiconductor device, wiring layers of a first multilayer wiring layer formed on a first semiconductor substrate and a second multilayer wiring layer formed on a second semiconductor substrate are connected by wafer bonding. The semiconductor device comprises a capacitive element with an upper electrode, a lower electrode, and a capacitive insulating film between the upper and lower electrodes. The upper and lower electrodes are formed by a first conductive layer of the first multilayer wiring layer and a second conductive layer of the second multilayer wiring layer. SHORT DESCRIPTION

[0005] A semiconductor device according to claims 1 to 7 and a method according to claims 8 to 14 are disclosed. BRIEF DESCRIPTION OF THE DRAWINGS Fig. is a cross-sectional view showing the structure of a semiconductor device of a first embodiment; Fig. are cross-sectional views showing the structures of memory cell arrays 26 and 36 of the first embodiment; Fig. are cross-sectional views showing a method for manufacturing the semiconductor device of the first embodiment; Fig. is a cross-sectional view showing the structure of a semiconductor device of a comparative example of the first embodiment; Fig. is a cross-sectional view showing the structure of the semiconductor device of the first embodiment; Fig. are top views showing a first example of the metal pads 17, 22, 29 and 32 of the first embodiment; Fig. are top views showing a second example of the metal pads 17, 22, 29 and 32 of the first embodiment; Fig. are top views showing a third example of the metal pads 17, 22, 29 and 32 of the first embodiment; Fig. are cross-sectional views showing a fourth example of the metal pads 17, 22, 29 and 32 of the first embodiment; Fig. These are cross-sectional views to illustrate the advantages of the semiconductor device of the first embodiment; Fig. is a cross-sectional view showing the structure of a semiconductor device of a second embodiment; Fig. are cross-sectional views for comparing the semiconductor device of the second embodiment and a semiconductor device of a comparison example of the same; Fig. is a cross-sectional view showing the structure of a semiconductor device with a first modification of the second embodiment; Fig. are cross-sectional views showing the structures of semiconductor devices of the second to fourth modifications of the second embodiment; Fig. are cross-sectional views showing a method for manufacturing a semiconductor device of a third embodiment; and Fig. These are cross-sectional views showing a method for manufacturing a semiconductor device of a modification of the third embodiment. DETAILED DESCRIPTION

[0006] The embodiments are now explained with reference to the accompanying drawings. Fig. Identical configurations are designated with the same reference numbers and letters, and duplicate descriptions are avoided.

[0007] In one embodiment, a semiconductor device includes: a first substrate, a first insulator provided on the first substrate, a first pad provided in the first insulator, a second insulator provided on the first insulator, and a second pad provided in the second insulator, which is arranged on the first contact surface and is in contact with the first pad. The device further includes: a third pad provided in the second insulator and arranged above the second pad, a third insulator provided on the second insulator, and a fourth pad provided in the third insulator, which is arranged on the third pad and is in contact with the third pad. Furthermore, the shape of the third or fourth pad differs from the shape of the first or second pad. (First embodiment)

[0008] Fig. is a cross-sectional view showing the structure of a semiconductor device of a first embodiment.

[0009] The semiconductor device in Fig. For example, a three-dimensional memory in which a circuit chip 1, an array chip 2 and an array chip 3 are bonded together. Fig. Figure 1 shows a bonding area S1 between a circuit chip 1 and an array chip 2 and a bonding area S2 between an array chip 2 and an array chip 3.

[0010] The circuit chip 1 includes a substrate 11, a plurality of transistors 12, an interlayer dielectric 13, a plurality of contact pins 14, a plurality of interconnects 15, a plurality of via pins 16, and a plurality of metal pads 17. Each transistor 12 includes a gate insulator 12a, a gate electrode 12b, a diffusion layer 12c, and a diffusion layer 12d. The substrate 11 is an example of a first substrate, and the interlayer dielectric 13 is an example of a first insulator. The metal pad 17 is an example of a first pad and an example of a first metal layer.

[0011] The array chip 2 includes an interlayer dielectric 21, a plurality of metal pads 22, a plurality of via pins 23, a plurality of interconnects 24, a plurality of via pins 25, a plurality of memory cell arrays 26, a plurality of interconnects 27, a plurality of via pins 28, and a plurality of metal pads 29. The interlayer dielectric 21 is an example of a second insulator, and the metal pad 22 is an example of a second pad and a second metal layer. The memory cell array 26 is an example of a first memory cell array, and the metal pad 29 is an example of a third pad and a third metal layer.

[0012] The array chip 3 includes an interlayer dielectric 31, a plurality of metal pads 32, a plurality of via pins 33, a plurality of interconnects 34, a plurality of via pins 35, a plurality of memory cell arrays 36, a plurality of interconnects 37, a plurality of via pins 38, and a passivation film 39. The interlayer dielectric 31 is an example of a third insulator, and the metal pad 32 is an example of a fourth pad and a fourth metal layer. The memory cell array 36 is an example of a second memory cell array.

[0013] Substrate 11, for example, is a semiconductor substrate such as a Si (silicon) substrate. Fig. The diagram shows X and Y directions that are perpendicular to each other and parallel to the surface of substrate 11, as well as a Z direction that is perpendicular to the surface of substrate 11. In this description, the +Z direction is defined as an upward direction and the -Z direction as a downward direction. The -Z direction may be the same as the direction of gravity or different from it.

[0014] Each transistor 12 includes a gate insulator 12a and a gate electrode 12b, which are sequentially provided on the substrate 11, as well as diffusion layers 12c and 12d, which are provided in the substrate 11. The gate electrode 12b of each transistor 12 is formed in the interlayer dielectric 13. The diffusion layers 12c and 12d of each transistor 12 serve as the source diffusion layer and the drain diffusion layer, respectively. Each transistor 12, for example, forms a logic circuit that controls the operation of the memory cell arrays 26 and 36.

[0015] The interlayer dielectric 13 is formed on the substrate 11. The interlayer dielectric 13 is a stacked insulator that encloses, for example, a silicon oxide film (SiO2 film) and other insulating films, also called insulating thin films.

[0016] The contact pins 14, the interconnects 15, the via pins 16, and the metal pads 17 are formed in the interlayer dielectric 13 and are arranged sequentially on the gate electrode 12b, the diffusion layer 12c, or the diffusion layer 12d. The in Fig. The plurality of contact pins 14 shown can further include contact pins 14 that are formed on sections other than the diffusion layers 12c and 12d in the substrate 11. The in Fig. The numerous interconnects 15 shown are provided in the same interconnect layer. Each metal pad 17, for example, encloses a copper (Cu) layer.

[0017] The interlayer dielectric 21 is formed on the interlayer dielectric 13. The interlayer dielectric 21 is a stacked insulator that, for example, encloses a SiO2 film and other insulators.

[0018] The metal pads 22, the via pins 23, the interconnects 24, and the via pins 25 are formed in the interlayer dielectric 21 and arranged sequentially on the metal pads 17. Each metal pad 22 is in contact with the corresponding metal pad 17 and is electrically connected to it. Each metal pad 22 encloses, for example, a copper layer. The in Fig. The large number of interconnects shown (24) is provided in the same interconnect layer.

[0019] The memory cell arrays 26 are formed in the interlayer dielectric 21 and arranged on the via pins 25. The operation of the memory cell arrays 26 is controlled by the logic circuits mentioned above via the metal pads 17 and 22. Each memory cell array 26 includes a plurality of memory cells in which data can be stored. Further details of the structure of each memory cell array 26 are described below.

[0020] The interconnects 27, the via pins 28, and the metal pads 29 are formed in the interlayer dielectric 21 and arranged sequentially on the memory cell array 26. The in Fig. The numerous interconnects 27 shown are provided in the same interconnect layer. These interconnects 27 serve, for example, as source lines for the memory cell arrays 26. These interconnects 27 can also include other interconnects 27 besides the source lines, and these other interconnects 27 can be located at positions other than those on the memory cell arrays 26. Each metal pad 29, for example, encloses a copper layer.

[0021] The interlayer dielectric 31 is formed on the interlayer dielectric 21. The interlayer dielectric 31 is a stacked insulator that, for example, encloses a SiO2 film and other insulators.

[0022] The metal pads 32, the via pins 33, the interconnects 34, and the via pins 35 are formed in the interlayer dielectric 31 and arranged sequentially on the metal pads 29. Each metal pad 32 is in contact with the corresponding metal pad 29 and is electrically connected to it. Each metal pad 32 encloses, for example, a copper layer. The in Fig. The large number of interconnects shown (34) is provided in the same interconnect layer.

[0023] The memory cell arrays 36 are formed in the interlayer dielectric 31 and arranged on the via pins 35. The operation of the memory cell arrays 36 is controlled by the logic circuits mentioned above via the metal pads 17, 22, 29, and 32. Each memory cell array 36 includes a plurality of memory cells in which data can be stored. Further details of the structure of each memory cell array 36 are described below.

[0024] The interconnects 37 and via pins 38 are formed in the interlayer dielectric 31 and arranged sequentially on the storage arrays 36. The in Fig. The numerous interconnects 37 shown are provided in the same interconnect layer. These interconnects 37 serve, for example, as source lines for the memory cell arrays 36. These interconnects 37 can also include other interconnects 37 besides the source lines, and these other interconnects 37 can be located at positions other than the positions on the memory cell arrays 36.

[0025] The passivation layer 39 is formed on the interlayer dielectric 31. The passivation film 39 is, for example, a stacked insulator enclosing a SiO2 film and a silicon nitride (SiN) film.

[0026] As described above, the semiconductor device of the present embodiment includes metal pads 17, 22, 29, and 32, with metal pads 29 and 32 positioned above metal pads 17 and 22. Specifically, metal pads 17 and 22 are located on the bonding surface S1 and electrically connect the circuit chip 1 and the array chip 2. Metal pads 29 and 32 are located on the bonding surface S2 and electrically connect the array chip 2 and the array chip 3. Each metal pad 22 is positioned on the corresponding metal pad 17, and each metal pad 32 is positioned on the corresponding metal pad 29. In the present embodiment, the shapes of metal pads 29 and 32 differ from the shapes of metal pads 17 and 22, as described below. Further details regarding the shapes of the metal pads 17, 22, 29 and 32 are described below.

[0027] Fig. These are cross-sectional views showing the structures of memory cells 26 and 36 of the first embodiment.

[0028] Each memory cell array 26 of the present embodiment has a structure which is in Fig. is shown. That in Fig. The memory cell array 26 shown includes a plurality of electrode layers 41, a plurality of insulators 42 and a plurality of columnar sections 43. Fig. shows one of the many columnar sections 43.

[0029] The multitude of electrode layers 41 and the multitude of insulators 42 are stacked alternately in the Z direction. Each electrode layer 41, for example, encloses a tungsten (W) layer and functions as a word conductor. Each insulator 42 is, for example, a SiO2 film.

[0030] Each column-shaped section 43 sequentially encloses a block insulator 43a, a charge storage layer 43b, a tunnel insulator 43c, a channel semiconductor layer 43d, and a core insulator 43e, which are formed successively on the side faces of the electrode layer 41 and the insulator 42. The block insulator 43a is, for example, a SiO2 film. The charge storage layer 43b is, for example, an insulator, such as a SiN film. The charge storage layer 43b can, for example, be a semiconductor layer, such as a polysilicon layer. The tunnel insulator 43c is, for example, a SiO2 film. The channel semiconductor layer 43d is, for example, a polysilicon layer. The core insulator 43e is, for example, a SiO2 film.

[0031] Each memory cell array 36 of the present embodiment has a structure which is in Fig. is shown. That in Fig. The memory cell array 36 shown includes a plurality of electrode layers 51, a plurality of insulators 52 and a plurality of columnar sections 53. Fig. shows one of the many columnar sections 53.

[0032] The multitude of electrode layers 51 and the multitude of insulators 52 are stacked alternately in the Z direction. Each electrode layer 51, for example, encloses a W layer and functions as a word conductor. Each insulator 52 is, for example, a SiO2 film.

[0033] Each column-shaped section 53 includes a block insulator 53a, a charge storage layer 53b, a tunnel insulator 53c, a channel semiconductor layer 53d, and a core insulator 53e, which are sequentially formed on the side faces of the electrode layers 51 and the insulators 52. The block insulator 53a is, for example, a SiO2 film. The charge storage layer 53b is, for example, an insulator such as a SiN film. The charge storage layer 53b can, for example, be a semiconductor layer such as a polysilicon layer. The tunnel insulator 53c is, for example, a SiO2 film. The channel semiconductor layer 53d is, for example, a polysilicon layer. The core insulator 53e is, for example, a SiO2 film.

[0034] Fig. are cross-sectional views showing a method for manufacturing the semiconductor device of the first embodiment.

[0035] Fig. Figure 1 shows a circuit wafer W1 containing a plurality of circuit chips 1, an array wafer W2 containing a plurality of array chips 2, and an array wafer W3 containing a plurality of array chips 3. The circuit wafer W1 is also referred to as a CMOS wafer, and the array wafers W2 and W3 are also referred to as memory wafers.

[0036] The alignment of the in Fig. The wafer arrays W2 and W3 shown are aligned in Fig. The array chips 2 and 3 shown are opposite each other. In the present embodiment, the circuit wafer W1, the array wafer W2 and the array wafer W3 are bonded together to produce a semiconductor device. Fig. shows the array wafers W2 and W3 before they are flipped for bonding, and Fig. shows the array chips 2, 3 after they have been flipped over for bonding, bonded and separated.

[0037] In Fig. Array wafer W2 includes a substrate 61 provided beneath the interlayer dielectric 21, and array wafer W3 includes a substrate 62 provided beneath the interlayer dielectric 31. Substrates 61 and 62 are, for example, semiconductor substrates such as silicon substrates. Substrate 61 is an example of a second substrate, and substrate 62 is an example of a third substrate.

[0038] The semiconductor device of the present embodiment is manufactured, for example, as follows.

[0039] First, on a substrate 11 of a circuit wafer W1 ( Fig. ) Transistors 12, interlayer dielectrics 13, contact pins 14, interconnects 15, via pins 16 and metal pads 17 are formed. In addition, an interlayer dielectric 21, metal pads 22, via pins 23, interconnects 24, via pins 25, memory cell arrays 26 and interconnects 27 are formed on a substrate 61 of an array wafer W2 ( Fig. ). Furthermore, an insulator 31a, metal pads 32, via pins 33, interconnects 34, via pins 35, memory cell arrays 36 and interconnects 37 are formed on a substrate 62 of an array wafer W2 ( Fig. ) formed. The insulator 31a is part of the interlayer dielectric 31. In the Fig. The procedure shown can be performed in any order for the circuit wafer W1, the procedure for the array wafer W2 and the procedure for the array wafer W3.

[0040] Next, as in Fig. As shown, the circuit wafer W1 and the array wafer W2 are bonded together by mechanical pressure. As a result, the interlayer dielectric 13 and the interlayer dielectric 21 are bonded together. Next, the circuit wafer W1 and the array wafer W2 are annealed at 400°C ( Fig. The metal pads 17 and 22 are heated to bond them together. Further details of this tempering process are described below in a third embodiment. In this way, the substrates 11 and 61 are bonded together, with the interlayer dielectric 13 and the interlayer dielectric 21 sandwiched between them. The underside of the interlayer dielectric 21 is bonded to the top side of the interlayer dielectric 13.

[0041] Next, the substrate 61 is removed, and via pins 28 and metal pads 29 are successively formed on the interconnects 27 in the interlayer dielectric 21 ( Fig. ). Substrate 61 is removed, for example, by chemical-mechanical polishing (CMP).

[0042] Next, as in Fig. As shown, the array wafer W2 and the array wafer W3 are bonded together by mechanical pressure. This causes the interlayer dielectric 21 and the insulator 31a (interlayer dielectric 31) to adhere. Next, the circuit wafer W1, the array wafer W2, and the array wafer W3 are annealed at 400 °C ( Fig. The metal pads 17, 22, 29, and 32 are heated so that metal pads 29 and 32 bond together. The annealing can be performed such that metal pads 29 and 32 are heated while metal pads 17 and 22 are not. Further details of this annealing process are described below in a third embodiment. In this way, the substrates 11 and 62 are bonded to each other via the interlayer dielectric 13, the interlayer dielectric 21, and the insulator 31a. The underside of the insulator 31a is bonded to the top side of the interlayer dielectric 21.

[0043] Next, the substrate 62 is removed, via pins 38 are formed at the interconnects 37 in the insulator 31a, and insulators 31b are formed on the insulator 31a and the via pins 38 ( Fig. ). The insulator 31b is part of the interlayer dielectric 31. The substrate 62 is removed, for example, by CMP.

[0044] Then a passivation layer 39 (see Fig. ) formed on the insulator 31b, and the circuit wafer W1, the array wafer W2, and the array wafer W3 are sliced ​​into a multitude of chips. In this way, the semiconductor device is formed from Fig. produced. Substrate 11 can be thinned by CMP before cutting.

[0045] The semiconductor device of the present embodiment is fabricated by bonding the circuit wafer W1 to the array wafer W2, and then bonding the array wafer W2 to the array wafer W3. However, the semiconductor device can also be fabricated by bonding the array wafer W2 to the array wafer W3, and then bonding the circuit wafer W1 to the array wafer W2. Furthermore, the semiconductor device of the present embodiment can also be fabricated with three or more array wafers bonded together. Regarding the above with respect to Fig. was and what follows with reference to Fig. As described, this also applies to bonding, as described in this paragraph.

[0046] Although Fig. The interface between the interlayer dielectric 13 and the interlayer dielectric 21, as well as the interfaces between the metal pads 17 and the metal pads 22, are shown. It is common practice that these interfaces are annealed after annealing. Fig. are no longer visible. However, the locations where these interfaces were situated can be estimated, for example, by determining the inclination of the side surfaces of the metal pads 17 or the side surfaces of the metal pads 22, or by determining the positional deviation between the side surfaces of the metal pads 17 and the metal pads 22. The same applies to the interface between the interlayer dielectric 21 and the interlayer dielectric 31, the interfaces between the metal pads 29 and the metal pads 32, and to the interface described in Fig. Tempering shown.

[0047] Furthermore, the semiconductor device of the present embodiment can be in Fig. The shown state can be traded after it has been cut into a multitude of chips, or it can be in the state of Fig. It is traded before being cut into a multitude of chips. Fig. shows a semiconductor device in a chip state and Fig. Figure 1 shows a semiconductor device in a wafer state. In the present embodiment, a plurality of semiconductor devices are in the chip state ( Fig. ) from a semiconductor device in the wafer state ( Fig. ) manufactured.

[0048] Next, with reference to Fig. The semiconductor device of the present embodiment was compared with a semiconductor device from comparative examples.

[0049] Fig. is a cross-sectional view showing the structure of a semiconductor device of a comparative example for the first embodiment.

[0050] As in Fig. shows Fig. Metal pads 17 in circuit chip 1, metal pads 22 and 29 in array chip 2, metal pads 32 in array chip 3 and the like. Fig. Figure 71 further shows insulators 71, 72, and 73, which are enclosed in the interlayer dielectrics 13, 21, and 31. Insulators 71, 72, 73, and 73 are examples of SiO₂ films. Insulators 72 and 73 are examples of SiN films. Insulators 72 are used as etch stops when forming via holes for embedding the via pins 16, 23, 28, and 33. Insulators 73 are used as etch stops when forming openings for embedding the metal pads 17, 22, 29, and 32.

[0051] In this comparative example, metal pads 17, 22, 29, and 32 have the same shape. Therefore, in this comparative example, metal pads 17, 22, 29, and 32 have the same shape in a top view, and they have the same thickness. The shape of these metal pads 17, 22, 29, and 32 in a top view is, for example, square, rectangular, or circular. The thickness of these metal pads 17, 22, 29, and 32 is their length in the Z-direction. In this comparative example, metal pads 22 and 32 have shapes that are formed by rotating metal pads 17 and 29 by 180 degrees.

[0052] Fig. is a cross-sectional view showing the structure of the semiconductor device of the first embodiment.

[0053] Fig. shows insulators 74, which are in the interlayer dielectrics 13 and 21 in addition to those in Fig. The components shown are included. The insulators 74 are, for example, silicon carbonitride (SiCN) films. In the present embodiment, the top surface of the interlayer dielectric 13 and the bottom surface of the interlayer dielectric 21 are formed by the insulators 74, and the top surface of the interlayer dielectric 21 and the bottom surface of the interlayer dielectric 31 are formed by the insulators 71. Therefore, the bonding surface S1 of the present embodiment is formed by the insulators 74, and the bonding surface S2 of the present embodiment is formed by the insulators 71. One of the insulators 71 and 74 is an example of first insulating materials, and the other of the insulators 71 and 74 is an example of second insulating materials.

[0054] In the present embodiment, the metal pads 17 have the same shape as the metal pads 22, and the metal pads 29 have the same shape as the metal pads 32, while the metal pads 17 and 22 have a different shape than the metal pads 29 and 32. Therefore, in the present embodiment, the top-view shape of the metal pads 17 and 22 differs from the shape of the metal pads 29 and 32, and / or the thickness of the metal pads 17 and 22 differs from the thickness of the metal pads 29 and 32. Fig. The shape of metal pads 17 and 22 differs from the shape of metal pads 29 and 32 in top view, and the thickness of metal pads 17 and 22 is the same as the thickness of metal pads 29 and 32. In the present embodiment, metal pads 22 have a shape formed by rotating the shape of metal pad 17 by 180 degrees in the Z direction, and metal pad 32 has a shape formed by rotating the shape of metal pad 29 by 180 degrees in the Z direction.

[0055] The in Fig. The interconnects shown extend in the X direction, while those in Fig. The interconnects 27 shown extend in the Y direction. Thus, the interconnects 27 of the present embodiment can extend in any direction. The same applies to the other interconnects 15, 24, 34 and 37 of the present embodiment.

[0056] The following describes the advantages of having different shapes for the metal pads 17 and 22 and the metal pads 29 and 32 of the present embodiment.

[0057] In Fig. The areas of metal pads 17 and 22 are defined as small in plan view, and the areas of metal pads 29 and 32 are defined as large in plan view. Defining small areas for metal pads 17 and 22 allows for a reduction in the grid spacing between adjacent metal pads 17 and 22. This improves the integration level of metal pads 17 and 22. However, defining small areas for metal pads 17 and 22 leads to difficulties in properly bonding them together. For example, if at least one of the circuit wafer W1 and the array wafer W2 exhibits significant warpage, misalignment is likely to occur between metal pads 17 and 22.The fixed area of ​​the metal pads 17 and 22 will likely result in the metal pads 17 and 22 exhibiting high resistance or conduction interruption, even if this offset is small.

[0058] The procedure of bonding circuit wafer W1 and array wafer W2 together, and then bonding array wafer W2 and array wafer W3 together, is highly likely to cause significant wafer distortion when the array wafers W2 and W3 are bonded together. Therefore, if the areas of metal pads 29 and 32 are also set to be small, it is very likely that metal pads 29 and 32 will exhibit high resistance or open circuitry. Conversely, even if the areas of metal pads 17 and 22 are set to be small, metal pads 29 and 32 are unlikely to exhibit high resistance or open circuitry. Therefore, in the present embodiment, the areas of metal pads 17 and 22 are set to be small, and the areas of metal pads 29 and 32 are set to be large.This makes it possible to improve the integration level of these pads while preventing high resistance and line interruption of these pads.

[0059] In Fig. Bonding surface S1 is formed from SiCN films (insulators 74) and bonding surface S2 is formed from SiO2 films (insulators 71). The SiCN films prevent the diffusion of Cu atoms more readily than the SiO2 films. Fig. A short grid spacing between adjacent metal pads 17 and a short grid spacing between adjacent metal pads 22 increases the density of the metal pads 17 and 22 covering the bonding surface S1. This increase in density can cause a large number of copper atoms to diffuse out of the metal pads 17 and 22. The present embodiment allows the bonding surface S1 to be formed with SiCN films in order to effectively prevent the diffusion of copper atoms out of the metal pads 17 and 22, even with an increase in the density of the metal pads 17 and 22 covering the bonding surface S1.

[0060] The metal pads 17 and 22 and the metal pads 29 and 32 of the present embodiment can have different shapes for another reason. The procedure in which the array wafer W2 and the array wafer W3 are bonded together, and then the circuit wafer W1 and the array wafer W2 are bonded together, is highly likely to result in significant wafer distortion when the circuit wafer W1 and the array wafer W2 are bonded together. In this case, the areas of the metal pads 17 and 22 can be set large and the areas of the metal pads 29 and 32 small.

[0061] Furthermore, the metal pads 22 of the present embodiment have the same shape as the metal pads 17, but may have a different shape. Likewise, the metal pads 32 of the present embodiment have the same shape as the metal pads 29, but may have a different shape. Furthermore, the in Fig. The variety of metal pads shown includes 17 metal pads with two or more shapes. The same applies to metal pads 22, 29, and 32.

[0062] Next, various examples of the metal pads 17, 22, 29 and 32 of the present embodiment are described with reference to Fig. described.

[0063] Fig. These are top views showing a first example of the metal pads 17, 22, 29 and 32 of the first embodiment.

[0064] Fig. The top view of metal pads 17, 22, 29, and 32 is shown. Metal pads 17 and 22 are square in top view, with four sides of length L1. Metal pads 29 and 32 are square in top view, with four sides of length L2 (L1 < L2). Therefore, metal pads 17 and 22 have different shapes than metal pads 29 and 32. The thickness of metal pads 17 and 22 can be the same as, or different from, that of metal pads 29 and 32.

[0065] Fig. These are top views showing a second example of the metal pads 17, 22, 29 and 32 of the first embodiment.

[0066] Fig. Figures 17, 22, 29, and 32 show the top view of their respective shapes. Metal pads 17 and 22 each have a rectangular shape in their top view, with two sides of length L3 and two sides of length L4. <L4). Hingegen haben die Metall-Pads 29 und 32 in Draufsicht jeweils eine quadratische Form mit vier Seiten der Länge L2. Daher haben die Metall-Pads 17 und 22 jeweils eine andere Form als die Metall-Pads 29 und 32. Die Dicke der Metall-Pads 17 und 22 kann in diesem Beispiel gleich der Dicke der Metall-Pads 29 und 32 sein oder anders als die Dicke der Metall-Pads 29 und 32 sein. In diesem Beispiel ist die Fläche L3×L4 der Metall-Pads 17 und 22 kleiner festgelegt als die Fläche L2×L2 der Metall-Pads 29 und 32 (L3×L4 < L2×L2).

[0067] Fig. are top views showing a third example of the metal pads 17, 22, 29 and 32 of the first embodiment.

[0068] Fig. Figure 17 shows the top-view shapes of metal pads 17, 22, 29, and 32. Metal pads 17 and 22 are each circular in top view with a diameter D1. In contrast, metal pads 29 and 32 are each circular in top view with a diameter D2 (D1). <D2). Somit haben die Metall-Pads 17 und 22 jeweils eine andere Form als die Metall-Pads 29 und 32. Die Dicke der Metall-Pads 17 und 22 kann in diesem Beispiel gleich der Dicke der Metall-Pads 29 und 32 sein oder anders als die Dicke der Metall-Pads 29 und 32 sein.

[0069] The first and third examples each have an advantage, which can, for example, reduce both the grid spacing between the metal pads 17 (or 22) in the X direction and the grid spacing between the metal pads 17 (or 22) in the Y direction. The metal pads 17, 22, 29, and 32 may have different shapes in a top view than those described in the first, second, and third examples.

[0070] Fig. are cross-sectional views showing a fourth example of the metal pads 17, 22, 29 and 32 of the first embodiment.

[0071] Fig. shows a vertical section through metal pads 17 and 22, and Fig. Figure 1 shows a vertical section through metal pads 29 and 32. Metal pads 17 and 22 each have a thickness T1, and metal pads 29 and 32 each have a thickness T2 (T1). <T2). Daher haben die Metall-Pads 17 und 22 jeweils eine andere Form als die Metall-Pads 29 und 32. Die Form der Metall-Pads 17 und 22 in Draufsicht kann in diesem Beispiel gleich der Form der Metall-Pads 29 und 32 sein oder anders als die Form der Metall-Pads 29 und 32 sein.

[0072] In general, as the thickness of a metal pad increases, a greater quantity of copper atoms diffuse out of the metal pad. Therefore, in the fourth example, bonding surface S1 can be formed from a SiO2 film and bonding surface S2 from a SiCN film. This makes it possible to more effectively prevent the diffusion of copper atoms from metal pads 29 and 32, even if the metal pads 29 and 32 are thick.

[0073] Fig. These are cross-sectional views to illustrate the advantages of the semiconductor device of the first embodiment.

[0074] Fig. show metal pads 17 in circuit chip 1, metal pads 22 and 29 in array chip 2, metal pads 32 in array chip 3 and the like. Fig. The figures further show the grid spacing P1 between adjacent metal pads 17 (or 22) and the grid spacing P2 between adjacent metal pads 29 (or 32). The present embodiment allows the areas of the metal pads 17 and 22 to be reduced in plan view in order to shorten the grid spacing P1 as described above. This allows the integration level of the metal pads 17 and 22 to be improved.

[0075] Fig. The graphs show the width X of the offset between metal pads 17 and 22 and between metal pads 29 and 32. With the large surface areas of metal pads 29 and 32, it is unlikely that they will exhibit high resistance or a circuit break due to offset. Conversely, the small surface areas of metal pads 17 and 22 are likely to lead to high resistance or a circuit break due to offset. The graph in Fig. The offset shown has the same width X as the one in Fig. The offset shown. However, the offset has an effect on metal pads 17 and 22 in Fig. probably more disadvantageous than with the metal pads 29 and 32 in Fig. .

[0076] However, in a case where the circuit wafer W1 and the array wafer W2 are bonded together, and then the array wafer W2 and the array wafer W3 are bonded together, the wafer distortion is likely to be minimal when the circuit wafer W1 and the array wafer W2 are bonded together. This allows the circuit wafer W1 and the array wafer W2 to be bonded together in such a way as to prevent misalignment. Therefore, in the present embodiment, the areas of the metal pads 17 and 22 are defined as small, and the areas of the metal pads 29 and 32 are defined as large. This allows for an improved integration level of these pads while preventing high resistance and conduction openness.

[0077] As described above, the shape of the metal pads 29 and 32 of the present embodiment differs from the shape of the metal pads 17 and 22 of the same embodiment. Thus, the present embodiment allows these metal pads 17, 22, 29 and 32 to be formed in a preferred manner, as described above. (Second embodiment)

[0078] Fig. is a cross-sectional view showing the structure of a semiconductor device of a second embodiment.

[0079] The semiconductor device of the present embodiment ( Fig. ) has similar components to the semiconductor device of the first embodiment. However, the array chip 2 of the present embodiment does not include a metal pad 29, but rather a via pin 28 near the bonding surface S2. Thus, the metal pad 32 of the present embodiment is connected to the via pin 28 instead of the metal pad 29, as in Fig. shown. The via pin 28 and the metal pad 32 in Fig. Examples include a W layer and a Cu layer. The via pin 28 and the metal pad 32 in Fig. Examples of a third metal layer and a fourth metal layer are shown. The semiconductor device of the present embodiment can, for example, be modified by omitting the procedure for forming the metal pad 29 according to the procedure described in Fig. The methods shown are used to produce the finished product.

[0080] Fig. Figure 1 shows a width W1 of the top side of interconnect 27, a width W2 of the bottom side of via pin 28, a width W3 of the top side of metal pad 32, a width W4 of the bottom side of via pin 33, a width W5 of the top side of via pin 33, and a width W6 of interconnect 34. Widths W2, W4, and W5 correspond to the pin diameters of via pins 28 and 33 on the top and bottom sides, respectively. The dimensions shown in Fig. The interconnects 27 and 34 shown extend in the Y direction, and the widths W1 and W6, which represent the lengths in the X direction, correspond to the interconnect widths of the interconnects 27 and 34 on the top and bottom sides, respectively.

[0081] Since in the present embodiment the via pin 28 is arranged on the interconnect 27, the width W2 of the via pin 28 is smaller than the width W1 of the interconnect 27 (W2 <W1). Da das Metall-Pad 32 unter dem Durchkontaktierungsstift 33 angeordnet ist, ist außerdem die Breite W3 des Metall-Pads 32 größer als die Breite W4 des Durchkontaktierungsstifts 33 (W3> W4). Since the via pin 33 is located below the interconnect 34, the width W5 of the via pin 33 is also smaller than the width W6 of the interconnect 34 (W5 <W6).

[0082] The structure of the via pin 28 of the present embodiment can also be applied to the via pin 33 instead of the via pin 28. In this case, the array chip 3 does not include a metal pad 32, and the metal pads 29 are connected to the via pin 33 instead of the metal pad 32. Likewise, the structure of the via pin 28 of the present embodiment can be applied to any via pin 16 or 23.

[0083] Fig. These are cross-sectional views for comparing the semiconductor device of the second embodiment and a semiconductor device of a comparison example thereof.

[0084] Fig. shows the semiconductor device of the comparison example. In Fig. The metal pads 32 are connected to the metal pads 29. In Fig. The metal pads 29 and 32 are offset.

[0085] Fig. shows the semiconductor device of the present embodiment. In Fig. The metal pads 32 are connected to the via pins 28. In Fig. The via pins 28 and the metal pads 32 are offset.

[0086] The in Fig. Arrow A1 indicates a gap between metal pad 29 and metal pad 32 of the comparison example. Both metal pad 29 and metal pad 32 are large, resulting in a very narrow gap between them due to the offset. This can worsen the breakdown voltage of the semiconductor device, for example, due to a short circuit between metal pads 29 and 32.

[0087] The in Fig. Arrow A2 indicates a gap between a via pin 28 and a metal pad 32 of the present embodiment. The via pin 28 is small and reliably provides a wide gap between it and the metal pad 32, even if they are misaligned. Therefore, the present embodiment prevents deterioration of the breakdown voltage of the semiconductor device, such as by preventing a short circuit between the via pin 28 and the metal pad 32.

[0088] Fig. These are cross-sectional views showing the structures of semiconductor devices of the first to fourth modification of the second embodiment.

[0089] The semiconductor device of the first modification ( Fig. ) has similar components to the semiconductor device of the first embodiment. However, the array chips 2 and 3 of the present modification do not enclose the metal pads 29 and 32 and have the via pins 28 and 33 located near the bonding area S2. Therefore, the via pin 33 of the present embodiment is connected to the via pin 28, as shown in Fig. shown. The via pins 28 and 33 in Fig. Examples include W-layers. The via pins 28 and 33 in Fig. These are examples of a third or fourth metal layer. The semiconductor device of the present modification can, for example, be modified by omitting the procedures for forming the metal pads 29 and 32 by the process described in Fig. The methods shown are used to manufacture the semiconductor device. The present modification makes it possible to prevent the deterioration of the breakdown voltage of the semiconductor device, for example by preventing a short circuit between the via pins 28 and 33 as in the second embodiment.

[0090] The semiconductor device of the second modification ( Fig. includes in addition to the in Fig. The components shown incorporate a multitude of metal pads (blind pads) 32'. These blind pads 32' are made of the same material as the metal pads 32. The semiconductor component of the third modification ( Fig. includes in addition to the in Fig. The components shown incorporate a multitude of through-hole plating pins (blind pins) 28'. These through-hole plating pins 28' are made of the same material as the through-hole plating pins 28. The semiconductor device of the fourth modification ( Fig. ) includes in addition to the ones in Fig. The components shown incorporate a multitude of through-hole plating pins (blind pins) 28'. These through-hole plating pins 28' are made of the same material as the through-hole plating pins 28.

[0091] In this way, if the structure of the second embodiment or the first modification is adopted, the array chip 2 or the array chip 3 can include blind pads 32' or blind pins 28'. The blind pads 32' are metal pads that are not used as pads for electrically connecting components in the semiconductor device. The blind pins 28' are via pins that are not used as pins for electrically connecting components in the semiconductor device. The pads 32' and the blind pins 28' can prevent CMP erosion. If the structure of the second embodiment or the first modification is adopted, the blind pads 32' (or blind pins 28') are preferably arranged only on one of the array chips 2 and 3, as shown in Fig. shown to reliably provide wide gaps, indicated by arrows A1 and A2.

[0092] As described above, the array chips 2 and 3 of the present embodiment have a structure in which the metal pads 32 and the via pins 28 are connected to each other, or a structure in which the via pins 33 and the via pins 28 are connected to each other. Therefore, the present embodiment allows these metal pads 32 and via pins 28 and 33 to be configured in a preferred manner, as described above. The present embodiment allows the via pins 28 and 33 to be provided with a similar function as bonding islands to, for example, the metal pads 32.

[0093] The structures of the second embodiment and the first through fourth modifications can be applied to bonding surface S1 instead of bonding surface S2. However, in a case where the circuit wafer W1 and the array wafer W2 are bonded together, and then the array wafer W2 and the array wafer W3 are bonded together, significant wafer distortion is very likely when the array wafers W2 and W3 are bonded together. In this case, misalignment between the metal pads is likely to occur when the array wafers W2 and W3 are bonded together. Therefore, in this case, it is preferable to apply the structures of the second embodiment and the first through fourth modifications to bonding surface S2 instead of bonding surface S1. (Third embodiment)

[0094] Fig. is a cross-sectional view showing a method for manufacturing a semiconductor device of a third embodiment.

[0095] The method for manufacturing the semiconductor device of the present embodiment is similar to that described in Fig. The method shown for manufacturing the semiconductor device of the first embodiment is described. However, in the present embodiment, the annealing temperature immediately after bonding the array wafers W2 and W3 is set to a temperature that differs from the annealing temperature immediately after bonding the circuit wafer W1 and the array wafer W2.

[0096] First, the circuit wafer W1 and the array wafer W2 are bonded together ( Fig. Next, the circuit wafer W1 and the array wafer W2 are annealed at a temperature Ta ( Fig. This heats up the metal pads 17 and 22. The temperature Ta is an example of an initial temperature.

[0097] The metal pads 17 and 22 of the present embodiment, for example, enclose copper layers. The copper layers can be sufficiently bonded together by annealing at 400 °C or higher. The annealing in Fig. However, it is performed at a temperature Ta that is set lower than 400 °C. Therefore, the metal pads 17 and 22 of the present embodiment are heated by the Fig. The tempering processes shown are not sufficiently connected. The tempering process in Fig. The annealing process is carried out for one hour at a temperature Ta, which is set, for example, to less than 300 °C. This annealing promotes the bonding of the interlayer dielectric 13 and the interlayer dielectric 21, but does not sufficiently bond the metal pads 17 and the metal pads 22.

[0098] Next, the array wafer W2 and the array wafer W3 are bonded together ( Fig. Then the circuit wafer W1, the array wafer W2 and the array wafer W3 are annealed at a temperature Tb that differs from the temperature Ta ( Fig. The metal pads 17, 22, 29, and 32 are heated. Temperature Tb is an example of a second temperature.

[0099] The metal pads 29 and 32 of the present embodiment, for example, enclose copper layers. The tempering process in Fig. is carried out at a temperature Tb, which is set at 400 °C or higher. Therefore, the metal pad 17 and the metal pad 22 of the present embodiment are heated by the Fig. The tempers shown are sufficiently connected, and the metal pads 29 and the metal pads 32 of the present embodiment are also connected by the in Fig. The tempering process shown is sufficiently connected. The tempering process in Fig. The annealing process is carried out for one hour at a temperature Tb, which is set, for example, to 400 °C. This annealing not only promotes the bonding of the interlayer dielectric 21 and the interlayer dielectric 31, but also sufficiently bonds the metal pads 17 and the metal pads 22, and sufficiently bonds the metal pads 29 and the metal pads 32.

[0100] If the temperature Ta is set to 400 °C or higher, the metal pads 17 and 22 are heated by the [missing information]. Fig. The tempers shown are sufficiently connected and are further in Fig. exposed to a temperature at which they can be sufficiently bonded by annealing. Consequently, excessive stress can be applied to the metal pads 17 and 22, and a large number of Cu atoms can diffuse out of the metal pads 17 and 22. In contrast, the present embodiment makes it possible to avoid these problems by setting the temperature Ta lower than 400 °C.

[0101] It is expected that the diffusion of Cu atoms will have a strong negative impact on the circuit wafer W1. Therefore, it is desirable to prevent the diffusion of Cu atoms from the metal pads 17 and 22, which are closer to the circuit wafer W1, more effectively than the diffusion of Cu atoms from the metal pads 29 and 32, which are farther away from the circuit wafer W1. The present embodiment allows the annealing of Fig. to carry out the process of heating only metal pads 17 and 22 of the metal pads 17, 22, 29 and 32 at a low temperature to effectively prevent the diffusion of Cu atoms from the metal pads 17 and 22.

[0102] The temperature Ta may be set to a different temperature than the temperature Tb for a different reason. For example, a semiconductor device may be heated according to the temperature specified in the diagram. Fig. The methods shown are used to produce the finished product.

[0103] Fig. These are cross-sectional views showing a method for manufacturing a semiconductor device according to a modification of the third embodiment.

[0104] First, the array wafer W2 and the array wafer W3 are bonded together ( Fig. Next, array wafer W2 and array wafer W3 are annealed at a temperature Tb ( Fig. In this process, metal pads 29 and 32 are heated. The temperature Tb is also an example of the second temperature.

[0105] The metal pads 29 and 32 of the present modification, for example, enclose copper layers. The annealing process in Fig. is performed at a temperature Tb, which is set at 400 °C or higher. Therefore, the metal pads 29 and the metal pads 32 of the present modification are heated by the temperature specified in Fig. The tempering process shown is sufficiently connected. The tempering process in Fig. The annealing process is carried out for one hour at a temperature Tb, which is set, for example, to 420 °C. This annealing not only promotes the bonding of the interlayer dielectric 21 and the interlayer dielectric 31, but also sufficiently bonds the metal pads 29 and the metal pads 32 together.

[0106] Next, the circuit wafer W1 and the array wafer W2 are bonded together ( Fig. Then the circuit wafer W1, the array wafer W2 and the array wafer W3 are annealed at a temperature Ta that differs from the temperature Tb ( Fig. The metal pads 17, 22, 29, and 32 are heated. The temperature Ta is also an example of the first temperature.

[0107] The metal pads 17 and 22 of the present modification, for example, enclose copper layers. The annealing process in Fig. is performed at a temperature Ta set at 400 °C or higher. Therefore, the metal pads 17 and the metal pads 22 of the present modification are heated by the process described in Fig. The tempering process shown is sufficiently connected. The tempering process in Fig. The annealing process is carried out for one hour at a temperature Ta, which is set, for example, to 400 °C. This annealing not only promotes the bonding of the interlayer dielectric 13 and the interlayer dielectric 21, but also sufficiently bonds the metal pads 17 and the metal pads 22 together.

[0108] As described above, it is desirable to prevent the diffusion of Cu atoms from metal pads 17 and 22, which are closer to the circuit wafer W1, more effectively than the diffusion of Cu atoms from metal pads 29 and 32, which are farther away from the circuit wafer W1. The present modification allows the diffusion of Cu atoms from metal pads 17 and 22 to be prevented only by the [missing information - likely a specific feature or characteristic]. Fig. shown tempers under the in Fig.The shown variations of the annealing process are heated to effectively prevent the diffusion of Cu atoms from the metal pads 17 and 22. Furthermore, the present modification allows the temperature Ta to be set lower than the temperature Tb, enabling the metal pads 17 and 22 to be annealed at a lower temperature, resulting in a more effective prevention of Cu atom diffusion from the metal pads 17 and 22.

[0109] As described above, the present embodiment allows the temperature Tb to be set to a temperature different from the temperature Ta in order to preferentially form the metal pads 17, 22, 29, and 32. In the description above, the temperature Tb is set higher than the temperature Ta. However, the principle of setting the temperature Tb lower than the temperature Ta can also be applied.

[0110] The method of the present embodiment can be used in the fabrication of the semiconductor device of the second embodiment instead of the fabrication of the semiconductor device of the first embodiment. In this case, the annealing process in the present embodiment not only joins metal pads to each other, but also joins metal pads and via pins, or it joins via pins to each other.

[0111] Although certain embodiments have been described, these embodiments are shown only for illustrative purposes. In fact, the novel devices and methods described herein can be embodied in a multitude of other forms; moreover, various omissions, substitutions, and modifications to the form of the devices and methods described herein can be made without departing from the spirit of the inventions.

Claims

[1] Semiconductor device, comprising: a first substrate (11); a first insulator (13) provided on the first substrate (11); a first pad (17) provided in the first isolator (13); a second insulator (21) provided on top of the first insulator (13); a second pad (22) provided in the second insulator (21) is arranged on the first pad (17) and is in contact with the first pad (17); a third pad (29) provided in the second insulator (21) and arranged above the second pad (22); a third insulator (31) provided on top of the second insulator (21); and a fourth pad (32) provided in the third insulator (31), is arranged on the third pad (29) and is in contact with the third pad (29), wherein the shape of the first pad (17) and the second pad (22) is the same in plan view and the shape of the third pad (29) and the fourth pad (32) is the same in plan view, and the shape of the third and fourth pads in top view differs from the shape of the first and second pads in top view. [2] Semiconductor device according to claim 1, wherein the shape of each of the first, second, third and fourth pads in plan view includes, in addition to the shape of a contact area, the size of a contact area of ​​each of the first, second, third and fourth pads. [3] Semiconductor device according to claim 1, wherein the thickness of the third or fourth pad differs from the thickness of the first or second pad. [4] Semiconductor device according to claim 1, further comprising: a first memory cell array (26) provided in the second isolator (21); and a second memory cell array (36) provided in the third isolator (31). [5] Semiconductor device according to claim 4, further comprising a circuit (12) provided in the first insulator (13) and configured to control the first and second memory cell array. [6] Semiconductor device according to claim 1, wherein a top side of the first insulator (13) or a bottom side of the second insulator (21) is formed from a first insulating material, and a top side of the second insulator (21) or a bottom side of the third insulator (31) is formed from a second insulating material that differs from the first insulating material. [7] Semiconductor device according to claim 6, wherein one of the first and second insulating materials contains silicon and oxygen, and another of the first and second insulating materials contains silicon, carbon and nitrogen. [8] Method for manufacturing a semiconductor device, comprising: Formation of a first insulator (13) on a first substrate (11); Forming a first pad (17) in the first insulator (13); Forming a second insulator (21) on a second substrate (61); Forming a second pad (22) and a third pad (29) in the second insulator (21); Forming a third insulator (31) on a third substrate (62); Forming a fourth pad (32) in the third insulator (31); Bonding the first and second insulators so that the first pad (17) is in contact with the second pad (22), and annealing at least the first and second pads at a first temperature after bonding the first (13) and second insulator (21); and Bonding the second and third insulators so that the third pad (29) is in contact with the fourth pad (32), and annealing at least the third and fourth pads at a second temperature after bonding the second and third insulators, where the second temperature differs from the first temperature, wherein the shape of the first pad (17) and the second pad (22) is the same in plan view and the shape of the third pad (29) and the fourth pad (32) is the same in plan view, and the shape of the third and fourth pads in top view differs from the shape of the first and second pads in top view. [9] Method according to claim 8, wherein the bonding of the second and third insulators is carried out after annealing at the first temperature. [10] Method according to claim 8, wherein the bonding of the first and second insulators is carried out after annealing at the second temperature. [11] The method of claim 8, further comprising: Forming a first memory cell array (26) on the second substrate prior to bonding the first and second insulators and bonding the second and third insulators; and Forming a second memory cell array (36) on the third substrate prior to bonding the first and second insulators and bonding the second and third insulators. [12] Method according to claim 11, further comprising forming a circuit (12) for controlling the first and second memory cell array on the first substrate (11), wherein the circuit is formed prior to bonding the first and second insulators and bonding the second and third insulators. [13] Method according to claim 12, wherein the second temperature is higher than the first temperature. [14] Method according to any one of claims 8 to 13, wherein the shape of each of the first, second, third and fourth pads in top view includes, in addition to the shape of a contact surface, the size of a contact surface of each of the first, second, third and fourth pads.

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