Air gap with inverted T-shaped lower section extending through at least one metal layer, and corresponding method

Abstract

Semiconductor device (270), comprising: a device layer (102) with a transistor gate (132) having a silicide layer (140) and an etch stop layer (142) over a gate body (134); at least one metal layer (110, 114) over the device layer (102), wherein the at least one metal layer (110, 114) comprises a dielectric (150) with a conductor (172) therein; and an air gap (250) extending through the dielectric (150) of the at least one metal layer (110, 114), wherein in a lower section of the air gap (250) a part of the etch stop layer (142) above the gate body (134) is removed and the lower section of the air gap (250) contacts the silicide layer (140) above the gate body (134), such that the lower section of the air gap (250) has an inverted T-shape above the gate body (134), wherein the etch stop layer (142) is formed from a material that etches faster than the dielectric (150) with respect to wet etching.

Description

BackgroundTechnical area

[0001] The present invention relates to semiconductor devices and, more particularly, to a semiconductor device having an air gap extending through at least one metal layer and having an inverted T-shaped lower portion in contact with a silicide layer over a gate body of a transistor gate. background

[0002] Radio frequency (RF) switches are commonly used in telecommunications devices such as smartphones to route high-frequency telecommunications signals through transmission paths. For example, RF switches are often used in smartphones to enable use with various digital wireless technology standards deployed in different regions. Current RF switches are typically fabricated on semiconductor-on-insulator (SOI) substrates. A challenge with RF switches fabricated in SOI substrates is the control of two competing parameters: the on-resistance (R on ), i.e. the resistance of the switch when switched on, and the switching-off capacity (C off), which indicates the amount of crosstalk or noise that can occur within the system, i.e., the extent to which transmitted signals in one circuit have an undesirable effect on another circuit. R on should be as low as possible when the RF switch is on to reduce power consumption, and C off should be minimized to reduce unwanted coupling noise. In conventional semiconductor manufacturing processes, a reduction of R on or C off to the opposite effect for the other parameter.

[0003] Document DE 10 2020 129 523 A1 describes a structure. This structure comprises an air gap structure, wherein the air gap structure comprises an opening in a first dielectric layer between adjacent conductors, a non-conforming dielectric layer above the opening, wherein the non-conforming dielectric layer closes an end portion of the opening, a connection point in the non-conforming dielectric layer above the end portion of the opening, and a conforming dielectric layer above the non-conforming dielectric layer. The conforming dielectric layer is structured such that it closes the connection point in the non-conforming dielectric layer and is free of wiring. The structure further comprises a wiring layer above the air gap structure.

[0004] A semiconductor device is described in DE 11 2020 002 933 T5. This semiconductor device comprises a gate electrode, a semiconductor layer including a source region and a drain region, with the gate electrode provided therebetween, contact plugs provided on the source region and the drain region, first metals stacked on the respective contact plugs, a first low-permittivity region provided in at least any region located between the first metals in an in-plane direction of the semiconductor layer and below a bottom surface of the first metal in a stacking direction of the semiconductor layer, and a second low-permittivity region provided in at least any region located between the contact plug and the gate electrode in the in-plane direction and below the first low-permittivity region in the stacking direction.US 2012 / 0235882 A1 in a planar region that is at least partially different from a planar region provided with the first low permittivity region.

[0005] A structure is known from document DE 10 2020 111 378 A1.This structure comprises a substrate having a first transistor and a second transistor formed thereon, the first transistor and the second transistor having the same height and each having source / drain regions and a gate structure, a local interconnect layer having source / drain contacts and gate contacts connected to the source / drain regions and the gate structure of the first transistor and the second transistor, the source / drain contacts being larger than the gate structures of the first and second transistors, a first interconnect layer on the local interconnect layer, the first interconnect layer having metal lines connected to the source / drain contacts and the gate contacts of the local interconnect layer, and an air gap extending into the local interconnect layer and the first interconnect layer. Summary

[0006] In a first aspect of the invention, a semiconductor device is provided according to independent claim 1. Advantageous embodiments thereof are defined in claims 2 to 7.

[0007] In a second aspect of the invention, a high-frequency semiconductor-to-insulator switch is provided according to independent claim 8. Advantageous embodiments thereof are defined in claims 9 to 14.

[0008] In a third aspect of the invention, a method according to independent claim 15 is provided. Advantageous embodiments thereof are defined in claims 16 to 20.

[0009] The above and other features of the invention will be apparent from the following more detailed description of embodiments of the invention. Short description of the drawings

[0010] The embodiments of this invention are described in detail with reference to the following figures, wherein like designations indicate like elements and wherein: Fig. 1 shows a cross-sectional view of embodiments of a starting structure for a method according to the invention. Fig. Figure 2 shows an enlarged cross-sectional view of an illustrative transistor gate. Fig. 3 shows a cross-sectional view of etching an opening for an air gap over a transistor gate according to embodiments of a method of the invention. Fig. 4 shows a cross-sectional view of the enlargement of the opening and the removal of an etch stop layer over a silicide layer over a gate body of the transistor gate according to embodiments of the method of the invention. Fig. 5 shows a cross-sectional view of the removal of an air gap mask according to embodiments of the invention. Fig. 6 shows a cross-sectional view of a formation of an air gap and a semiconductor device, such as a high-frequency SOI switch, including the air gap, according to embodiments of the invention. Fig. 7 shows a cross-sectional view of a formation of an air gap and a semiconductor device, such as a high-frequency SOI switch, including the air gap according to other embodiments of the invention. Fig. 8 shows a cross-sectional view of the formation of an air gap and a semiconductor device, such as a high-frequency SOI switch, including the air gap according to other embodiments of the invention. Fig. 9 shows a cross-sectional view of the formation of an air gap and a semiconductor device including the air gap according to alternative embodiments of the invention.

[0011] The drawings of the invention are not to scale. The drawings are intended to illustrate only typical aspects of the invention and are therefore not to be considered limiting the scope of the invention. Like reference numerals refer to like elements throughout the drawings. Detailed description

[0012] In the following description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the present invention may be practiced. These embodiments have been described in sufficient detail to enable those skilled in the art to practice the present invention, and it will be understood that other embodiments may be utilized and changes may be made without departing from the scope of the present invention. The following description, therefore, is illustrative only.

[0013] When an element such as a layer, region, or substrate is described as being "on" or "over" another element, it may be directly on top of the other element, or there may be intervening elements. On the other hand, when an element is described as being "directly on" or "directly over" another element, there may not be any intervening elements. When an element is described as being "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be any intervening elements. On the other hand, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0014] Reference throughout the specification to "one embodiment" or "an embodiment" of the present invention, as well as other variations thereof, means that a particular feature, structure, characteristic, etc. described in connection with the embodiment is included in at least one embodiment of the present invention. Therefore, the phrases "in one embodiment," as well as any other variations appearing at various points in the specification, are not necessarily all referring to the same embodiment. It is to be understood that the use of " / ," "and / or," and "at least one of," such as in the cases "A / B," "A and / or B," and "at least one of A and B," is intended to encompass only the selection of the first listed option (A), only the selection of the second listed option (B), or the selection of both options (A and B).Another example: In the cases of "A, B and / or C" and "at least one of options A, B and C", this wording is intended to cover only the first listed option (A), or only the selection of the second listed option (B), or only the selection of the third listed option (C), or the selection of the first and second listed options (A and B), or the selection of the first and third listed options (A and C), or the selection of the second and third listed options (B and C), or the selection of all three options (A and B and C). This can be extended to any number of listed options, as will be readily apparent to a person skilled in the art.

[0015] The present invention relates to methods for fabricating semiconductor devices having an air gap extending through at least one metal layer, and to the semiconductor device thus fabricated. Embodiments of the invention utilize an air gap extending through the dielectric of at least one metal layer. The air gap has a lower portion contacting a silicide layer over a gate body of the transistor gate and having an inverted T-shape over the gate body. The air gap reduces the capacitance between a transistor gate in a device layer and adjacent wires and vias used to contact the source and drain of the transistor.This capacitance reduction can reduce the transistor's off-state capacitance when used in applications such as high-frequency switches in semiconductor-on-insulator (SOI) or bulk (non-SOI) substrates. The use of an air gap spanning two or more metal layers across a transistor gate provides a mechanism for reducing the off-state capacitance of any device that utilizes it by controlling one of the primary factors in a field-effect transistor's (FET) intrinsic capacitance: the effective dielectric constant of the contact or device layer and at least the first metal layer.

[0016] While the invention is described with reference to a SOI substrate and an RF switch, the embodiments can be applied, without limitation, to various alternative semiconductor devices, such as low-noise amplifiers (LNAs) and power amplifiers. Furthermore, the teachings can be applied to various substrates, such as a bulk substrate.

[0017] In Fig. 1 is a cross-sectional view of a first process of a method of forming an air gap for a semiconductor device according to embodiments of the invention. Fig. 1 shows a semiconductor device 100 after formation of a device layer 102, a first interconnect layer 104, and a second interconnect layer 106. The first interconnect layer 104 includes a first metal layer 110 (M1) and a first via layer 112 (V0 layer), and the second interconnect layer 106 includes a second metal layer 114 (M2) and a second via layer 116 (V1). The invention can also be applied to devices with multiple interconnect layers. The device layer 102 is illustrated as comprising a semiconductor-on-insulator (SOI) substrate 120 having a semiconductor substrate 122 with an insulator layer 124 thereover and a semiconductor-on-insulator (SOI) layer 126 thereover. The substrate 122 and the SOI layer 126 may comprise any semiconductor material without limitation to silicon, germanium, silicon germanium, and silicon carbide.Furthermore, a portion or all of the semiconductor substrate 122 and / or the SOI layer 126 may be strained. For example, the SOI layer 126 may be stretched. The SOI layer 126 may be segmented by shallow trench isolations (STIs) 128. The insulator layer 124 may comprise any suitable dielectric material for the desired application, e.g., silicon oxide (SiOx) or (less commonly) sapphire. The insulator layer 124 and / or the STI 128 may also comprise the same material, e.g., silicon dioxide or another interlayer dielectric material described herein.

[0018] The device layer 102 also includes a number of transistors 130 formed therein. Each transistor 130 may comprise any transistor structure known today or later developed, such as doped source / drain regions (not labeled) in the SOI layer 126 with a transistor gate 132 above and therebetween. Fig. 2 shows, for illustrative purposes, an enlarged cross-sectional view of a transistor gate 132. Each transistor gate 132 may include, among other structures, a gate body 134 made of polysilicon or a metal (commonly referred to as "PC"), spacers 136 around the gate body 134, a gate dielectric 138 under the gate body 134, a silicide layer 140 over the gate body 134 (i.e., a silicon-metal alloy), and an etch stop layer 142 over the silicide layer 140 and / or the spacers 136. The spacers 136 may comprise any now known or later developed spacer material, such as silicon nitride (Si3N4), and the gate dielectric 138 may comprise any now known or later developed gate dielectric, such as silicon nitride (Si3N4). B.: Hafnium silicate (HfSiO), hafnium oxide (HfO2), zirconium silicate (ZrSiO x), zirconium oxide (ZrO2), silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), high-k material, or a combination of these materials. The etch stop layer 142 may comprise any now known or later developed etch stop material, such as silicon nitride, capable of etching as described herein. The silicide layer 140 may be formed from any now known or newly developed silicide material, e.g., titanium, nickel, cobalt, etc. Of course, each transistor gate 132 may extend into, out of, or across the page, as shown.

[0019] Back to Fig. 1: Each metal layer 110, 114 and via layer 112, 116 may comprise a dielectric 150. The dielectric 150 may comprise any known interlayer dielectric (ILD) having an etch rate in dilute hydrofluoric acid (DHF) lower than that of silicon nitride. In one non-limiting example, the dielectric 150 comprises an undoped fused silica glass such as tetraethyl orthosilicate (TEOS) silicon oxide. Each metal layer 110, 114 may have a corresponding metal cap layer 154 on its top surface. Similarly, each via layer 112 may have a corresponding via cap layer 156 on its top surface. Each cap layer 154, 156 may comprise one or more layers, e.g., B. a silicon oxide layer 158 and an etch stop layer 160 formed of silicon nitride (nitride), silicon carbon nitride (SiCN), etc., as is known in the art.Of course, various other forms of cover layers may also be used. Furthermore, although cover layers 154, 156 are depicted as identical, they may be formed from different materials, thicknesses, etc.

[0020] A number of conductors in the form of contacts 170 may extend through the dielectrics 150 of the via layers 112, 116 to various parts of the device layer 102 and / or underlying metal layers, e.g., the first metal layer 110. In the example shown, the contacts 170 in the first via layer 112 extend to the source / drain regions of the transistors 130. Of course, each contact 170 may comprise a conductor such as aluminum or copper within a refractory metal layer of ruthenium; however, other refractory metals such as tantalum (Ta), titanium (Ti), tungsten (W), iridium (Ir), rhodium (Rh), and platinum (Pt), etc., or mixtures thereof, may also be used. Typically, the contacts 170 extend primarily vertically within the semiconductor device 100 to connect the conductors in the layers, i.e., vertically on the side, as shown.Each metal layer 110, 114 may include a number of conductors in the form of metal wires 172 therein. The same materials as listed for contacts 170 may be used for each metal wire 172. Unlike contacts 170, metal wires 172 typically extend horizontally or laterally within a layer within semiconductor device 100 to connect contacts 170 therein, i.e., into, out of, or across a side, as shown. In this way, first metal layer 110 may include a metal wire 172 extending into or out of the side and possibly laterally parallel to transistor gate 132 in device layer 102. Similarly, second metal layer 114 may include a metal wire 172 extending into or out of the side and perhaps laterally across the side to connect contacts in second via layer 116.

[0021] The Fig. 1 can be manufactured using any semiconductor manufacturing technique known today or later developed, such as material deposition, photolithographic patterning and etching, doping, etc. Although the contacts 170 and the wires 172 in Fig. 1 are shown as single damascene layers, they may also be formed with dual damascene layers comprising refractory metal coated with copper or tungsten, as is known in the art. Although two interconnect layers (104, 106) are shown, each with a metal layer (110, 114), the invention is applicable to any number of interconnect layers and metal layers.

[0022] “Deposition” or “deposition” as described herein may include any technique now known or later developed suitable for the material to be deposited, including, without limitation, for example: chemical vapor deposition (CVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), semi-atmosphere CVD (SACVD), high density plasma CVD (HDPCVD), rapid thermal CVD (RTCVD), ultra-high vacuum CVD (UHVCVD), reaction limited CVD (LRPCVD), metal organic CVD (MOCVD), sputter deposition, ion beam deposition, electron beam deposition, laser assisted deposition, thermal oxidation, thermal nitriding, spin-on methods, physical vapor deposition (PVD), atomic layer deposition (ALD), chemical oxidation, molecular beam epitaxy (MBE), plating, and evaporation.

[0023] Fig. 1 also shows formation of an air gap mask 176 exposing a portion 178 of a topmost metal layer, which, as shown, includes the second metal layer 114 (i.e., its metal cap layer 154) of the second interconnect layer 106. The second metal layer 114 overlies the second via layer 116 of the second interconnect layer 106, which overlies the first metal layer 110, overlies the first via layer 112 of the first interconnect layer 104, which overlies the device layer 102. The mask 176 may be formed, for example, after damascene planarization of the second metal layer 114, e.g., using chemical mechanical polishing (CMP), and may include any masking material known today or later developed. The mask 176 is patterned and etched in a conventional manner to create openings 180 therein.In one embodiment, transistor gate 132 is approximately 200 nanometers (nm) wide, and openings 180 in air gap mask 176 may have a size of approximately 160 nm to 240 nm, particularly 200 nm. These widths may scale with larger or smaller channel transistor widths or with larger or smaller widths of contact 170 and wire 172.

[0024] Fig. 3 shows a cross-sectional view of the formation of an opening 200 through the dielectric 150 of at least one metal layer over the transistor gate 132 in the device layer 102 of a semiconductor structure. (For descriptive purposes, two metal layers 110, 114 are shown, but one or more than two are possible.) Fig. 9 shows a device with an air gap 250 in a metal layer 110. The opening 200 may be formed by etching the opening 200 through the second interconnect layer 106, through at least the first metal layer 110 of the first interconnect layer 104, and a portion of the first via layer 112 using the air gap mask 176. Forming the opening 200 creates a multi-layer opening with a single etch process instead of a two-step process and results in a more consistent center-to-edge width. The opening 200 exposes the sidewalls 202 of the dielectrics 150 of the interconnect layers 104, 106, including those of the first and second metal layers 110, 114 and the second via layer 116, as well as a portion of the first via layer 112.Etching generally refers to the removal of material from a substrate (or from structures formed on the substrate) and is often performed using a mask so that material can be selectively removed from certain areas of the substrate while leaving other areas untouched. There are generally two categories of etching processes: (i) wet etching and (ii) dry etching. Wet etching is performed using a solvent (e.g., an acid or a base) chosen to selectively dissolve a particular material (e.g., oxide) while leaving another material (e.g., polysilicon or nitride) relatively intact. This ability to selectively etch specific materials is fundamental to many semiconductor manufacturing processes. Wet etching generally etches a homogeneous material (e.g., oxide) isotopically, but wet etching can also etch single-crystalline materials (e.g.,Silicon wafers) can be etched anisotropically. Dry etching can be performed using a plasma. Plasma systems can operate in different modes by adjusting the plasma parameters. In conventional plasma etching, high-energy, neutrally charged free radicals are generated, which react at the wafer's surface. Because the neutral particles attack the wafer from all angles, this process is isotopic. In ion milling or sputter etching, the wafer is bombarded with high-energy noble gas ions that approach the wafer from only one direction, which is why this process is highly anisotropic. Reactive ion etching (RIE) operates under conditions that are intermediate between sputter and plasma etching and can be used to create deep, narrow structures, such as STI trenches. Fig. 3, the etching (indicated by arrows) may include an RIE. As used herein, "over the transistor gate" means when referring to the opening 200 and / or an air gap 250 formed therewith ( Fig. 6-8) that the transistor gate 132 is overlapped in some way.

[0025] According to the presentation in Fig. 3, the opening 200 may expose the etch stop layer 142 above the silicide layer 140 above the gate body 134 of the transistor gate 132. Considering the depth of the opening 200, the etching of the opening 200 may be terminated when the opening 200 exposes the etch stop layer 142. The etching process in Fig. 3 can be controlled to select the extent of exposure of a top surface of the transistor gate 132. Although two openings 200 are illustrated, any number of openings 200 may be formed over any number of transistor gates 132. Furthermore, the openings 200 may take the form of trenches (e.g., into the side or out of the side or across the side at various cross-sections of the device). In this way, the air gaps 250 ( Fig. 6-7) formed according to embodiments of the invention have a variety of different lateral arrangements.

[0026] According to the presentation in Fig. 3, forming the opening 200 exposes an edge 206 of a first metal cap layer 154 over a top metal layer (e.g., a second metal layer 114) of the at least one metal layer 110, 114 and the dielectric 150 beneath the top metal cap layer 114 in the upper region of the opening 200. Forming the opening 200 may also expose an edge 208 of a second metal cap layer 154 over another metal layer (e.g., the first metal layer 110) of the at least one metal layer 110, 114 located beneath the top metal layer 114, and a dielectric 150 beneath the second metal cap layer 154. Similarly, the (unnumbered) edges of the via cap layers 156 may be exposed by forming the opening 200.

[0027] At this stage of air gap formation, processing may include an enlargement of the opening 200. Fig. Figure 4 shows cross-sectional views of the enlargement of the opening 200 above the transistor gate 132 to remove the etch stop layer 142 and expose the silicide layer 140 above the transistor gate 132, i.e., the gate body 134. In the enlargement, the dielectric 150 above the transistor gate 132 is undercut. In this way, the opening 200 (and possibly the air gap 250 ( Fig. 6-8)) has a lower portion that contacts the silicide layer 140 above the gate body 134 and has an inverted T-shape above the gate body 134 (see reference to the inverted T-shape in Fig. 4). Due to the enlargement, a portion of the etch stop layer 142 above the gate body 134 is removed, which reduces its effective dielectric constant above the gate body 134. Due to the enlargement, the opening 200 may also extend below a top surface 220 of the silicide layer 140 and along an upper portion of the gate body 134. That is, the opening 200 exposes the sides of the upper portion of the gate body 134, e.g., its spacer 136, and is in contact with the upper portion of the gate body 134. Consequently, the air gap 250 may, as shown in the Fig. 6 and Fig. 8, also extend below the upper surface 220 of the silicide layer 140. The enlargement also reveals the side walls 202 ( Fig. 3) of the dielectric 150 of the connecting layers 104, 106 in the opening 200. Among other advantages, the increase in the (width between the) sidewalls causes an increase in the opening 200 and thus the air gaps 250 ( Fig. 6-8), thereby reducing the effective dielectric constant of the interconnect layers 104, 106, while the upper opening of the air gap, which is to be sealed in the next process step, remains narrower than the air gap itself. If silicon oxide films, such as undoped fused silica (USG), are used for the dielectrics 150 of the metal layers 110, 114 and silicon nitride for the cap layer(s) 154, 156, a hydrofluoric acid (HF) wet etch could be used for this magnification process (indicated by arrows in Fig. 4). In one embodiment, this method may include any known or later developed treatment of the etch stop layer 142, e.g., an RIE cleaning or similar treatment, and subjecting the opening 200 to a wet etch, e.g., using dilute hydrofluoric acid (DHF). The HF concentration may, e.g., range from 10:1 to 500:1 dilution with water. The etch stop layer 142, e.g., of ultraviolet silicon nitride, etches faster than the dielectrics 150, e.g., of USG.

[0028] Since the dielectrics 150 also etch faster than the dielectric(s) of the cover layer(s) 154, 156, Fig. 4, that the width W1 of the opening 200 is, for example, wider than the width W2 ( Fig. 3) at the same location before enlargement. In a Fig. 4, the recessing of the exposed side walls 202 ( Fig. 3) the dielectrics 150 of the interconnect layers 104, 106 in the opening 200 expose the edges 206, 208 of at least one of the metal cap layers 154 of the first metal layer 110 (if not already exposed), as shown. In some cases, the recess may expose the edges of the via cap layers 156 of one or more via layers 112, 116. The enlargement process may also enlarge the opening 200 to be adjacent to the edge(s) 206, 208 of at least one cap layer 154, 156 of the metal layer(s) 110, 114, i.e., the opening 200 is located adjacent to, above, and below the edges 206, 208. That is, the air gap 250 ( Fig. 6-8) after its formation, adjoins the edge(s) 206, 208 of the cover layer(s) 154, 156 above the metal layer(s) 110, 114. In certain embodiments, the air gap 250 ( Fig. 6-8) the edge(s) 206, 208 of the cap layer(s) 154, 156 above the metal layer(s) 110, 114. As previously mentioned, the etching removes the etch stop layer 140 above the silicide layer 140 above the gate body 134. In a non-limiting example, the opening 200 may have an average width of 160 nm, i.e., between 135 and 185 nm, after enlargement.

[0029] Fig. 5 shows a cross-sectional view of the semiconductor device after removal of the air gap mask 176. The air gap mask 176 ( Fig. 1, Fig. 3 and Fig. 4) can be removed with any known or later developed resist strip, in-situ or ex-situ.

[0030] Fig. 6 shows a cross-sectional view of forming an air gap 250 (by at least one metal layer 110, 114) by forming a dielectric layer 252 over the opening 200 to seal the opening 200. A lower portion of the air gap 250 contacts the silicide layer 140 above the gate body 134 and has an inverted T-shape above the gate body 134. The air gap 250 also extends below the top surface 220 of the silicide layer 140, e.g., the sides of the T-shape curve around the silicide layer 140, the spacers 136, and the gate body 134. The gate body 134 remains covered by the silicide layer 140 and the spacers 136. An air gap 250 is formed over the transistor gate 132 by depositing a dielectric layer 252, which acts as an air gap cap layer to seal the opening 200 at a surface of the top metal layer 114. As shown in Fig. 8, a side wall 202 ( Fig. 3) the dielectric layers 150 of the metal layers 110, 114 are coated with the dielectric layer 252 (shaded slightly darker for clarity), ie, the air gap 250 is slightly narrowed. Although not shown, the edges 206, 208 of the cover layers 154 of the metal layers 110, 114 and the (unnumbered) edges of the via layers 112, 116 can also be covered. The side walls 202 ( Fig. 3) the dielectric 150 may be coated if, for example, the dielectric layer 252 is able to penetrate into the opening 200 during formation and / or the opening 200 is wide enough to allow the dielectric layer 252 to enter before the opening is closed.

[0031] The air gap 250 is shown vertically aligned with the transistor gate 132, although perfect alignment is not required in all cases. The dielectric layer 252 may comprise any dielectric material capable of sealing the opening 200 and acting as an interlayer dielectric (ILD) for a next via layer to be formed therein. In one embodiment, the dielectric layer 252 may comprise a chemical vapor deposited (CVD) dielectric. In another embodiment, the dielectric layer 252 may comprise a plasma enhanced chemical vapor deposition (PECVD) silane oxide. PECVD silane oxide may be chosen because it has very low step coverage, resulting in a larger air gap volume. In other embodiments, the dielectric layer 252 may comprise a thin silicon nitride layer with an ILD oxide, e.g.,a TEOS-based PECVD oxide, a PVD oxide, or a similar oxide (individual layers are not shown for clarity). The dielectric layer 252 may include more than one layer of interlayer dielectric material. The air gap 250 does not expose any contact 170 or metal wire 172 within the dielectric 150 of the interconnect layers 104, 106. That is, the dielectric 150 or any lining of the dielectric 150 through the dielectric layer 252 covers any conductive wire 172 in the first metal layer 110 and the second metal layer 114 or any conductive contact 170 in the first via layer 112 and the second via layer 116.

[0032] According to the presentation in Fig. 6, the air gap 250 extends vertically across at least one metal layer 110, 114. In particular, the air gap 250 extends vertically above and below the metal wires 172 in the first metal layer 110 and the second metal layer 114, i.e., below the dielectric 150 of the first metal layer 110 and above the metal wire 172 in the second metal layer 114. The air gap 250 also extends across a top surface of the second metal layer 114. As shown in Fig. 6, the air gap 250 may vertically contact the silicide layer 140 of the transistor gate 132, i.e., the silicide layer 140 may be exposed in the air gap 250. The air gap 250 may surround the edges 206, 208 of the cap layer 154 of the metal layers 110, 114 (and the unlabeled edges of the cap layer 156 of the via layers 112, 116). The air gap 250 extends only partially into the dielectric layer 252 covering the air gap, so that the dielectric layer 252 can serve as a dielectric for a third via layer with minimal disturbance from the air gap 250. The through holes 260 in the dielectric layer 252 may extend to another metal layer (not shown) that may be formed in the dielectric layer 252 or an overlying dielectric layer using a conventional or later developed technique. The dielectric layer 252 closes the opening 200 ( Fig. 6) Independent of the lateral arrangement. The lateral arrangement of the opening 200 can be controlled to avoid its exposure by subsequently formed vias 260, thereby preventing the conductor of the via 260 from entering the air gap 250.

[0033] With reference to Fig. 6 and Fig. 7 also shows a semiconductor device 270 according to embodiments of the invention. In one embodiment, the semiconductor device 270 may include a device layer 102 having a transistor gate 132 with a silicide layer 140 over the gate body 134. The etch stop layer 142 is removed from at least a portion of the silicide layer 140, e.g., where an air gap 250 is present. The transistor 130 may be in the form of a CMOS field-effect transistor (FET) known today or developed later. The semiconductor device 270 may also include at least one metal layer 110, 114 over the device layer 102. The metal layers 110, 114 may be part of the interconnect layers 104, 106, respectively, over the device layer 102. The first interconnect layer 104 may include one or more interconnect layers, e.g.,the first via layer 112 and the first metal layer 110; and the second interconnect layer 106 may include one or more interconnect layers, e.g., the second via layer 116 and the second metal layer 114. That is, the first metal layer 110 is part of the first interconnect layer 104, which also includes the first via layer 112, and the second metal layer 114 is part of the second interconnect layer 106, which also includes the second via layer 116. In each case, the metal layers 110, 114 include a dielectric 150 with conductors (e.g., wires 172) therein.

[0034] The semiconductor device 270 also includes an air gap 250 that extends through the dielectric 150 of the at least one metal layer 110, 114. The air gap 250 is continuous through the at least one metal layer 110, 114, i.e., there is no interruption in the air gap. The at least one metal layer may include at least a first metal layer 110 above the device layer 102 and a second metal layer 114 above the first metal layer 110. The air gap 250 may extend through any number of additional metal layers, e.g., a third, fourth, fifth metal layer, etc., as well as through any intermediate via layers. The air gap 250 may extend through the second via layer 116 and a portion of the first via layer 112. The air gap 250 is located above the transistor gate 132 in the device layer 102 below a bottommost metal layer, e.g., a B.the first metal layer 110 of the at least one metal layer. A lower portion of the air gap 250 contacts the silicide layer 140 above the gate body 134 and has an inverted T-shape above the gate body 134. As shown in FIGS. Fig. 6 and Fig. 8, the air gap 250 may also extend below the upper surface 220 of the silicide layer 140, e.g., the sides of the T-shape curve around the silicide layer 140, the spacers 136, and the gate body 134. Thus, the air gap 250 may extend adjacent to an upper portion of the gate body 134, ie, it is located laterally of a part of the upper part of the gate body 134. As shown in Fig. 7, a lower portion of the air gap 250 may contact the silicide layer 140 above the gate body 134 and have the inverted T-shape above the gate body 134, but may not extend below an upper surface of the silicide layer 140 or along an upper portion of the gate body 134. In any case, the gate body 134 remains covered by the silicide layer 140 and the spacers 136. The dielectric layer 252 seals the air gap 250 and may, as in Fig. 8, the side wall 202 ( Fig. 3) coating the dielectric 150 with at least one metal layer 110, 114 (lining).

[0035] The semiconductor device 270 may also include at least one cap layer 154 over each metal layer 110, 114. The metal cap layer 154 of a topmost metal layer (e.g., the second metal layer 114) is located above the dielectric 150 of the second metal layer 114, and the metal cap layer 154 of the second metal layer 114 is located above the dielectric 150 of the first metal layer 110 (with the second via layer 116 therebetween). The air gap 250 may surround the edge(s) 206, 208 of the cap layer(s) 154 over each metal layer 110, 114 (and the unlabeled edges of the cap layer 156 of the via layers 112, 116). That is, the air gap 250 is located adjacent to, above, and below the edges.

[0036] The air gap 250 includes a dielectric layer 252 that seals an upper end of the air gap. As shown in Fig. 8, a film layer of dielectric layer 252 (not shown) may reduce the width from that present after the enlargement. In one embodiment, air gap 250 may have a height-to-width ratio greater than about 6.5. Other dimensions and / or ratios are also possible. Although not shown, air gap 250 may be extended laterally into and out of the page and may have any desired lateral configuration.

[0037] Fig. 9 shows a cross-sectional view of the semiconductor device 270 with the air gap 250 in a metal layer 110. Although Fig. 9 the air gap 250 in the form of the embodiment of Fig. 6 shows, it can have any of the formats described here.

[0038] Any number of air gaps 250 may be provided, with each air gap 250 extending through each of the at least one metal layer 110, 114, etc., and contacting the silicide layer 140 above a corresponding gate body 134 of a transistor gate 132. Each air gap 250 has an inverted T-shape in contact with the silicide layer 140 at a lower portion thereof.

[0039] The semiconductor device 270 can be used to form a variety of devices, such as a radio-frequency semiconductor-on-insulator (RFSOI) switch, a low-amplitude amplifier, a power amplifier, etc. The use of the air gap 250 above the transistor gate 132 according to the various embodiments of the invention provides a mechanism for reducing the turn-off capacitance and on-resistance of any device using it by controlling one of the primary factors in intrinsic FET capacitance: the effective dielectric constant of the first via layer 112 and the first metal layer 110.

[0040] The process described above is used in the manufacture of integrated circuit chips. The resulting integrated circuit chips can be distributed by the manufacturer in the form of a raw wafer (e.g., a single wafer comprising multiple unpackaged chips), as a bare chip, or in packaged form. The chip can be integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of an intermediate or final product. The final product can be any product that includes integrated circuit chips, such as computer products with a display, keyboard, or other input device, and a central processor.

[0041] The terminology used herein is for the purpose of describing particular embodiments only and is not limiting of the invention. As used herein, the singular forms “a,” “an,” and “the” include the plural forms unless the context clearly indicates otherwise. It is further understood that the terms “comprises” and / or “comprising,” when used in this description, specify the presence of certain features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. “Optional” means that the subsequently described event or circumstance may or may not occur, and that the description includes instances where the event occurs and instances where it does not occur.

[0042] Vague language, as used herein in the specification and claims, can be used to modify any quantitative representation that could permissibly vary without resulting in a change in the basic function to which it relates. Accordingly, a value modified by one or more terms such as "approximately," "approximately," and "substantially" is not limited to the precisely stated value. In at least some cases, the vague language may correspond to the accuracy of an instrument for measuring the value. Here and throughout the specification and claims, range limitations may be combined and / or interchanged; such ranges are identified and include all subranges encompassed therein, unless the context or language indicates otherwise.The term "approximately", when referring to a specific value within a range, applies to both values ​​and, unless otherwise dependent on the precision of the measuring instrument, may mean + / - 10% of the stated value(s).

Claims

[1] A semiconductor device (270) comprising: a device layer (102) having a transistor gate (132) comprising a silicide layer (140) and an etch stop layer (142) over a gate body (134); at least one metal layer (110, 114) over the device layer (102), wherein the at least one metal layer (110, 114) comprises a dielectric (150) having a conductor (172) therein; and an air gap (250) extending through the dielectric (150) of the at least one metal layer (110, 114), wherein in a lower portion of the air gap (250) a portion of the etch stop layer (142) above the gate body (134) is removed and the lower portion of the air gap (250) contacts the silicide layer (140) above the gate body (134), such that the lower portion of the air gap (250) has an inverted T-shape above the gate body (134), wherein the etch stop layer (142) is formed of a material that etches faster than the dielectric (150) with respect to a wet etch. [2] The semiconductor device (270) of claim 1, wherein the at least one metal layer (110, 114) comprises at least a first metal layer (110) over the device layer (102) and a second metal layer (114) over the first metal layer (110). [3] The semiconductor device (270) of claim 1, further comprising at least one capping layer (154) over each metal layer (110, 114), wherein the air gap (250) surrounds an edge (206) of the at least one capping layer (154) over each metal layer (110, 114). [4] The semiconductor device (270) of claim 1, wherein the at least one metal layer (110, 114) comprises at least two metal layers (110, 114) comprising a first metal layer (110) that is part of a first interconnect layer (104) that also includes a first via layer (112), and a second metal layer (114) that is part of a second interconnect layer (106) that also includes a second via layer (116), wherein the air gap (250) extends through the second via layer (116) and a part of the first via layer (114). [5] The semiconductor device (270) of claim 1, further comprising a dielectric layer (252) sealing the air gap (250) and coating a sidewall (202) of the dielectric (150) of the at least one metal layer (110, 114). [6] The semiconductor device (270) of claim 1, wherein the air gap (250) extends below a top surface of the silicide layer (140). [7] The semiconductor device (270) of claim 6, wherein the air gap (250) extends adjacent to an upper portion of the gate body (134). [8] High-frequency semiconductor-on-insulator switch, comprising a transistor gate (132) in a semiconductor-on-insulator device layer (102) of a semiconductor-on-insulator substrate (120), the transistor gate (132) comprising a silicide layer (140) and an etch stop layer (142) over a gate body (134); at least one metal layer (110, 114) over the semiconductor-on-insulator device layer (102), the at least one metal layer (110, 114) comprising a dielectric (150) having a conductor (172) therein; and an air gap (250) extending through the dielectric (150) of the at least one metal layer (110, 114), wherein in a lower portion of the air gap (250) a portion of the etch stop layer (142) above the gate body (134) is removed and the air gap (250) contacts the silicide layer (140) above the gate body (134) such that the air gap (250) has an inverted T-shape above the gate body (134), wherein the etch stop layer (142) is formed of a material that etches faster than the dielectric (150) with respect to a wet etch. [9] The high-frequency semiconductor-on-insulator switch of claim 8, wherein the at least one metal layer (110, 114) comprises at least a first metal layer (110) over the semiconductor-on-insulator device layer (102) and a second metal layer (114) over the first metal layer (110). [10] The high-frequency semiconductor-on-insulator switch of claim 8, further comprising at least one cap layer (154) over each metal layer (110, 114), wherein the air gap (250) is adjacent to an edge (206) of the at least one cap layer (154) over each metal layer (110, 114). [11] The high-frequency semiconductor-on-insulator switch of claim 8, wherein the at least one metal layer (110, 114) comprises a first metal layer (110) that is part of a first interconnect layer (104) that also includes a first via layer (112), and a second metal layer (114) that is part of a second interconnect layer (106) that also includes a second via layer (116), wherein the air gap (250) extends through the second via layer (116) and a part of the first via layer (112). [12] The high-frequency semiconductor-on-insulator switch of claim 8, further comprising a dielectric layer (252) sealing the air gap (250) and coating a sidewall (202) of the dielectric (150) of the at least one metal layer (110, 114). [13] The high-frequency semiconductor-on-insulator switch of claim 8, wherein the air gap (250) extends below a top surface of the silicide layer (140). [14] The high-frequency semiconductor-on-insulator switch of claim 13, wherein the air gap (250) extends adjacent to an upper portion of the gate body (134). [15] Method comprising: forming an opening (200) through a dielectric (150) of at least one metal layer (110, 114) over a transistor gate (132), the opening exposing an etch stop layer (142) over a silicide layer (140) over a gate body (134) of the transistor gate (132); enlarging the opening (200) above the transistor gate (132) to remove the etch stop layer (142) and expose the silicide layer (140) above the transistor gate (132), wherein the enlargement of the opening (200) undercuts the dielectric (150) above the transistor gate (132); and forming an air gap (250) by forming a dielectric layer (252) over the opening (200) to seal the opening (200), wherein a lower portion of the air gap (250) contacts the silicide layer (140) over the gate body (134) and has an inverted T-shape over the gate body (134). [16] The method of claim 15, wherein forming the opening (200) comprises performing a reactive ion etch and enlarging comprises treating the etch stop layer (142) and applying a dilute hydrofluoric acid etch to the opening (200). [17] The method of claim 15, wherein the opening (200) extends through the enlargement below an upper surface of the silicide layer (140) and along an upper portion of the gate body (134), and wherein the air gap (250) extends below the upper surface of the silicide layer (140). [18] The method of claim 15, wherein said enlarging extends said opening (200) to surround an edge (206) of at least one cap layer (154) over said at least one metal layer (110, 114), and wherein said air gap (250) is adjacent to said edge (206) of said at least one cap layer (154) over said at least one metal layer (110, 114). [19] The method of claim 15, wherein the at least one metal layer (110, 114) comprises a first metal layer (110) that is part of a first interconnect layer (104) that also comprises a first via layer (112), and a second metal layer (114) that is part of a second interconnect layer (106) that also comprises a second via layer (116), wherein the air gap (250) extends through the second via layer (116) and a part of the first via layer (112). [20] The method of claim 15, wherein forming the air gap (250) connects a sidewall (202) of the dielectric (150) of the at least one metal layer (110, 114) to the dielectric layer (252).

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