METHOD AND STORAGE CONTROLLER FOR OPTIMIZING AN ACCESS SCHEME FOR A HOST'S STORAGE ACCESS TO A DATA STORAGE

Abstract

A method for optimizing an access scheme for storage accesses of a host to a data store managed by a storage controller with one or more storage media, in particular flash memory, is executed by the storage controller and includes: receiving an access scenario communicated by the host that defines a specific sequence of accesses to the data store to be performed by the host using the storage controller;Optimizing an access scheme corresponding to the received access scenario, which defines a specific sequence of physical memory accesses to the data storage to be performed by the memory controller to implement the access scenario, wherein the optimization to reduce the overall access time for the access scenario includes modifying at least one of the memory accesses by shifting a respective physical memory area to be addressed with respect to an address translation and / or by bringing forward the respective memory access in time; and storing access information defining the optimized access scheme, such that the optimized access scheme can subsequently be activated by a call in such a way that it is automatically executed in response to the call according to the stored access information.

Description

[0001] The present invention relates to a method for determining an optimized access scheme that corresponds to a specific access scenario for accesses of a host to a data storage device via a storage controller, as well as to a storage controller configured to carry out the method and to a computer program or computer program product configured therefor.

[0002] Communication between the host and the memory controller primarily takes place via accesses, in particular read accesses where the host wants to read data from the data memory (e.g. data previously written by the host itself), or write accesses where it wants to write new data to the data memory. To do this, the host initiates an access to the memory controller which includes at least a memory address and access size before the actual data follows, be it data transmitted from the host to the memory controller in the case of a write access or data transmitted from the memory to the host in the case of a read access. The initiated accesses are then served by the memory controller, i.e. either data to be written transmitted by the host is stored in the data memory so that it is available at the specified memory address for future read accesses, or data to be read is read from the data memory and transmitted to the host.

[0003] When a host accesses its assigned data storage, a distinction can be made between sequential access, in which successive accesses occur to physically consecutive memory areas in the data storage, and random access, in which the memory areas affected by the successive accesses can be located anywhere in the data storage relative to each other. In many cases, such as with hard disk storage and flash memory, random accesses are generally less performant than sequential accesses.

[0004] US 2015 / 186052 A1 describes a data transfer control method for a storage device. The storage device communicates with a host via a SATA bus. The data transfer control method comprises the following steps: First, an X_RDY primitive is issued by the storage device to the host. After the storage device receives an R_RDY primitive from the host, a first frame is transmitted to the host. After the first frame is completely transmitted and within a specified time period before the transmission of a second frame, several SYNC primitives are issued by the storage device to the host. If the host does not issue the X_RDY primitive within the specified time period, the second frame is transmitted to the host. Definitions of terms

[0005] The term "host," as used herein, refers in particular to any device or system, e.g., a computer or an embedded system, on which an application can be executed that provides the actual functionality of the device or system. To do so, the host requires access to a data storage device, to which it performs write and / or read accesses to execute the application.

[0006] The term "data storage" or "memory" for short, as used herein, refers to an information storage device for storing data and reading it out. If the data represents one or more computer programs, the memory can also serve, in particular, as program memory. The memory can comprise one or more storage media. In particular, non-volatile memories, such as flash memories with one or more flash memory chips or embedded flash memory arrays serving as storage media, magnetic disk storage devices with one or more disks serving as storage media, or magnetic tape drives with one or more magnetic tapes serving as storage media are each data storage devices within the meaning defined here.

[0007] The term "memory controller," or "controller" for short, as used here, refers in particular to a device, such as an electronic circuit, that regulates data flow between the host and a data storage device with one or more storage media to which the host has access. The memory controller can, in particular, be part of a (persistent) data storage device. It abstracts properties of the data storage device for the host and can, in particular, independently perform optimizations to improve the performance of the host's accesses.

[0008] The term “access time”, as used here, refers to the time required by the memory controller to serve each access, i.e., for write access, the time between receipt of the write access request from the host and completion of storing the data in the data memory, and for read access, the time between the read access request from the host and completion of transmission of the read data to the host.

[0009] The term "access scenario," as used here, refers to a specific sequence of host accesses to the data memory to be executed with the aid of the memory controller. The access scenario can be defined, in particular, as a sequence of access segments and, if applicable, pauses in between, whereby an access segment defines an access using a memory address and an access size (in particular, a quantity of data to be read or written) and, if different access types are possible, also the type of access (read, write). If the memory controller performs an address translation (...If the system performs a mapping (address mapping) of logical memory addresses to physical memory addresses, the addresses specified in the access segments of the access scenario are usually logical memory addresses which are converted to physical memory addresses in the memory controller when the associated access is executed, in order to be able to access the data memory directly.

[0010] The term "access scheme," as used herein, refers to a specific sequence of physical memory accesses by the memory controller to the data memory using physical addresses, suitable for executing a given access scenario and corresponding thereto. A given access scenario can have multiple different access schemes. If no address translation is provided and the access requests transmitted from the host to the memory controller are already defined based on physical memory addresses, the access scenario is also the access scheme, so that both coincide.

[0011] The term "optimizing the / an access scheme," as used herein, refers in particular to the creation of an access scheme corresponding to a given access scenario, which, when executed, exhibits higher performance than another access scheme corresponding to the access scenario, from which the optimization is based. In cases without address translation, where the access scenario and a corresponding access scheme coincide, a modification of the access scheme made during the optimization requires the same modification of the access scenario.

[0012] The terms "comprises," "includes," "includes," "has," "has," "with," or any other variation thereof, as used herein, are intended to cover non-exclusive inclusion. For example, a method or apparatus that includes or has a list of elements is not necessarily limited to those elements, but may include other elements not expressly listed or that are inherent in such a method or apparatus.

[0013] Furthermore, unless explicitly stated to the contrary, "or" refers to an inclusive "or" and not an exclusive "or." For example, a condition A or B is satisfied by one of the following conditions: A is true (or present) and B is false (or absent), A is false (or absent) and B is true (or present), and both A and B are true (or present).

[0014] The terms "a" or "an" as used herein are defined as "one or more." The terms "another" and "another," and any other variations thereof, are defined as "at least one other."

[0015] The term “plurality” as used herein shall mean “two or more”.

[0016] The terms "first," "second," "third," and similar terms in the description and claims are used to distinguish between similar or otherwise similarly named elements and not necessarily to describe a sequential, spatial, or chronological order. It is understood that the terms so used are interchangeable under appropriate circumstances, and that the embodiments of the solution described herein may also function in orders other than those described or illustrated herein.

[0017] The term “configured” or “set up” to perform a specific function (and respective variations thereof), as used here where appropriate, is to be understood that a relevant device or component thereof is already in a design or setting in which it can perform the function or is at least adjustable – i.e. configurable – so that it can perform the function after being set accordingly. The configuration can be carried out, for example, by appropriately setting parameters of a process sequence or of switches or the like for activating or deactivating functionalities or settings. In particular, the device can have a plurality of predetermined configurations or operating modes, such that the configuration can be carried out by selecting one of these configurations or operating modes. Problem with random access

[0018] To illustrate the problems associated with random accesses and the associated performance degradation (synonymous with poor individual access times) compared to sequential accesses, some causes of performance limitations are explained below. The headings that introduce the descriptions of the respective causes list a key aspect of each cause in parentheses. 1. Physical properties of storage media (positioning)

[0019] For some storage media that operate sequentially, achievable access times (at least on average) depend heavily on the access pattern due to the underlying physical properties of these storage media. An example is a hard disk whose read head must move between consecutive accesses if the associated data is located on different tracks (read access) or is to be written (write access). If the accesses are random, the read head must move, on average (expected value), over half the storage medium, which is time-consuming. 2. Maintaining expected access data (predictability)

[0020] A memory controller can anticipate upcoming read accesses by pre-loading the data to be read from the data memory and storing it in a dedicated memory (or one or more registers) of the memory controller. This method is often referred to as "read ahead." This can significantly increase performance in a usage scenario where data is requested in bursts. The memory controller uses the idle times (during which, for example, the host must first process previously received data before requesting new data) to reduce the memory controller's overhead during subsequent read accesses, at least for correctly predicted read accesses.

[0021] During a sequential read access to the (logical) memory address i, the contents of the memory areas accessible at the (logical) memory addresses i + 1 to i + n are then preloaded by the memory controller, although initially only the actually requested access to memory address i is serviced. If a subsequent access to memory address i+1 or subsequent memory addresses then occurs, this subsequent access can also be serviced directly by the memory controller without the data first having to be read from the data memory. Otherwise, i.e., if an unanticipated access follows, the prematurely loaded data will be discarded in due time, so that the anticipatory loading was in vain. 3. Acceleration through interleaving of storage media (predictability)

[0022] In many cases, a single storage controller can manage multiple storage media within a data storage system. If accesses are optimally distributed and the data from accesses that are expected to be contiguous are stored alternately on the storage media (interleaving), performance and often also robustness against errors can be significantly improved. With a random access pattern, however, there is usually a significant probability that the same storage medium will have to be used multiple times in succession, and performance is therefore limited solely by this storage medium. 4. Resolution of logical to physical address ranges (access size)

[0023] If a translation from logical to physical addresses takes place by the memory controller, this translation must be carried out for each new access, whereas with sequential access this is generally only necessary once per access, since the data of the successive accesses are written to or read from the physical memory consecutively across accesses or, in the case of constant distances between the memory areas (for example due to the aforementioned interleaving), at least no complete address translation is required. 5. Additional effort due to interaction with the host (number of accesses per unit of time)

[0024] For (small) random accesses, the additional overhead for interacting with the host (usually the same for each access operation) is more significant in the overall runtime than for larger random accesses or sequential accesses. This overhead can arise particularly when host requests must be answered according to the protocol and / or the relevant information about the requested access (i.e., access type, (logical) address, access size) must be extracted from the request.

[0025] Especially for the flash memory application, the problem of random access at the physical level is generally not present, since in particular no positioning of a read head or similar is required.

[0026] However, for storage media that have a linear arrangement that is traversed by a mechanism (tape, CD, hard drive), the positioning problem is critical. However, even here, with a certain degree of access predictability, a translation from logical to physical addresses is fundamentally possible, so that a logical distance between different addresses does not necessarily imply a physical gap in the linear arrangement of the storage medium.

[0027] Such address translation could then counteract the poor positioning of the data when accesses are predictable, but would require a memory controller that performs this translation and applies heuristics to predict accesses.

[0028] It is an object of the present invention to solve at least one of the aforementioned challenges (positioning, predictability, access size and accesses per time unit) in order to achieve a significant performance increase for accesses of a host to a data storage device using a storage controller in certain application cases.

[0029] This problem is solved according to the teaching of the independent claims. Various embodiments and further developments of the solution are the subject of the dependent claims.

[0030] A first aspect of the solution presented here relates to a method for optimizing an access scheme for memory accesses of a host to a data memory managed by a memory controller, in particular a non-volatile memory, with one or more storage media, in particular flash memories, wherein the method is carried out by the memory controller and comprises: (i) receiving an access scenario communicated by the host that defines a specific sequence of accesses to the data storage by the host using the storage controller; (ii) optimizing an access scheme corresponding to the received access scenario, which defines a specific sequence of physical memory accesses to the data memory to be executed by the memory controller to implement the access scenario, wherein the optimization to shorten an overall access time for the access scenario comprises modifying at least one of the memory accesses by means of a shift of a respective physical memory area to be addressed thereby with respect to an address translation and / or by means of a temporal advance of the respective memory access; and (iii) storing access information defining the optimized access scheme, in particular in the memory controller itself or in a memory area of ​​the data memory assigned to it, so that the optimized access scheme can subsequently be activated by a call in such a way that it is automatically executed in response to the call according to the stored access information.

[0031] Receiving the access scenario can, in particular, comprise executing the access scenario, wherein the host transmits the accesses defined in the access scenario to the memory controller according to the defined chronological sequence. The memory controller then uses an initial, corresponding access scheme to execute the corresponding physical memory accesses. This initial access scenario is then subsequently subjected to the aforementioned optimization by the memory controller. Additionally or instead, it is also possible for the host to transmit the access scenario only as information, and for the memory controller to execute the optimization based on this, without requiring an actual physical memory access according to the initial access scheme.

[0032] The method thus determines an optimization for a given access scenario communicated by the host to the memory controller to achieve a shortened overall access time for the access scenario. This optimization utilizes the degrees of freedom regarding address translation and timing of physical accesses that still exist when determining the access scheme, even for a fixed access scenario, to achieve a performance increase (based on shortened individual access times). In particular, the optimization can be extended to the point where the performance of a sequential access is achieved with an access size corresponding to the cumulative total access size of the access scenario across the individual accesses. The actual performance increase achieved depends on the specific access scenario.

[0033] In addition to an increase in performance, when using the method, compared to a corresponding execution of the same access scenario without applying the method, depending on the access scenario, (i) a reduction in the general management overhead of the storage controller for executing the access scenario, (ii) an extension of the expected or actual lifetime of the storage medium and / or (iii) a reduction in the power consumption of the storage controller required to execute the access scenario can be achieved.

[0034] In cases (i) and (ii), the improvement can be based in particular on the fact that, given a known access scenario with an optimized access scheme, read-ahead operations that subsequently prove to be unnecessary can be largely avoided. In these cases, the garbage collection that is otherwise regularly performed, especially in flash memory controllers, can usually be significantly reduced or even eliminated, thus reducing the overall number of physical accesses required to manage the memory.

[0035] Especially in case (iii), the power consumption must be considered for the entire access process. Although it is still possible that the power consumption is temporarily higher at some point during the access, the energy savings achieved by shortening the access process will generally dominate, resulting in a reduced power consumption on average.

[0036] The memory controller and the entire memory system can continue to be usable outside of the access scenario, in particular in such a way that during regular operation of the memory controller (i.e. outside of an execution of the method) its behavior changes little to not at all (possibly maintaining memory for write accesses of the access scenario). Example use cases for the procedure

[0037] The method is particularly advantageous for use cases in which one or more a priori fixed or little-changeable access scenarios are used, so that the access scenario occurs again with a high probability or even certainly, in particular repeatedly, and thus the access scheme optimized in this regard can be used to increase performance during the repetitions.

[0038] Below, some of these use cases are explained in more detail by way of example and without this being understood as a restriction of the procedure to these use cases: Boot process

[0039] The access scenarios during the boot process are generally very similar or identical for successive executions. Especially in the case of boot processes within the framework of firmware or other embedded or industrial systems, in which updates tend to occur monolithically and in which non-deterministic influences during the boot process (e.g., due to network access) are unlikely, boot processes are often consistent for a specific system for a given firmware or update version, i.e., identical from time to time. The method is preferably applied immediately after each update in order to generate an optimized corresponding access scheme for the (new) access scenario for the new boot process before the update is subsequently used productively. The access scenario can be communicated to the memory controller in particular by executing a simple boot process after the update (i.e., by a reset). Hibernation

[0040] Hibernation is a process that allows the host to completely shut down, but then restores the host to its state before the shutdown when it is turned back on (usually by applying power). Typically, a large part of the hibernation process involves writing the contents of a (volatile) RAM to a (non-volatile) storage medium. Application start

[0041] An application running or capable of running on the host, whose execution is either constant or changes only at known times, at least in phases, e.g., at application start or application end, can be optimized using the method. Criteria for suitable use cases

[0042] In general, suitable use cases can exist in particular if they can be classified into at least one of the following three categories, each of which justifies why the access scenario is not carried out entirely with respect to a (non-volatile) host memory: 1. The RAM is not (yet) available (boot / hibernation), 2. The effort of preparing the memory is too complex (application start) and 3. The total size of the access scenario exceeds the size of the (currently free) RAM (application start).

[0043] Various exemplary embodiments of the method are described below, each of which, unless expressly excluded or technically impossible, can be combined with each other as well as with the other aspects of the present solution described below.

[0044] In some embodiments, an associated logical memory area is specified in the access scenario for each access defined therein, which is translated into a corresponding physical memory area of ​​the data memory as part of an address translation defined in the access scheme. These embodiments are particularly suitable for use with flash memory controllers, where address translation from logical to physical addresses is typically used.

[0045] In some such embodiments, optimizing the access scheme includes modifying the address translation such that, for two or more consecutive accesses in the access scenario, their corresponding physical memory areas are combined so that they can be addressed contiguously by means of a sequential memory access upon subsequent activation of the optimized access scheme. In this way, the time advantages that arise with sequential access compared to random access can be utilized. In particular, the aforementioned "read-ahead" approach can be used to achieve an average performance improvement through shortened access times.

[0046] In particular, according to some of these embodiments, the merging of the physical memory areas can occur with respect to two or more accesses that are directly consecutive in the access scenario (i.e., possibly with a pause, but without further access in between), in which the access size of their respective corresponding physical memory area falls below the minimum access size (in the case of flash memory, for example, the size of a memory page), while the sum of their access sizes corresponds at least to the minimum access size. Such merging is possible and advantageous because the associated memory accesses occur directly consecutively, so that a single common memory access that serves all of these combined accesses is particularly efficient.

[0047] In some embodiments, the data storage device comprises at least two storage media, and the accesses to be merged in the access scheme that directly follow one another in the access scenario are defined as alternating between the storage media within the framework of interleaving. In this case, the merging of the physical memory areas takes place within the framework of optimizing the access scheme such that each subsequent access continues the interleaving from a physical memory location at which the interleaving of the preceding access ends. Thus, the advantages of interleaving can also be utilized in combination with those of the aforementioned merging of physical memory areas, particularly with regard to the use of sequential memory accesses for directly consecutive accesses in the access scenario or access scheme.

[0048] In some embodiments, the access scheme defines two or more physical write accesses. Furthermore, optimizing the access scheme here includes modifying the address translation such that, for at least two of the write accesses, their associated physical memory areas are placed in the same memory unit of the data memory, which can be contiguously erased within the scope of a single erase access. This is particularly advantageous with regard to data memory types (in particular flash memory) in which writing to a previously written memory area must be preceded by erasing this memory area. A minimum erase access size (e.g., block size) is applicable for the erasure, which may be larger than the minimum write access size.Preparing the data storage for the multiple write accesses defined in the access scheme can thus be carried out for at least two of these write accesses in a time- and / or energy-saving manner by means of a single delete access.

[0049] In some embodiments, the access scheme defines one or more physical write accesses, and the optimization comprises modifying the address translation such that a sufficiently large writable (i.e., unoccupied) memory space is reserved for all of these write accesses in total for their subsequent execution according to the optimized access scheme. In this way, prior deletion of the relevant memory area can be dispensed with when executing the access scheme, which in turn can be used to save time and / or energy. In particular, the aforementioned memory area merging can also be advantageously used here to enable sequential write accesses to the reserved memory area, with which multiple consecutive write accesses can be served in the access scenario or access scheme.

[0050] In some embodiments, optimizing comprises bringing forward the timing of a second access defined in the access scenario such that, within the framework of the optimized access scheme, the start of the physical memory access corresponding to the second access is brought forward to an execution time for which a pause is provided in the access scenario between a first access preceding the second access and the second access. Thus, in particular in the case of read accesses, a working memory (or register) of the memory controller can be preloaded, in particular until it is full, and the read accesses can be answered directly by the host by transmitting the requested read data already preloaded in the working memory (or register) of the memory controller as soon as the associated access calls are received by the host or retrieved after activation of the access scheme according to the access information.

[0051] In some embodiments, the method further comprises activating the access scheme following the storage of the access information in response to a call to the access scenario in order to execute the access scheme as defined by the access information. Thus, the access scenario can be triggered simply by its call and executed based on the associated optimized access scheme represented by the access information, without the host having to (re)call the accesses defined in the access scenario individually. Activation can occur, in particular, in response to a call to the access scenario received from the host and / or automatically during startup (e.g., boot, in particular after a reset) of the memory controller.It is also conceivable that the memory controller recognizes an access scenario that the host is currently transmitting based on a subset (in particular an initial sequence) of the accesses and / or pauses contained therein and then selects and executes the corresponding access scheme on its own initiative.

[0052] In some embodiments, the reception of the access scenario from the host occurs in response to the receipt of a start signal received from the host. Furthermore, the reception of the access scenario from the host can be completed in response to the receipt of an end signal received from the host. The host can thus easily signal to the memory controller the period in which the method is executed. In particular, the memory controller is thus signaled that the sequence of accesses received from the host in the period is to be interpreted as an access scenario (to be trained), for which an optimized access scheme is to be determined by the memory controller according to the method.

[0053] In some embodiments, the method is defined as an iterative method such that: (i) in the first iteration, the access scenario is received and a corresponding first access scheme and an execution time for its execution are determined; (ii) in each further iteration: - the access scenario is received again (in the case of an access scenario with variable access parameters, however, possibly with at least partially different access parameters, see below); - the optimization is carried out starting from the previous access scheme determined in the last previous iteration in order to determine a current access scheme; - an indicator for a difference between the execution time of the current access scheme and the execution time of the previous access scheme is determined; - the indicator is compared with a defined minimum requirement; and - if the comparison shows that the difference indicated by the indicator does not yet meet the minimum requirement, proceed to the next iteration, - otherwise, the current access scheme is set as the optimized access scheme and saved based on the access information.

[0054] This iterative approach ensures, in particular, that the ultimately determined optimized access scheme meets the specified minimum requirement, rather than requiring all conceivable optimization options to be implemented from the outset. For example, if a modification of the address translation determined during the iteration is sufficient to meet the minimum requirement, other optimizations, such as prioritizing accesses, can be omitted. Overall, the minimum requirement can be met in a particularly efficient manner, which can be used, in particular, to shorten the optimization time.

[0055] In particular, for each iteration, the previous access scheme can be executed as the starting point for the optimization running in this iteration and its execution time can be measured for use in the above comparison.

[0056] In some embodiments, any variable accesses in the pull-through scenario are detected for each iteration when it is executed multiple times during the iteration, wherein variable accesses are characterized by the fact that they change across different iterations with regard to their access address, their access size and / or the length of a pause between successive accesses compared to a directly preceding or directly following execution in the access scenario, while remaining at the same location within the access scenario. In the case of a detected variable write access, if the access size is known, writable storage space in the data memory is reserved at least to the extent of this access size. In contrast, if the access size is unknown, i.e. variable, writable storage space in the data memory is reserved at least to the extent of the largest size that has occurred for this access in the previous iterations.This ensures with a high degree of probability that, despite the variability, there will always be enough reserved free storage space available for write accesses.

[0057] In some embodiments, the method further comprises: (i) returning the access scenario received from the host to the host; (ii) subsequently receiving verification information from the host indicating whether the returned access scenario corresponds to the access scenario previously transmitted by the host; and (iii) if this is the case, performing the optimization of the access scheme corresponding to the received access scenario, otherwise requesting a retransmission of the access scenario from the host.

[0058] This allows the host to check whether the storage controller correctly received and recognized the access scenario, while the storage controller requests a retry of the access scenario if correction is needed, rather than executing the optimization based on a potentially faulty or incorrectly received / recognized access scenario. Overall, this increases the reliability of the process.

[0059] In some embodiments, the method further comprises (i) determining an updated access scenario that corresponds to the optimized access scheme and / or to one of the access schemes determined within the scope of one of the aforementioned iterations; and (ii) at least partially transmitting this updated access scenario to the host. This opens up the possibility of making not only changes to the access scheme within the scope of the optimization, but also corresponding changes to the underlying access scenario. This is particularly relevant with regard to any changes to the temporal sequence of accesses defined in the access scenario, where, for example, the access scenario itself can be shortened by bringing forward individual accesses into previous access pauses. The host can accordingly use the updated access scenario in the future, particularly within the scope of the iterative execution of the method.In particular, it is conceivable that the decision as to whether the updated access scenario will be used instead of the previous access scenario in the future is left to the host. In this case, the controller makes an optimization suggestion, which the host can accept or reject.

[0060] In some of these embodiments, an estimate of the performance improvement achievable with the updated access scenario compared to the received access scenario is additionally created and transmitted to the host. This informs the host of the achieved or achievable performance improvement and allows it to be taken into account when incorporating the access scenario (particularly relative to other accesses outside the access scenario) into the communication with the memory controller in the future.

[0061] In particular, according to some embodiments where updating the access scenario is possible, the optimized access scheme can be determined depending on feedback received from the host regarding the updated access scenario. Thus, the host retains a chance to participate, possibly even a decisive role, in determining the optimized access scheme.

[0062] In some of these embodiments, the memory controller does not receive any further accesses from the host to the data memory while optimizing the access scheme and / or does not implement such accesses if necessary. Ideally, the host is configured to grant the memory controller the time required for optimization before making further accesses. The required time can, in particular, be agreed a priori and specified, for example, by a parameter, or the memory controller can communicate to the host via appropriate signaling when the optimization or an intermediate stage reached during the optimization process has been achieved.

[0063] A second aspect of the present solution relates to a memory controller, in particular a flash memory controller. It comprises one or more processors, non-volatile computer-readable memory, and one or more programs stored in the memory, which, when executed on the one or more processors, cause the memory controller to execute the method according to the first aspect.

[0064] A third aspect of the present solution relates to a computer program or computer program product comprising instructions for causing a memory controller, in particular the memory controller according to the second aspect, to execute the method according to the first aspect.

[0065] The computer program can in particular be stored on a non-volatile data carrier, in particular in the data memory or a memory in the memory controller itself. The data carrier can also be in the form of an optical data carrier or a flash memory module. This can be advantageous if the computer program as such is to be able to be handled independently of the memory controller. In another implementation, the computer program can be present as a file on a data processing unit, in particular on a server, and can be downloaded via a data connection, for example the Internet or a dedicated data connection, such as a proprietary or local network. In addition, the computer program can have a plurality of interacting individual program modules. The modules can in particular be configured or at least be usable in such a way that they can be used in the sense of distributed computing (DC).“Distributed Computing”) are executed on different devices (e.g. computers or processor units) that are geographically separated from each other and connected to each other via a data network.

[0066] The features and benefits explained with regard to the first aspect of the solution also apply to the other aspects of the solution.

[0067] Further advantages, features and possible applications of the present solution will become apparent from the following detailed description in conjunction with the figures.

[0068] It shows: Fig. 1 shows a computer system having a host, a data storage, and a storage controller for managing the data storage, according to an exemplary embodiment; Fig. 2A and Fig. 2B schematically shows two exemplary address conversions between logical and physical memory addresses; Fig. 3 is a flowchart illustrating a first exemplary embodiment of the method for optimizing an access scheme for memory accesses; Fig. 4 an exemplary representation of an access scenario defined on the basis of logical memory addresses and its implementation into a corresponding access scheme defined on the basis of physical memory addresses; Fig. 5 is a flowchart illustrating a second exemplary embodiment of the method for optimizing an access scheme for memory accesses; and Fig. 6 an exemplary representation of an optimization of an access scenario, in particular according to the method from Fig. 5.

[0069] In the figures, like reference numerals designate like, similar, or corresponding elements. Elements shown in the figures are not necessarily drawn to scale. Rather, the various elements shown in the figures are depicted in such a way that their function and general purpose will be understood by those skilled in the art. Connections and couplings shown in the figures between functional units and elements of the computer system of Fig. 1 may, unless expressly stated otherwise, also be implemented as an indirect connection or coupling. Unless otherwise stated, functional units may, in particular, be implemented as hardware, software, or a combination of hardware and software.

[0070] The Fig. The exemplary computer system 100 illustrated in Figure 1 with a memory system 102 comprises a memory controller 104 for controlling the memory system 102 and a data memory (or abbreviated to "memory") 106 controlled, in particular managed, thereby, which can in particular comprise a non-volatile memory (NVM), such as a flash memory, for example of the NAND type. The data memory 106 can in particular comprise a plurality of storage media 106a and 106b, such as a plurality of semiconductor memory modules. The storage media 106a, 106b can in particular be addressable via a common physical and / or logical address space.If the data storage device, as in the present example, has a plurality of storage media 106a and 106b, this also enables interleaving, wherein, within the scope of the method and the access scenario, directly consecutive accesses to be combined in the sense of a sequential access sequence can be defined in the corresponding access scheme such that these consecutive accesses occur alternately on the storage media 106a, 106b. Each subsequent access then continues the interleaving from a physical storage location at which the interleaving of the preceding access ends. Accordingly, if the last access was made to the first storage medium 106a, the subsequent access within the scope of the interleaving thus occurs on the next storage medium 106b.

[0071] The memory system 102 is connected to a host 108, such as a computer to which the memory system 102 is assigned, via a set of address lines AL, a set of data lines DL, and a set of control lines CL. The memory controller 104 has a processor unit 104a and an internal memory 104b, typically of the embedded type, and is connected to the data memory 106 via an address bus AB, a data bus DB, and a control bus CB. Accordingly, the host 108 has indirect read and / or write access to the memory 3 via its connections AL, DL, and CL to the memory controller 2, which in turn can access the memory 3 directly via the buses AB, DB, and CB. Each of the line sets or buses AL, DL, CL, AB, DB, and CD can be implemented using one or more individual communication lines. The lines AL, CL, and the bus AB can also be omitted.

[0072] A computer program, preferably as firmware, is stored in the internal memory 104b of the memory controller 104. It is configured, when executed on the processor platform 104a of the memory controller 104, to implement the method according to the first aspect, in particular according to one of its embodiments described below with reference to Fig. 3 or Fig. 5 described embodiments.

[0073] The internal memory 104b can also be configured to be usable as a buffer or register for a "read-ahead", so that the memory controller can read data from the data memory 106 in advance and temporarily store it in the internal memory 104b before the host 108 makes the actual access request to this data, which has been loaded in advance from the data memory in the sense of a "read-ahead".

[0074] For the following explanation of embodiments of the method, reference is made to the computer system 100 and in particular to its memory controller 104, without this being construed as a limitation thereto.

[0075] Fig. 2A schematically illustrates a first exemplary address translation 200 between logical memory addresses LA1 to LA8 defined in a logical address space LAS and physical memory addresses PA1 to PA8 defined in a physical address space PAS. This unidirectional or bidirectional address translation between the two address spaces can be performed in particular by a memory controller, such as memory controller 104. In the case of multiple storage media 106a, 106b in data memory 106d, their respective physical address spaces PAS a , PAS bin particular, be merged into a consistent common physical address space PAS, as illustrated.

[0076] During address translation 200, the communication of memory addresses between the host 108 and the memory controller 104 takes place using the logical address space LAS. The communication of memory addresses between the memory controller 104 and the data memory 106, however, takes place using the physical address space PAS. Fig. 2, the implementation is symbolized by the various arrows between the two address spaces. While it is possible for logical addresses to coincide with the corresponding physical addresses (cf. LA7 / LP / or LA8 / LP8), this is usually not the case. In the present example, Fig. 2 For example, if a read command originating from host 108 requests reading the memory contents of the address block with the sequentially consecutive logical memory addresses LA1 to LA6, this sequence would be resolved during address translation 200, resulting in no sequential reading in the physical address space PAS, but rather address jumps of varying sizes and even in different jump directions. Such an address translation would therefore be rather disadvantageous from a performance perspective because it would be slow on the physical side.

[0077] Fig. 2B, on the other hand, schematically illustrates a second exemplary address translation 201, in which non-sequential memory accesses occurring in the logical address space LAS are "de-randomized," i.e., at least partially converted into corresponding memory accesses occurring as sequential accesses in the physical address space PAS. In this way, an accelerated access sequence can be achieved on the physical side, thus increasing the overall available performance for memory accesses of the host to the data memory 106. For this purpose, an access scenario originating from the host 108 is considered as an example, in which first a sequential access to the logical addresses LA3 and LA4 occurs, then another sequential access to the logical addresses LA7 and LA8, then another sequential access to the logical addresses LA5 and LA6, and finally another sequential access to the logical addresses LA1 and LA2.In the logical address space LAS, multiple jumps in different jump directions thus occur. However, in the physical address space PAS, due to address translation 201, a corresponding access sequence results, in which the address ranges of the aforementioned accesses follow one another sequentially and can thus be implemented at the physical level with high performance.

[0078] Fig. 3 shows a flowchart of a first exemplary embodiment 300 of the method for optimizing an access scheme for memory accesses. The method can be executed, in particular, by a memory controller, such as memory controller 104 of computer system 100, as described below.

[0079] When reference is made below to a "step" or "steps" of the procedure, this does not mean that the associated action must necessarily be carried out in a single, coherent process. Rather, it is also possible that a "step" is composed of several individual processes in the sense of a process and thus corresponds to a sub-process of the procedure.

[0080] In method 300, a start signal transmitted by host 108 is first received in a step 306, indicating that host 108 will subsequently transmit an access scenario. The transmission can thus occur, in particular, in such a way that host 108 actually executes the access scenario by successively transmitting the access requests defined therein based on logical memory addresses LA from address space LAS to memory controller 104. The access scenario is received by memory controller 104 in step 308. After the access scenario has been completely transmitted, host 108 transmits an end signal, which is received by memory controller 104 in step 310 and signals the end of the transmission to memory controller 104.

[0081] In particular, within the scope of the method, it can be provided that the memory controller 106 transmits the received access scenario back to the host 108 in a suitable manner (step 312) to enable the host 108 to check whether the previous transmission of the access scenario to the memory controller 106 was error-free or faulty. The host 108 then transmits the check result to the memory controller 106 so that the latter can receive and evaluate the check result (steps 314 and 316). In the event of an error (316 - yes), a retransmission of the access scenario to the memory controller 106 can then be requested (step 318). Otherwise (316 - no), the method can continue without requesting a retransmission of the access scenario.

[0082] An example access scenario is shown in abstract form 402 and as a concrete example 404 in Fig. 4 on the left side. Each access of access scenario 402 / 404 is specified by a logical memory address LA, an access size S (e.g., a number of bytes or kilobytes (KB)), and an access type identifier (R = read, W = write). Furthermore, in access scenario 402 / 404, pauses P between consecutive accesses can also be defined, which can each be specified in particular by their respective pause length (e.g., in microseconds).

[0083] If a correctly transmitted access scenario is present at the memory controller 104, it can define and optimize a corresponding access scheme based on the physical address space. For this purpose, the address translation can be redefined or modified based on a previous address translation already specified for the access scenario (step 320a). The resulting optimized access scheme can thus be de-randomized to a greater degree, in particular, by increasing the proportion of sequential accesses, as already described above by way of example with reference to Fig. 2 was explained.

[0084] Additionally or instead, the optimization may also include a temporal shift 320b, in particular, bringing forward, of accesses within the scope of the access scheme. This may, in particular, be carried out such that a next physical access according to the optimized access scheme already begins at a point in time in the access sequence for which a pause is still provided in the access scenario.

[0085] Both optimization methods are also combined in Fig. 4 illustrates where the concrete access scenario 404 is converted by the memory controller 104 into an optimized access scheme 406 in such a way that this defines both a de-randomization within the scope of the address translation and a shortening of pauses P and thus a temporal advancement of physical accesses.

[0086] It may also be provided within the scope of method 300 that no further (attempted) memory accesses from the host 108 are received during the optimization process 320. This can be done, in particular, by placing the memory controller 104 into an operating mode in which it is not ready to receive during this time, or by not further processing received access requests from the host 108 or at least temporarily pausing them until the optimization 320 is completed.

[0087] Within the scope of method 300, during or after optimization 320, access information defining the optimized access scheme is stored 328. The access information can be stored, in particular, in the internal memory 104b of the memory controller itself or in the data memory 106. The storage takes place in such a way that the access scheme itself can be easily retrieved in order to activate it. For example, an identifier can be assigned to the access scheme, by means of which it can be selectively retrieved from its storage location. This initially completes the process of defining an optimized access scheme.

[0088] If the host 108 subsequently wishes to execute the underlying access scenario 404 again, for example as part of a boot process, it can transmit a corresponding call to the memory controller 104, where the call is received (step 332) and the access scheme 406 associated with the access scenario 404 specified in the call can be retrieved from its memory location and activated for its execution 334 by the memory controller 104.

[0089] Fig. 5 shows a flowchart of a second exemplary embodiment 500 of the method for optimizing an access scheme for memory accesses. The method can also be executed, in particular, by a memory controller, such as memory controller 104 of computer system 100.

[0090] Method 500 represents an extension of method 300, whereby the same method steps for both methods are identified by the same reference numerals and will not be described in detail again below. Instead, the explanations already given above for method 300 apply accordingly.

[0091] In contrast to method 300, method 500 is designed iteratively with regard to the optimization of the access scheme. Optimization is therefore regularly performed here based on several consecutive iterations, in each of which an optimization process is executed in step 320, starting from the previous state of the access scheme. For indexing successive iterations, for example, a running index i can be used, which can be initialized in step 302.

[0092] If optimization step 320 has been performed in a current iteration i, a required execution time can be determined for the current access scheme defined therein, e.g., by summing the time required for the individual accesses and pauses defined in the current access scheme. Then, in step 322, a difference between the execution time of the current access scheme of iteration i and the execution time of the previous access scheme of iteration i-1 can be determined and represented by an indicator J.

[0093] The indicator J can then be compared with a predetermined reference threshold J max (test 324), which serves as the exit criterion for the iterative process. If J falls below the reference threshold J max(324 - yes), the iterative process has converged sufficiently and is terminated, allowing the process to proceed to step 328. Otherwise (324 - no), the iterative process continues, for which purpose the running index i is also incremented in step 326 and a retransmission of the access scenario is requested from host 108 in step 318.

[0094] Optionally, it can also be provided that, in a further step 330, the current access scheme resulting from the last executed iteration is transmitted to the host. Additionally or instead, the memory controller 104 can also transmit a suggested improvement for the access scenario determined during the determination of the optimized access scheme to the host 108. This allows the host 108 to adapt the underlying access scenario itself in the interest of optimization.

[0095] A simple example is given to explain this: The original access scenario transmitted to the memory controller could be something like this: 1. Switch on the data storage (Power on) 2nd break 3. Read access, 600KB, scattered in the logical address space LAS 4. Break 5. Read access, 600KB, scattered in the logical address space LAS 6. Break 7. Read access, 600KB, scattered in the logical address space LAS

[0096] The memory controller 104 can then determine an optimized access scenario, as described in particular with reference to methods 300 and 500.

[0097] However, it may happen that the memory controller 104 determines that the access scenario itself can be optimized with regard to the capabilities and limitations of the memory controller 104. For example, in the present example, the memory controller 104 could determine that the access size S of the read accesses is greater than the size of the internal memory 104b, which is limited to 500 KB, so that the memory controller 104 must always pause for a short time after 500 KB to process the accesses in order to read in additional requested data from the data memory 106. It can therefore transmit to the host 108 in step 330 the appropriately adapted access scheme with accesses whose access size does not exceed the size of the internal memory 104b, or corresponding suggestions for optimizing the underlying access scenario previously received from the host 108 in step 308.

[0098] For example, the following modified access scenario could be suggested in this way or determined by the host 108 itself on the basis of the information transmitted in step 330 1. Switch on the data storage (Power on) 2nd break 3. Read access, 500 KB, scattered in the logical address space LAS 4. Break 5. Read access, 500 KB, scattered in the logical address space LAS 6. Break 7. Read access, 500 KB, scattered in the logical address space LAS 8. Read access, 300 KB, scattered in the logical address space LAS

[0099] Although the same addresses appear in the same order, the changes in the access sizes result in an optimized access scenario that would be easier for the memory controller to process than the original access scenario. The host 108 could then accept or reject this suggestion and instead forgo the optimization or achieve it in another way, for example, by creating an optimized access scenario itself based on the transmitted information.

[0100] A simple, further example of such an optimization of the access scenario is in Fig. 6. Here, the original access scenario 600 is further optimized in one or more optimization iterations, with particular attention being given to access times T a varied (as illustrated), and pauses P may be inserted (as illustrated), removed or changed. LIST OF REFERENCE SYMBOLS 100 computer systems 102 Storage system 104 memory controllers 104a Processor unit 104b internal memory of the memory controller 104 106 data storage 106a first storage medium 106b second storage medium 108 Host 200 first example of an address conversion 201 second example of an address translation 300 Procedure, first embodiment 302-334 Process steps or sub-processes of process 300 or 500 400 Definition of an access scheme based on an access scenario 402 access scenario, abstract 404 access scenario in concrete terms 406 access scheme 500 procedures, second embodiment (iterative) 600 original access scenario 602 updated (optimized) access scenario AB address bus DB data bus CB control bus AL address line(s) DL data line(s) CL control cable(s) J Indicator for the difference in execution times between two access schemes J max Reference threshold LA, LA1-LA8 logical memory addresses LP, LP1-LP8 physical memory addresses LAS logical address space PAS physical address space PAS a physical (sub-)address space of the first storage medium 106a PAS b physical (sub-)address space of the first storage medium 106b P Pause R Read access S access size T a Access time W Write access

Claims

[1] Method (300; 500) for optimizing an access scheme (406) for memory accesses (R, W) of a host (108) to a data memory (106) managed by a memory controller (104) with one or more storage media (106a; 106b), in particular flash memories, wherein the method (300; 500) is carried out by the memory controller (104) and comprises: Receiving (306) an access scenario (402, 404) communicated by the host (108) which defines a specific sequence of accesses (R, W) of the host (108) to the data memory (106) to be carried out using the memory controller (104); Optimizing (320) an access scheme (406) corresponding to the received access scenario (402, 404), which defines a specific sequence of physical memory accesses (R, W) to the data memory (106) to be executed by the memory controller (104) to implement the access scenario (402, 404), wherein the optimization (320) for shortening an overall access time for the access scenario (402, 404) comprises modifying (320a) at least one of the memory accesses (R, W) by shifting a respective physical memory area to be accessed thereby with respect to an address translation (201) and / or by bringing forward (320b) the respective memory access; and Storing (328) access information defining the optimized access scheme (406) such that the optimized access scheme (406) can subsequently be activated by a call such that it is automatically executed in response to the call according to the stored access information. [2] Method (300; 500) according to claim 1, wherein in the access scenario (402, 404) for the accesses (R, W) defined therein, an assigned logical memory area (LAS) is specified, which is translated in the context of an address conversion (201) to a corresponding physical memory area of ​​the data memory (106) which is defined in the access scheme (406). [3] Method (300; 500) according to claim 2, wherein the optimizing (320) of the access scheme (406) comprises modifying (320a) the address translation (201) such that for two or more consecutive accesses (R, W) in the access scenario (402, 404), their respective corresponding physical memory areas are combined such that they can be addressed contiguously by means of a sequential memory access during a subsequent activation of the optimized access scheme (406). [4] Method (300; 500) according to claim 3, wherein the merging of the physical memory areas takes place with respect to two or more accesses (R, W) which are directly consecutive in the access scenario (402, 404), in which the access size (S) of their respective corresponding physical memory area falls below the minimum access size (S), while the sum of their access sizes (S) corresponds at least to the minimum access size (S). [5] Method (300; 500) according to claim 3 or 4, wherein the data memory (106) has at least two storage media (106a; 106b), and the accesses (R, W) which are directly consecutive and to be merged in the access scenario (402, 404) are defined alternately in the access scheme (406) as part of an interleaving between the storage media (106a; 106b), wherein the merging of the physical memory areas as part of the optimization of the access scheme (406) takes place in such a way that a respective subsequent access (R, W) continues the interleaving from a physical memory location at which the interleaving of the access preceding it ends. [6] Method (300; 500) according to one of claims 2 to 5, wherein the access scheme (406) defines two or more physical write accesses (R, W) and the optimization (320) of the access scheme (406) comprises modifying (320a) the address translation (201) such that for at least two of the write accesses (R, W) their associated physical memory areas are placed in a same memory unit of the data memory (106) which can be deleted contiguously within the scope of a single delete access. [7] Method (300; 500) according to one of claims 2 to 6, wherein the access scheme (406) defines one or more physical write accesses (R, W) and the optimization (320) comprises modifying (320a) the address translation (201) such that a sufficiently large writable memory space is reserved for all of these write accesses (R, W) for their subsequent execution according to the optimized access scheme (406). [8] Method (300; 500) according to one of the preceding claims, wherein the optimization (320) comprises a temporal advancement (320b) of a second access defined in the access scenario (402, 404) such that, within the framework of the optimized access scheme (406), the start of the physical memory access corresponding to the second access (R, W) is brought forward to an execution time for which a pause is provided in the access scenario (402, 404) between a first access (R, W) preceding the second access (R, W) and the second access (R, W). [9] Method (300; 500) according to one of the preceding claims, further comprising activating (334) the access scheme (406) in response to a call (332) of the access scenario (402, 404) following the storage of the access information in order to execute the access scheme (406) according to its definition by the access information. [10] Method (300; 500) according to claim 9, wherein the activation in response to a call (332) of the access scenario (402, 404) received from the host (108) and / or occurs automatically as part of starting up the memory controller (104). [11] Method (300; 500) according to one of the preceding claims, wherein receiving (308) the access scenario (402, 404) from the host (108) occurs in response to receiving (308) a start signal received from the host (108). [12] The method (300; 500) of any preceding claim, wherein receiving (308) the access scenario (402, 404) from the host (108) is completed in response to receiving (310) an end signal received from the host (108). [13] Method (500) according to one of the preceding claims, wherein the method (500) is defined as an iterative method (500) such that: in the first iteration, the access scenario (402, 404) is received and a corresponding first access scheme (406) and an execution time for its execution are determined; in each further iteration: the access scenario (402, 404) is received again; the optimization is carried out starting from the previous access scheme determined in the last preceding iteration in order to determine a current access scheme (406); an indicator (J) for a difference between the execution time of the current access scheme (406) and the execution time of the previous access scheme (406) is determined; the indicator (J) is compared with a defined minimum requirement; and if the comparison shows that the difference indicated by the indicator (J) does not yet meet the minimum requirement, proceed to the next iteration, otherwise, the current access scheme (406) is defined as an optimized access scheme (406) and stored based on the access information. [14] Method (500) according to claim 13, wherein for each iteration the previous access scheme (406) is executed as the starting point of the optimization running in this iteration and its execution time is measured. [15] The method (500) of claim 14, wherein: variable accesses (R, W) in the access scenario (402, 404) are detected during its multiple execution during the iteration, wherein variable accesses (R, W) are characterized in that they change, while remaining at the same position within the access scenario (402, 404), over different iterations with regard to their access address (LA), their access size (S) and / or the length of a pause (P) between successive accesses (R, W) compared to a directly preceding or directly following execution in the access scenario (402, 404); and in case of a detected variable write access (W): if the access size (S) is known, writable storage space in the data memory (106) is reserved at least to the extent of this access size (S), and if the access size (S) is unknown, writable storage space in the data memory (106) is reserved at least to the extent of the largest size that has occurred in the previous iterations for this access (W). [16] Method (300; 500) according to one of the preceding claims, further comprising: Retransmitting (312) the access scenario (402, 404) received from the host (108) to the host (108); subsequently receiving (314) check information from the host (108) indicating whether the retransmitted access scenario (402, 404) corresponds to the access scenario (402, 404) previously transmitted by the host (108); and if this is the case, performing the optimization (320) of the access scheme (406) corresponding to the received access scenario (402, 404), otherwise requesting (318) a retransmission of the access scenario (402, 404) from the host (108). [17] Method (300; 500) according to one of the preceding claims, further comprising: Determining an updated access scenario (602) that corresponds to the optimized access scheme (406) and / or to one of the access schemes (406) determined according to claims 13 to 15 within the scope of one of the iterations; and Transmitting this updated access scenario (602), at least partially, to the host (108). [18] Method (300; 500) according to claim 17, wherein an estimate for a performance increase achievable with the updated access scenario (402, 404) compared to the received access scenario (402, 404) is additionally created and transmitted to the host (108). [19] The method (300; 500) of claim 17 or 18, wherein the optimized access scheme (406) is determined in dependence on a received feedback from the host (108) regarding the updated access scenario (402, 404). [20] Method (300; 500) according to one of the preceding claims, wherein the memory controller (104) does not receive and / or implement any further accesses (R, W) of the host (108) to the data memory (106) during the optimization of the access scheme (406). [21] Memory controller (104), in particular flash memory controller, comprising: one or more processors (104a); non-volatile computer-readable memory (104b); and one or more programs stored in the memory which, when executed on the one or more processors (104a), cause the memory controller (104) to execute the method (300; 500) according to any one of claims 1 to 20. [22] A computer program or computer program product comprising instructions for causing a memory controller (104) according to claim 21 to perform the method (300; 500) according to any one of claims 1 to 20.

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