Continuous-time sigma-delta analog / digital converter

Abstract

Circuit that has the following: a continuous-time sigma-delta analog-to-digital converter (sigma-delta ADC) comprising a voltage divider circuit located within the ADC, the voltage divider circuit comprising a first resistive element coupled to a resistive input of a digital-to-analog converter (DAC), the ADC being configured to receive an analog input voltage at an input terminal and compare the analog input voltage to a voltage reference, the voltage reference being generated either by the voltage divider circuit or by a voltage reference circuit located external to the ADC; wherein the first resistive element has a first end for coupling to a power supply of the ADC; wherein the resistive input of the DAC has a first end and a second end, wherein the first end of the resistive input of the DAC is configured to be coupled to a second end of the first resistive element, and wherein the second end of the resistive input of the DAC is configured to couple to a reference voltage; a control circuit; and a switching element coupled between the second end of the first resistive element and the first end of the resistive input of the DAC, the switching element having an open state and a closed state, the control circuit being configured to operate the switching element.

Description

Area of ​​Revelation

[0001] This document relates generally, but not in a limiting way, to integrated circuits and, in particular, to analog-to-digital converter circuits and analog-to-digital converter systems. background

[0002] In many electronics applications, an analog input signal is converted into a digital output signal (e.g., for further digital signal processing). For example, in precision measurement systems, the electronics may be equipped with one or more sensors to perform measurements, and these sensors can generate an analog signal. The analog signal can then be provided as an input to an analog-to-digital converter (ADC) to generate a digital output signal for further processing. In another case, in a receiver of a mobile device, an antenna can generate an analog signal based on the electromagnetic waves that carry information / signals in the ether. The analog signal generated by the antenna can then be provided as an input to an ADC to generate a digital output signal for further processing.

[0003] A difference between the input voltage and the output voltage of the ADC can correspond to the ADC's quantization error. In some ADCs, the quantization error can be further processed by ADC circuitry to "shape" the quantization error, which appears as quantization noise in the frequency domain. Noise shaping techniques can, for example, shift the quantization noise away from the signal band of interest and into higher frequencies.

[0004] A sigma-delta modulator is a feedback system capable of achieving high-resolution digital signals. Sigma-delta modulators have been implemented in a wide variety of electronic circuits, including, but not limited to, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), frequency synthesizers, and other electronic circuits.

[0005] Sigma-delta modulation-based ADCs have been widely used in digital audio systems and high-precision measurement equipment. Typically, a sigma-delta ADC encodes an analog signal using a sigma-delta modulator (e.g., using a low-resolution ADC such as a 1-bit ADC, a flash ADC, a low-resolution successive approximation register (SAR), etc.) and then, if appropriate, applies a digital filter to the output of the sigma-delta modulator to form a higher-resolution digital output. A loop filter may be provided to provide error feedback to the sigma-delta modulator. One property of a sigma-delta modulator is its noise-shaping capability. As a result, sigma-delta ADCs can generally achieve high-resolution analog-to-digital conversion.

[0006] US 2014 0 035 770 A1 relates to an integrated continuous sigma-delta analog-to-digital converter with a single-ended analog input, a converter reference input, and a ground connection. The converter has a resistance-capacitance integrator that receives the single-ended analog input. The integrator includes a differential amplifier. The converter further has a clocked comparator connected to an output of the integrator and a circuit that can maintain the reference inputs of the amplifier and the comparator at a common voltage derived from the converter reference input. Summary of Revelation

[0007] It is an object of the invention to provide a precision ADC with a precision reference voltage with low noise without the need for a reference buffer or digital correction.

[0008] A circuit according to claim 1 and a method for operating a continuous-time sigma-delta analog / digital converter according to claim 13 are disclosed. Advantageous embodiments are mentioned in the subclaims. Brief description of the drawings

[0009] In the drawings, which are not necessarily drawn to scale, like reference characters may describe like components in different views. Like reference characters with different letter suffixes may represent different instances of like components. The drawings generally illustrate, by way of example but not limitation, various embodiments discussed in this document. Fig. Figure 1 is a schematic block diagram of an example data acquisition system that can implement a sigma-delta modulator. Fig. Figure 2 is a block diagram of an example of a single-bit first-order sigma-delta ADC. Fig. 3 is an example of a continuous-time sigma-delta ADC that can implement various techniques of this disclosure. Fig. 4 is an example of a continuous-time sigma-delta ADC that can implement various techniques of this disclosure. Fig. 5 is another example of a continuous-time sigma-delta ADC that can implement various techniques of this disclosure. Fig. 6 is an example of an amplifier circuit configured to generate a common-mode voltage and provide the common-mode voltage to an amplifier circuit of an integrator circuit of a continuous-time sigma-delta ADC. Fig. Figure 7 is another example of a continuous-time sigma-delta ADC that can implement various techniques of this disclosure. Fig. Figure 8 is another example of a continuous-time sigma-delta ADC that can implement various techniques of this disclosure. Fig. 9 is another example of a continuous-time sigma-delta ADC that can implement various techniques of this disclosure. Fig. Figure 10 is an example of a continuous-time sigma-delta ADC combined with a sensor. Detailed description

[0010] The present inventors have recognized that existing techniques have limitations in providing a precision reference voltage to a precision analog-to-digital converter (precision ADC). For discrete-time ADCs, the challenge arises from both the settling of the reference input and the filtering of the reference source noise. Discrete-time ADCs use a sample-and-hold type with a switched capacitor on both the ADC input and the reference inputs. The switching action can generate a noise such as charge injection at the reference input. The charge injection can generate a voltage noise at the reference input because the reference source does not have a zero output impedance.

[0011] A conventional approach to solving this problem is to use a reference buffer circuit with low output impedance and high bandwidth to overdrive the reference input, ensuring that the voltage disturbance caused by charge injection will not introduce an accuracy error beyond the desired accuracy of the ADC. A reference buffer amplifier is almost always required to achieve the desired performance. However, the buffer adds power, area, noise, and a DC error.

[0012] For a continuous-time sigma-delta ADC (CTSD ADC), the reference input settling issue is mitigated. CTSD ADC circuits contain inputs coupled with resistive elements (also referred to as "resistive-input ADCs"), which can make them easy to drive and provide inherent anti-aliasing properties. CTSD ADCs have purely resistive inputs, so there is no need to overdrive the ADC input or the reference input to overcome problems from charge injection. The CTSD's resistive reference input no longer requires a wide-bandwidth buffer amplifier to drive it. However, the noise filtering issue still exists, and there is no good solution other than reintroducing the reference buffer to construct a filter. Again, the buffer adds power, area, noise, and a DC error.

[0013] This disclosure describes, among other things, techniques for providing a precision, low-noise reference voltage to a precision ADC without the need for a reference buffer or digital correction. In one example, the technique may use a divider with an integrated resistor and an external capacitor to derive a precision, low-noise reference voltage from either the ADC's power supply or an integrated reference source.

[0014] In some examples, these techniques can take advantage of the CTSD ADC's resistive input and the excellent trimming characteristics of the integrated resistor networks to generate a precision reference voltage from another source. Additionally, the techniques can use the internal resistor with an external capacitor to form an RC filter to help limit broadband noise from the source voltage and the internal resistor. In some examples, an additional auxiliary amplifier can be included to help reduce the reference voltage error introduced by the common-mode variation of the input voltage.

[0015] Fig. Figure 1 is a schematic block diagram of an example of a data acquisition system 10 that may implement a sigma-delta modulator. The data acquisition system 10 may be an electronic device (including electronic circuitry and / or one or more components) configured to convert signals (such as analog signals) into a usable form. In various implementations, the data acquisition system 10 may convert physical states into a digital form that may be stored and / or analyzed. Fig. 1 has been simplified for clarity. Additional features may be added to the data acquisition system 10 in other embodiments of the data acquisition system 10, and some of the described features may be replaced or eliminated.

[0016] In Fig. 1, the data acquisition system 10 may include an input signal 15 representing a physical state such as temperature, pressure, velocity, flow rate, position, another physical state, or a combination thereof. A sensor circuit block 20 may receive an input signal 15 and convert the physical state (represented by the input signal 15) into an electrical signal such as an analog signal 25. The analog signal 25 may be a voltage or current representing the physical state (represented by the input signal 15).

[0017] A signal conditioning circuit block 30 may receive and adjust the analog signal 25 within an acceptable range of an analog-to-digital converter (ADC), providing a conditioned analog signal 35. The conditioned analog signal 35 may be provided to the ADC circuit block 40 such that the signal conditioning circuit block 30 may act as an interface between the sensor circuit block 20 and the ADC circuit block 40, conditioning the analog signal 25 (and thus providing the conditioned analog signal 35) before the ADC circuit block 40 digitizes the analog signal. The signal conditioning circuit block 30 may amplify, attenuate, filter, and / or perform other conditioning functions on the analog signal 25. The ADC circuit block 40 can receive the conditioned analog signal 35 and convert it into digital form, providing a digital signal 45.The digital signal 45 may represent the physical quantity received by the sensor via the input signal 15. A digital signal processor (DSP) circuit block 50 may receive and process the digital signal 45.

[0018] The ADC circuit block 40 may include a sigma-delta ADC that generates a digital signal using a feedback technique, where the sigma-delta ADC may apply oversampling to its input signal (here, the conditioned analog signal 35) and perform noise shaping to achieve a high-resolution digital signal (here, the digital signal 45). The sigma-delta ADC may include a sigma-delta modulator 60 and a digital filter / decimator 70. The sigma-delta modulator 60 may use oversampling (e.g., a sampling rate above the Nyquist rate) and filtering to generate a digital signal representative of the input signal received by the sigma-delta ADC (such as the conditioned analog signal 35).

[0019] In various implementations, the feedback loop of the sigma-delta ADC forces the modulator output to be a good representation of the input signal in the bandwidth of interest. The digital filter / digital decimator 70 may attenuate noise and / or reduce a data rate of the digital signal (e.g., to a Nyquist sampling rate) providing the digital signal 45. The digital filter / digital decimator 70 may include a digital filter, a decimator, or both. The digital filter may attenuate the digital signal received from the sigma-delta modulator 60, and the decimator may reduce a sampling rate of the digital signal received from the sigma-delta modulator 60.

[0020] Fig. Figure 2 is a block diagram of an example of a single-bit first-order sigma-delta ADC. Sigma-delta modulator 100 may be an example of sigma-delta modulator 60 of Fig. 1. The sigma-delta modulator 100 may receive an input signal (Vin) at a rate determined by a sampling clock frequency Kf s determined, into a continuous, serial stream of ones and zeros. A single-bit digital-to-analog converter (single-bit DAC) 102 may be driven by the serial output data stream to generate a feedback signal. The output of the digital-to-analog converter (DAC) 102 may be subtracted from the input signal using a summing element 104. The summing element 104 may be implemented as the summing node of an operational amplifier (op amp), such as the op amp of an integrator 106.

[0021] The integrator 106 may integrate the output of the summing element 104 and the output of the integrator 106 may be applied to a clocked, latched comparator 108.

[0022] For a zero input signal, the comparator output may contain an approximately equal number of ones and zeros. For a positive input voltage, the comparator output has more ones than zeros. For a negative input voltage, the comparator output has more zeros than ones. The average of the comparator output over a number of cycles represents the input voltage. The comparator output may be applied to a digital filter and digital decimator 110 that averages every M cycles, where M is a positive integer greater than 1. The digital filter and decimator 110 may be an example of the digital filter / digital decimator 70 of Fig. 1. The decimator reduces the effective sampling rate at the output to the sampling rate f s .

[0023] Fig. 3 is an example of a continuous-time sigma-delta ADC 200 that can implement various techniques of this disclosure. The CTSD ADC 200 can include a resistive input, represented by a resistor 202, for receiving an analog input signal 204, such as a voltage VIN. The CTSD ADC 200 can include a summing circuit 206, a continuous-time integrator 208, one or more integrators 210, an analog-to-digital converter (ADC) 212, and a digital-to-analog converter (DAC) 214, such as a resistive DAC. An intrinsic resistance of the DAC 214 is represented by a resistor 216.

[0024] The summing circuit 206 may receive the analog input signal 204. The output of the summing circuit 206 may be coupled to an input of the continuous-time integrator 208. The output of the continuous-time integrator 208 may be coupled to the input of the integrator(s) 210, which may be one or more integrators. Other integrators may be used in subsequent stages, and these other integrators may be continuous-time integrators or a partially continuous-time and partially switched capacitor in a hybrid implementation. The output of the integrators 210 may be connected to the inputs of the ADC 212, which may be a single-bit ADC or a multi-bit ADC acting as a quantizer.

[0025] The output of the ADC 212 forms an output signal 218 and can also be input to the DAC 214.

[0026] As mentioned above, this disclosure describes, among other things, techniques for providing a precision ADC such as a CTSD ADC, such as the CTSD ADC 200 of Fig. 3, to provide a precision, low-noise reference voltage without the need for a buffer or digital correction. In one example, the technique may use a divider with an integrated resistor and an external capacitor to derive a precision, low-noise reference voltage from either the ADC's power supply or an integrated reference source, such as in Fig. 4 and Fig. 5 is shown.

[0027] Fig. 4 is an example of a CTSD ADC 400 that can implement various techniques of this disclosure. The CTSD ADC 400 can include an internal voltage divider circuit 402 located within the ADC. The voltage divider circuit 402 can include an internal first resistive element R1 connected to a resistive input R DACLOAD of the DAC, digital-to-analog converter (DAC). The resistive input R DACLOAD is in Fig. 3 by resistor 216. The CTSD ADC 400 is configured to receive an analog input voltage VIN at an input terminal and compare the input voltage VIN to a voltage reference REFCAP, wherein the voltage reference REFCAP is generated by the voltage divider circuit 402.

[0028] The first resistive element R1, such as a resistor, has a first end 404 for coupling to a power supply 406 of the ADC. As shown in Fig. As can be seen in Figure 4, the power supply 406 is a voltage source external to the ADC, such as an IC supply voltage. The resistive input R DACLOAD of the DAC has a first end 408 and a second end 410, wherein the first end of the resistive input R DACLOAD of the DAC is configured to be coupled to a second end 412 of the first resistive element R1 and is configured to couple to a capacitor C1 located outside the ADC, for example, to filter reference noise. The capacitor C1 can be sized depending on a desired noise performance. The second end 410 of the resistive input R DACLOAD of the DAC is designed to couple to a reference voltage such as a ground reference (AGND).

[0029] In some examples, the switching element R1 may have an on-resistance that corresponds to a resistance of the resistive input RDACLOAD of the DAC is proportional.

[0030] By using these techniques, a reference buffer amplifier is not required. Furthermore, these techniques can limit the bandwidth of the reference source noise. Furthermore, these techniques can provide low gain error and low gain error drift, e.g., R1 can be made to DACLOAD Finally, the techniques can enable ratiometric measurement using a ratiometric sensor if the input signal VIN and the supply voltage VDD are also ratiometric.

[0031] As described in more detail below, the CTSD ADC 400 may also include a switching element S1 such as a transistor, such as a field effect transistor (FET).

[0032] Fig. Figure 5 is another example of a CTSD ADC 500 that can implement various techniques of this disclosure. The CTSD ADC 500 is similar to the CTSD ADC 400 of Fig. 4, however, the CTSD-ADC 500 has an integrated reference source.

[0033] The CTSD ADC 500 may include an internal voltage divider circuit 502 located within the ADC. The voltage divider circuit 502 may include an internal first resistive element R1 connected to a resistive input R DACLOAD of the DAC, digital-to-analog converter (DAC). The resistive input R DACLOAD is in Fig. 3 by resistor 216. The CTSD ADC 500 is configured to receive an analog input voltage VIN at an input terminal and compare the input voltage VIN to a voltage reference REFCAP, wherein the voltage reference REFCAP is generated by the voltage divider circuit 502.

[0034] The first resistance element R1 has a first end 504 for coupling to a power supply 506 of the ADC. As shown in Fig. As can be seen in Figure 5, the power supply 406 is a voltage source located within the ADC, such as an integrated reference source. The resistive input R DACLOAD of the DAC has a first end 508 and a second end 510, wherein the first end 508 of the resistive input R DACLOAD of the DAC is configured to be coupled to a second end 512 of the first resistive element R1 and is configured to couple to a capacitor C1 located outside the ADC, for example, to filter reference noise. The second end 510 of the resistive input R DACLOAD of the DAC is designed to couple to a reference voltage such as a ground reference (AGND).

[0035] By using these techniques, a reference buffer amplifier is not required. Furthermore, these techniques can limit the bandwidth of the reference source noise. Furthermore, these techniques can provide low gain error and low gain error drift, e.g., R1 can be made to DACLOAD Finally, any drop in the resistance of R1 can be compensated by increasing the voltage of the higher reference source 506.

[0036] Fig. 6 is an example of an amplifier circuit configured to generate a common-mode voltage and provide the common-mode voltage to an amplifier circuit of an integrator circuit of a CTSD ADC. Integrator circuit 600 includes an amplifier circuit 602 coupled to a comparator circuit 604.

[0037] The amplifier circuit 602 is configured to receive the voltages vp, vn. If the amplifier circuit 608 is not present, the common mode at the voltages vp, vn can change depending on the input common-mode voltage (CM) of the circuit. This, in turn, changes the load current from the reference voltage VREFIN. Only common-mode signals influence the current from the voltage reference V REFIN (the reference voltage at the ADC pin). Without the amplifier circuit 608, the CTSD input common mode (Vinp + Vinm) / 2 changes the current flowing from the voltage reference V REFIN is pulled.

[0038] If the voltage reference V REFIN with a low impedance, the voltage reference V REFIN constant. However, any resistance in series with the V REFINpin may introduce a change in the ADC voltage reference (a gain error) that depends on the CTSD input (Vinp + Vinm) / 2, such as a common mode rejection ratio (CMRR) error.

[0039] When the common mode voltage changes, the voltages vp, vn change such that the voltage drop between V REFIN and vp, vn. Thus, there is a different load current flowing through the resistor R1 in Fig. 4 and Fig. 5 flows, such that a reference voltage V REFIN generated by modulating the load current.

[0040] To solve this problem, the inventors realized that an amplifier circuit 608, such as an auxiliary amplifier, may be included to increase the common-mode voltage at the input of the amplifier circuit 602 to a desired voltage VCM, such as V REFIN / 2. The amplifier circuit 608 is configured to generate a common-mode voltage VCM, which is applied to both differential inputs vp and vn of the amplifier circuit 602 of the integrator circuit 600. The common-mode voltage VCM can be connected to the reference voltage V REFIN , which can be a reference voltage for the DAC.

[0041] In this way, the CTSD input common-mode voltage (Vinp + Vinm) / 2 does not change the current flowing through resistor R1 because the common-mode voltage at amplifier circuit 602 is driven by common-mode amplifier circuit 608. In some examples, the common-mode voltage VCM may be derived ratiometrically from the reference voltage VDD, which may enable ratiometric measurements when an input signal VIN is ratiometric with respect to the voltage VDD.

[0042] The techniques described above, such as those relating to Fig. 4 and Fig. 5, eliminate the need for a reference buffer. That is, the techniques from Fig. 4 and Fig. 5 can use a divider with an integrated resistor and an external capacitor to derive a precision, low-noise reference voltage either from the ADC's power supply or from an integrated reference source. However, in some implementations, it may be desirable to include a reference buffer circuit that can be enabled or disabled as desired by the user. Examples of various user-configurable implementations are described in Fig. 7-9 shown.

[0043] Fig. Figure 7 is another example of a CTSD ADC 700 that can implement various techniques of this disclosure. The CTSD ADC 700 can include an internal voltage divider circuit located within the ADC. The voltage divider circuit can include an internal first resistive element R1 connected to a resistive input R DACLOAD of the DAC, digital-to-analog converter (DAC). The resistive input R DACLOAD is in Fig. 3 by resistor 216. The CTSD-ADC 700 is configured to receive an analog input voltage at an input terminal and compare the input voltage to a voltage reference.

[0044] The first resistive element R1 has a first end for coupling to a power supply VDD of the ADC. The resistive input R DACLOADof the DAC has a first end and a second end, wherein the first end of the resistive input R DACLOAD of the DAC is configured to be coupled to a second end of the first resistive element R1 via a switching element S1, such as a transistor, such as a field-effect transistor (FET). The switching element S1, which may have an open state or a closed state, may be connected between the second end of the first resistive element R1 and the first end of the resistive input R DACLOAD of the DAC.

[0045] The first end of the resistive input R DACLOAD is also designed to couple to a capacitor C1 located outside the ADC, for example, to filter reference noise. The second end of the resistive input R DACLOAD of the DAC is designed to couple to a reference voltage such as a ground reference (AGND).

[0046] The CTSD ADC 700 may include a reference buffer circuit 702 located within the ADC. A control circuit 704 may output a control signal to enable / disable the reference buffer circuit 702. Furthermore, the control circuit 704 is configured to output a control signal to operate the switching element S1. As one example, the control circuit 704 may include a register circuit configured to store a setting for establishing a state of the switching element S1.

[0047] As in Fig. As can be seen in Figure 7, the switching element S1 is in the closed state and the control circuit 704 has deactivated the reference buffer circuit 702. When the switching element S1 is in the closed state, the voltage reference (“modulator reference”) is generated by the voltage divider circuit formed by R1 and R DACLOAD is formed.

[0048] Fig. Figure 8 is another example of a CTSD ADC 800 that can implement various techniques of this disclosure. Some of the components of the CTSD ADC 800 are similar to components in the CTSD ADC 700 of Fig. 7 and for the sake of conciseness, these components will not be described again.

[0049] The CTSD ADC 800 may include a reference buffer circuit 702 located within the ADC. As shown in Fig. As can be seen in Figure 8, the switching element S1 is in the open state and the control circuit 704 has activated the reference buffer circuit 702. When the switching element S1 is in the open state, a voltage reference circuit 802, located external to the ADC, is configured to generate the voltage reference ("modulator reference").

[0050] Fig. Figure 9 is another example of a CTSD-ADC 900 that can implement various techniques of this disclosure. Some of the components of the CTSD-ADC 900 are similar to components in the CTSD-ADC 700 of Fig. 7 and in the CTSD-ADC 800 Fig. 8 and for the sake of conciseness, these components will not be described again.

[0051] The CTSD ADC 900 may include a reference buffer circuit 702 located within the ADC and a reference buffer circuit 902 located external to the ADC and coupled to a voltage reference circuit 802 located external to the ADC. The reference buffer circuit 902 may include various components for filtering noise from the voltage reference circuit 802.

[0052] As in Fig. As can be seen in Figure 9, switching element S1 is in the open state, and control circuit 704 has deactivated internal reference buffer circuit 702. When switching element S1 is in the open state, voltage reference circuit 802, located external to the ADC, is configured to generate the voltage reference ("modulator reference") that can be buffered (and optionally filtered) by reference buffer circuit 902.

[0053] Fig. 10 is an example of a CTSD-ADC 1000 in combination with a sensor 1002. The CTSD-ADC 1000 may implement the techniques of this disclosure, such as described above with reference to Fig. 7, in which the switching element is in a closed state. In some examples, sensor 1002 may be an external ratiometric sensor, such as a bridge sensor.

[0054] As in Fig. 10, the sensor 1002 operates using the same voltage supply VDD as the CTSD-ADC 1000. The reference voltage of the CTSD-ADC 1000 (the “modulator reference” from Fig. 7) may change if the supply voltage VDD fluctuates. However, any change in the supply voltage VDD will also affect the reference voltage of the voltage divider circuit, such as R1 and R DACLOAD in Fig. 7 formed, influence.

[0055] The output of sensor 1002 is ratiometric with respect to the supply voltage VDD. As the supply voltage varies, the output of sensor 1002 varies accordingly in a fixed ratio. In other words, the output of sensor 1002 follows any changes in the supply voltage VDD. This combination of a ratiometric sensor and an ADC implementing various techniques of this disclosure provides suppression of any fluctuation in the supply voltage VDD. Various comments

[0056] Each of the non-limiting aspects or examples described herein may stand alone or may be combined in various permutations or combinations with one or more of the other examples.

[0057] The above detailed description includes references to the accompanying drawings, which form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as "examples." Such examples may include elements in addition to those shown or described. However, the inventors of the present invention also contemplate examples in which only those elements shown or described are provided.In addition, the inventors of the present invention also contemplate examples using any combination or permutation of those elements shown or described (or one or more aspects thereof), either with respect to a particular example (or one or more aspects thereof) or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0058] In the event of any inconsistency between this document and any documents incorporated by reference, the usage in this document shall prevail.

[0059] Throughout this document, the terms "a(n)" and "a" are used as is customary in patent documents to include one or more than one, regardless of any other instances or uses of "at least one" or "one or more." Throughout this document, the term "or" is used to refer to a non-exclusive or, such that "A or B" includes "A but not B," "B but not A," and "A and B," unless otherwise indicated. Throughout this document, the terms "including" and "at which" are used as the plain-language equivalents of the respective terms "comprising" and "wherein."

[0060] Furthermore, the terms "including" and "comprising" in the following claims are open-ended, meaning that a system, apparatus, article of manufacture, composition, formulation, or process that includes elements in addition to those listed after such a term in a claim will still be considered within the scope of that claim. Furthermore, in the following claims, the terms "first," "second," and "third," etc., are used merely as identifiers and are not intended to impose numerical requirements on their subject matter.

[0061] Method examples described herein may be at least partially machine- or computer-implemented. Some examples may include a computer-readable medium or a machine-readable medium encoded with instructions operable to configure an electronic device to perform methods as described in the above examples. Implementation of such methods may include code such as microcode, assembly language code, high-level language code, or the like. Such code may include computer-readable instructions for performing various methods. The code may form portions of computer program products. Further, in one example, the code may be stored on one or more transient, non-transitory, or non-transitory, tangible, computer-readable media in a tangible manner, such as during execution or at other times.Examples of these tangible, computer-readable media may include, but are not limited to, hard disks, removable magnetic disks, removable optical disks (e.g., compact disks and digital video disks), magnetic cassettes, memory cards or memory sticks, random access memory (RAM), read-only memory (ROM), and the like.

[0062] The above description is intended to be illustrative and not restrictive. For example, the examples described above (or one or more aspects thereof) may be used in combination with one another. Other embodiments may be used, such as would be apparent to one of ordinary skill in the art upon review of the above description. The abstract is provided to enable the reader to quickly grasp the essence of the technical disclosure. It is presented with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Furthermore, in the above detailed description, various features may be grouped together to streamline the disclosure. This should not be interpreted as intending that an unclaimed disclosed feature is indispensable to any claim.Rather, the subject matter of the invention may lie in fewer than all features of a particular disclosed embodiment. Thus, the following claims are hereby incorporated as examples or embodiments in the detailed description, with each claim standing on its own as a single embodiment, and it is contemplated that such embodiments may be combined in various combinations or permutations. The scope of the invention should be determined by reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

[0063] In the present disclosure, one aspect is directed to techniques for providing a precision, low-noise reference voltage to a precision analog-to-digital converter without the need for a reference buffer or digital correction. In one example, a technique may use a divider with an integrated resistor and an external capacitor to derive a precision, low-noise reference voltage from either the ADC's power supply or an integrated reference source.

Claims

[1] Circuit comprising: a continuous-time sigma-delta analog-to-digital converter (sigma-delta ADC) comprising a voltage divider circuit located within the ADC, the voltage divider circuit comprising a first resistive element coupled to a resistive input of a digital-to-analog converter (DAC), the ADC being configured to receive an analog input voltage at an input terminal and compare the analog input voltage to a voltage reference, the voltage reference being generated either by the voltage divider circuit or by a voltage reference circuit located external to the ADC; wherein the first resistive element has a first end for coupling to a power supply of the ADC; wherein the resistive input of the DAC has a first end and a second end, wherein the first end of the resistive input of the DAC is configured to be coupled to a second end of the first resistive element, and wherein the second end of the resistive input of the DAC is configured to couple to a reference voltage; a control circuit; and a switching element coupled between the second end of the first resistive element and the first end of the resistive input of the DAC, the switching element having an open state and a closed state, the control circuit being configured to operate the switching element. [2] The circuit of claim 1, wherein the voltage reference is external to the ADC. [3] The circuit of claim 1, wherein the voltage reference is located within the ADC. [4] A circuit according to any one of the preceding claims, comprising: an integrator circuit having a first amplifier circuit; and a second amplifier circuit for generating a common-mode voltage, wherein the first amplifier circuit is configured to receive the common-mode voltage. [5] A circuit according to any preceding claim, comprising a reference buffer circuit. [6] Circuit according to one of claims 1 to 4, comprising: a reference buffer circuit (702) located within the ADC, wherein, when the switching element is in the closed state, the control circuit is designed to deactivate the reference buffer circuit (702), and where the voltage reference is generated by the voltage divider circuit. [7] Circuit according to one of claims 1 to 4, comprising: a reference buffer circuit (702) located within the ADC, wherein, when the switching element is in the open state, the control circuit is adapted to activate the reference buffer circuit (702), and wherein the voltage reference circuit outside the ADC is configured to generate the voltage reference. [8] A circuit according to any one of claims 1 to 4, comprising: a reference buffer circuit (702) located within the ADC (900), and a reference buffer circuit (902) located outside the ADC (900) and coupled to the voltage reference circuit (802) outside the ADC (900), wherein, when the switching element (S1) is in the open state, the control circuit (704) is configured to deactivate the reference buffer circuit (702) located within the ADC (900), and wherein the voltage reference circuit (802) outside the ADC (900) is configured to provide the voltage reference (V REFIN ) to generate. [9] Circuit according to one of the preceding claims in conjunction with a ratiometric sensor. [10] A circuit according to any one of the preceding claims, wherein the switching element has an on-resistance proportional to a resistance of the resistive input of the DAC. [11] A circuit according to any preceding claim, wherein the voltage reference is generated by the voltage divider circuit. [12] A circuit according to any one of claims 1 to 10, wherein the voltage reference is generated by the voltage reference circuit external to the ADC. [13] A method for operating a continuous-time sigma-delta analog-to-digital converter (sigma-delta ADC), the method comprising: Coupling a voltage divider circuit located within the ADC, comprising: coupling a first resistive element to a resistive input of a digital-to-analog converter (DAC), the ADC being configured to receive an analog input voltage at an input terminal and to compare the analog input voltage to a voltage reference, the voltage reference being generated either by the voltage divider circuit or by a voltage reference circuit external to the ADC; coupling a first end of the first resistive element to a power supply of the ADC; and coupling a first end of the resistive input of the DAC to a second end of the first resistive element and coupling a second end of the resistive input of the DAC to a reference voltage; coupling a switching element between the second end of the first resistive element and the first end of the resistive input of the DAC, the switching element having an open state and a closed state; and Controlling an operation of the switching element. [14] The method of claim 13, wherein the continuous-time sigma-delta ADC comprises an integrator circuit comprising a first amplifier circuit, the method comprising: Generating a common-mode voltage by a second amplifier circuit; and Applying the common-mode voltage to the first amplifier circuit. [15] The method of claim 13 or 14, wherein the continuous-time sigma-delta ADC comprises a reference buffer circuit (702) located within the ADC (900), the method comprising: Deactivating the reference buffer circuit (702); Controlling the operation of the switching element such that the switching element is placed in the closed state; and Generating the voltage reference through the voltage divider circuit. [16] The method of claim 13 or 14, wherein the continuous-time sigma-delta ADC comprises a reference buffer circuit (702) located within the ADC (900), the method comprising: Activating the reference buffer circuit (702); Controlling the operation of the switching element such that the switching element is placed in the open state; and Generating the voltage reference by the voltage reference circuit outside the ADC. [17] The method of claim 13 or 14, wherein the continuous-time sigma-delta ADC (900) comprises an internal reference buffer circuit (702) and an external reference buffer circuit (902) located external to the ADC (900) and coupled to the voltage reference circuit (802) external to the ADC (900), the method comprising: Deactivating the reference buffer circuit (702) located within the ADC (900); Controlling the operation of the switching element (S1) such that the switching element (S1) is placed in the open state; and Generating the voltage reference (V REFIN ) by the voltage reference circuit (802) outside the ADC (900).

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