DYNAMIC ANTI-ALIAS FILTER FOR AN ANALOGUE-TO-DIGITAL CONVERTER FRONTEND

Abstract

Analog front-end (AFE) system with an anti-aliasing filter circuit including a filter bypass switch configured to provide charge injection and / or clock pass-through independent of an input signal, wherein the AFE system comprises: at least one sampling capacitor of an analog-to-digital converter (ADC) circuit configured to sample an output of the anti-aliasing filter circuit; an amplification or buffer circuit with an input for receiving the input signal; and the anti-aliasing filter circuit coupled to an output of the amplification or buffer circuit, wherein the filter circuit comprises the following: a filter resistor; a filter capacitor coupled to one terminal of the filter resistor; and the filter bypass switch, which is connected in a bootstrapped configuration to pull a control terminal of the filter bypass switch above or below a supply voltage, wherein the filter bypass switch is connected in parallel to the filter resistor, wherein the filter bypass switch has an ON state and an OFF state, wherein, when in the ON state, the filter bypass switch is configured to bypass the filter resistance, allowing the amplification or buffer circuit to drive the at least one sampling capacitor through the filter bypass switch; and wherein, when in the OFF state, the filter bypass switch is designed to cause the amplification or buffer circuit to drive the at least one sampling capacitor through the filter resistor.

Description

CLAIM OF PRIORITY

[0001] The present application claims priority over the preliminary US patent application filed on November 13, 2016, with serial number 62 / 421,344 entitled “INTERFERENCE-IMMUNE DIAGNOSTIC QUALITY ECG RECORDING FOR WIRELESS PATIENT MONITORING APPLICATIONS” for Arthur J. Kalb et al., and the preliminary US patent application filed on November 14, 2016, with serial number 62 / 421,650 entitled “INTERFERENCE-IMMUNE DIAGNOSTIC QUALITY ECG RECORDING FOR WIRELESS PATIENT MONITORING APPLICATIONS” to Arthur J. Kalb et al. and the preliminary US patent application filed on May 1, 2017, with serial number 62 / 492,406 entitled “QUANTIZATION NOISE CANCELTION IN A FEEDBACK LOOP” to Arthur J. Kalb et al., all contents of each herein being incorporated by reference. AREA OF REVELATION

[0002] The present disclosure relates generally to integrated circuits and in particular, among other things, to low-noise precision input stages for analog-to-digital converters. GENERAL STATE OF THE ART

[0003] In many electronics applications, an analog-to-digital converter (ADC) can translate analog electrical signals representing a real-world phenomenon, such as light, sound, temperature, or pressure, into a digital output signal using digital processing, for example, for further signal processing. For instance, in precision measurement systems, electronics with one or more sensors may be used to take measurements and generate analog signals. These analog signals can then be fed to an ADC to generate a digital output signal for further processing.

[0004] ADWs are found in many places, such as broadband communication systems, audio systems, receiver systems, etc. ADWs can be used in a wide range of applications, including communications, energy, healthcare, instrumentation and measurement, motor and power control, industrial automation, and aerospace / defense. BRIEF SUMMARY OF THE REVELATION

[0005] Analog-to-digital converters (ADCs) can be used for various applications, including, for example, wireless patient monitoring. The inventors of the present invention recognized that one problem to be solved is aliasing due to sampling out-of-band noise or interference. The inventors of the present invention recognized that a dynamic anti-aliasing filter (AAF) coupled upstream of an ADC circuit may have a bypass switch which, due to charge injection and capacitive coupling, can inject a significant charge into the AAF filter capacitor when the bypass switch is turned off, potentially causing a differential error at the ADC input.The inventors of the present invention have solved this problem by realizing that a bootstrapped bypass switch can be integrated into the dynamic AAF filter, making charge injection and capacitive coupling independent of the input signal. This significantly reduces the settling time requirements, resulting in a better compromise between noise aliasing and the power consumption / bandwidth of the amplifier driving the AAF filter and the ADW.

[0006] In some aspects, the present disclosure relates to an analog front-end (AFE) system with an anti-aliasing filter circuit having a filter bypass switch configured to provide charge injection and / or clock feedthrough, independent of an input signal. The AFE system comprises at least one sampling capacitor of an analog-to-digital converter (ADC) circuit configured to sample an output of the anti-aliasing filter circuit, a gain or buffer circuit with an input for receiving the input signal, and the anti-aliasing filter circuit coupled to an output of the gain or buffer circuit, wherein the filter circuit comprises: a filter resistor; a filter capacitor coupled to a terminal of the filter resistor;and the filter bypass switch, which is connected in a bootstrapped configuration to pull a control terminal of the filter bypass switch above or below a supply voltage, wherein the filter bypass switch is connected in parallel to the filter resistor, wherein the filter bypass switch has an ON state and an OFF state, wherein, when in the ON state, the filter bypass switch is configured to bypass the filter resistor, thereby allowing the amplification or buffer circuit to drive the at least one sampling capacitor through the filter bypass switch; and wherein, when in the OFF state, the filter bypass switch is configured to cause the amplification or buffer circuit to drive the at least one sampling capacitor through the filter resistor.

[0007] In some aspects, the present disclosure relates to a method for operating an analog front-end (AFE) system with an anti-aliasing filter circuit having a filter bypass switch configured to provide charge injection and / or clock pass-through independent of an input signal. The method includes: providing at least one sampling capacitor of an analog-to-digital converter (ADC) circuit configured to sample the output of the anti-aliasing filter circuit; providing an amplification or buffer circuit with an input for receiving the input signal; and coupling the anti-aliasing filter circuit to the output of the amplification or buffer circuit, wherein the anti-aliasing filter circuit comprises: a filter resistor, a filter capacitor coupled to a terminal of the filter resistor, and the filter bypass switch configured in a bootstrapped configuration.to pull a control terminal of the filter bypass switch above or below a supply voltage, wherein the filter bypass switch is connected in parallel to the filter resistor, wherein the filter bypass switch has an ON state and an OFF state, wherein, when in the ON state, the input signal is received and the filter bypass switch is controlled to bypass the filter resistor so that the amplification or buffer circuit can drive the at least one sampling capacitor through the filter bypass switch, and wherein, when in the OFF state, the input signal is received and the filter bypass switch is controlled to cause the amplification or buffer circuit to drive the at least one sampling capacitor through the filter resistor.

[0008] In some aspects, the present disclosure relates to an electrocardiogram (ECG) measurement circuit comprising: an analog front-end (AFE) system with an anti-aliasing filter circuit having a filter bypass switch configured to provide charge injection and / or clock pass-through independent of an input signal. The AFE system comprises at least one sampling capacitor of an analog-to-digital converter (ADC) circuit configured to sample the output of the anti-aliasing filter circuit; an amplification or buffer circuit with an input for receiving the input signal; and the anti-aliasing filter circuit coupled to the output of the amplification or buffer circuit, wherein the filter circuit comprises: a filter resistor; a filter capacitor coupled to a terminal of the filter resistor;and the filter bypass switch, which is connected in a bootstrapped configuration to pull a control terminal of the filter bypass switch above or below a supply voltage, wherein the filter bypass switch is connected in parallel to the filter resistor, wherein the filter bypass switch has an ON state and an OFF state, wherein, when in the ON state, the filter bypass switch is configured to bypass the filter resistor, thereby allowing the amplification or buffer circuit to drive the at least one sampling capacitor through the filter bypass switch; and wherein, when in the OFF state, the filter bypass switch is configured to cause the amplification or buffer circuit to drive the at least one sampling capacitor through the filter resistor.

[0009] This overview is intended to provide a general understanding of the subject matter of the present patent application. It is not intended to be an exclusive or exhaustive explanation of the invention. The detailed description is included to provide further information about the present patent application. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In the drawings, which are not necessarily drawn to scale, the same numbers in different views may describe similar components. The same numbers with different letter suffixes may represent different instances of similar components. The drawings generally show, by way of example but not as a limitation, various embodiments discussed in this document. Fig. Figure 1 shows an example of a dynamic anti-aliasing filter circuit. Fig. Figure 2 shows an example of a dynamic anti-aliasing filter circuit that can implement various techniques of the present disclosure. Fig. Figure 3 shows an example of a dynamic anti-alias filter circuit with a filter bypass switch, switched in a bootstrapped configuration. Fig. Figure 4 shows an example of a dynamic anti-aliasing filter circuit from Fig. 3 with the filter bypass switch in an ON state. Fig. Figure 5 is a flowchart that presents an example of a method for operating an analog front-end (AFE) system with an anti-alias filter circuit with a filter bypass switch, configured to provide charge injection and / or clock pass-through independent of an input signal, using various techniques of the present disclosure. Fig. Figure 6 is an example of a schematic representation of the analog frontend system of the Fig. 2-4 in combination with an electrocardiogram (ECG) measuring circuit.

[0011] In the drawings, which are not necessarily drawn to scale, the same numbers in different views may describe similar components. The same numbers with different letter suffixes may represent different instances of similar components. The drawings generally show, by way of example but not as a limitation, various embodiments discussed in this document. DETAILED DESCRIPTION

[0012] Anti-aliasing (AAF) filter circuits can be used before an analog-to-digital converter (ADC) input stage (or front end) to prevent aliasing (due to sampling) of out-of-band noise / interference into the in-band signal by filtering out the out-of-band frequency content. The AAF can be a low-pass filter, a band-pass filter, a high-pass filter, etc. An amplifier can be used to amplify the input signal and drive the ADC front end through the AAF filter. The bandwidth of the AAF filter can be a compromise between a settling time, which is desirable to meet precision requirements, and rejection of out-of-band noise / interference.

[0013] Dynamic AAF filters can be used to overcome this limitation, as described in US Patent No. 9,391,628, "Low noise precision input stage analog-to-digital converters," granted to Colin Lyden et al. A dynamic AAF filter may include a bypass switch that allows the AAF filter to be bypassed, enabling the amplifier to directly drive an ADW sampling capacitor for a short period to achieve a fast settling time. Later, the bypass switch can be disengaged, and the amplifier can drive the ADW sampling capacitor through the AAF filter for the final settling period. During this period, the AAF filter can attenuate out-of-band noise / interference before the ADW samples the input signal.

[0014] One challenge with dynamic AAF filters, such as in an analog front end (AFE), is that when the bypass switch turns off, charge injection and capacitive coupling can inject a significant charge into the AAF filter capacitor, potentially causing an error. This error can be a function of the input voltage and can result in a differential signal error. This differential error should "settle" by the time the ADW's input sampling capacitor enters the hold state. Therefore, a significant portion of the sampling period can be spent in this mode to meet precision settling requirements, reducing the time available for the amplifier to settle directly. This can lead to increased current consumption in the amplifier to achieve faster settling across a wider amplifier bandwidth.

[0015] As described in detail below, the inventors of the present invention have recognized that a filter bypass switch configured in a bootstrapped manner to pull a control terminal of the filter bypass switch above or below a supply voltage can be used to solve the problems mentioned above. The use of bootstrapped switches allows both the charge injection and capacitive coupling of the differential AAF filter bypass switches to operate in common-mode mode. The bootstrapped switch can be a single type of transistor, such as an N-FET or a P-FET, wherein the gate can be driven to the input voltage when the switch is OFF, but to the input voltage plus the supply voltage when the switch is ON.Thus, the differential input signal of the ADW is not affected up to a first order by the charge injection and capacitive coupling of the bypass switches in the AAF filter. In some implementations, only 30% of the sampling period was used when the AAF filter was active, which greatly reduced the amplifier's power consumption.

[0016] Fig. Figure 1 shows an example of a dynamic anti-aliasing filter circuit 10. The dynamic AAF circuit 10, which can be part of an analog front-end (AFE) system 11, can include a filter bypass switch 12, a filter resistor 14, and a filter capacitor 16 coupled to one terminal of the filter resistor 14. The filter bypass switch 12 can, for example, be a transmission gate with a first transistor 18 and a second transistor 20. In some examples, the first and second transistors 18 and 20 can be field-effect transistors, with the first transistor 18 being a first type, e.g., a P-type, and the second transistor 20 being a second type, e.g., an N-type. As shown in Fig. As can be seen in Figure 1, the first and second transistors 18, 20 can be controlled using complementary control signals ϕ and ϕ_bar, so that both transistors 18, 20 are ON or OFF over a larger range of voltages than they would be individually.

[0017] The AFE system 11 may further include a gain circuit 22, for example, a capacitive gain amplifier (CGA) with an input for receiving an input signal 24 and an output configured to apply a signal to the filter bypass switch 12. For example, the gain circuit 22 may provide an input to the dynamic anti-aliasing filter circuit 10, and the dynamic anti-aliasing filter circuit 10 may output a filtered signal to an analog-to-digital converter (ADC) circuit 26 for conversion to a digital signal. For example, at least one sampling capacitor of an analog-to-digital converter (ADC) circuit may sample an output of the anti-aliasing filter circuit. In some examples, the gain circuit 22 may be a buffer circuit.

[0018] In some examples, the filter capacitor 16 can include an ADW sampling capacitor of the ADW circuit 26. The bypass switch 12 can be used to bypass the AAF filter circuit, allowing the gain circuit 22 to directly drive an ADW sampling capacitor for a short period. Later, the bypass switch 12 can be switched off, and the gain circuit 22 can drive the ADW sampling capacitor through the AAF filter circuit during the final settling time. The AAF filter can attenuate out-of-band noise / interference before the ADW samples the input signal.

[0019] If in Fig. When the filter bypass switch 12 is switched on, the amplification circuit 22 can drive the filter capacitor 16, e.g., an ADW sampling capacitor, by bypassing the filter resistor 14. Then the filter bypass switch 12 can be switched off, which connects the filter resistor 14 to the amplification circuit 22, and the input signal from the amplification circuit 22 can be supplied through the RC filter to the ADW, which includes the filter resistor 14 and the filter capacitor 16.

[0020] When the filter bypass switch 12 is turned on and the input is below Vdd / 2, the second transistor 20, e.g., an N-type device, may be active, while the first transistor 18, e.g., a P-type device, may be off. When the filter bypass switch 12 is turned off, two sources of error can occur: charge injection and clock pass-through. Charge injection can cause errors because the channel charge is discharged into the drain and source terminals of the transistor when the transistor turns off. Clock pass-through can cause errors because the control signal ϕ and ϕ_bar, e.g., a clock signal, couples into the circuit via the gate-drain or gate-source overlap capacitance.

[0021] When the switch turns on, the channel charge injection through the second transistor 20 can split to both the source and the drain. However, because the input impedance at the filter capacitor 16 is lower than the input impedance of the amplifier 22, most of the gate charge goes to the filter capacitor 16. Analogous behavior can occur if the input is above Vdd / 2 when the first transistor 18 is turned on but the second transistor 20 is turned off. Thus, the input voltage to the ADF can be distorted by the charge injection of the bypass switch, which changes with the input voltage of the AAF filter.

[0022] The charge injection at the bypass switch can be described by the following equations 1 and 2: Qchn≅−WnLnCox(ϕH−VIN−V1n) Qchp≅WpLpCox(VIN−ϕL−|Vtp|)

[0023] Equation 1 describes N-channel charge injection, and equation 2 describes P-channel charge injection. In equations 1 and 2, ϕ H (e.g. 5 volts (V)) and ϕ L (e.g. 0 V) ​​on the high and low levels of the filter bypass switch 12 V IN is the input voltage (e.g. 0-5 V), V tn is the N-channel threshold voltage, V tp is the P-channel threshold voltage, W and L are the width and length of the transistor, and C ox is the oxide capacitance of the transistor.

[0024] In equation 1, the N-channel charge injection is a function of the difference between ϕ H and V IN If the voltage V IN rises and ϕ H As the N-channel charge injection approaches the higher voltage, it decreases. The P-channel charge injection is a function of the difference between V and the lower voltage. IN and ϕ L If the voltage V IN As the P-channel charge injection increases, so does the P-channel charge injection.

[0025] With an input voltage V IN Near a mid-range, the N-channel and P-channel charge injections can cancel each other out. However, while the input voltage V IN As the N-channel and P-channel charge injections approach the high or low side of a region, they may not cancel each other out.

[0026] Although the circuit in Fig. Although shown as ground-referenced, it can also be connected in a differential configuration. A differential configuration can lead to a significant voltage spike at the output (e.g., 2 mV) when the input voltage V approaches the input voltage. INAt the high or low end of a region, the P-channel device can inject charge into the filter capacitor 16 while the N-channel device is switched off, or vice versa. This voltage surge can be dampened by the RC filter consisting of the filter resistor 14 and the filter capacitor 16, but this may require a significant settling time.

[0027] If, as mentioned above, filter bypass switch 12 is switched off, clock pass-through can be another source of error. Clock pass-through can be described by equation 3 below: Vout=Vin−ColCol+C(ϕH−ϕL)

[0028] In equation 3, ϕ H and ϕ L the high and low levels of the control signal, e.g., the clock signal, of the filter bypass switch 12, C olis the overlap capacitance of the transistor, and C is the capacitance of the output transistor, e.g., the filter / sampling capacitor 16. If the difference between ϕ H and ϕ L a fixed value, is the caused V OUT The voltage surge is the same regardless of the input. As such, the output clock pass-through is not signal-dependent. However, if ϕ H or ϕ L If the voltage is a function of the input voltage, then the caused voltage is OUT -Voltage surge is a function of the input voltage.

[0029] In some implementations, for illustrative purposes only, a 4 / 1 CMOS switch with an 8 pF filter capacitor can produce a 3 mV output error due to charge injection for an input differential voltage of 1.2 V. However, it may be desirable to achieve an ADW input settling below 5 µV. As such, an RC time constant (τ) of 6.4 was required. For a 240 kilohertz (kHz) AAF filter circuit, τ is 660 nanoseconds (ns). However, a τ of 6.4 is equal to 4.2 µs, which does not allow sufficient time for the amplification circuit 22, e.g., the CGA, to settle if the ADW samples at 240 kHz.

[0030] As stated above, the inventors of the present invention have solved this problem by recognizing that a bootstrapped bypass switch can be integrated into the dynamic AAF filter, which can make charge injection and capacitive coupling independent of the input signal. That is, charge injection and capacitive coupling will occur in common mode and can be rejected.

[0031] Fig. Figure 2 shows an example of a dynamic anti-aliasing filter circuit 30 that can implement various techniques of this revelation. The dynamic AAF circuit 30, which can form part of an analog front-end (AFE) system 31, can be switched to a filter bypass switch 32 (in a bootstrapped configuration, as in Figure 2). Fig. 3 and Fig. (as shown in Figure 4), comprising a filter resistor 14 and a filter capacitor 16 coupled to one terminal of the filter resistor 14. The filter circuit 30 can be coupled to the output of the amplification or buffer circuit 22.

[0032] In some examples, the filter capacitor 16 and an ADW sampling capacitor of the ADW circuit 26 are the same capacitor, and in other examples, the filter capacitor 16 and an ADW sampling capacitor may be different capacitors.

[0033] In some example configurations, the filter bypass switch 32 can be a single transistor, as shown in Fig. Figure 2 shows that in some examples, the filter bypass switch 32 can be a single type of transistor, namely an N-type or a P-type transistor. The transistor can be, for example, a field-effect transistor (FET), including, but not limited to, a metal-oxide-semiconductor field-effect transistor (MOSFET), a JFET (junction gate field-effect transistor), a DMOS transistor, and a gallium nitride transistor.

[0034] As in Fig. As shown in Figure 2, the filter bypass switch 32 can be controlled by applying a control signal ϕ to a control terminal 34 to turn the switch 32 ON or OFF. For example, the control terminal can be a gate terminal of a FET. A gain amplifier 22, e.g., a capacitive gain amplifier (CGA), can provide an input to the dynamic anti-aliasing filter circuit 30, and the dynamic anti-aliasing filter circuit 30 can output a filtered signal to an analog-to-digital converter (ADC) circuit 26 for conversion to a digital signal.

[0035] Fig. Figure 3 shows an example of a dynamic anti-aliasing filter circuit with a filter bypass switch, configured in a bootstrapped state. Specifically, the filter circuit 30 shows the filter bypass switch 32 in an OFF state. When the filter bypass switch 32 is in the OFF state, it can cause the gain circuit 22 or the buffer circuit to drive the filter capacitor 16, e.g., one or more sampling capacitors, through the filter resistor 14.

[0036] In the example configuration shown, the anti-aliasing filter circuit 30 can include a number of bootstrap switches, shown as switches SW1-SW5, to pull a control terminal of the filter bypass switch 32, e.g., a gate terminal of a transistor, above or below a supply voltage to turn the switch ON or OFF. The filter circuit 30 can also include one or more bootstrap capacitors 36. A control circuit 38 of an ADW system, with control lines (not shown) coupled to switches SW1-SW5, can control the operation of switches SW1-SW5.

[0037] As in Fig. As shown in Figure 3, the control circuit 38 can close switch SW5 to couple the control terminal 34 of the filter bypass switch 32, e.g., a gate terminal of a FET, to the output of the amplification circuit 22, which in turn can switch off the filter bypass switch 32. The control circuit 38 can open switches SW2 and SW3 to decouple the bootstrap capacitor(s) 36 from 1) the control terminal 34 of the bypass switch 32 and 2) an input terminal 40, e.g., a source terminal, of the bypass switch 32. When the control circuit 38 closes switches SW1 and SW3, the bootstrap capacitor(s) 36 can then be connected to the supply voltage V. REF e.g., charge with 5V.

[0038] Fig. Figure 4 shows an example of a dynamic anti-aliasing filter circuit from Fig. 3 with the filter bypass switch in an ON state. When the filter bypass switch 32 is in the ON state, it can bypass the filter resistor 14 and allow the amplification circuit 22 to drive the filter capacitor 16, e.g., one or more sampling capacitors, via the source terminal 40 and the drain terminal 42 of the bypass switch 32.

[0039] As in Fig. As can be seen in Figure 4, the control circuit 38 can open switches SW1 and SW3 to disconnect the bootstrap capacitor(s) 36 from the supply voltage V. REF to decouple. The control circuit 38 can open switch SW5 and close switches SW2 and SW4 to couple the bootstrap capacitor(s) to 1) the control terminal 34 of the bypass switch 32 and 2) the input terminal 40 of the bypass switch 32, in order to derive a combination, e.g., a sum or difference, from the supply voltage V REF and an input signal voltage of 24 V INto connect to the control terminal 34 of the bypass switch 32. The control terminal 34 of the bypass switch 32 is connected to a voltage V REF + V IN , and the input terminal 40 of the bypass switch 32 is at a voltage V IN , which leads to a voltage V REF between the control terminal 34 and the input terminal 40, e.g. a gate-source voltage of V REF , which can switch on the bypass switch 32. Note that the gate-source voltage of the bypass switch 32 is independent of the input voltage 24.

[0040] Referring again to the charge injection problem described above, if the bypass switch 32 is a P-type device, the charge injection is a function of the input voltage V. IN minus the low level ϕ L of the bypass switch 32. Using bootstrapping techniques from Fig. 3 and Fig. 4 is the low-level voltage ϕ Lthe input voltage V IN , so that the charge injection of the bypass switch becomes independent of the input voltage.

[0041] If the bypass switch 32 is an N-type device, the charge injection is a function of the high-level voltage ϕ. H of the bypass switch 32 minus the input voltage V IN Using the bootstrapping techniques of Fig. 3 and Fig. 4 is the high-level voltage ϕ H the input voltage V IN plus V REF , so that the high-level voltage ϕ H (V IN + V REF ) minus the input voltage V IN equal V REF This makes the charge injection independent of the input signal.

[0042] Referring again to the clock pass-through problem described above, clock pass-through is a function of the difference between high and low levels ϕ. H and ϕ Lof the filter bypass switch 32. Using the bootstrapping techniques of Fig. 3 and Fig. 4 is the high-level voltage ϕ H the input voltage V IN plus V REF , and the low-level voltage ϕ L is the input voltage V IN Thus, the high-level voltage ϕ H (V IN + V REF ) minus the low-level voltage ϕ L (V IN ) equals V REF In this way, the clock signal is made independent of the input signal.

[0043] Fig. Figure 5 is a flowchart illustrating an example of Method 50 for operating an analog front-end (AFE) system with an anti-aliasing filter circuit having a filter bypass switch configured to provide charge injection and / or clock pass-through independent of an input signal, using various techniques of this disclosure. At block 52, Method 50 may include providing one or more sampling capacitors of an ADW circuit configured to sample the output of the anti-aliasing filter circuit. For example, the analog front-end system 31 of Fig. 2 have an ADW circuit with one or more sampling capacitors, e.g. capacitor 16, configured to sample the output of the anti-aliasing filter circuit 30.

[0044] In block 54, method 50 can include providing an amplification or buffer circuit with an input for receiving the input signal. For example, the analog front-end system 31 of Fig. 2 have a gain or buffer circuit 22 for receiving an input signal 24.

[0045] In block 56, method 50 may include providing a filter circuit coupled to the output of the amplification or buffer circuit, including providing a filter resistor, providing a filter capacitor coupled to a terminal of the filter resistor, and providing a filter bypass switch connected in a bootstrapped configuration to pull a control terminal of the filter bypass switch above or below a supply voltage, the filter bypass switch being connected in parallel with the filter resistor, and the filter bypass switch having an ON state and an OFF state. For example, the AFE system of Fig. 2-4 feature a filter circuit 30 with the filter resistor 14, the filter capacitor 16 and a filter bypass switch 32, connected in a bootstrapped configuration.

[0046] In block 56, method 50, in the ON state, can involve controlling the filter bypass switch to bypass the filter resistor, allowing the amplification or buffer circuit to drive the sampling capacitor(s), and in the OFF state, controlling the filter bypass switch to cause the amplification or buffer circuit to drive the sampling capacitor(s) through the filter resistor. For example, as in Fig. As can be seen in Figure 4, the control circuit 38 controls the filter bypass switch 32 to switch on and bypass the filter resistor 14, which allows the amplification or buffer circuit 22 to drive the sampling capacitor(s), e.g., capacitor 16. As shown in Fig. As can be seen in Figure 3, the control circuit 38 can control the filter bypass switch 32 to switch it off and cause the amplification or buffer circuit 22 to drive the sampling capacitor(s), e.g. the capacitor 16, through the filter resistor 14.

[0047] Fig. Figure 6 is an example of a schematic representation of the analog frontend system 31 of Fig. 2-4 in combination with an electrocardiogram (ECG) measuring circuit 60. The system 60 can include a gain circuit 62 with a first input 64 for receiving an analog input signal 24, the dynamic anti-aliasing filter circuit 30 (with a filter bypass switch), and an ADW circuit 26, e.g., a sigma-delta ADW or a SAR (successive approximation register) ADW, for receiving an output of the AAF filter circuit 30. In the example configuration shown, the gain circuit 62 can include an adder circuit 66 and a gain or buffer circuit 22, e.g., a capacitive gain amplifier (CGA).

[0048] The ADW 26 can generate a first digital output signal 68 corresponding to the analog input signal 24, e.g., an ECG output signal. As in Fig. As shown in Figure 6, the analog signal 70 from a digital-to-analog converter (DAW) circuit 72 can be applied to a second input 74 of the amplification circuit 62. The adder circuit 66 can subtract the analog output signal 70 from the DAW circuit 72 from the original analog input signal 24. It should be noted that the adder circuit 66 is shown for conceptual purposes, but in some configurations it forms part of the amplification or buffer circuit 22 itself. In some examples, the subtraction and amplification can be performed in a CGA, which can then be fed into a high-resolution ADW 26, such as a sigma-delta converter, for reasons of linearity.

[0049] A feedback loop 76 of Fig. 6 can include a frequency-selective filter circuit 78 for receiving the digital output signal 68 of the ADW circuit 26 and supplying an output signal 80 to a quantizer circuit 82, e.g., a digital sigma-delta modulator. In some example implementations, the frequency-selective filter circuit 78 can include an integrator circuit and / or a low-pass filter circuit.

[0050] As in Fig. As shown in Figure 6, the quantizer circuit 82 can output a quantized signal 84 to the DAW 72. In some example implementations, the DAW 72 can be a noise-shaped DAW circuit, e.g., a sigma-delta DAW. In some examples, the filter circuit output signal 80 can have an initial number of bits, e.g., 16 bits, and the quantized signal 84 can have a second number of bits smaller than the initial number of bits, e.g., 7 bits.

[0051] An AFE system output circuit 86 includes a recombination path 88, including, for example, a scaling circuit 90 and an adder circuit 92. The adder circuit 92 can combine a scaled version of the quantized signal 84 with the digital output signal 68 from the ADW 26 to generate an output signal 90, e.g., an ECG output signal. Together with the reconstruction of the input signal 24, this recombination can substantially eliminate the quantization noise of the quantizer circuit 82. Additional information regarding the recombination path 88 can be found in the applicant's own US patent application No. 15 / 621,621, entitled "QUANTIZATION NOISE CANCELTION IN A FEEDBACK LOOP," filed on June 13, 2017, in Kalb et al., the entire contents of which are hereby incorporated by reference. Various comments

[0052] Each of the non-restrictive aspects or examples described herein can stand on its own or can be combined with one or more of the other examples in various permutations or combinations.

[0053] The above detailed description contains references to the accompanying drawings, which form part of the detailed description. The drawings illustrate specific embodiments in which the invention can be practiced. These embodiments are also referred to herein as "aspects" or "examples." Such examples may include elements in addition to those shown or described. However, the inventors of the present invention also consider examples in which only those elements shown or described are provided.Furthermore, the inventors of the present invention also consider examples using any combination or permutation of those elements shown or described (or one or more aspects thereof), either relating to a particular example (or one or more aspects thereof) or relating to other examples (or one or more aspects thereof) shown or described herein.

[0054] In the event of inconsistencies in usage between this document and any documents incorporated by reference, the usage in this document shall prevail.

[0055] In this document, the expressions "one" are used, as is customary in patent documents, to include more than one, irrespective of any other instances or uses of "at least one" or "one or more". In this document, the expression "or" is used to refer to a non-exclusive "or", so that "A or B" includes "A but not B", "B but not A", and "A and B" unless otherwise specified. In this document, the expressions "with" and "in which" are used as plain English equivalents of the respective expressions "incorporating" and "whereby". Furthermore, in the following claims, the expressions "with" and "incorporating" are open, i.e.,A system, device, article, composition, formulation, or process that includes elements in addition to those listed in a claim according to such a term shall continue to be considered to fall within the scope of protection of that claim. Furthermore, in the following claims, the terms "first," "second," and "third," etc., are used merely as designations and are not intended to impose any numerical requirements on their objects.

[0056] The procedure examples described herein may be at least partially machine- or computer-implemented. Some examples may include a computer-readable or machine-readable medium encoded with instructions executable for configuring an electronic device to perform procedures as described in the examples above. An implementation of such procedures may include code, such as microcode, assembly language code, higher-level language code, or the like. Such code may contain computer-readable instructions for performing various procedures. The code may form sections of computer program products. Furthermore, in one example, the code may be physically stored on one or more volatile, non-temporary, or non-volatile physical computer-readable media, such as during execution or at other times.Examples of these physical, computer-readable media include hard drives, removable magnetic disks, removable optical disks (e.g., CDs and DVDs), magnetic cassettes, memory cards or sticks, random access memory (RAMs), read-only memory (ROMs), and the like.

[0057] The above description is intended to be illustrative and not restrictive. For example, the examples described above (or one or more aspects thereof) may be used in combination with one another. Other embodiments may be used, such as by a person skilled in the art reviewing the above description. The summary is presented to comply with 37 CFR §1.72(b) so that the reader can quickly ascertain the nature of the technical disclosure. It is presented with the understanding that it is not to be used to interpret or limit the scope or meaning of the claims. Furthermore, various features may be grouped together in the above detailed description to simplify the disclosure. This should not be interpreted as implying that any unclaimed disclosed feature is essential to any claim.Rather, the subject matter of the invention may consist of fewer than all features of a particular disclosed embodiment. Therefore, the following claims are hereby included in the detailed description as examples or embodiments, each claim constituting a separate embodiment in itself, and it is considered that such embodiments may be combined with one another in various combinations or permutations. The scope of protection of the invention should be determined with reference to the appended claims together with the full range of equivalents to which such claims are entitled.

Claims

[1] Analog front-end (AFE) system with an anti-aliasing filter circuit with a filter bypass switch configured to provide charge injection and / or clock pass-through independent of an input signal, wherein the AFE system comprises: at least one sampling capacitor of an analog-to-digital converter (ADC) circuit configured to sample an output of the anti-aliasing filter circuit; an amplification or buffer circuit with an input for receiving the input signal; and the anti-aliasing filter circuit coupled to an output of the amplification or buffer circuit, wherein the filter circuit comprises the following: a filter resistor; a filter capacitor coupled to one terminal of the filter resistor; and the filter bypass switch, which is connected in a bootstrapped configuration to pull a control terminal of the filter bypass switch above or below a supply voltage, wherein the filter bypass switch is connected in parallel to the filter resistor, wherein the filter bypass switch has an ON state and an OFF state, wherein, when in the ON state, the filter bypass switch is configured to bypass the filter resistance, allowing the amplification or buffer circuit to drive the at least one sampling capacitor through the filter bypass switch; and wherein, when in the OFF state, the filter bypass switch is designed to cause the amplification or buffer circuit to drive the at least one sampling capacitor through the filter resistor. [2] AFE system according to claim 1, wherein the filter bypass switch, which is switched in a bootstrapped configuration, comprises: the bypass switch comprising an input terminal configured to receive the input signal, an output terminal and the control terminal, and; at least one bootstrap capacitor; and several bootstrap switches that are trained to: When the filter bypass switch is in the OFF state, couple the at least one bootstrap capacitor to a supply voltage to charge the at least one bootstrap capacitor to the supply voltage, couple the control terminal of the bypass switch to the input terminal of the bypass switch, and decouple the at least one bootstrap capacitor from 1) the control terminal of the bypass switch and 2) the input terminal of the bypass switch. When the filter bypass switch is in the ON state, decouple the at least one bootstrap capacitor from the supply voltage and couple the at least one bootstrap capacitor to 1) the control terminal of the bypass switch and 2) the input terminal of the bypass switch to apply a combination of the supply voltage and a voltage of the input signal to the control terminal of the bypass switch. [3] AFE system according to claim 2, further comprising: a control circuit designed to manage switch configurations of multiple bootstrap switches. [4] AFE system according to a preceding claim, wherein the bypass switch is a single transistor. [5] AFE system according to a preceding claim, wherein the bypass switch is a single type of field-effect transistor (FET), which is only one of an N-FET or a P-FET. [6] AFE system according to claim 5, wherein the output terminal is a drain terminal, wherein the input terminal is a source terminal, wherein the control terminal is a gate terminal, and where the multiple bootstrap switches are configured for: When the filter bypass switch is in the OFF state, couple the at least one bootstrap capacitor to a supply voltage to charge the at least one bootstrap capacitor to the supply voltage, couple the gate terminal of the filter bypass switch to the source terminal of the bypass switch, and decouple the at least one bootstrap capacitor from 1) the gate terminal of the single bypass switch and 2) the source terminal of the single bypass switch. and When the filter bypass switch is in the ON state, the at least one bootstrap capacitor is decoupled from the supply voltage and the at least one bootstrap capacitor is coupled to 1) the gate terminal of the single bypass switch and 2) the source terminal of the single bypass switch to apply a combination of the supply voltage and a voltage of the input signal to the gate terminal of the single bypass switch. [7] AFE system according to a preceding claim, wherein the at least one sampling capacitor includes the filter capacitor. [8] AFE system according to a preceding claim in combination with an electrocardiogram (ECG) measuring circuit. [9] Method for operating an analog front-end (AFE) system with an anti-alias filter circuit having a filter bypass switch configured to provide charge injection and / or clock pass-through independent of an input signal, wherein the method comprises: Providing at least one sampling capacitor of an analog-to-digital converter (ADC) circuit configured to sample the output of the anti-aliasing filter circuit; Providing an amplification or buffer circuit with an input for receiving the input signal; and Coupling the anti-aliasing filter circuit to the output of the amplification or buffer circuit, wherein the anti-aliasing filter circuit comprises the following: a filter resistor; a filter capacitor coupled to one terminal of the filter resistor; and the filter bypass switch, which is connected in a bootstrapped configuration to pull a control terminal of the filter bypass switch above or below a supply voltage, wherein the filter bypass switch is connected in parallel to the filter resistor, wherein the filter bypass switch has an ON state and an OFF state, and wherein, when in the ON state, the input signal is received and the filter bypass switch is controlled to bypass the filter resistance, so that the amplification or buffer circuit can drive the at least one sampling capacitor through the filter bypass switch; and where, when in the OFF state, the input signal is received and the filter bypass switch is controlled to cause the amplification or buffer circuit to drive the at least one sampling capacitor through the filter resistor. [10] Method according to claim 9, wherein providing the anti-aliasing filter circuit with the filter bypass switch, in a bootstrapped configuration, includes the following: Providing the filter bypass switch with an input terminal configured to receive the input signal, an output terminal and the control terminal; Provide at least one bootstrap capacitor; and Providing multiple bootstrap switches, the procedure further comprising the following: When the filter bypass switch is in the OFF state, control the multiple bootstrap switches to couple the at least one bootstrap capacitor to a supply voltage to charge the at least one bootstrap capacitor to the supply voltage, couple the control terminal of the bypass switch to the input terminal of the bypass switch, and decouple the at least one bootstrap capacitor from 1) the control terminal of the bypass switch and 2) the input terminal of the bypass switch. When the filter bypass switch is in the ON state, control the multiple bootstrap switches to decouple the at least one bootstrap capacitor from the supply voltage and couple the at least one bootstrap capacitor to 1) the control terminal of the bypass switch and 2) the input terminal of the bypass switch to apply a combination of the supply voltage and a voltage of the input signal to the control terminal of the bypass switch. [11] Method according to claim 9 or 10, wherein providing the filter bypass switch includes providing a single transistor. [12] Method according to any one of claims 9 to 11, wherein providing the filter bypass switch includes providing a single type of field-effect transistor (FET), which is now an N-FET or a P-FET. [13] Method according to claim 12, wherein providing the filter bypass switch with an input terminal configured to receive the input signal, an output terminal and the control terminal comprises the following: Providing the filter bypass switch with a source terminal configured to receive the input signal, a drain terminal, and a gate terminal. [14] Method according to any one of claims 9 to 13, wherein the filter capacitor includes at least one sampling capacitor of the ADW circuit. [15] Electrocardiogram (ECG) measuring circuit, comprising: an analog front-end (AFE) system with an anti-aliasing filter circuit including a filter bypass switch configured to provide charge injection and / or clock pass-through independent of an input signal, wherein the AFE system comprises: at least one sampling capacitor of an analog-to-digital converter (ADC) circuit configured to sample the output of the anti-aliasing filter circuit; an amplification or buffer circuit with an input for receiving the input signal; and the anti-aliasing filter circuit coupled to the output of the amplification or buffer circuit, wherein the filter circuit comprises the following: a filter resistor; a filter capacitor coupled to one terminal of the filter resistor; and the filter bypass switch, which is connected in a bootstrapped configuration to pull a control terminal of the filter bypass switch above or below a supply voltage, wherein the filter bypass switch is connected in parallel to the filter resistor, wherein the filter bypass switch has an ON state and an OFF state, wherein, when in the ON state, the filter bypass switch is configured to bypass the filter resistance, allowing the amplification or buffer circuit to drive the at least one sampling capacitor through the filter bypass switch; and wherein, when in the OFF state, the filter bypass switch is designed to cause the amplification or buffer circuit to drive the at least one sampling capacitor through the filter resistor. [16] ECG measuring circuit according to claim 15, wherein the filter bypass switch, which is switched in a bootstrapped configuration, comprises the following: the bypass switch comprising an input terminal configured to receive the input signal, an output terminal and the control terminal, and; at least one bootstrap capacitor; and several bootstrap switches that are trained to: When the filter bypass switch is in the OFF state, couple the at least one bootstrap capacitor to a supply voltage to charge the at least one bootstrap capacitor to the supply voltage, couple the control terminal of the bypass switch to the input terminal of the bypass switch, and decouple the at least one bootstrap capacitor from 1) the control terminal of the bypass switch and 2) the input terminal of the bypass switch. When the filter bypass switch is in the ON state, the at least one bootstrap capacitor is decoupled from the supply voltage and the at least one bootstrap capacitor is coupled to 1) the control terminal of the bypass switch and 2) the input terminal of the bypass switch to apply a combined voltage from the supply voltage and a voltage from the input signal to the control terminal of the bypass switch. [17] ECG measuring circuit according to claim 15 or 16, wherein the bypass switch is a single transistor. [18] ECG measuring circuit according to one of claims 15 to 17, wherein the bypass switch is a single type of field-effect transistor (FET), which is only one of an N-FET or a P-FET. [19] ECG measuring circuit according to claim 18, wherein the output terminal is a drain terminal, the input terminal is a source terminal and the control terminal is a gate terminal. [20] ECG measuring circuit according to one of claims 15 to 19, wherein the at least one sampling capacitor includes the filter capacitor.

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