Semiconductor component comprising a semiconductor enclosed between two conductor frames and method for manufacturing the same

Abstract

A conductor frame (10) for flip-chip mounting of a semiconductor, which comprises a rectangular area divided into individual pads, wherein the individual pads comprise a first pad (11), a second pad (12) and a third pad (14), wherein the first pad (11) is larger than the second pad (12) and larger than the third pad (14), and the second pad (12) is arranged in a first corner region of the rectangular area and the third pad (14) is arranged in a second corner region of the rectangular area, the second corner region being arranged diagonally opposite the first corner region.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device and a method of manufacturing the same. BACKGROUND

[0002] Power semiconductor packages contain a power semiconductor die embedded in a molded compound. A major problem with semiconductor packages is the dissipation of excessive heat generated by the semiconductor die during operation. The heat generated by the power semiconductor die must be efficiently dissipated from the semiconductor package to the environment. In a leadless surface-mount semiconductor package, the heat can be dissipated via the underside of the circuit board. However, additional cooling of the top side is an important trend in semiconductor package manufacturing. In this case, a metallic contact connected to the semiconductor die is exposed to the outside so that a heat sink can be connected to the metallic contact.

[0003] However, surface-mounted semiconductor packages have the general disadvantage that in the case of mechanical stresses, e.g. due to different thermal expansion coefficients, no compensation mechanism can be provided due to the lack of flexibility of the metal contacts lying on the circuit board surface, which leads to a lack of board level reliability (BLR). SUMMARY

[0004] A first aspect of the present disclosure relates to a semiconductor device comprising a first lead frame including a first die pad and one or more first conductors formed integrally with the first die pad and extending outwardly from the first die pad in a first direction, a second lead frame including a second die pad and one or more second conductors formed integrally with the second die pad and extending outwardly from the second die pad in a second direction different from the first direction, a semiconductor die disposed between the first die pad and the second die pad, and an encapsulant embedding the semiconductor dies, wherein the first conductors and the second conductors are disposed outside the encapsulant.

[0005] Due to the fact that the first and second conductors are arranged outside the encapsulation after the semiconductor devices are mounted on a printed circuit board, the conductors are more flexible to absorb any type of mechanical stress between the semiconductor device and the printed circuit board, which can increase board-level reliability.

[0006] According to one embodiment of the semiconductor device of the first aspect, the second die pad of the second lead frame is at least partially exposed to the outside, so that a heat sink can be mounted on a surface of the second die pad remote from the semiconductor device. The heat sink can be mounted either during the manufacturing process of the semiconductor device or by the customer. In particular, the second die pad can be completely exposed to the outside. Otherwise, it can be partially exposed, and the encapsulation is exposed to the outside in the remaining part.

[0007] According to an embodiment of the semiconductor device of the first aspect, the first die pad is arranged in a first level, and the second die pad is arranged in a second level, and the first conductors extend outside the encapsulation from the first level to a third level, and the second conductors extend outside the encapsulation from the second level to the third level.

[0008] According to one embodiment of the semiconductor device of the first aspect, the encapsulation comprises a lower surface facing the circuit board after mounting the semiconductor device on a circuit board. In some embodiments, this lower surface may be located in the third level, so that the encapsulation is in contact with the surface of the circuit board after mounting the semiconductor device on a circuit board, thereby enabling heat dissipation through the circuit board during operation of the semiconductor device. Otherwise, the lower surface of the encapsulation may be arranged above the third level, in which case cooling of the underside is not possible.

[0009] According to one embodiment of the semiconductor device of the first aspect, the first conductors are angled from the first die pad by a first angle, and the second conductors are angled from the second die pad by a second angle. According to another example, the second angle is different from the first angle. According to another example, neither of the first and second angles is zero.

[0010] According to one embodiment of the semiconductor device of the first aspect, the semiconductor die is a semiconductor transistor die. In particular, the semiconductor die can be one or more of a vertical semiconductor transistor die, a power IGBT die, an IGBT die, a MOSFET die, a CoolMOS die, a wide bandgap semiconductor transistor die, in particular a SiC transistor die.

[0011] According to one embodiment of the semiconductor device of the first aspect, the semiconductor transistor comprises a first main surface and a second main surface opposite the first main surface, as well as a source pad arranged on the first main surface and a drain pad arranged on the second main surface. According to one embodiment, the drain pad is connected to the first lead frame, and the source pad is connected to the second lead frame. According to a further embodiment, the semiconductor device further comprises a gate pad arranged on the first main surface and possibly also a source / sense pad, which is also arranged on the first main surface.

[0012] A second aspect of the present disclosure relates to a method for manufacturing a semiconductor device, the method comprising the following steps: providing a first lead frame, providing a semiconductor die having a first main surface and a second main surface opposite the first main surface, connecting a first main surface of the semiconductor die to a first portion of the first lead frame, connecting a first main surface of the semiconductor die to a first portion of the first lead frame, providing a second lead frame, connecting a first portion of the second lead frame to the second main surface of the semiconductor die, applying an encapsulation to the semiconductor die and to the first portions of the first and second lead frames such that second portions of the first and second lead frames are arranged outside the encapsulation.

[0013] When the method is performed as described above, the first portions of the first and second lead frames become die pads and the second portions of the first and second lead frames become leads of the semiconductor device according to the first aspect.

[0014] The method according to the second aspect can be carried out in different ways with regard to the order of the method steps. What all embodiments have in common is that the semiconductor component to be manufactured has first sections of the lead frames that serve as die pads, and second sections that are angled away from the first sections and serve as leads. A very practical manufacturing method is for a lead frame supplier to pre-bend the lead frames and then send the pre-bent lead frames to a customer for assembly of semiconductor packages. In general, the method can be carried out such that the second sections are partially or completely bent out of the first sections when the lead frames are initially provided. Finally, the method can be carried out such that the second sections are completely bent away from the first sections after the encapsulation has been applied.

[0015] According to one embodiment of the method of the second aspect, the second sections of the first leadframe are bent by a first angle, and the second sections of the second leadframe are bent by a second angle. According to a further embodiment, the second angle is different from the first angle.

[0016] According to an embodiment of the method of the second aspect, the method is performed such that a surface of the first portion of the second lead frame, which is remote from the semiconductor die, is exposed to the outside.

[0017] According to an embodiment of the method of the second aspect, two semiconductor devices are manufactured in parallel by connecting two semiconductor devices to the first lead frame, providing two second lead frames, connecting each of the two second lead frames to one of the semiconductor devices, applying two encapsulations to each of the semiconductor devices and to first portions of the first and second lead frames, and singulating two separate semiconductor devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings are provided to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and, together with the description, serve to explain the principles of the embodiments. Other embodiments and many of the intended advantages of the embodiments will be readily appreciated as they become better understood by reference to the following detailed description.

[0019] The elements in the drawings are not necessarily to scale. Like reference numbers indicate like or similar elements. Fig. 1 shows a cross-sectional view of an example of a semiconductor device according to the first aspect. Fig. 2 includes the Fig. 2A to 2C and shows cross-sectional views of other examples of semiconductor devices according to the first aspect. Fig. 3 includes the Fig. 3A to 3C and shows cross-sectional views illustrating a method for producing the Fig. 1 shown example of a semiconductor device. Fig. 4 includes the Fig. 4A to 4C and shows cross-sectional views for illustrating a method of manufacturing another example of a semiconductor device. Fig. 5 includes the Fig. 5A to 5E and shows cross-sectional views illustrating a method for manufacturing two or more semiconductor devices in a parallel process. DESCRIPTION OF THE EMBODIMENTS

[0020] In the following detailed description, reference is made to the accompanying drawings, which form a part of this document, and in which is shown by way of illustration certain embodiments in which the disclosure may be practiced. In this context, directional terms such as "top," "bottom," "front," "back," etc., are used with reference to the orientation of the described figure(s). Since the components of the embodiments can be positioned in a number of different orientations, the directional terminology is for the purpose of illustration and is not limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure.The following detailed description is therefore not to be taken in a limiting sense, and the scope of the present disclosure is defined by the appended claims.

[0021] It is understood that the features of the various exemplary embodiments described herein may be combined with one another unless expressly stated otherwise.

[0022] As used in this description, the terms "connected," "attached," "coupled," and / or "electrically connected / electrically coupled" are not intended to imply that the elements or layers must be in direct contact with one another; intermediate elements or layers may be provided between the "connected," "attached," "coupled," and / or "electrically connected / electrically coupled" elements. However, according to the disclosure, the above terms may also have the specific meaning that the elements or layers are in direct contact with one another, i.e., that no intermediate elements or layers are provided between the "connected," "attached," "coupled," and / or "electrically connected / electrically coupled" elements.

[0023] Furthermore, the word "over," used in reference to a part, element, or layer of material formed or disposed "over" a surface, may be used herein to mean that the part, element, or layer of material is disposed (e.g., placed, formed, deposited, etc.) "indirectly upon" the implied surface, with one or more additional parts, elements, or layers disposed between the implied surface and the part, element, or layer of material. However, the word "over," used in reference to a part, element, or layer of material formed or disposed "over" a surface, may optionally also have the specific meaning that the part, element, or layer of material is disposed (e.g., placed, formed, deposited, etc.) "directly," that is, in direct contact with the implied surface. DETAILED DESCRIPTION

[0024] Fig. 1 shows a cross-sectional view of an example of a semiconductor device device according to the first aspect.

[0025] In particular, Fig. 1 shows a semiconductor device 10 having a first lead frame 11 with a first die pad 11A and one or more first conductors 11B formed integrally with the first die pad 11A and extending outwardly from the first die pad 11A in a first direction, a second lead frame 12 with a second die pad 12A and one or more second conductors 12B formed integrally with the second die pad 12A and extending outwardly from the second die pad 12A in a second direction different from the first direction, a semiconductor die 13 arranged between the first die pad 11A and the second die pad 12A, and an encapsulation 14 embedding the semiconductor dies 13, wherein the first conductors 11B and the second conductors 12B are arranged substantially or for the most part outside the encapsulation 14.

[0026] The semiconductor die 13 may be connected with its upper main surface to the first die pad 11A via a first conductive layer 15, and the semiconductor die 13 may be connected with its lower main surface to the upper main surface of the second die pad 12A via a second conductive layer 16. The first and second conductive layers 15 and 16 may, for example, consist of soldered or sintered layers.

[0027] The first conductors 11B and the second conductors 12B both have end attachment elements 11B.1 and 12B.1, which have horizontal bottom surfaces lying in a common horizontal plane PP and with whose bottom surfaces the semiconductor component 10 can be attached to a substrate such as a printed circuit board. Generally, various types of conductors can be used, such as gull-wing type, J-conductor type, C-conductor type, or through-hole type.

[0028] As in the example of a semiconductor device 10 of Fig. 1, the encapsulation 14 may include a lower horizontal surface 14A and sloped side walls 14B disposed between the first die pad 11A and the lower horizontal surface 14A. As shown in Fig. 1, the lower horizontal surface 14A of the encapsulation 14 is located above the horizontal plane PP. Other embodiments are presented below in which the lower horizontal plane of the encapsulation is arranged coplanar with the horizontal plane PP.

[0029] If the semiconductor components 10 in the Fig. 1 are mounted on a substrate, e.g. a printed circuit board, the semiconductor component 10 therefore only comes into contact with the printed circuit board via its first and second conductors 11B and 12B, but not with the encapsulation 14. In the example shown, heat dissipation occurs mainly via the top side and only via the conductors to the bottom side.

[0030] As will be shown later, the first conductors 11B and the second conductors 12B can be formed by bending first corresponding portions from the first die pad 11A and second corresponding portions from the second die pad 12A. As shown in Fig. 1, there is a first angle α between the first conductors 11B and the first die pad 11A and a second angle β between the second conductors 11B and the second die pad 11A.

[0031] The Fig. The example shown in Figure 1 is further characterized in that the first pad 11A is fully exposed to the outside. As other examples will show, it is also possible for the first pad to be only partially exposed to the outside. In any case, this offers the possibility of attaching an external heat sink to enable cooling of the top surface during operation. The first conductors 11B are angled from the first die pad 11A at a first angle, and the second conductors 12B are angled from the second die pad 12A at a second angle.

[0032] Furthermore, the semiconductor die 13 may be a semiconductor transistor die 13 and in particular one or more of a vertical semiconductor transistor die, a power IGBT die, an IGBT die, a MOSFET die, a CoolMOS die and a wide-gap semiconductor transistor die, in particular a SiC transistor die.

[0033] More specifically, the semiconductor transistor 13 may comprise a first main surface and a second main surface opposite the first main surface, as well as a source pad arranged on the first main surface and a drain pad arranged on the second main surface, and possibly also a gate pad and a source / sense pad, both arranged on the first main surface.

[0034] The encapsulation 14 may comprise a conventional mold compound, such as a resin material, in particular an epoxy resin material. Furthermore, the encapsulation 14 may comprise a thermally conductive material to enable efficient heat dissipation to external heat sinks. The material of the encapsulation 14 may, in particular, comprise a resin such as an epoxy resin material filled with particles such as SiO or other ceramic particles or thermally conductive particles such as Al2O3, BN, AlN, Si3N4, diamond, or other thermally conductive particles.

[0035] Fig. 2 includes the Fig. 2A to 2C and shows cross-sectional views of other examples of semiconductor devices according to the first aspect.

[0036] Fig. 2A shows an example of a semiconductor device 20 including a first lead frame 21 having a first die pad 21A and one or more first conductors 21B formed integrally with the first die pad 21A and extending outwardly from the first die pad 21A in a first direction, a second lead frame 22 having a second die pad 22A and one or more second conductors 22B formed integrally with the second die pad 22A and extending outwardly from the second die pad 22A in a second direction different from the first direction, a semiconductor die 23 disposed between the first die pad 21A and the second die pad 22A, and an encapsulant 24 embedding the semiconductor die 23, wherein the first conductors 21B and the second conductors 22B are substantially or mostly disposed outside the encapsulant 24.

[0037] In contrast to the Fig. 1, a lower main surface 24A of the encapsulation 24 is coplanar with the plane PP (see Fig. 1) and thus with the lower main surfaces of the end attachment elements 21B.1 and 22B.1 of the first and second conductors 21B and 22B. A further difference is that the first die pad 21A is connected to an extended metallic terminal 21A.1 arranged on the encapsulation 24. In a further embodiment, 21A and 21A.1 can consist of a single piece of metal. Due to the process, it can happen that after encapsulation, a surface area of ​​the encapsulation material is exposed to the outside laterally next to the first pad 21A. If this is not desired, this surface area can be subsequently removed and replaced by the metallic terminal 21A.1, which can be deposited, for example, by electroplating.

[0038] In the Fig. During operation, both cooling from below and cooling from above for heat dissipation are possible for the semiconductor component 20 shown in Figure 2A.

[0039] Fig. 2B shows an example of a semiconductor device 30 including a first lead frame 31 having a first die pad 31A and one or more first conductors 31B formed integrally with the first die pad 31A and extending outwardly from the first die pad 31A in a first direction, a second lead frame 32 having a second die pad 32A and one or more second conductors 32B formed integrally with the second die pad 32A and extending outwardly from the second die pad 32A in a second direction different from the first direction, a semiconductor die 33 disposed between the first die pad 31A and the second die pad 32A, and an encapsulant 34 embedding the semiconductor die 33, wherein the first conductors 31B and the second conductors 32B are substantially or mostly disposed outside the encapsulant 34.

[0040] In contrast to the Fig. 1, a lower main surface of the encapsulation 34 is coplanar with the plane PP (see Fig. 1) and thus with the lower major surfaces of the end attachment elements 31B.1 and 32B.1 of the first and second conductors 31B and 32B. Another difference is that a portion of the surface of the encapsulant 34 faces outward laterally adjacent to the first pad 31A. Another difference is that a portion of the die pad 31A has a greater thickness than the conductors 31B. This portion of the die pad 31A completely covers the semiconductor dies 33. The first lead frame 31 can therefore comprise a lead frame with two thicknesses.

[0041] Generally, lead frames can consist of a single lead frame with a relatively thin thickness or two lead frames with a relatively thick thickness. In this case, the first and second lead frames can be one-dimensional lead frames with the same thin thickness or two-dimensional lead frames with the same thick thickness. Otherwise, the first and second lead frames have different thicknesses, in particular, one of them is a single-gauge lead frame and the other is a dual-gauge lead frame.

[0042] In the Fig. In the semiconductor component 30 shown in Figure 2B, both downward cooling and top cooling for heat dissipation are possible during operation, with the downward cooling also taking place via the encapsulation and not only via the conductors.

[0043] Fig. 2C shows an example of a semiconductor device 40 including a first lead frame 41 having a first die pad 41A and one or more first leads 41B formed integrally with the first die pad 41A and extending outwardly from the first die pad 41A in a first direction, a second lead frame 42 having a second die pad 42A and one or more second leads 42B formed integrally with the second die pad 42A and extending outwardly from the second die pad 42A in a second direction different from the first direction, a semiconductor die 43 disposed between the first die pad 41A and the second die pad 42A, and an encapsulant 44 embedding the semiconductor die 43, wherein the first leads 41B and the second leads 42B are substantially or mostly disposed outside the encapsulant 44.

[0044] In contrast to the Fig. 1, a lower main surface of the encapsulation 44 is coplanar with the plane PP (see Fig. 1) and thus with the lower major surfaces of the end attachment elements 41B.1 and 42B.1 of the first and second conductors 41B and 42B. Another difference is that a surface area of ​​the encapsulation 44 is exposed to the outside laterally adjacent to the first pad 41A. As a further difference, the first die pad 41A and the first conductors 41B have a greater thickness over their entire length than the second die pad 42A and the second conductors 42B.

[0045] In the Fig. During operation, both cooling from below and cooling from above for heat dissipation are possible for the semiconductor component 40 shown in Figure 2C.

[0046] Fig. 3 includes the Fig. 3A to 3C and shows cross-sectional views illustrating a method for producing the Fig. 1 shown example of the semiconductor components.

[0047] Fig. 3A shows the provision of a first lead frame 11 in the form of a flat sheet made of a Cu metal. A semiconductor die 13 has a first main surface and a second main surface opposite the first main surface and is connected by its first main surface to a first portion of an upper side of the first lead frame by means of a first conductive layer 15. A second lead frame 12 is provided, which also has the form of a flat sheet made of a Cu metal. The second lead frame 12 is connected by a first portion to the second main surface of the semiconductor die 13 via a second conductive layer 16. The first and second conductive layers 15 and 16 can be soldered or sintered layers 16.

[0048] Fig. 3B shows the application of an encapsulant 14 to the semiconductor die 13 and to the first portions of the first and second lead frames 11 and 12. As already mentioned, the encapsulant 14 may be made of a conventional molding compound, such as a resin material, in particular an epoxy resin material, possibly filled with thermally conductive particles. The encapsulant 14 is applied such that it only embeds the semiconductor die 13 and first portions of the first and second lead frames 11 and 12, leaving second portions exposed. The encapsulant 14 may be applied by transfer molding or compression molding.

[0049] Fig. 3C shows the bending of the second sections 11B and 12B of the first and second lead frames 11 and 12 such that the outer ends of the second sections 11B and 12B lie in a plane parallel to the first sections 11A and 12A of the first and second lead frames 11 and 12. In this way, the first sections 11A and 12A of the lead frames 11 and 12 become the die pads 11A and 12A, and the second sections 11B and 12B become the leads 11B and 12B. The end fastening elements 11B.1 and 12B.1 can be formed by correspondingly bending the end sections of the first and second leads 21B. As already mentioned, the bending, as in Fig. 3C, can also be performed before forming. It is also possible for only one of the conductors 11B or 12B to be bent, then the forming is performed, and then the other of the conductors 11B or 12B is bent.

[0050] Fig. 4 includes the Fig. 4A to 4C and shows cross-sectional views for illustrating a method of manufacturing another example of a semiconductor device.

[0051] Fig. 4A is similar to Fig. 3A, so not all details are repeated here. One difference to Fig. 3A is that the second lead frame 12 is provided from the outset to include a die pad 12A and one or more leads 12B bent from the die pad 12A.

[0052] Fig. 4B shows the application of an encapsulation 24 to the semiconductor die 13 and to the first sections of the first and second lead frames 11 and 12. The encapsulation 24 may have the same or similar properties as the encapsulation 14 of Fig. 3. The difference from encapsulation 14 is that encapsulation 24 is applied such that it includes an additional section 24.1 on one side of semiconductor die 13. This additional area provides a more robust encapsulation and possibly also increased high-voltage withstand capacity, i.e., greater resistance of the semiconductor component to high electrical voltages. The device produced in this way is therefore particularly suitable for high-voltage applications.

[0053] Fig. 4C shows the bending of the second sections 11B from the first section 11A, so that now the first section 11A can be referred to as die pad 11A and the second sections 11B as leads 11B of the second lead frame 11.

[0054] Fig. 5 includes the Fig. 5A to 5E and shows cross-sectional views illustrating a method for manufacturing two or more semiconductor devices in a parallel process.

[0055] Fig. 5A shows the provision of a first leadframe 51 comprising two opposing regions 51.1 and 51.2 and a region 51.3 designed so that the two regions 51.1 and 51.2 can be easily separated from each other in a later step. Region 51.3 essentially comprises a number of connecting bridges between regions 51.1 and 51.2, which are intended to serve as conductors for the semiconductor devices to be manufactured after they have been cut in the final process step.

[0056] Fig. 5B shows the connection of two semiconductor dies 53.1 and 53.2 to the two regions 51.1 and 51.2 of the first lead frame 51.

[0057] Fig. 5C shows the connection of the two second lead frames 52.1 and 52.2 to the top surfaces of the two semiconductor dies 53.1 and 53.2.

[0058] Fig. Figure 5D shows the application of encapsulations to the two semiconductor dies 53.1 and 53.2 and sections of the two lead frames 52.1 and 52.2. After cutting the connecting bridges of region 51.3, two semiconductor components are obtained.

[0059] Fig. Figure 5E shows another solution where even four semiconductor devices can be obtained. Here, two assemblies are used, as in Fig. 5C, arranged side by side, and one encapsulation is applied to each of the two upper and lower regions of the combination assembly. Four semiconductor components can then be obtained by singulation. EXAMPLES

[0060] Specific examples of the present disclosure are described below.

[0061] Example 1 is a semiconductor device including a first lead frame having a first die pad and one or more first leads formed integrally with the first die pad and extending outwardly from the first die pad in a first direction, a second lead frame having a second die pad and one or more second leads formed integrally with the second die pad and extending outwardly from the second die pad in a second direction different from the first direction, a semiconductor die disposed between the first die pad and the second die pad, and an encapsulant embedding the semiconductor die, wherein the first leads and the second leads are disposed outside the encapsulant.

[0062] Example 2 is the semiconductor device according to Example 1, wherein the first die pad is arranged on a first level and the second die pad is arranged on a second level, and the first conductors extend outside the encapsulation from the first level to a third level, and the second conductors extend outside the encapsulation from the second level to the third level.

[0063] Example 3 is the semiconductor device according to example 1 or 2, wherein the first die pad of the first lead frame is at least partially exposed at the top side of the package.

[0064] Example 4 is the semiconductor device according to any one of the preceding examples, wherein the semiconductor die is a vertical semiconductor transistor die, in particular a semiconductor power transistor die, an IGBT die, a MOSFET die, a CoolMOS die, a wide bandgap semiconductor transistor die, in particular a SiC transistor die.

[0065] Example 5 is the semiconductor device according to Example 4, wherein the semiconductor transistor comprises a first main surface and a second main surface opposite to the first main surface, and a source pad arranged on the first main surface and a drain pad arranged on the second main surface.

[0066] Example 6 is the semiconductor device according to Example 5, wherein the drain pad is connected to the first die pad of the lead frame and the source pad is connected to the second die pad of the second lead frame.

[0067] Example 7 is the semiconductor device according to example 5 or 6, further comprising a gate pad arranged on the first main surface.

[0068] Example 8 is the semiconductor device according to any one of the preceding examples, wherein the device is a leaded package, in particular a gull-wing package, a J-lead package, a C-lead package or a through-hole package.

[0069] Example 9 is a method of manufacturing a semiconductor device, the method comprising the steps of: providing a first lead frame, providing a semiconductor die having a first main surface and a second main surface opposite the first main surface, connecting a first main surface of the semiconductor die to a first portion of the first lead frame, connecting a first main surface of the semiconductor die to a first portion of the first lead frame, providing a second lead frame, connecting a first portion of the second lead frame to the second main surface of the semiconductor die, applying an encapsulation to the semiconductor die and to the first portions of the first and second lead frames such that second portions of the first and second lead frames are arranged outside the encapsulation.

[0070] Example 10 is the method according to Example 9, wherein after applying the encapsulation, at least a part of the second sections of the first and second lead frames is bent such that the outer ends of the second sections lie in a plane that is parallel to the first sections of the first and second lead frames, or the first and second lead frames or both are provided in the form of pre-bent lead frames.

[0071] Example 11 is the method of Example 10, wherein the second portions of the first lead frame are bent by a first angle and the second portions of the second lead frame are bent by a second angle.

[0072] Example 12 is the method of any one of Examples 9 to 11, wherein the method is performed such that a surface of the first portion of the first lead frame removed from the semiconductor die is exposed at the top surface of the package.

[0073] Example 13 is the method according to any one of Examples 9 to 12, wherein at least two semiconductor devices are manufactured in parallel by connecting two semiconductor dies to the first lead frame, providing two second lead frames, connecting each of the two second lead frames to one of the semiconductor dies, applying two encapsulants to each of the semiconductor dies and to first portions of the first and second lead frames, and singulating into two separate semiconductor devices.

[0074] Furthermore, while a particular feature or aspect of an embodiment of the disclosure may have been disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects of the other implementations as may be desired and advantageous for a given or particular application. Wherever the terms "comprising," "having," "with," or other variations thereof are used in the detailed description or claims, these terms are intended to be comprehensive in a manner similar to the term "comprising." Furthermore, it is to be understood that embodiments of the disclosure may be implemented in discrete circuits, partially integrated circuits, or fully integrated circuits or programming means.The term "exemplary" is also to be understood as an example only, not as the best or optimal. Please also note that the features and / or elements depicted herein are shown with specific dimensions relative to each other for simplicity and clarity, and that actual dimensions may vary significantly from those depicted.

[0075] Although specific embodiments have been illustrated and described herein, those skilled in the art will recognize that the specific embodiments illustrated and described may be replaced with a variety of alternative and / or equivalent implementations without affecting the scope of the present disclosure. This application is intended to cover all adaptations or variations of the embodiments described herein. Therefore, this disclosure is to be limited only by the claims and their equivalents.

Claims

[1] Semiconductor component (10) comprising - a first lead frame (11) having a first die pad (11A) and one or more first leads (11B) formed integrally with the first die pad (11A) and extending outwardly from the first die pad (11A) in a first direction; - a second lead frame (12) having a second die pad (12A) and one or more second leads (12B) formed integrally with the second die pad (12A) and extending outwardly from the second die pad (12A) in a second direction different from the first direction; - a semiconductor die (13) arranged between the first die pad (11A) and the second die pad (12A); and - an encapsulation (14) embedding the semiconductor die (13), wherein the first conductors (11B) and the second conductors (12B) are arranged outside the encapsulation (14). [2] The semiconductor device (10) of claim 1, wherein the first die pad (11A) is arranged on a first level and the second die pad (12A) is arranged on a second level, and the first conductors (11B) extend outside the encapsulation (14) from the first level to a third level, and the second conductors (12B) extend outside the encapsulation (14) from the second level to the third level. [3] Semiconductor device (10) according to claim 1 or 2, wherein the first die pad (11A) of the first lead frame (11) is at least partially exposed at the top of the package. [4] Semiconductor component (10) according to one of the preceding claims, wherein the semiconductor die (13) is a vertical semiconductor transistor die, in particular a power IGBT die, a MOSFET die, a CoolMOS die, a wide bandgap semiconductor transistor die, in particular a SiC transistor die. [5] Semiconductor device (10) according to claim 4, wherein the semiconductor transistor (13) has a first main surface and a second main surface opposite the first main surface, and a source pad arranged on the first main surface and a drain pad arranged on the second main surface. [6] The semiconductor device (10) of claim 5, wherein the drain pad is connected to the first die pad (11A) of the lead frame (11) and the source pad is connected to the second die pad (12A) of the second lead frame (12). [7] The semiconductor device (10) of claim 5 or 6, further comprising a gate pad disposed on the first main surface. [8] Semiconductor component according to one of the preceding claims, wherein the device is a leaded package, in particular a gull-wing package, a J-lead package, a C-lead package or a through-hole package. [9] A method of manufacturing a semiconductor device, the method comprising - providing a first lead frame (11); - Providing a semiconductor die (13) having a first main surface and a second main surface opposite the first main surface; - connecting a first main surface of the semiconductor die (13) to a first portion of the first lead frame (11); - providing a second lead frame (12); - connecting a first portion of the second lead frame (12) to the second main surface of the semiconductor die (13); - applying an encapsulation (14; 24) to the semiconductor die (13) and to the first sections of the first and second lead frames (11, 12) such that second sections of the first and second lead frames (11, 12) are arranged outside the encapsulation (14; 24). [10] The method of claim 9, further comprising, after applying the encapsulation (14; 24), bending at least a portion of the second portions of the first and second lead frames (11, 12) such that the outer ends of the second portions lie in a plane parallel to the first portions of the first and second lead frames, or providing one or both of the first and second lead frames in the form of pre-bent lead frames. [11] The method of claim 10, wherein the second portions of the first lead frame are bent by a first angle and the second portions of the second lead frame are bent by a second angle. [12] The method of any one of claims 9 to 11, wherein the method is performed such that a surface of the first portion of the first lead frame (11) removed from the semiconductor die (13) is exposed at the top surface of the package. [13] Method according to one of claims 9 to 12, wherein at least two semiconductor components are manufactured in parallel by - Connecting two semiconductor dies to the first lead frame; - Providing two second lead frames; - Connecting each of the two second lead frames to one of the semiconductor dies; - applying two encapsulations to each of the semiconductor dies and to first portions of the first and second lead frames; and - Separation into two separate semiconductor components.

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