Semiconductor package structure

Abstract

Semiconductor package structure (200) comprising: a capacitor substrate (106) with a first surface (107A) and a second surface (107B) opposite the first surface and comprising: a first redistribution structure (108) arranged on the first surface (107A); a second redistribution structure (118) arranged on the second surface (107B); a via (112) electrically connecting the first redistribution structure (108) to the second redistribution structure (118); and a first capacitor structure (116) arranged between the first redistribution structure (108) and the second redistribution structure (118) and electrically connected to the second redistribution structure (118); a first semiconductor die (126A) arranged above the capacitor substrate (106) and electrically connected to the first capacitor structure (116) via the second redistribution structure (118);an interconnect structure (135) arranged beneath the capacitor substrate (106) and electrically connecting the capacitor substrate (106) to a second semiconductor die (146); a second capacitor structure (202) beneath the capacitor substrate (106) and laterally adjacent to the interconnect structure (135); and a molding material (140) surrounding the second capacitor structure (102) and the interconnect structure (135).

Description

BACKGROUND OF THE INVENTION Field of invention The present invention relates to semiconductor technology and in particular to a semiconductor package structure comprising a capacitor structure. Description of the state of the art A semiconductor packaging structure can not only protect a semiconductor die from environmental contaminants, but can also provide an electrical connection between the semiconductor die packaged within it and a substrate, such as a printed circuit board (PCB). Although existing semiconductor package structures have generally met the requirements, they have not been satisfactory in every respect. For example, high power supply leads to heat loss, and a current ramp is required for high-performance computing. Therefore, further improvements to semiconductor package structures are needed. US 2018 / 0190580A1 describes a bonded structure. The bonded structure includes an element and a passive electronic component bonded to the element. US 2021 / 0225809A1 describes a semiconductor package with a memory stack connected to a logic device. BRIEF SUMMARY OF THE INVENTION Semiconductor package structures are provided. An exemplary embodiment of a semiconductor package structure comprises a capacitor substrate and a first semiconductor die. The capacitor substrate has a first surface and a second surface opposite the first surface and includes a first redistribution structure, a second redistribution structure, a via, and a first capacitor structure. The first redistribution structure is located on the first surface. The second redistribution structure is located on the second surface. The via electrically connects the first redistribution structure to the second redistribution structure. The first capacitor structure is located between the first redistribution structure and the second redistribution structure and is electrically connected to the second redistribution structure.The first semiconductor die is arranged above the capacitor substrate and electrically connected to the first capacitor structure via the second redistribution structure. Another embodiment of a semiconductor package structure comprises a substrate, a first capacitor structure, a capacitor substrate, and a first semiconductor die. The first capacitor structure is arranged above the substrate. The capacitor substrate is arranged above the first capacitor structure and electrically connected to it. The capacitor substrate comprises a semiconductor layer, a second capacitor structure, a redistribution structure, and a first via. The second capacitor structure is embedded in the semiconductor layer. The redistribution structure is arranged above the semiconductor layer and electrically connected to the second capacitor structure. The first via extends through the semiconductor layer. The first semiconductor die is arranged above the capacitor substrate and electrically connected to the second capacitor structure. Another embodiment of a semiconductor package structure comprises an interposer, a capacitor substrate, and a first semiconductor die. The interposer includes a first deep-trench capacitor. The capacitor substrate is positioned above the interposer and includes a second deep-trench capacitor, a redistribution structure, and a first via. The redistribution structure is positioned above the second deep-trench capacitor and is electrically connected to it. The first via is adjacent to the second deep-trench capacitor and is electrically connected to the redistribution structure. The first semiconductor die is positioned above the capacitor substrate and is electrically connected to both the first and second deep-trench capacitors. BRIEF DESCRIPTION OF THE DRAWINGS The present invention may be better understood by reading the following detailed description and examples with reference to the accompanying drawings, in which: Fig. 1 is a cross-sectional view of an exemplary semiconductor package structure according to some embodiments of the present disclosure; Fig. 2 is a cross-sectional view of an exemplary semiconductor package structure according to some embodiments of the present disclosure; Fig. 3 is a cross-sectional view of part of an exemplary semiconductor package structure according to some embodiments of the present disclosure; and Fig. 4 is a cross-sectional view of an exemplary semiconductor package structure according to some embodiments of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION The following description serves to explain the general principles of the invention. The scope of the invention is best determined by reference to the accompanying claims. The present disclosure is described with respect to certain embodiments and with respect to certain drawings. The described drawings are only schematic and are not restrictive. In the drawings, the size of some elements may be exaggerated for descriptive purposes and need not be shown to scale. The dimensions and relative dimensions do not correspond to the actual dimensions in the embodiment of the disclosure. Additional elements can be added based on the embodiments described below. For example, the description "a first element over a second element" can cover embodiments in which the first element is in direct contact with the second element, and can also cover embodiments in which additional elements are arranged between the first element and the second element, so that the first element and the second element are not in direct contact. Furthermore, the description of "a first element extending through a second element" can cover embodiments in which the first element is arranged within the second element and extends from one side of the second element to an opposite side of the second element, wherein a surface of the first element may be substantially at the same level as a surface of the second element, or a surface of the first element may lie outside a surface of the second element. The spatially relative descriptions of the first and second elements may change when the structure is operated or used in different orientations. Furthermore, the present disclosure may repeat reference numerals and / or letters in the various embodiments. This repetition serves for simplicity and clarity and does not in itself imply any relationship between the different described embodiments. According to some embodiments of the present disclosure, a semiconductor package structure with a capacitor substrate is described. The capacitor substrate has one or more capacitor structures that provide it with capacitance, so that the requirements for high supply power and a high current ramp can be met. Fig. 1 is a cross-sectional view of a semiconductor package structure 100 according to some embodiments of the present disclosure. Additional elements can be added to the semiconductor package structure 100. Some of the elements described below can be substituted or omitted for different embodiments. To simplify the illustration, only a portion of the semiconductor package structure 100 is shown. As shown in Fig. 1, the semiconductor structure 100, according to some embodiments, includes a substrate 102. The substrate 102 can be a coreless substrate or a cored substrate to prevent deformation of the substrate 102. The substrate 102 can include a wiring structure (not shown) therein. In some embodiments, the wiring structure includes conductive pads, conductive vias, conductor tracks, conductive pillars, the like, or a combination thereof. The wiring structure can be formed from conductive materials, including metals (e.g., tungsten, titanium, tantalum, ruthenium, cobalt, copper, aluminum, platinum, tin, silver, gold), metal compounds (e.g., tantalum nitride, titanium nitride, tungsten nitride), the like, an alloy thereof, or a combination thereof. The wiring structure can be arranged in dielectric layers. These dielectric layers can also be referred to as intermetal dielectric (IMD) layers. In some embodiments, the IMD layers can be formed from organic materials such as polymer-based materials, inorganic materials such as silicon nitride, silicon oxide, silicon oxynitride, or the like, or a combination thereof. It should be noted that the configuration of substrate 102 shown in the figures is only exemplary and is not intended to limit the present disclosure. Any desired semiconductor element can be formed in and on the substrate 102. However, for the sake of simplicity, only the flat substrate 102 is shown. According to some embodiments, the semiconductor package structure 100 comprises a capacitor substrate 106 arranged above the substrate 102 and electrically connected to the wiring structure of the substrate 102 via several conductive structures 104. The conductive structures 104 may include microbumps, flip-chip (C4) bumps, solder balls, ball grid array (BGA) balls, the like, or a combination thereof. The semiconductor package structure 100 can include an underfill material (not shown) arranged between the capacitor substrate 106 and the substrate 102. The underfill material can fill gaps between the conductive structures 104 to provide structural support. In some embodiments, the underfill material is formed from a polymer such as epoxy. The underfill material can be dispensed by capillary action and can then be cured by any suitable curing method. As shown in Fig. 1, the capacitor substrate 106 can have a first surface 107A and a second surface 107B opposite the first surface 107A. According to some embodiments, the capacitor substrate 106 has a first redistribution structure 108 arranged on the first surface 107A and a second redistribution structure 118 arranged on the second surface 107B. The first redistribution structure 108 can have a wiring structure 109 in dielectric layers 110, and the second redistribution structure 118 can have a wiring structure 119 in dielectric layers 120. The wiring structures 109 and 119 can comprise conductive pads, conductive vias, conductor tracks, conductive pillars, the like, or a combination thereof. The wiring structures 109 and 119 can be formed from conductive materials, and exemplary conductive materials have been described previously. In some embodiments, the dielectric layers 110 and 120 can be formed from organic materials such as polymer-based materials, inorganic materials including silicon nitride, silicon oxide, and silicon oxynitride, the like, or a combination thereof. According to some embodiments, the capacitor substrate 106 has a semiconductor layer 114 arranged between the first redistribution structure 108 and the second redistribution structure 118. As shown in Fig. 1, the sidewalls of the semiconductor layer 114 can be substantially coplanar with the sidewalls of the first redistribution structure 108 and the sidewalls of the second redistribution structure 118. Semiconductor layer 114 can contain a bulk semiconductor, a compound semiconductor, an alloy semiconductor, the like, or a combination thereof. Semiconductor layer 114 can be made of any suitable semiconductor material, such as silicon or germanium. Semiconductor layer 114 can be doped (e.g., using p- or n-type dopants) or undoped. For example, p-type dopants can include boron, and n-type dopants can include phosphorus or arsenic. According to some embodiments, the capacitor substrate 106 comprises one or more capacitor structures 116 embedded in the semiconductor layer 114. The capacitor structures 116 can be deep-trench capacitors, each of which may have an interlayer dielectric layer between two electrode layers (not shown). The electrode layers can be made of conductive materials, and the interlayer dielectric layer can be made of silicon oxide, silicon nitride, silicon oxynitride, high-k dielectrics (e.g., HfO2, ZrO2, La2O3, Al2O3, TiO2), the like, or a combination thereof. According to some embodiments, the capacitor substrate 106 has one or more vias 112 extending through the semiconductor layer 114 and electrically connecting the first redistribution structure 108 to the second redistribution structure 118. The vias 112 can be made of conductive material, including copper, aluminum, nickel, gold, silver, the like, an alloy thereof, or a combination thereof. The vias 112 can extend into the dielectric layers 120. As shown in Fig. 1, in some embodiments the width of the vias 112 decreases in one direction from the first surface 107A to the second surface 107B. According to some embodiments, the capacitor substrate 106 may have a lining layer 113 covering the sidewalls of the vias 112. The lining layer 113 may extend into the dielectric layers 120. In some embodiments, the lining layer 113 is made of insulating material, including silicon oxide, silicon nitride, silicon oxynitride, the like, or a combination thereof. The capacitor substrate 106 may have a nucleation layer (not shown) arranged between the vias 112 and the lining layer 113. The nucleation layer may have a titanium layer and a copper layer on the titanium layer. Alternatively, the nucleation layer may have a copper layer. According to some embodiments, the semiconductor package structure 100 comprises one or more semiconductor dies 126 (for example, 126A and 126B) arranged above the capacitor substrate 106. In some embodiments, the semiconductor dies 126A and 126B each independently include system-on-chip (SoC) dies, logic devices, memory devices, radio frequency (RF) devices, the like, or a combination thereof.For example, semiconductor dies 126A and 126B may each include microcontroller (MCU) dies, microprocessor unit (MPU) dies, power control circuit (PMIC) dies, high frequency front end (RFFE) dies, accelerated processing unit (APU) dies, central processing unit (CPU) dies, graphics processing unit (GPU) dies, input / output (I / O) dies, dynamic random access memory (DRAM) controllers, static random access memory (SRAM), high bandwidth memory (HBM), application processor (AP) dies, application-specific integrated circuit (ASIC) dies, the like, or a combination thereof. The semiconductor dies 126A and 126B can have the same or different features. For example, the semiconductor package structure 100 can have more than two semiconductor dies. The semiconductor package structure 100 can also have one or more passive components arranged above the capacitor substrate 106, such as resistors, capacitors, or inductors. The semiconductor dies 126A and 126B can be electrically connected to the capacitor substrate 106 by hybrid bonding, which can be formed by a combination of dielectric-dielectric and conductor-conductor bonding. For example, the conductive pads 122 can be bonded to each other by conductor-conductor bonding, which can be metal-to-metal direct bonding, such as copper-to-copper direct bonding. For example, the dielectric layers 124 can be bonded to each other by dielectric-dielectric bonding. The use of hybrid bonding allows for a narrower bond center-to-center distance and eliminates the need for underfilling. As shown in Fig. 1, the sidewalls of the dielectric layers 124 can be substantially coplanar with the sidewalls of the capacitor substrate 106 and / or the sidewalls of the semiconductor dies 126A or 126B. In some embodiments, the dielectric layer 124 between the capacitor substrate 106 and the semiconductor die 126A is spaced apart from the dielectric layer 124 between the capacitor substrate 106 and the semiconductor die 126B. In these embodiments, a portion of the upper surface of the capacitor substrate 106 may be exposed. By arranging a capacitor substrate 106, which features capacitor structures 116, the capacitance of the semiconductor package structure 100 can be increased. This allows the requirements for high power supply and high current ramp to be met. Furthermore, the capacitor substrate 106 features the redistribution structure 118, which can electrically connect the semiconductor dies 126 arranged on it, thus enabling the integration of chiplets. In addition, the distance between the capacitor structures 116 and the semiconductor dies 126 can be reduced. Fig. 2 is a cross-sectional view of a semiconductor package structure 200 according to some embodiments of the disclosure. It should be noted that the semiconductor package structure 200 may have the same or similar components as the semiconductor package structure 100 shown in Fig. 1, and for the sake of simplicity, these components are not described again in detail. In the following embodiments, the semiconductor package structure 200 has additional capacitor structures. As shown in Fig. 2, the semiconductor package structure 200, according to some embodiments, has an embedded capacitor structure 202 arranged above the substrate 102. The embedded capacitor structure 202 can have a semiconductor layer 130. The semiconductor layer 130 can be made of any suitable semiconductor material, such as silicon or germanium. The semiconductor substrate 130 can be doped (e.g., using p- or n-type dopants) or undoped. For example, p-type dopants can include boron, and n-type dopants can include phosphorus or arsenic. According to some embodiments, the embedded capacitor structure 202 has one or more capacitor structures 216 in the semiconductor layer 130. The capacitor structures 216 can consist of deep-trench capacitors. A section 300 of the semiconductor package structure 200, which includes the capacitor structures 216, will be described later with reference to Fig. 3. According to some embodiments, the embedded capacitor structure 202 has one or more vias 131 adjacent to the capacitor structures 216. The vias 131 can extend through the semiconductor layer 130. The vias 131 can be made of conductive material, including copper, aluminum, nickel, gold, silver, the like, an alloy thereof, or a combination thereof. According to some embodiments, the embedded capacitor structure 202 has a wiring structure 133 arranged above the semiconductor layer 130 and electrically connected to the capacitor structures 216 and the vias 131. The wiring structure 133 can comprise conductive pads, conductive vias, conductor tracks, conductive pillars, the like, or a combination thereof. The wiring structure 133 can be arranged in dielectric layers 132. The dielectric layers 132 can be made of organic materials, such as polymer-based materials, inorganic materials, including silicon nitride, silicon oxide, silicon oxynitride, the like, or a combination thereof. According to some embodiments, several conductive pads 134 are arranged over the wiring structure 133 such that they are electrically connected to the wiring structure 133. The conductive pads 134 can be made of conductive material, including copper, aluminum, nickel, gold, silver, the like, an alloy thereof, or a combination thereof. According to some embodiments, the semiconductor package structure 200 has an interconnect structure 135 adjacent to the embedded capacitor structure 202. The interconnect structure 135 may include a wiring structure 136. In some embodiments, the wiring structure includes conductive pads, conductive vias, conductor tracks, conductive pillars, the like, or a combination thereof. The interconnect structure 135 can electrically connect the capacitor substrate 106 to a semiconductor die 146. The semiconductor die 146 may include the components described above in relation to the semiconductor die 126, and these components are not repeated. The semiconductor dies 146 and 126 may have the same or different features. In some embodiments, a molding material 140 surrounds the embedded capacitor structure 202 and the interconnect structure 135. The molding material 140 can protect the embedded capacitor structure 202 and the interconnect structure 135 from the environment, thereby preventing damage from stresses, chemicals, and moisture. The molding material 140 can separate the embedded capacitor structure 202 from the interconnect structure 135. The molding material 140 can be made of a non-conductive material, including a moldable polymer, epoxy, resin, the like, or a combination thereof. For illustrative purposes, only one interconnect structure 135 is shown, but more than one interconnect structure may be present. According to some embodiments, the semiconductor package structure 200 has more than one interconnect structure 135, and these interconnect structures 135 may be surrounded by and spaced apart from each other by the mold material 140. Furthermore, the semiconductor package structure 200 may have more than two semiconductor dies and one or more passive components above the mold material 140, such as resistors, capacitors, or inductors. According to some embodiments, one or more vias 138 are arranged in the mold material 140. The vias 138 can extend through the mold material 140. The vias 138 can resemble the vias 112 as shown in Fig. 1 and are not repeated. According to some embodiments, the semiconductor package structure 200 comprises several conductive structures 144 arranged above the mold material 140 and several conductive structures 104 arranged below the mold material 140. The conductive structures 104 and 144 can each independently include microbumps, flip-chip (C4) bumps, solder balls, ball grid array (BGA) balls, the like, or a combination thereof. The capacitor substrate 106 and the semiconductor die 146 can be electrically connected to the substrate 102 via the embedded capacitor structure 202, the interconnect structure 135, the vias 138, and the conductive structures 104, 144. The capacitance of the semiconductor package structure 200 can be further increased by arranging the capacitor structures 216. Furthermore, the interconnect structure 135 can electrically connect the capacitor substrate 106 and the capacitor structures 216 to one or more semiconductor dies, such as the semiconductor die 146. Fig. 3 is a cross-sectional view of section 300 of the semiconductor package structure 200 according to some embodiments of the disclosure. As shown in Fig. 3, each of the capacitor structures 216 according to some embodiments has an interlayer dielectric layer 216D arranged between two electrode layers 216M. The electrode layers 216M can be formed of conductive materials such as metals. The interlayer dielectric layer 216D can be formed of silicon oxide, silicon nitride, silicon oxynitride, high-k dielectrics (e.g., HfO₂, ZrO₂, La₂O₃, Al₂O₃, TiO₂), the like, or a combination thereof. Fig. 4 is a cross-sectional view of a semiconductor package structure 400 according to some embodiments of the disclosure. It should be noted that the semiconductor package structure 400 may have the same or similar components as the semiconductor package structure 200 shown in Fig. 2, and for the sake of simplicity, these components are not described again in detail. In the following embodiments, the semiconductor package structure 400 includes an interposer with capacitor structures. As shown in Fig. 4, the semiconductor package structure 400, according to some embodiments, includes an interposer 148 arranged above the substrate 102. The interposer 148 can comprise a bulk semiconductor, a compound semiconductor, an alloy semiconductor, the like, or a combination thereof. The interposer 148 can be made of any suitable semiconductor material, such as silicon or germanium. The interposer 148 can have a semiconductor layer 145. The semiconductor layer 145 can be made of any suitable semiconductor material, such as silicon or germanium. The semiconductor substrate 145 can be doped (e.g., using p- or n-type dopants) or undoped. For example, boron can be used as a p-type dopant, and phosphorus or arsenic can be used as an n-type dopant. According to some embodiments, the semiconductor package structure 400 comprises one or more capacitor structures 416 embedded in the semiconductor layer 145. The capacitor structures 416 may consist of deep-trench capacitors. The capacitor structures 416 may include the components described above with respect to the capacitor structures 216, as shown in Fig. 2, and are not repeated. The interposer 148 can have dielectric layers 147 arranged above the semiconductor layer 145. The dielectric layers 147 can be made of organic materials, such as polymer-based materials, inorganic materials including silicon nitride, silicon oxide, silicon oxynitride, the like, or a combination thereof. A wiring structure 154 can be arranged above the capacitor structures 416. The wiring structure 154 can include the components described above with respect to the wiring structure 133 and the vias 131, as shown in Fig. 2, and is not repeated. The interposer 148 can have a wiring structure 150 between the capacitor substrate 106 and the semiconductor die 146, which electrically connects the capacitor substrate 106 to the semiconductor die 146. In some embodiments, the wiring structure includes conductive pads, conductive vias, conductor tracks, conductive pillars, the like, or a combination thereof. The semiconductor dies 146 and 126 can have the same or different features. Furthermore, the semiconductor package structure 400 can include more than two semiconductor dies and can also include one or more passive components arranged above the interposer 148, such as resistors, capacitors, or inductors. According to some embodiments, the semiconductor package structure 400 has one or more vias 152 extending through the interposer 148. The vias 152 may resemble the vias 138 as shown in Fig. 2 and are not repeated. According to some embodiments, the semiconductor package structure 400 comprises several conductive structures 144 arranged above the interposer 148 and several conductive structures 104 arranged below the interposer 148. The conductive structures 104 and 144 can each independently include microbumps, flip-chip (C4) bumps, solder balls, ball grid array (BGA) balls, the like, or a combination thereof. The capacitor substrate 106 and the semiconductor die 146 can be electrically connected to the substrate 102 via the interposer 148 and the conductive structures 104, 144. By arranging the interposer 148 with the capacitor structures 416, the capacitance of the semiconductor package structure 400 can be further increased. Furthermore, the wiring structure 150 in the interposer 148 can electrically connect the capacitor substrate 106 and the capacitor structures 416 to one or more additional semiconductor dies, such as the semiconductor die 146. In summary, the semiconductor package structure according to the present disclosure comprises a capacitor substrate that includes one or more capacitor structures providing capacitance. This enables the fulfillment of requirements for high power handling and high current ramp. Furthermore, the capacitor substrate features redistribution structures that establish an electrical connection to semiconductor dies mounted on it, thus enabling chiplet integration. Additionally, the distance between the capacitor structures and the semiconductor dies can be reduced. The invention has been described by way of example and with regard to preferred embodiments.

Claims

Semiconductor package structure (200) comprising: a capacitor substrate (106) with a first surface (107A) and a second surface (107B) opposite the first surface and comprising: a first redistribution structure (108) arranged on the first surface (107A); a second redistribution structure (118) arranged on the second surface (107B); a via (112) electrically connecting the first redistribution structure (108) to the second redistribution structure (118); and a first capacitor structure (116) arranged between the first redistribution structure (108) and the second redistribution structure (118) and electrically connected to the second redistribution structure (118); a first semiconductor die (126A) arranged above the capacitor substrate (106) and electrically connected to the first capacitor structure (116) via the second redistribution structure (118);an interconnect structure (135) arranged beneath the capacitor substrate (106) and electrically connecting the capacitor substrate (106) to a second semiconductor die (146); a second capacitor structure (202) beneath the capacitor substrate (106) and laterally adjacent to the interconnect structure (135); and a molding material (140) surrounding the second capacitor structure (102) and the interconnect structure (135). Semiconductor package structure (200) according to claim 1, further comprising a hybrid bond (122 / 124) which electrically connects the first semiconductor die (126A) to the second redistribution structure (118), wherein the hybrid bond (122 / 124) preferably has a side wall which is substantially coplanar with a side wall of the capacitor substrate (106). Semiconductor package structure (200) according to claim 1 or 2, wherein the capacitor substrate (106) further comprises a semiconductor layer (114) arranged between the first redistribution structure (108) and the second redistribution structure (118), and the first capacitor structure (116) is arranged in the semiconductor layer (114), wherein the semiconductor layer (114) preferably has a side wall which is substantially coplanar with a side wall of the first redistribution structure (108). Semiconductor package structure (200, 400) comprising: a substrate (102); a first capacitor structure (216, 416) arranged above the substrate (102); a capacitor substrate (106) arranged above and electrically connected to the first capacitor structure (216, 416), the capacitor substrate (106) comprising: a semiconductor layer (114); a second capacitor structure (116) embedded in the semiconductor layer (114); a redistribution structure (108) arranged above the semiconductor layer (114) and electrically connected to the second capacitor structure (116); and a first via (112) extending through the semiconductor layer (114); a first semiconductor die (126A) arranged above the capacitor substrate (106) and electrically connected to the second capacitor structure (116);a second semiconductor die (126B) adjacent to the first semiconductor die (126A) and electrically connected to the redistribution structure (108); and a hybrid bond (122 / 124) that electrically connects the redistribution structure (108) to the first semiconductor die (126A) and the second semiconductor die (126B). Semiconductor package structure (200, 400) according to claim 4, further comprising an interconnect structure (135) adjacent to the first capacitor structure (216, 416) and electrically connecting the capacitor substrate (106) to a third semiconductor die (146). Semiconductor package structure (200, 400) according to claim 5, wherein the semiconductor package structure (200, 400) further comprises a mold material (140) that surrounds the first capacitor structure (216, 416) and the interconnect structure (135) and separates the first capacitor structure (216, 416) from the interconnect structure (135). Semiconductor package structure (200, 400) according to claim 6, wherein the semiconductor package structure (200, 400) further comprises a second via (138) which extends through the mold material (140) and is electrically connected to the substrate (102). Semiconductor package structure (200, 400) according to claim 4, wherein the first capacitor structure (216, 416) is arranged in an interposer (148), and the interposer (148) further comprises a second via (152) adjacent to the first capacitor structure (116) and electrically connected to the substrate (102). Semiconductor package structure (400) comprising: an interposer (148) comprising a first deep-trench capacitor (416); a capacitor substrate (106) arranged above the interposer (148) comprising: a second deep-trench capacitor (116); a redistribution structure (108) arranged above the second deep-trench capacitor (116) and electrically connected to it; and a first via (112) adjacent to the second deep-trench capacitor (116) and electrically connected to the redistribution structure (108); a first semiconductor die (126A) arranged above the capacitor substrate (106) and electrically connected to the first deep-trench capacitor (416) and the second deep-trench capacitor (116); and a second semiconductor die (126B) which is arranged above the capacitor substrate (106) and is electrically connected to it via hybrid bonds (122 / 124). Semiconductor package structure (400) according to claim 9, wherein the semiconductor package structure (400) further comprises a third semiconductor die (146) arranged above the interposer (148) and electrically connected to the first deep trench capacitor (416). Semiconductor package structure (400) according to claim 10, wherein the semiconductor package structure (400) further comprises a second via (152) which is embedded in the interposer (148) and electrically connected to the capacitor substrate (106). Semiconductor package structure (400) according to one of claims 9 to 11, further comprising a hybrid bond (122 / 124) which electrically connects the first semiconductor die (126A) to the capacitor substrate (106).

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