SEMICONDUCTOR DEVICE

Abstract

Semiconductor device (PKG1) comprising: a wiring substrate (SUB1) with an upper surface (2t), a lower surface (2b) facing the upper surface (2t), and several wiring layers (WL1-WL8) provided between the upper surface (2t) and the lower surface (2b); and a semiconductor chip (CHP1) with a first surface (3t), several bump electrodes (3BP) formed on the first surface (3t), and a second surface (3b) facing the first surface (3t), wherein the semiconductor chip (CHP1) is mounted over the several bump electrodes (3BP) on the upper surface (2t) of the wiring substrate (SUB1), wherein the semiconductor chip (CHP1) comprises a first analog circuit (AC1), wherein the several wiring layers (WL1-WL8) of the wiring substrate (SUB1) comprise: a first wiring layer (WL8),which is closest among the multiple wiring layers of the lower surface (2b) and is provided with multiple contact surface patterns (2LD); and a second wiring layer (WL7) which is second closest to the lower surface (2b) after the first wiring layer (WL8), wherein a first power supply potential pattern (LVD4), which can apply a first power supply potential (VD1) to the first analog circuit (AC1), and a first reference potential pattern (LVS4), which can apply a first reference potential (VS1) to the first analog circuit (AC1), are electrically connected to the first analog circuit (AC1), wherein one of the first power supply potential pattern (LVD4) and the first reference potential pattern (LVS4) is provided in the first wiring layer (WL8),wherein another of the first power supply potential pattern (LVD4) and the first reference potential pattern (LVS4) is provided in the second wiring layer (WL7), and wherein the first power supply potential pattern (LVD4) and the first reference potential pattern (LVS4) extend in the same direction (X) and overlap each other.

Description

background The present disclosure relates to a semiconductor device. One disclosed technique is listed below. [Patent document 1] Japanese unexamined patent application with publication number JP 2005 - 340 247 A A semiconductor device already exists in which a semiconductor chip is mounted on a wiring substrate having multiple wiring layers using a flip-chip interconnection method. For example, patent document 1 discloses, as a countermeasure against crosstalk noise of digital signals in a wiring substrate, a structure in which a large plane and a power plane (“plane” meaning a large-area conductor pattern), each acting as a shield, are arranged between a wiring layer in which signal transmission terminals are arranged and a wiring layer in which signal transmission wiring is arranged. Document US 2020 / 0 096 923 A1 describes an image generation device in which an oscillator for clocking an integrated real-time clock is located in the space between a printed circuit board and a heat sink covering the circuit. Publication US 2007 / 0 194 433 A1 describes an electronic circuit with two semiconductor devices connected on a mounting substrate, in which substrate leads of different lengths compensate for the unequal lengths of mounting leads of the second device. Summary A technique for reducing the influence of noise in a path designed to supply power to a circuit is required, along with enhanced functionality of a semiconductor device, to stabilize the operation of the circuit within the device. For example, an analog circuit, such as a phase-locked loop (PLL), may be provided in a semiconductor chip within a semiconductor device to stabilize the transmission quality of a digital signal. Noise can more readily affect the operation of the analog circuit than a digital circuit; therefore, a path designed to supply power to the analog circuit may preferably have a shorter path length than other paths (e.g., a path designed to supply power to the digital circuit). As the functionality of a semiconductor device increases, the number of external connections within the device tends to increase. The density of these external connections also tends to increase in order to reduce the size of the semiconductor device. Consequently, some paths between an electrode of a semiconductor chip and the respective external connection designed to supply power to an analog circuit may have a longer path length. A power supply path with a long path length from the semiconductor chip electrode to the external connection exhibits a large inductance component. Thus, the power supply potential or reference potential flowing in this path is easily affected by noise. Further problems and new features are evident from the description in this document and the drawings. A semiconductor device according to one embodiment comprises a wiring substrate with multiple wiring layers and a semiconductor chip with a first analog circuit. A first power supply potential pattern, capable of applying a first power supply potential to the first analog circuit, and a first reference potential pattern, capable of applying a first reference potential to the first analog circuit, are electrically connected to the first analog circuit. A pattern of the first power supply potential pattern and the first reference potential pattern is provided in a first wiring layer located closest to a lower surface of the wiring substrate, below the wiring layers.Another pattern of the first power supply potential pattern and the first reference potential pattern is provided in a second wiring layer, which is the second closest to the bottom surface after the first wiring layer. The first power supply potential pattern and the first reference potential pattern extend in the same direction and overlap each other. According to the embodiment described above, the performance of a semiconductor device can be improved. Brief description of the drawings Fig. 1 is a top view of a semiconductor device according to one embodiment. Fig. 2 is a bottom view of the semiconductor device of Fig. 1. Fig. 3 is a top view of an internal structure of the semiconductor device shown in Fig. 1 on a wiring substrate with the cover element removed. Fig. 4 is a cross-sectional view along line AA of Fig. 1. Fig. 5 is an illustrative representation of an exemplary circuit structure contained in the semiconductor device of Fig. 4. Fig. 6 is a schematic illustrative representation of paths designed to supply power to an analog circuit of Fig. 5. Fig. 7 is an enlarged top view of exemplary noise reduction measures for power supply potential supply paths and reference potential supply paths shown in Fig. 6. Fig. 8 is an enlarged cross-sectional view along line BB of Fig. 7.Figure 9 is an enlarged top view of further exemplary noise mitigation measures for the power supply potential supply paths and reference potential supply paths shown in Figure 6. Figure 10 is an enlarged cross-sectional view along line CC of Figure 9. Figure 11 is an enlarged top view of yet more exemplary noise mitigation measures for the power supply potential supply paths and reference potential supply paths shown in Figure 6. Figure 12 is an enlarged cross-sectional view along line DD of Figure 11. Figure 13 is an enlarged top view of just one power supply potential pattern and one reference potential pattern shown in Figure 11. Figure 14 is an enlarged top view of yet more exemplary noise mitigation measures for the power supply potential supply paths and reference potential supply paths shown in Figure 6.Figure 15 is an enlarged top view of another variation of Figure 11. Figure 16 is an enlarged top view of another variation of Figure 11. Figure 17 is an enlarged top view of an exemplary form of a conductor pattern formed in the third wiring layer from the bottommost wiring layer shown in Figure 10. Figure 18 is an enlarged top view of an exemplary form of a conductor pattern formed in the third wiring layer from the bottommost wiring layer shown in Figure 12. Figure 19 is a top view comparing the difference between the width of a signal wiring designed to transmit an electrical signal to the analog circuit shown in Figure 5 and the wiring widths of a reference potential pattern and a power supply potential pattern shown in Figure 9 or Figure 11.Figure 20 is an enlarged cross-sectional view of a modification example of Fig. 10 or Fig. 12. Detailed description <Beschreibung des Erläuterungsformats, Grundbegriffe und ihre Verwendung in der vorliegenden Anmeldung> For convenience, the invention is described in several sections or embodiments in the present application where necessary. Unless otherwise specified, these sections or embodiments are not irrelevant to one another. Regardless of whether it precedes or follows the description, a part of a simple example is a specified part, a part, or the entirety of a modified example of the other. Furthermore, repeated descriptions of the same part are generally avoided. Moreover, not every element in an embodiment is indispensable unless otherwise specified, the number is logically limited, or this is clearly not the case from the context. When a material, composition, or the like is described in the description of embodiments or the like as "X consisting of A" or the like, something having components other than A is not excluded unless it is expressly stated otherwise or is clear from the context. For example, the component means "X containing A as a major component" or the like. For example, the component means "X containing A as a major component" or the like. For example, it is understood that a "silicon material" and the like includes not only pure silicon but also SiGe alloys (silicon-germanium alloys) or other multi-component alloys containing silicon as a major component, or a material containing other additives or the like.Furthermore, gold plating, copper plating, nickel plating and the like include not only pure material, but also objects that contain gold, copper, nickel and the like as their main component, unless otherwise specified. Furthermore, even when a specific numerical value and a specific numerical quantity are mentioned, the specific numerical value and the specific numerical quantity may exceed or be less than the specific numerical values, unless otherwise stated, the number is logically limited, or this is clearly not the case from the context. Furthermore, in each drawing of the embodiment, identical or similar parts are identified by the same or similar symbol or reference numeral, and a description thereof is generally not repeated. Furthermore, in some cases, even in cross-sectional views, the accompanying drawings omit hatching or similar markings, for example, when complications arise or when a section needs to be clearly distinguished from a gap. In this context, even in a closed hole, a background outline is omitted in a top view if this is evident from the explanation or for other reasons. Moreover, in some cases, even if the drawing is not a cross-sectional view, hatching or a dot pattern is added to clarify that the section is not the gap, or to clearly indicate a boundary between areas. In this description, a "semiconductor component" is a component that utilizes electrons in a semiconductor. Examples of "semiconductor components" include a semiconductor chip and a semiconductor device housing a semiconductor chip. Regardless of whether the semiconductor is involved, a component embedded in an electrical circuit and performing an electrical function is referred to as an "electronic component." Examples of electronic components include not only semiconductor components but also resistors, capacitors, inductors, and the like. <halbleitervorrichtung> Fig. 1 is a top view of a semiconductor device according to one embodiment. Fig. 2 is a bottom view of the semiconductor device of Fig. 1. Fig. 3 is a top view of an internal structure of the semiconductor device shown in Fig. 1 on a wiring substrate with the cover element removed. Fig. 4 is a cross-sectional view along line AA of Fig. 1. A semiconductor device PKG1 according to the present embodiment comprises a wiring substrate SUB1 and a semiconductor chip CHP1 (see Fig. 3) mounted on the wiring substrate SUB1. The semiconductor device PKG1 includes a bonding layer BND1 arranged on the semiconductor chip CHP1 and a covering element LID designed to cover the entire semiconductor chip CHP1, the entire bonding layer BND1, and a portion of the wiring substrate SUB1, and fixed to the bonding layer BND1. As shown in Fig. 4, the wiring substrate SUB1 has an upper surface (surface, main surface, chip mounting surface, first main surface) 2t on which the semiconductor chip CHP1 is mounted, and an opposing lower surface (surface, main surface, mounting surface, second main surface) 2b, which faces the upper surface 2t. The wiring substrate SUB1 has several sides 2s (see Fig. 1, Fig. 2 to Fig. 3) which, in plan view, form the outer edges of the upper surface 2t and the lower surface 2b. In the present embodiment, the upper surface 2t (see Fig. 1) and the lower surface 2b (see Fig. 2) of the wiring substrate SUB1 are rectangular, and the wiring substrate SUB1 has four sides 2s in plan view. The wiring substrate SUB1 comprises several (eight in the example of Fig. 4) wiring layers WL1, WL2, WL3, WL4, WL5, WL6, WL7, and WL8, which are provided between the upper surface 2t and the lower surface 2b. The wiring layers include wiring layer WL1, which is closest among the several wiring layers to the upper surface 2t of the wiring substrate SUB1 and is provided with terminals (terminals 2PD). The wiring layers also include wiring layer WL8, which is closest among the several wiring layers to the lower surface 2b of the wiring substrate SUB1 and is provided with terminals (contact surfaces 2LD). Each wiring layer has a conductor pattern, for example, a wiring, which is a path designed to deliver an electrical signal or power. An insulating layer 2e is arranged between the wiring layers. The respective wiring layers are electrically connected to each other via a via 2v, which is a conductive intermediate path that penetrates the insulating layer 2e or a through-hole wiring 2THW. In the present embodiment, a wiring substrate with eight wiring layers is shown as an example of the wiring substrate SUB1; however, the number of wiring layers of the wiring substrate SUB1 is not limited to eight. In a modified example, a wiring substrate comprising seven or fewer wiring layers or nine or more wiring layers can be used. The wiring layer WL1 (the uppermost layer) closest to the upper surface 2t is covered with an insulating film SR1. The insulating film SR1 has openings, and the terminals 2PD provided on the wiring layer WL1 are exposed at these openings. Several contact pads are provided on the wiring layer WL8 (the lowest wiring layer), which is closest to the lower surface 2b of the wiring substrate SUB1. The wiring layer WL8 is covered with an insulating film SR2. Both the insulating film SR1 and the insulating film SR2 are solder masks.The connections 2PD provided on the wiring layer WL1 are each electrically connected to the contact surfaces (contact surface patterns) 2LD provided on the wiring layer WL8 via the conductor patterns (wirings 2d or large-area conductor patterns), the vias 2v and the through-hole wirings 2THW, which are formed on the wiring layers of the wiring substrate SUB1. The wiring substrate SUB1 is formed, for example, by a build-up process in which the respective wiring layers are stacked on an upper surface 2Ct and a lower surface 2Cb of an insulating layer (core material, core insulating layer) 2CR, which consists of prepreg in which a glass fiber is impregnated with resin. The wiring layer WL4 on the upper surface 2Ct side of the insulating layer 2CR is electrically connected to the wiring layer WL5 on the lower surface 2Cb side via multiple through-hole wirings 2THW embedded in several through-holes designed to penetrate from one of the upper surface 2Ct and the lower surface 2Cb to the other. In the example shown in Fig. 4, the wiring substrate SUB1 is described as a wiring substrate in which several wiring layers are stacked on the sides of the upper surface 2Ct and the lower surface 2Cb of the insulating layer 2CR as the core material. A modified example of Fig. 4 uses a so-called coreless substrate in which the insulating layers 2e and the conductor patterns, such as the wiring 2d, are stacked sequentially, without the insulating layer 2CR being made of a hard material such as prepreg. In the case of the coreless substrate, the wiring layers are electrically connected by the vias 2v, without the through-hole wiring 2THW being formed. In the example shown in Fig. 4, solder balls (solder materials, external terminals, electrodes, external electrodes) SB are each connected to the contact pads 2LD. The solder balls SB are conductive elements designed to electrically connect multiple terminals (not shown) on the mainboard side to the contact pads 2LD when the semiconductor device PKG1 is mounted on the mainboard (not shown). The solder balls SB consist, for example, of a lead (Pb)-containing Sn-Pb solder material or a so-called lead-free solder material that contains substantially no Pb. Examples of lead-free solder include pure tin (Sn), tin-bismuth (Sn-Bi), tin-copper-silver (Sn-Cu-Ag), tin-copper (Sn-Cu), and the like. The lead-free solder described here refers to a material whose lead (Pb) content is 0.1 wt.% or less, where the content is defined according to the Restriction of Hazardous Substances Directive (RoHS Directive). Several solder balls SB are arranged in a matrix (array) configuration, as shown in Fig. 2. Although not shown in Fig. 2, the contact pads 2LD connected to the solder balls SB (see Fig. 4) are also arranged in a matrix (array) configuration. Thus, a semiconductor device in which several external connections (solder balls SB, contact pads 2LD) are arranged in a matrix on the mounting surface of the wiring substrate SUB1 is called a planar array semiconductor device. In the planar array semiconductor device, the mounting surface (lower surface 2b) of the wiring substrate SUB1 is effectively used as the arrangement space for the external connections, and therefore this type is preferable with regard to suppressing an increase in the mounting area of ​​the semiconductor device, even with an increase in the number of external connections.This means that a semiconductor device with an increased number of external connections, as well as higher functionality and higher integration, can be mounted in a small space. The semiconductor device PKG1 comprises the semiconductor chip CHP1, which is mounted on the wiring substrate SUB1. As shown in Fig. 4, each semiconductor chip CHP1 has a front surface (main surface, top surface) 3t and a back surface (main surface, bottom surface) 3b, which faces the front surface 3t. The semiconductor chip CHP1 has multiple sides 3s, which, in plan view, form the outer edges of the front surface 3t and the back surface 3b. The semiconductor chip CHP1 has a square outer shape with a smaller flat area than that of the wiring substrate SUB1 in plan view, as shown in Fig. 3. Thus, the semiconductor chip CHP1 has four sides 3s in plan view. In the example of Fig. 3, the semiconductor chip CHP1 is mounted in the middle of the upper surface 2t of the wiring substrate SUB1, and the four sides 3s of the semiconductor chip CHP1 each extend along the four sides 2s of the wiring substrate SUB1. Several electrodes (contact points, electrode contact points, bond points) 3PD are formed on the top surface 3t of the semiconductor chip CHP1. In the example shown in Fig. 4, the semiconductor chip CHP1 is mounted on the wiring substrate SUB1 in a state where the top surface 3t faces the top surface 2t of the wiring substrate SUB1. Such a mounting method is called a face-down mounting method or flip-chip interconnection method. Although not shown, several semiconductor elements (circuit elements) are formed on the main surface of the semiconductor CHP1 (more precisely, a semiconductor element formation area provided on an element formation surface of a semiconductor substrate, which is a base element of the semiconductor chip BHKW1). The multiple electrodes 3PD are each electrically connected to the multiple semiconductor elements via wiring (not shown) formed on a wiring layer located inside the semiconductor chip CHP1 (more precisely, between the top surface 3t and a semiconductor element formation area (not shown)). The semiconductor substrate provided in the semiconductor chip CHP1 consists, for example, of silicon (Si). An insulating film is formed on the upper surface 3t of the semiconductor chip CHP1, covering the semiconductor substrate and the wiring, and a portion of each electrode 3PD (see Fig. 4) is exposed through an opening formed in the insulating film. The electrodes 3PD consist of a metal, in the present embodiment, for example, aluminum (Al). As shown in Fig. 4, the electrodes 3PD are each connected to stud electrodes 3BP, and the electrodes 3PD of the semiconductor chip CHP1 are each electrically connected to the terminals 2PD of the wiring substrate SUB1 via the stud electrodes 3BP. The stud electrodes 3BP are metal elements (conducting elements) shaped to protrude from the surface 3t of the semiconductor chip CHP1. In the present embodiment, the stud electrodes 3BP are so-called solder studs, in which a solder material is stacked over an electrode 3PD by an underlying metal film (beneath the stud metal). The solder material can be either lead-containing or lead-free, making the solder studs resemble solder balls SB.When the semiconductor chip CHP1 is mounted on the wiring substrate SUB1, a heating process (melting process) is performed, during which the solder bumps previously formed on both electrodes 3PD and terminals 2PD are brought into contact with each other, thus merging the solder bumps to form the bump electrodes 3BP. In a modified embodiment, column bumps, in which a solder film is formed on a tip surface of a conductor column made of copper (Cu) or nickel (Ni), can be used as bump electrodes 3BP. An underfill resin (insulating resin) UF is arranged between the semiconductor chip CHP1 and the wiring substrate SUB1, as shown in Fig. 4. The underfill resin UF is positioned to fill a space between the front surface 3t of the semiconductor chip CHP1 and the upper surface 2t of the wiring substrate SUB1. The prong electrodes 3BP are sealed by the underfill resin UF. The underfill resin UF consists of an insulating (non-conductive) material (e.g., resin) and is positioned to seal the electrical connections (bonding parts of the prong electrodes 3BP) between the semiconductor chip CHP1 and the wiring substrate SUB1. By covering the bonding parts between the prong electrodes 3BP and the terminals 2PD with the underfill resin UF in this way, the mechanical stress caused at the electrical connections between the semiconductor chip CHP1 and the wiring substrate SUB1 can be reduced.The mechanical stress caused at the bonding points between the electrodes 3PD of the semiconductor chip CHP1 and the bump electrodes 3BP can also be reduced. Furthermore, the main surface of the semiconductor chip CHP1, on which the semiconductor elements (circuit elements) are formed, can be protected. The cover element (lid, heat spreader, heat dissipator) LID is located on the back surface 3b of the semiconductor chip CHP1. The cover element LID is, for example, a metal plate with a higher thermal conductivity than that of the wiring substrate SUB1 and serves to dissipate heat generated within the semiconductor chip CHP1 to the outside. The cover element LID is thermally connected to the semiconductor chip CHP1 via the bonding layer BND1. The bonding layer BND1 makes contact between the semiconductor chip CHP1 and the cover element LID. The bonding layer BND1 consists of an adhesive obtained, for example, by curing a paste mixed with a filler in a resin paste. Examples of fillers include metal particles and metal oxide particles such as aluminum oxide. The bonding layer BND1 contains a filler that is added to improve heat dissipation properties and can thus improve the thermal conductivity between the semiconductor chip CHP1 and the cover element LID compared to filler-free resin adhesives. A circumferential area of ​​the cover element LID is bonded and fixed to the upper surface 2t of the wiring substrate SUB1 via a bonding layer BND2. Unlike bonding layer BND1, bonding layer BND2 does not require heat dissipation properties, therefore its material is not particularly restricted and can be selected optionally, as long as the material exhibits the required adhesive strength. For example, if the same material as that of bonding layer BND1 is used, the manufacturing steps can be simplified. Alternatively, a material with a higher adhesive strength than that of bonding layer BND1 can also be used. A semiconductor device to which the cover element LID is attached, which functions as a heat dissipation element similarly to the semiconductor device PKG1, can operate the circuits contained therein stably even in the case of higher functionality, since the semiconductor chip CHP1 exhibits high heat dissipation efficiency. In a modified example of the present embodiment, a later described structure of the wiring substrate SUB1 can be applied to a semiconductor device without the cover element LID, the bond layer BND1 and the bond layer BND2, which are shown in Fig. 4. <Beispielhafte Schaltungsstruktur> Next, an exemplary circuit structure provided in the semiconductor device PKG1 of Fig. 4 is described. Fig. 5 is an illustrative representation of an exemplary circuit structure provided in the semiconductor device PKG1 of Fig. 4. It should be noted that some of the multiple circuits, some of the multiple signal transmission paths, and some of the multiple power supply paths provided in the semiconductor device PKG1 are shown in Fig. 5 as examples. As shown in Fig. 5, the semiconductor chip CHP1 of the semiconductor device PKG1 according to the present embodiment comprises an analog circuit AC1. In the example of Fig. 5, the semiconductor chip CHP1 comprises the analog circuit AC1 and a core circuit CC1 that is electrically coupled to the analog circuit AC1. The analog circuit AC1 is, for example, a PLL circuit designed to generate a new signal that is synchronized with the phase of an input signal. In the example shown in Fig. 5, a signal (AC signal, high-frequency signal) SG1 from an external device of the semiconductor device PKG1 is input into the analog circuit AC1. The signal SG1 is fed into the analog circuit AC1 of the semiconductor chip CHP1 via a signal transmission path PSG1 of the wiring substrate SUB1. The analog circuit AC1 comprises a phase comparator, a filter circuit, and an oscillator (not shown) and outputs a new signal (AC signal, high-frequency signal) SG2, which is synchronized with a phase of the signal SG1 and a phase of a comparison target input signal (not shown). The signal SG2 is input into the core circuit CC1. The core circuit CC1 performs data processing (e.g., operational processing) on ​​the input signal SG2 and outputs a signal (AC signal, high-frequency signal) SG3.The signal SG3 is output from the core circuit CC1 of the semiconductor chip CHP1 via a signal transmission path PSG3 of the wiring substrate SUB1 to an external device (not shown). The analog circuit AC1, i.e., the PLL circuit, performs synchronization processing on the signal SG2, which is to be input into the core circuit CC1. This results in the signal SG2 being fed to the core circuit CC1 with reduced phase variance (jitter). The core circuit CC1 is, for example, a digital circuit, but it can also be an analog circuit. The semiconductor chip CHP1 comprises a power circuit AC2, designed to supply power to (and capable of supplying power to) the analog circuit AC1, and a power circuit CC2, designed to supply power to (and capable of supplying power to) the core circuit CC1. The AC2 power circuit supplies the analog circuit AC1 with a supply potential VD1 and a reference potential VS1. Conversely, the CC2 power circuit supplies the core circuit CC1 with a power supply potential VD2 and a reference potential VS2. The power supply potential VD1 is supplied to the power circuit AC2 of the semiconductor chip CHP1 via a power supply potential supply path PVD1 of the wiring substrate SUB1. The reference potential VS1 is supplied to the power circuit AC2 of the semiconductor chip CHP1 via a reference potential supply path PVS1 of the wiring substrate SUB1. The power supply potential VD2 is supplied to the power circuit CC2 of the semiconductor chip CHP1 via a power supply potential supply path PVD2 of the wiring substrate SUB1. The reference potential VS2 is supplied to the power circuit CC2 of the semiconductor chip CHP1 via a reference potential supply path PVS2 of the wiring substrate SUB1. It should be noted that the reference potential VS1 differs from the power supply potential VD1 and can be a potential other than ground. Likewise, the reference potential VS2 differs from the power supply potential VD2 and can be a potential other than ground. The reference potential VS1 can be the same as the reference potential VS2 or different from it. As described later, in the present embodiment, the reference potential supply path PVS1 and the reference potential supply path PVS2 are constructed from separate wiring patterns even when the reference potential VS1 is the same as the reference potential VS2. To operate the analog circuit AC1 of Fig. 5 stably, it is necessary to reduce changes in the potential difference between the power supply potential VD1 and the reference potential VS1, which is supplied to the analog circuit AC1 via the power circuit AC2. This is because changes in the potential difference between the power supply potential VD1 and the reference potential VS1 reduce the quality of the signal SG2 output by the analog circuit AC1. Examples of noise sources that can influence changes in the potential difference between the power supply potential VD1 and the reference potential VS1 include the following. For example, noise induced by the signal SG1 or the signal SG3, which is a high-frequency signal, can affect the potential difference between the power supply potential VD1 and the reference potential VS1.Furthermore, the power supply potential VD2 can change instantaneously due to the power demand of the core circuit CC1. If the power supply potential supply path PVD2 is located near the power supply potential supply path PVD1 and the reference potential supply path PVS1, noise generated in the power supply potential VD2 can influence the potential difference between the power supply potential VD1 and the reference potential VS1. To reduce the influence of noise on the potential difference between the power supply potential VD1 and the reference potential VS1, it is preferred to shorten the path lengths of the power supply potential path PVD1 and the reference potential supply path PVS1. The shortened path lengths reduce the inductance of the power supply potential path PVD1 and the reference potential supply path PVS1, thus reducing the influence of noise. However, the number of external connections for each semiconductor device tends to increase with the increasing functionality of the semiconductor device. Furthermore, the density of multiple external connections tends to be high in order to reduce the size of the semiconductor device. The power supply potential path PVD1 and the reference potential path PVS1 may necessarily be longer. In other words, if the influence of noise can be reduced, even if the path lengths of the power supply potential path PVD1 and the reference potential path PVS1 are long, the design freedom can be improved. A technique for reducing the influence of noise is described in the following section, which involves developing the arrangement of the power supply potential path PVD1 and the reference potential path PVS1 within the wiring substrate SUB1. <Entwurf der Leistungsversorgungspfade> Fig. 6 is a schematic explanatory representation of the paths designed to supply power to the analog circuits of Fig. 5. The outline of a region R1 that overlaps with the semiconductor chip CHP1 is shown in Fig. 6 with a dashed line. The semiconductor device PKG1 comprises several pairs of power supply potential paths PVD1 and reference potential supply paths PVS1, as shown in Fig. 6. The power supply potential paths PVD1 and the reference potential supply paths PVS1 are arranged in pairs. The hump electrodes 3BP are arranged within region R1, which overlaps the semiconductor chip CHP1. The contact pads 2LD, which are contained either in the power supply potential supply paths PVD1 or the reference potential supply paths PVS1, are located outside region R1 in the top view. The contact pads contained in the power supply potential supply path PVD2 and in the reference potential supply path PVS2, which are designed to primarily supply power to the core circuit CC1 of Fig. 5, are located within region R1 (specifically, in the area that overlaps with core circuit CC1 of Fig. 5). Thus, it is difficult to ensure sufficient space within region R1 for arranging the contact pads 2LD contained either in the power supply potential supply paths PVD1 or the reference potential supply paths PVS1.It should be noted that some of the contact surfaces 2LD, which are either contained in the power supply potential supply paths PVD1 or the reference potential supply paths PVS1, may be located within the area R1. The hump electrodes 3BP and the electrically connected contact surfaces 2LD are preferably arranged close to each other in a transparent top view. However, depending on the design constraints, it can be difficult to position the contact surfaces 2LD near the hump electrodes 3BP. The example in Fig. 6 shows a power supply potential path PVD1S and a reference potential supply path PVS1S, whose path segments connecting the hump electrodes 3BP and the contact surfaces 2LD are relatively short, as well as a power supply potential path PVD1L and a reference potential supply path PVS1L, whose path segments connecting the hump electrodes 3BP and the contact surfaces 2LD are relatively long.Figure 6 further shows a power supply potential supply path PVD1M and a reference potential supply path PVS1M, whose path segments connecting the hump electrodes 3BP and the contact surfaces 2LD are relatively medium in size. The path lengths of the power supply potential path PVD1S and the reference potential supply path PVS1S (one path length DVDS and one path length DVSS between the hump electrodes 3BP and the contact surfaces 2LD) are, for example, 5 mm or less. The path lengths of the power supply potential path PVD1M and the reference potential supply path PVS1M (one path length DVDM and one path length DVSM between the hump electrodes 3BP and the contact surfaces 2LD) are, for example, more than 5 mm and 7 mm or less. The path lengths of the power supply potential supply path PVD1L and the reference potential supply path PVS1L (one path length DVDL and one path length DVSL between the hump electrodes 3BP and the contact surfaces 2LD) are, for example, more than 7 mm. The path lengths of the power supply potential supply path PVD1L and the reference potential supply path PVS1L can be 10 mm or more. The relationships between the path segments shown in Fig. 6 can be expressed as follows. The path segment of the power supply potential supply path PVD1L with a power supply potential pattern LVD1 (see Fig. 11 described later) between a bump electrode 3BP of the semiconductor chip CHP1 (see Fig. 4) and a contact area 2LD of the wiring substrate SUB1 is assumed to be path segment DVDL. The path segment of the reference potential supply path PVS1L with a reference potential pattern LVS1 (see Fig. 11 described later) between a bump electrode 3BP of the semiconductor chip CHP1 and a contact area 2LD of the wiring substrate SUB1 is assumed to be path segment DVSL. The path segment of the power supply potential supply path PVD1S with a power supply potential pattern LVD3 (see Fig. 11 described later) is assumed to be path segment DVSL.7) The path path between a 3BP electrode of the semiconductor chip CHP1 and a 2LD contact area of ​​the wiring substrate SUB1 is assumed to be path path DVDs. The path path of the reference potential supply path PVS1S with a reference potential pattern LVS3 (see Fig. 7 described later) between a 3BP electrode of the semiconductor chip CHP1 and a 2LD contact area of ​​the wiring substrate SUB1 is assumed to be path path DVSS. The path path of the power supply potential supply path PVD1M with a power supply potential pattern LVD4 (see Fig. 9 described later) between a 3BP electrode of the semiconductor chip CHP1 (see Fig. 4) and a 2LD contact area of ​​the wiring substrate SUB1 is assumed to be path path DVDM. The path section of the reference potential supply path PVS1M with a reference potential pattern LVS4 (see Fig. described later).9) The path between a bump electrode 3BP of the semiconductor chip CHP1 and a contact pad 2LD of the wiring substrate SUB1 is assumed to be path DVSM. In this case, path DVDL is longer than path DVDM, path DVDS, path DVSM, and path DVSS. Path DVSL is longer than path DVDM, path DVDS, path DVSM, and path DVSS. Path DVDM is longer than path DVDS and path DVSS. Path DVSM is longer than path DVDS and path DVSS. In the example shown in Fig. 6, noise reduction measures must preferably be applied to the power supply potential supply path PVD1L and the reference potential supply path PVS1L. Noise reduction measures must preferably be applied to the power supply potential supply path PVD1M and the reference potential supply path PVS1M with respect to the power supply potential supply path PVD1S and the reference potential supply path PVS1S. The noise reduction measures are described in detail below. <Erste Rauschgegenmaßnahme> Noise countermeasures effectively applicable to the power supply potential supply path PVD1S and the reference potential supply path PVS1S, shown in Fig. 6, are first described as initial noise countermeasures. Fig. 7 is an enlarged top view of exemplary noise countermeasures for the power supply potential supply paths and reference potential supply paths shown in Fig. 6. Fig. 8 is an enlarged cross-sectional view along line BB of Fig. 7. Symbols in Fig. 7 and Fig. 8 are given to schematically represent an inductive coupling state between the power supply potential pattern LVD3, which forms the power supply potential supply path PVD1, and the reference potential pattern LVS3, which forms the reference potential supply path PVS1. The wiring layer shown in Fig. 7 under the components shown in Fig.Of the wiring layers shown in Figure 4, one example is wiring layer WL7. Wiring layer WL7 is the second closest to wiring layer WL8, which is closest to the lower surface 2b of the wiring substrate SUB1, as shown in Figures 4 and 8. Although not shown, in a modified example, the power supply potential pattern LVD3 and the reference potential pattern LVS3, similar to those in Figure 7, can be arranged in wiring layers other than wiring layer WL7. An inductive coupling method of the power supply potential pattern LVD3 and the reference potential pattern LVS3 is effective in reducing the influence of noise on the power supply potential path PVD1 and the reference potential supply path PVS1, which are shown in Fig. 6. Inductive coupling is a condition in which mutual induction between a power supply potential path and a reference potential supply path is predominant. When a power supply potential path and a reference potential supply path are inductively coupled, the loop inductance between the paths can be reduced by mutual induction. Consequently, voltage fluctuations with respect to high-frequency current components can be suppressed (in other words, the intrinsic noise can be reduced).For example, if high-frequency noise or pulse noise occurs on the power supply potential pattern LVD3, to which a fixed potential is applied, and the power supply potential pattern LVD3 and the reference potential pattern LVS3 are inductively coupled, potential fluctuations with respect to the high-frequency current components flowing in the loop path can be suppressed. The power supply potential pattern LVD3 and the reference potential pattern LVS3 are formed in the same wiring layer WL7, as shown in Fig. 7. The power supply potential pattern LVD3 and the reference potential pattern LVS3 extend in the same direction and are adjacent to each other in plan view. The power supply potential pattern LVD3 and the reference potential pattern LVS3 are inductively coupled, as shown schematically with the capacitor circuit symbols in Figs. 7 and 8. The effects of the noise reduction measures using inductive coupling between the power supply potential pattern LVD3 and the reference potential pattern LVS3 are proportional to the magnitude of the mutual inductance between the power supply potential pattern LVD3 and the reference potential pattern LVS3. Thus, the larger the facing path width of the power supply potential pattern LVD3 and the reference potential pattern LVS3, which face each other across the insulating layer 2e, and the smaller the separation distance between the facing patterns, the more effective the noise reduction measure. It should be noted that the facing path width refers to the width of the portion where the power supply potential path and the reference potential path face each other. In the example of Fig. 8, a respective thickness (respective length in the Z-direction of Fig. 8) corresponds to a certain thickness (respective length in the Z-direction of Fig. 8).8) of the power supply potential pattern LVD3 and the reference potential pattern LVS3 of the facing path width. In the example of Fig. 8, the thicknesses of the power supply potential pattern LVD3 and the reference potential pattern LVS3, which are parallel to each other, are preferably larger and the separation distance between the power supply potential pattern LVD3 and the reference potential pattern LVS3 is preferably shorter. In the top view of Fig. 7, conductor patterns 2CP are arranged adjacent to the power supply potential pattern LVD3 and the reference potential pattern LVS3, respectively. The conductor patterns 2CP are paths through which any desired potential is supplied. For example, conductor pattern 2CP forms either the power supply potential path PVD2 or the reference potential path PVS2, which are described in Fig. 5. Alternatively, the conductor pattern 2CP shown in Fig. 7 can form other potential supply paths, which are not shown. The wiring substrate SUB1 includes a reference potential pattern LVS2 (see Fig. 8) capable of supplying the reference potential VS2 to a circuit other than the analog circuit AC1 of Fig. 5 (such as the core circuit CC1 of Fig. 5). The reference potential pattern LVS2 is a conductor pattern that forms part of the reference potential supply path PVS2 of Fig. 5. As shown in Fig. 8, the reference potential patterns LVS2 are formed in wiring layers WL6 and WL8, which are adjacent to wiring layer WL7. In WL7, a power supply potential pattern LVD3 and a reference potential pattern LVS3 are formed beneath the wiring layers of the wiring substrate SUB1, and overlap with the power supply potential pattern LVD3 and the reference potential pattern LVS3.The reference potential patterns LVS2 in the wiring layer WL6 and the wiring layer WL8 preferably extend in the same direction and overlap with the power supply potential pattern LVD3 and the reference potential pattern LVS3. The reference potential pattern LVS2 acts as an electromagnetic shield designed to prevent ambient noise from reaching the power supply potential pattern LVD3 and the reference potential pattern LVS3. When the reference potential pattern LVS2, acting as an electromagnetic shield, is provided as shown in Fig. 8, the noise affecting the power supply potential pattern LVD3 and the reference potential pattern LVS3 can be reduced. Figures 7 and 8 illustrate the embodiment in which the power supply potential pattern LVD3 and the reference potential pattern LVS3 are formed in the wiring layer WL7, and thus the reference potential patterns LVS2, which serve as electromagnetic shields, are arranged in the wiring layers WL6 and WL8. In a modified example, the power supply potential pattern LVD3 and the reference potential pattern LVS3 can be formed in the wiring layer WL8. If, in this case, the reference potential pattern LVS2 is arranged in the wiring layer WL7, the structure of the wiring layer WL6 is not particularly restricted. In the method shown in Figures 7 and 8, it is difficult to significantly increase the thicknesses of the power supply potential pattern LVD3 and the reference potential pattern LVS3. For example, the thicknesses of the power supply potential pattern LVD3 and the reference potential pattern LVS3 shown in Figure 8 are approximately 10 to 20 µm. Therefore, the upper limit of the mutual induction between the power supply potential pattern LVD3 and the reference potential pattern LVS3 is low. Consequently, the method shown in Figures 7 and 8 is only of limited effectiveness for noise reduction measures, for example, on long paths with high path inductance, such as the power supply potential-supply path PVD1M or the power supply potential-supply path PVD1L of Figure 6. As described above, the power supply potential path PVD1S and the reference potential path PVS1S, shown in Fig. 6, have path lengths DVDS and DVSS, respectively, of 5 mm or less and exhibit low path inductance (they have lower path inductance than, for example, the power supply potential path PVD1M or the power supply potential path PVD1L). Therefore, the power supply potential pattern LVD3 and the reference potential pattern LVS3 can reduce noise even when the power supply potential pattern LVD3 and the reference potential pattern LVS3 are implemented in the same wiring layer WL7, as shown in Fig. 7. <Zweite Rauschgegenmaßnahmen> The noise reduction technique, which is effectively applicable to the power supply potential supply path PVD1M and the power supply potential supply path PVD1L shown in Fig. 6, is described below as the second noise reduction technique. The second and third noise reduction techniques are described below assuming that at least one of the power supply potential pattern LVD1 and the reference potential pattern LVS1 is located in the lowest wiring layer WL8. A method for adding a new wiring layer for noise reduction in addition to the wiring layers WL1 to WL8 of Fig. 4 may also be considered.However, increasing the number of wiring layers leads to disadvantages such as an increase in the thickness of the semiconductor device, an increase in the number of steps required to manufacture the wiring substrate, or an increase in manufacturing costs due to an increase in the number of materials required to produce the wiring substrate. Therefore, the inventors of the present invention have investigated a technique for reducing noise by using the bottommost wiring layer WL8 without adding the wiring layer as a noise countermeasure. Fig. 9 is an enlarged top view of further exemplary noise reduction measures for the power supply potential supply paths and reference potential supply paths shown in Fig. 6. Fig. 10 is an enlarged cross-sectional view along line CC of Fig. 9. In the noise reduction measures shown in Figs. 9 and 10, the power supply potential pattern LVD1 and the reference potential pattern LVS1 are arranged separately in adjacent wiring layers. When images of wiring layer WL7 and wiring layer WL8 of Fig. 9 overlap, the power supply potential pattern LVD4 and the reference potential pattern LVS4 are difficult to distinguish. Thus, Fig. 9 must show wiring layer WL7 and wiring layer WL8 in a transparent top view, but shows part of wiring layer WL7 and part of the overlapping wiring layer WL8 in a vertical arrangement.Figure 9 correctly shows the positional relationship between the power supply potential pattern LVD4, the reference potential pattern LVS4, and the contact surfaces 2LD in a transparent top view when the wiring substrate SUB1 is viewed from the lower surface 2b (see Figure 10), and Figure 9 can be viewed as a transparent top view. Figures 11, 14, 15, and 16, described later, are each also a view illustrating a portion of the wiring layer WL7 and a portion of the overlapping wiring layer WL8, arranged vertically similarly to Figure 9, and each of these drawings can be viewed as a transparent top view. Figures 17 and 18, described later, are each a view illustrating a portion of the wiring layer WL6, a portion of the overlapping wiring layer WL7, and a portion of the overlapping wiring layer WL8, arranged vertically similarly to Figure 9.9 are arranged vertically, and each of these drawings can be viewed as a transparent top view. The symbols in Fig. 9 and Fig. 10 are intended to schematically illustrate a state in which the power supply potential pattern LVD4 and the reference potential pattern LVS4 are inductively coupled. The analog circuit AC1 of Fig. 5 is electrically connected to the power supply potential pattern LVD4 (see Fig. 9), which can supply the power supply potential VD1 to the analog circuit AC1, and to the reference potential pattern LVS4 (see Fig. 9), which can supply the reference potential VS1 to the analog circuit AC1. The power supply potential pattern LVD4, shown in Figs. 9 and 10, forms part of the power supply potential supply path PVD1M of Fig. 5. The reference potential pattern LVS4 forms part of the reference potential supply path PVS1M of Fig. 5. As shown in Figures 9 and 10, one pattern of the power supply potential pattern LVD4 and the reference potential pattern LVS4 is provided in wiring layer WL8, and another is provided in wiring layer WL7. Note that the example in Figures 9 and 10 shows the power supply potential pattern LVD4 being provided in wiring layer WL8, while the reference potential pattern LVS4 is provided in wiring layer WL7. However, in a variation, the reference potential pattern LVS4 could be provided in wiring layer WL8, while the power supply potential pattern LVD4 could be provided in wiring layer WL7. The power supply potential pattern LVD4 and the reference potential pattern LVS4 extend in the same direction, overlapping each other in the transparent top view. One pattern (that is, the power supply potential pattern LVD4 in Fig. 10) of the power supply potential pattern LVD4 and the reference potential pattern LVS4, located in the wiring layer WL8, is configured to extend over a width WV4. Another pattern (that is, the reference potential pattern LVS4 in Fig. 10), located in the wiring layer WL7, is similarly configured to extend over a width WV4. In the case of the noise reduction measures shown in Fig. 10, the power supply potential pattern LVD4 and the reference potential pattern LVS4 face each other via the insulating layer 2e, which acts as a dielectric body in the thickness direction of the wiring substrate SUB1 (in the Z-direction in Fig. 10). Thus, the area of ​​the facing portion of the power supply potential pattern LVD4 and the reference potential pattern LVS4 can be made larger than in the example shown in Figs. 7 and 8. In the example shown in Fig. 9, for instance, the width WV4 is approximately 50 to 200 µm and is greater than the thickness TV4 (for example, approximately 10 to 20 µm) of the power supply potential pattern LVD4 and the reference potential pattern LVS4 shown in Fig. 10.Therefore, the mutual induction between the power supply potential pattern LVD4 and the reference potential pattern LVS4 is greater than the mutual induction between the power supply potential pattern LVD3 and the reference potential pattern LVS3, which are shown in Fig. 7. The thickness of the power supply potential pattern LVD1 and the reference potential pattern LVS1, which are shown in Figs. 11 to 16, 18 and 19, is, for example, about 10 to 20 µm, similar to the thickness TV4 of the power supply potential pattern LVD4 and the reference potential pattern LVS4, which are shown in Fig. 10. The configuration shown in Figures 9 and 10 is particularly applicable to power supply potential supply paths with a longer path length, such as power supply potential supply path PVD1M or power supply potential supply path PVD1L, which are shown in Figure 6. A configuration described later in Figures 12 and 13 is more effective for power supply potential supply path PVD1L of Figure 6. In the example shown in Fig. 9, the power supply potential pattern LVD4 is arranged in the wiring layer WL8 between two adjacent contact surfaces 2LD, below the contact surfaces 2LD in the Y-direction, which intersects (and is orthogonal to) the direction in which the power supply potential pattern LVD4 extends (in the X-direction in Fig. 9). The width WV4 is smaller than a center-to-center distance PLD between adjacent contact surfaces 2LD in the Y-direction and is smaller than a separation distance GLD. <Dritte Rauschgegenmaßnahmen> Next, the noise reduction technique, which is particularly effective on the power supply potential supply path PVD1L shown in Fig. 6, is described below as the third noise reduction measure. Fig. 11 is an enlarged top view of further exemplary noise reduction measures for the power supply potential supply paths and reference potential supply paths shown in Fig. 6. Fig. 12 is an enlarged cross-sectional view along line DD of Fig. 11. Fig. 13 is an enlarged top view of only the power supply potential pattern and the reference potential pattern shown in Fig. 11. In the noise reduction measures shown in Fig. 11, Fig. 12 to Fig. 13, the power supply potential pattern LVD1 and the reference potential pattern LVS1 are arranged separately in adjacent wiring layers. Thus, Fig.11 a part of the wiring layer WL7 and a part of the overlapping wiring layer WL8 in a vertical arrangement, similar to Fig. 9 . Symbols in Fig. 11 and Fig. 12 are intended to schematically illustrate a state in which the power supply potential pattern LVD1 and the reference potential pattern LVS1 are inductively coupled. The analog circuit AC1 of Fig. 5 is electrically connected to the power supply potential pattern LVD1 (see Fig. 11), which can supply the power supply potential VD1 to the analog circuit AC1, and to the reference potential pattern LVS1 (see Fig. 11), which can supply the reference potential VS1 to the analog circuit AC1. The power supply potential pattern LVD1, shown in Figs. 11 and 12, forms part of the power supply potential supply path PVD1L of Fig. 5. The reference potential pattern LVS1 forms part of the reference potential supply path PVS1L of Fig. 5. As shown in Figures 11 and 12, one of the power supply potential pattern LVD1 and the reference potential pattern LVS1 is provided in wiring layer WL8, and another of these is provided in wiring layer WL7. Note that the example in Figures 11 and 12 shows that the power supply potential pattern LVD1 is provided in wiring layer WL8, while the reference potential pattern LVS1 is provided in wiring layer WL7. However, in a variation, the reference potential pattern LVS1 could be provided in wiring layer WL8, while the power supply potential pattern LVD1 could be provided in wiring layer WL7. As shown in Figures 11 and 12, one of the power supply potential pattern LVD1 and the reference potential pattern LVS1 is provided in wiring layer WL8, and another of these is provided in wiring layer WL7. The example in Figures 11 and 12 shows that the power supply potential pattern LVD1 is provided in wiring layer WL8 and the reference potential pattern LVS1 in wiring layer WL7, but in a variation, the reference potential pattern LVS1 can be provided in wiring layer WL8 and the power supply potential pattern LVD1 can be provided in wiring layer WL7. As shown in Fig. 11, a pattern (the power supply potential pattern LVD1 in the example of Fig. 11) of the power supply potential pattern LVD1 and the reference potential pattern LVS1, arranged in the wiring layer WL8, has a planar shape extending along the outer edges of the contact pads 2LD, which are located adjacent to the power supply potential pattern LVD1 between the contact pads 2LD. The power supply potential pattern LVD1 comprises several wide parts LWD1 (see Fig. 13) with a width WV1W in the Y-direction, which intersects (in Fig. 11 is orthogonal to it) in a direction in which the power supply potential pattern LVD1 extends (in the X-direction in Fig. 11), and several narrow parts LND1 (see Fig. 13) with a width WV1N that is smaller than the width WV1W in the Y-direction. As shown in Fig. 13, the wide parts LWD1 and the narrow parts LND1 are arranged alternately in the direction (the X-direction) in which the power supply potential pattern LVD1 extends. As shown in Fig. 11, the width WV1W is greater than the separation distance GLD between adjacent contact surfaces 2LD across the power supply potential pattern LVD1 in the Y-direction. The narrow parts LND1 (see Fig. 13) and the wide parts LWD1 (see Fig. 13) overlap with a pattern (the reference potential pattern LVS1 in the example of Fig. 11) of the power supply potential pattern LVD1 and the reference potential pattern LVS1, which is arranged in the wiring layer WL7. As shown in Fig. 12, in the case of the third noise countermeasures, the presence of the wide parts LWD1 allows the area of ​​the facing part of the power supply potential pattern LVD1 and the reference potential pattern LVS1 to be made larger than that of the second noise countermeasures of Fig. 10. In the example of Fig. 11, the width WV1W is, for example, about 200 to 800 µm and is larger than the width WV4 of the power supply potential pattern LVD4 and the reference potential pattern LVS4 shown in Fig. 9. Thus, the mutual induction between the power supply potential pattern LVD1 and the reference potential pattern LVS1 is much greater than the mutual induction between the power supply potential pattern LVD4 and the reference potential pattern LVS4 shown in Figs. 9 and 10. Even when the third noise countermeasures of Figs. 11, 12 to 10 are used, the overall noise reduction is significantly greater than the combined induction between the power supply potential pattern LVD4 and the reference potential pattern LVS4 shown in Figs. 9 and 10.13 can be applied to a path with a path length DVDL (or path length DVSL) of 7 mm or more, such as the power supply potential supply path PVD1L or the reference potential supply path PVS1L shown in Fig. 6, therefore the influence of noise on the power supply potential supply path PVD1L can be reduced. As shown in the wide parts LWD1 and narrow parts LND1 in Fig. 13, the wide part LWD1 is defined as a portion of the power supply potential pattern LVD1 extending with a width WV1W, which can be considered essentially constant. The width WV1W is wider (larger) than the separation distance GLD between adjacent contact surfaces 2LD. Because the wide parts LWD1 are thus provided with a width WV1W greater than the separation distance GLD, the third noise countermeasures of Figs. 11 and 12 can achieve greater noise reduction than the second noise countermeasures of Figs. 9 and 10. In the example shown in Fig. 11, the width WV1W is narrower (smaller) than the center-to-center distance PLD between adjacent contact surfaces 2LD in the Y-direction. In a modified example described below, the width WV1W can be wider (larger) than the center-to-center distance PLD between adjacent contact surfaces 2LD in the Y-direction. The narrow part LND1 is defined as the part whose width is smaller than the width WV1W. Therefore, the width of the narrow part LND1 is not always constant, as shown in Fig. 13. The smallest width WV1N in the widths of the narrow parts LND1 is smaller than the separation distance GLD between adjacent contact surfaces in Fig. 11. As shown in Fig. 11, the narrow part LND1 (see Fig. 13) includes a wider portion than the separation distance GLD between adjacent contact surfaces 2LD. The shape of the narrow part LND1 is determined by the shape of a conductor pattern, for example, the contact surface 2LD adjacent to the power supply potential pattern LVD1. Therefore, the shape of the narrow part LND1 in Fig. 13 is exemplary and can be modified in various ways.However, the power supply potential pattern LVD1 is arranged such that it extends between adjacent contact surfaces 2LD in the Y direction, and thus each of the narrow parts LND1 includes at least one part with a width WV1N that is narrower (smaller) than the separation distance GLD between adjacent contact surfaces 2LD. Next, a form of the reference potential pattern LVS1 is described, which is arranged in the wiring layer WL7 such that it faces the power supply potential pattern LVD1 arranged in the wiring layer WL8. As shown in Fig. 13, in the present embodiment the power supply potential pattern LVD1 and the reference potential pattern LVS1 have a similar planar shape. More precisely, a pattern (the reference potential pattern LVS1 in the example of Fig. 11) of the power supply potential pattern LVD1 and the reference potential pattern LVS1, which is arranged in the wiring layer WL7, is designed such that in a transparent top view it mimics a shape of a pattern (the power supply potential pattern LVD1 in the example of Fig. 11) which is formed in the wiring layer WL8. In the Y-direction, several wide parts LWS1 (see Fig. 13) with width WV1W and several narrow parts LNS1 (see Fig. 13) with a width (e.g., WV1N) smaller than WV1W are provided in the Y-direction, which intersects (and is orthogonal to in Fig. 11) the direction (X-direction) in which the reference potential pattern LVS1 extends. The wide parts LWS1 and the narrow parts LNS1 are arranged alternately in the direction (X-direction) in which the reference potential pattern LVS1 extends. In the transparent top view, the narrow parts LND1 and the narrow parts LNS1 overlap each other, and the wide parts LWD1 and the wide parts LWS1 overlap each other. It should be noted that the definition of the broad part LWS1 is applicable to the definition of the broad part LWD1 by replacing the power supply potential pattern LVD1 with the reference potential pattern LVS1. Similarly, the definition of the narrow part LNS1 is applicable to the definition of the narrow part LND1 by replacing the power supply potential pattern LVD1 with the reference potential pattern LVS1. In this way, the reference potential pattern LVS1 and the power supply potential pattern LVD1 are largely aligned if the planar shape of the reference potential pattern LVS1 and the planar shape of the power supply potential pattern LVD1 are identical, if the narrow parts LND1 and the narrow parts LNS1 overlap, and if the wide parts LWD1 and the wide parts LWS1 overlap. This case is particularly advantageous because it allows a path to be reduced through which noise from other power supply paths or signal transmission paths can intrude. In the example shown in Fig. 11, the expression "designed to mimic" means that the reference potential pattern LVS1 and the power supply potential pattern LVD1 are formed in the same shape. However, this does not preclude minor shape differences due to manufacturing precision. For example, the shape of the reference potential pattern LVS1 and the shape of the power supply potential pattern LVD1 may not be partially identical due to limitations in the design of the wiring layer WL7 or the wiring layer WL8. In other words, the meaning of "designed to mimic" is not limited to a perfect match between the shape of the reference potential pattern LVS1 and the shape of the power supply potential pattern LVD1 in all paths.In this case too, if the shape of the reference potential pattern LVS1 partially matches that of the power supply potential pattern LVD1, the effects of the noise countermeasures described in this section will be achieved on the matching part. Preferably, however, 80% or more of all paths in the reference potential pattern LVS1 and 80% or more of all paths in the power supply potential pattern LVD1 are of the same shape and arranged to overlap. All paths described herein in the reference potential pattern LVS1 are defined as paths from one end of the reference potential pattern LVS1 (a via contact pad connected to a via not shown) to the other end thereof (a via 2LD connected to the reference potential pattern LVS1). All paths in the power supply potential pattern LVD1 are defined as paths from one end of the power supply potential pattern LVD1 (a via contact pad connected to a via not shown) to the other end thereof (a via 2LD connected to the power supply potential pattern LVD1). The expression “A is trained to imitate B” is used in the following description in the same sense unless a different interpretation with a different meaning is explicitly described. Although not shown, in a modified example of Figures 11 and 13, the planar shape of the reference potential pattern LVS1 formed in the wiring layer WL7 can be a belt shape with a width of WV1W extending in the Y direction. Even in this case, the power supply potential pattern LVD1 of Figures 11 and 13 is mostly oriented towards the reference potential pattern LVS1, and therefore this case is effective for countermeasures to reduce noise components penetrating the power supply potential pattern LVD1. However, in this case, part of the reference potential pattern LVS1 overlaps with a different conductor pattern (e.g., contact area 2LD) than the power supply potential pattern LVD1.With regard to suppressing the penetration of noise components into the reference potential pattern LVS1 formed in the wiring layer WL7 from the contact surface 2LD, the reference potential pattern LVS1 is preferably designed to mimic the shape of the power supply potential pattern LVD1 as shown in Fig. 11 and Fig. 13. <Abwandlungsbeispiele der dritten Rauschgegenmaßnahmen> Next, we describe variations of the third noise reduction measures shown in Figures 11, 12, and 13. Figure 14 is an enlarged top view of further exemplary noise reduction measures for the power supply potential pathways and reference potential pathways shown in Figure 6. Symbols in Figure 14 are given to schematically illustrate a state in which the power supply potential pattern LVD1 and the reference potential pattern LVS1 are inductively coupled. In the following variations, only the enlarged top view of Figure 11 is used, and the enlarged cross-sectional view of Figure 12 and the enlarged top view of Figure 13 are omitted, with Figures 12 and 13 being used for further description as needed. The modified example in Fig. 14 differs from the example in Fig. 11 in that the width WV1W of the wide parts LWD1 (see Fig. 13) in the power supply potential pattern LVD1 and the width WV1W of the wide parts LWS1 (see Fig. 13) in the reference potential pattern LVS1 are much larger. The contact surfaces 2LD are arranged at the same intervals in the example in Fig. 9 and the example in Fig. 14. In the example in Fig. 14, the width WV1W is greater than the center-to-center distance PLD between adjacent contact surfaces 2LD under the contact surfaces 2LD across the power supply potential pattern LVD1 in the Y-direction. In the modified example of Fig. 14, the path width of the facing part of the power supply potential pattern LVD1 and the reference potential pattern LVS1 can be made much larger than in the example of Fig. 11. Thus, the effect of reducing noise components penetrating the power supply potential pattern LVD1 or the reference potential pattern LVS1 is much greater than in the example of Fig. 11. On the other hand, in the example of Fig. 14, the area of ​​the power supply potential pattern LVD1 arranged between the contact surfaces 2LD is large, and therefore the example of Fig. 11 is more favorable with regard to increasing the degree of freedom in the design of the wiring connected to the contact surfaces 2LD, in other words, one degree of freedom in the design of the wiring layer WL8. That is, in the example of Fig. 11, the width WV1W is smaller than the center-to-center distance PLD between adjacent contact surfaces 2LD below the contact surfaces 2LD across the power supply potential pattern LVD1 in the Y-direction. In this case, the degree of freedom in the design of the wiring layer WL8 can be increased compared to the modified example of Fig. 14. Fig. 15 is an enlarged top view of another modification of Fig. 11. In Figs. 15 and 16, symbols are shown to schematically represent a state in which the power supply potential pattern LVD1 and the reference potential pattern LVS1 are inductively coupled. The modification of Fig. 15 differs from the example of Fig. 11 in that some of the contact surfaces 2LD are located at positions surrounded by the power supply potential pattern LVD1. In the modification of Fig. 15, the area of ​​the facing portion of the power supply potential pattern LVD1 and the reference potential pattern LVS1 can be made much larger than in the modification of Fig. 14. Thus, the effect of reducing noise components penetrating the power supply potential pattern LVD1 or the reference potential pattern LVS1 is much greater than in the example of Fig. 14. In the modified example of Fig. 15, several (two in Fig. 15) adjacent narrow parts LND1 are provided across the contact surface 2LD in the Y-direction. Although not shown, the width WV1W of the wide part LWD1 in the power supply potential pattern LVD1 can be made much larger. On the other hand, as described above, the example in Fig. 11 is more favorable with regard to increasing the degrees of freedom in the design of the wiring layer WL8. In the example in Fig. 15, it is necessary to connect the vias so that they overlap with the contact pads 2LD in order to electrically connect the other wiring layer and the contact pads 2LD, which are surrounded by the power supply potential pattern LVD1. Fig. 16 is an enlarged top view of another variation of Fig. 11. The variation in Fig. 16 differs from the examples in Fig. 9, Fig. 11, Fig. 14, and Fig. 15 in the arrangement pattern of the contact surfaces 2LD. In the example in Fig. 16, the center-to-center distance PLD1 between adjacent contact surfaces 2LD across the power supply potential pattern LVD1 is greater than the center-to-center distance PLD2 between adjacent contact surfaces 2LD in the direction (X-direction in Fig. 16) in which the power supply potential pattern LVD1 extends. The minimum width (i.e., the width WV1N) of the narrow part LWD1 is greater than the center-to-center distance PLD2. The modified example of Fig. 16 has a structure unlike the modified example of Fig. 15, which lacks the contact area 2LD surrounded by the power supply potential pattern LVD1. This structure allows the path width of the noise reduction component of the power supply potential pattern LVD1 and the reference potential pattern LVS1 to be much larger than in the modified example of Fig. 15. Therefore, the effect of reducing noise components penetrating the power supply potential pattern LVD1 or the reference potential pattern LVS1 can be much greater than in the example of Fig. 15. A reduction in the number of connections due to the application of the modification example of Fig. 16 can be suppressed if part of the power supply potential pattern LVD1 is used for the contact surfaces 2LD in the modification example of Fig. 16 (or if solder balls SB (see Fig. 4) are connected to the power supply potential pattern LVD1 exposed by openings formed in the insulating film SR2 (see Fig. 4) covering the power supply potential pattern LVD1). The variations shown in Figures 14, 15, and 16 demonstrate that the reference potential pattern LVS1, located in the wiring layer WL7, has the same planar shape as the power supply potential pattern LVD1, located in the wiring layer WL8. However, as described above, in one variation, the planar shape of the reference potential pattern LVS1 in the wiring layer WL7 can be a belt shape with a width WV1W extending in the Y direction. In another variation of the examples in Figures 14, 15, and 16, the reference potential pattern LVS1 can be located in the wiring layer WL8, while the power supply potential pattern LVD1 can be located in the wiring layer WL7. <Rauschgegenmaßnahmen mittels einer elektromagnetischen Abschirmung> A more advantageous aspect than the noise reduction measures described in Figs. 7, 8, 9, 10, 11, 12, 13, 14, 15 to 16 is described in a modified example in which a conductor pattern acting as an electromagnetic shield is arranged at the overlap position between the power supply potential pattern LVD1 and the reference potential pattern LVS1. Fig. 17 is an enlarged top view of an exemplary form of a conductor pattern formed in the third wiring layer counting from the bottommost wiring layer shown in Fig. 10. Wiring layer WL6 is located third closest to the bottom surface 2b after wiring layer WL7 (see Fig. 4). The enlarged cross-sectional view along line CC in Fig. 17 is similar to that of Fig. 10 and is therefore not shown again. Symbols in Fig.17 are shown to schematically illustrate a state in which the power supply potential pattern LVD1 and the reference potential pattern LVS1 are inductively coupled. The wiring substrate SUB1 described in Fig. 5 includes the reference potential pattern LVS2 (see Fig. 17), which is capable of supplying the reference potential VS2 to a circuit other than the analog circuit AC1 (such as the core circuit CC1). As shown in Fig. 10, the wiring layers in the wiring substrate SUB1 include the wiring layer WL6, which is the third closest to the lower surface 2b after the wiring layer WL7. As shown in Fig. 17, the reference potential pattern LVS2 is provided in the wiring layer WL6 and overlaps with the power supply potential pattern LVD4 and the reference potential pattern LVS4.The reference potential pattern LVS2, which is arranged to overlap with the power supply potential pattern LVD4 and the reference potential pattern LVS4, acts as an electromagnetic shield, thus preventing noise components from other conductors from penetrating the power supply potential pattern LVD4 and the reference potential pattern LVS4. Furthermore, instead of the reference potential pattern LVS2 of Fig. 17, a power supply potential pattern (not shown) can be used that is capable of supplying the power supply potential VD2 to a circuit other than the analog circuit AC1 (e.g., the core circuit CC1). However, the reference potential pattern LVS2 is a conductor pattern that forms part of the reference potential supply path PVS2, which is designed to supply a reference potential to many circuits other than the analog circuit AC1, and which has the lowest intrinsic noise among the conductor patterns contained in the wiring carrier SUB1. Therefore, the reference potential pattern LVS2 is particularly preferred for the conductor pattern used as electromagnetic shielding. In the example shown in Fig. 17, the power supply potential pattern LVD4, the reference potential pattern LVS4, and the reference potential pattern LVS2 extend in the same direction, overlapping each other in the transparent top view. The width WV2 of the reference potential pattern LVS2 is equal to the width WV4 of the power supply potential pattern LVD4 and the width WV4 of the reference potential pattern LVS4. In other words, the reference potential pattern LVS2 has the same planar shape as the power supply potential pattern LVD4 and the reference potential pattern LVS4. In a modified example of Fig. 17, in addition to the reference potential pattern LVS4 located in the wiring layer WL7, the large-area reference potential pattern LVS2 can also be provided, overlapping with the conductor patterns 2CP located on both sides of the reference potential pattern LVS4. If a potential supplied to the conductor patterns 2CP, which are arranged on both sides of the reference potential pattern LVS2 in the wiring layer WL6 of Fig. 17, is a different potential (or signal) than the reference potential VS2 of Fig. 5, one degree of freedom in the design of the wiring layer WL6 is improved by sufficiently minimizing the shape of the reference potential pattern LVS2 to act as an electromagnetic shield. Fig. 18 is an enlarged top view of an exemplary form of a conductor pattern formed in the third wiring layer, counting from the bottommost wiring layer shown in Fig. 12. Wiring layer WL6 is located third closest to the lower surface 2b after wiring layer WL7 (see Fig. 4). The enlarged cross-sectional view along line DD in Fig. 18 is similar to that in Fig. 12, therefore it is not shown again. The electromagnetic shielding described in Fig. 17 is applicable in combination with the structure described in Figs. 11, 12 to 13. As shown in Fig. 18, the reference potential pattern LVS2 is provided in the wiring layer WL6 and overlaps with the power supply potential pattern LVD1 and the reference potential pattern LVS1. The reference potential pattern LVS2, arranged to overlap with the power supply potential pattern LVD1 and the reference potential pattern LVS1, acts as electromagnetic shielding, thus preventing noise components from other conductor patterns from penetrating the power supply potential pattern LVD1 and the reference potential pattern LVS1. In the example of Fig. 18, the wide parts LWD1 (see Fig. 13) and the narrow parts LND1 (see Fig. 13) in the power supply potential pattern LVD1 and the wide parts LWS1 (see Fig. 13) and the narrow parts LNS1 (see Fig. 13) in the reference potential pattern LVS1 overlap with the reference potential pattern LVS2, which is formed in the wiring layer WL6. In a modified example of Fig. 18, the large-area reference potential pattern LVS2, which overlaps with the conductor patterns 2CP arranged on both sides of the reference potential pattern LVS1, can be provided in addition to the reference potential pattern LVS1 arranged in the wiring layer WL7 of Fig. 18. In the example of Fig. 18, the planar shape of the reference potential pattern LVS2 arranged in the wiring layer WL6 is the same as the planar shape of the reference potential pattern LVS1 arranged in the wiring layer WL7 and the planar shape of the power supply potential pattern LVD1 arranged in the wiring layer WL8. The reference potential pattern LVS2, the reference potential pattern LVS1, and the power supply potential pattern LVD1 extend in the same direction, overlapping each other in the transparent top view. More precisely, the reference potential pattern LVS2 formed in the wiring layer WL6 is designed in a transparent top view to mimic the shape of the power supply potential pattern LVD1 formed in the wiring layer WL8. Several wide parts LWS2 with a width WV1W and several narrow parts LNS2 with a width smaller than WV1W are provided in the Y-direction, which intersects (and is orthogonal to in Fig. 18) the direction in which the reference potential pattern LVS2 extends. The wide parts LWS2 and the narrow parts LNS2 are arranged alternately in the direction (X-direction) in which the reference potential pattern LVS2 extends. In the transparent top view, the narrow parts LND1 and the narrow parts LNS2 overlap each other, and the wide parts LWD1 and the wide parts LWS2 overlap each other. As shown in Fig. 18, one degree of freedom in the design of the wiring layer WL6 is improved by sufficiently minimizing the shape of the reference potential pattern LVS2 to act as an electromagnetic shield. The embodiments that use the reference potential pattern LVS2 as electromagnetic shielding and are described in Figures 17 and 18 are referred to as representative examples. However, the reference potential pattern LVS2 described in Figures 17 and 18 can be arranged in the wiring layer WL6 (see Figure 4) in any of the structures described in Figures 14, 15, and 16. In this case, it can suppress noise components from other conductor patterns from penetrating the power supply potential pattern LVD1 and the reference potential pattern LVS1, which are shown in Figures 14, 15, and 16. <musterbreite> Next, the widths of the reference potential pattern LVS1, the reference potential pattern LVS4, the power supply potential pattern LVD1, and the power supply potential pattern LVD4, as described in Figures 9, 10, 11, 12, 13, 14, 15, 16, 17 to 18, are described. Figure 19 is a top view for comparison of the width of the signal wiring designed to transmit an electrical signal to the analog circuit shown in Figure 5 and the widths of the wiring of the reference potential pattern and the power supply potential pattern shown in Figure 9 or Figure 11. The wiring substrate SUB1 of Fig. 5 comprises a wiring (signal wiring, signal wiring pattern) LSG (see Fig. 19) that forms part of the signal transmission path PSG1, designed to transmit a signal (electrical signal) SG1 to the analog circuit AC1. In other words, the analog circuit AC1 is electrically connected to the wiring (signal wiring, signal wiring pattern) LSG, which is capable of transmitting an electrical signal to the analog circuit AC1. As shown in Fig. 19, the width WV4 of the power supply potential pattern LVD4 and the width WV4 of the reference potential pattern LVS4, described in Fig. 9, are larger than the wiring width WSG of the wiring LSG. Similarly, the minimum width WV1N of the power supply potential pattern LVD1 and the minimum width WV1N of the reference potential pattern LVS1 are shown in Fig.As described in section 11, the wiring widths are greater than the wiring width WSG of the wiring LSG. Even if the conductor pattern designed to supply power to the analog circuit AC1 extends as described above, its width is greater than the wiring width WSG of the wiring LSG. Thus, as described above, the mutual induction can be increased by overlapping the power supply potential pattern LVD1 and the reference potential pattern LVS1 in the thickness direction, or by overlapping the power supply potential pattern LVD4 and the reference potential pattern LVS4 in the thickness direction, and thus the effect of reducing penetrating noise can be enhanced. <Trennungsabstand zwischen Mustern> Next, a separation distance between the patterns shown in Figures 10 and 20 is described. Figure 20 is an enlarged cross-sectional view of a modified example of the example in Figure 10 or Figure 12. The noise countermeasures and their modified examples described in Figures 7, 8, 9, 10, 11, 12, 13, 14, 15 to 16 are techniques for reducing the noise components penetrating the paths through inductive coupling of a power supply potential path and a reference potential supply path connected to the analog circuit. However, preferably, the penetration of noise into the power supply paths is suppressed to stabilize the power supply of the analog circuit. In the example shown in Fig. 20, a separation distance GWL8 between the power supply potential pattern LVD1 (or the power supply potential pattern LVD4), located in the wiring layer WL8, and the contact area 2LD is greater than an interlayer distance G78 between the wiring layer WL7 and the wiring layer WL8. The interlayer distance G78 can also be considered as the separation distance between the conductor pattern located in the wiring layer WL8 and the conductor pattern located in the wiring layer WL7 in the thickness direction. Making the separation distance GWL8 larger than the interlayer distance G78 can prevent the penetration of noise components and increase mutual induction. The invention devised by the inventors of the present application has been described in detail above with reference to its embodiments. It goes without saying, however, that the present invention is not limited to the embodiments described above and that various modifications are possible within the scope of the present invention.< / musterbreite> < / halbleitervorrichtung>

Claims

Semiconductor device (PKG1) comprising: a wiring substrate (SUB1) with an upper surface (2t), a lower surface (2b) facing the upper surface (2t), and several wiring layers (WL1-WL8) provided between the upper surface (2t) and the lower surface (2b); and a semiconductor chip (CHP1) with a first surface (3t), several bump electrodes (3BP) formed on the first surface (3t), and a second surface (3b) facing the first surface (3t), wherein the semiconductor chip (CHP1) is mounted over the several bump electrodes (3BP) on the upper surface (2t) of the wiring substrate (SUB1), wherein the semiconductor chip (CHP1) comprises a first analog circuit (AC1), wherein the several wiring layers (WL1-WL8) of the wiring substrate (SUB1) comprise: a first wiring layer (WL8),which is closest among the multiple wiring layers of the lower surface (2b) and is provided with multiple contact surface patterns (2LD); and a second wiring layer (WL7) which is second closest to the lower surface (2b) after the first wiring layer (WL8), wherein a first power supply potential pattern (LVD4), which can apply a first power supply potential (VD1) to the first analog circuit (AC1), and a first reference potential pattern (LVS4), which can apply a first reference potential (VS1) to the first analog circuit (AC1), are electrically connected to the first analog circuit (AC1), wherein one of the first power supply potential pattern (LVD4) and the first reference potential pattern (LVS4) is provided in the first wiring layer (WL8),wherein another of the first power supply potential pattern (LVD4) and the first reference potential pattern (LVS4) is provided in the second wiring layer (WL7), and wherein the first power supply potential pattern (LVD4) and the first reference potential pattern (LVS4) extend in the same direction (X) and overlap each other. Semiconductor device (PKG1) according to claim 1, wherein a first pattern of the first power supply potential pattern (LVD4) and the first reference potential pattern (LVS4) formed in the first wiring layer (WL8) is configured to have a planar shape along an outer edge of a contact pad pattern (2LD) adjacent to the first pattern among the multiple contact pad patterns (2LD), and to have multiple first wide parts (LWD1) with a first width (WV1W) in a first direction intersecting with a direction in which the first pattern extends, and multiple first narrow parts (LND1) with a width (WV1N) smaller than the first width (WV1W) in the first direction, wherein the multiple first wide parts (LWD1) and the multiple first narrow parts (LND1) are arranged alternately in the direction in which the first pattern extends.wherein the first width (WV1W) is greater than a separation distance (GLD) between adjacent contact surface patterns (2LD) across the first pattern in the first direction, and wherein the multiple first narrow parts (LND1) and the multiple first wide parts (LWD1) overlap with a second pattern formed from the first power supply potential pattern (LVD4) and the first reference potential pattern (LVS4) in the second wiring layer (WL7). Semiconductor device (PKG1) according to claim 2, wherein the second pattern of the first power supply potential pattern (LVD4) and the first reference potential pattern (LVS4) formed in the second wiring layer (WL7) is configured to mimic a shape of the first pattern formed in the first wiring layer (WL8) in a transparent top view, and to have several second wide parts (LWS1) with the first width (WV1W) in a second direction that intersects with a direction in which the second pattern extends, and several second narrow parts (LNS1) with a width that is smaller than the first width (WV1W), wherein the several second wide parts (LWS1) and the several second narrow parts (LNS1) are arranged alternately in the direction in which the second pattern extends.and wherein the several first narrow parts (LND1) and the several second narrow parts (LNS1) overlap each other, and the several first wide parts (LWD1) and the several second wide parts (LWS1) overlap each other. Semiconductor device (PKG1) according to claim 2, wherein the multiple contact surface patterns (2LD) are arranged at equal intervals, and wherein the first width (WV1W) is greater than a center-to-center distance (PLD) between adjacent contact surface patterns (2LD) over the first pattern in the first direction under the multiple contact surface patterns (2LD). Semiconductor device (PKG1) according to claim 4, wherein some of the multiple contact surface patterns (2LD) are located at positions surrounded by the first pattern. Semiconductor device (PKG1) according to claim 2, wherein the multiple contact surface patterns (2LD) are arranged at equal intervals and the first width (WV1W) is smaller than a center-to-center distance (PLD) between adjacent contact surface patterns (2LD) across the first pattern in the first direction under the multiple contact surface patterns (2LD). Semiconductor device (PKG1) according to claim 2, wherein a first center-to-center distance (PLD1) between adjacent contact surface patterns (2LD) across the first pattern among the multiple contact surface patterns (2LD) is longer than a second center-to-center distance (PLD2) between adjacent contact surface patterns (2LD) in the direction in which the first pattern extends, and a minimum width (WV1N) of the multiple first narrow parts (LND1) is greater than the second center-to-center distance (PLD2). Semiconductor device (PKG1) according to claim 1, wherein the wiring substrate (SUB1) has a second reference potential pattern (LVS2) that can apply a second reference potential (VS2) to a first circuit (CC1) that is not the first analog circuit (AC1), wherein the multiple wiring layers (WL1-WL8) in the wiring substrate (SUB1) further comprise a third wiring layer (WL6) that is the third closest to the lower surface (2b) after the second wiring layer (WL7), and wherein the second reference potential pattern (LVS2) is provided in the third wiring layer (WL6) and overlaps with the first power supply potential pattern (LVD4) and the first reference potential pattern (LVS4). Semiconductor device (PKG1) according to claim 8, wherein the first power supply potential pattern (LVD4), the first reference potential pattern (LVS4) and the second reference potential pattern (LVS2) extend in the same direction (X) and overlap each other. Semiconductor device (PKG1) according to claim 9, wherein the first pattern of the first power supply potential pattern (LVD4) and the first reference potential pattern (LVS4) formed in the first wiring layer (WL8) is configured to have a planar shape along an outer edge of a contact pad pattern (2LD) adjacent to the first pattern among the multiple contact pad patterns (2LD), and to have multiple first wide parts (LWD1) with a first width (WV1W) in a first direction intersecting with a direction in which the first pattern extends, and multiple first narrow parts (LND1) with a width (WV1N) less than the first width (WV1W) in the first direction, wherein the multiple first wide parts (LWD1) and the multiple first narrow parts (LND1) are arranged alternately in the direction in which the first pattern extends.wherein the first width (WV1W) is greater than a separation distance (GLD) between adjacent contact surface patterns (2LD) across the first pattern in the first direction, and wherein the multiple first narrow parts (LND1) and the multiple first wide parts (LWD1) overlap with a second pattern formed from the first power supply potential pattern (LVD4) and the first reference potential pattern (LVS4) in the second wiring layer (WL7), and overlap with the second reference potential pattern (LVS2) formed in the third wiring layer (WL6). Semiconductor device (PKG1) according to claim 10, wherein the second pattern of the first power supply potential pattern (LVD4) and the first reference potential pattern (LVS4) formed in the second wiring layer (WL7) is configured to mimic a shape of the first pattern formed in the first wiring layer (WL8) in a transparent top view, and to have several second wide parts (LWS1) with the first width (WV1W) in a second direction that intersects with a direction in which the second pattern extends, and several second narrow parts (LNS1) with a width that is less than the first width (WV1W), wherein the several second wide parts (LWS1) and the several second narrow parts (LNS1) are arranged alternately in the direction in which the second pattern extends, and wherein the several first narrow parts (LND1) and the several second narrow parts (LNS1) overlap each other.the multiple first wide parts (LWD1) and the multiple second wide parts (LWS1) overlap each other, and the multiple first narrow parts (LND1), the multiple second narrow parts (LNS1), the multiple first wide parts (LWD1) and the multiple second wide parts (LWS1) overlap in a transparent top view with the second reference potential pattern (LVS2) formed in the third wiring layer (WL6). Semiconductor device (PKG1) according to claim 1, wherein a third power supply potential pattern (LVD3) that can supply the first power supply potential (VD1) to the first analog circuit (AC1) and a third reference potential pattern (LVS3) that can supply the first reference potential (VS1) to the first analog circuit (AC1) are further electrically connected to the first analog circuit (AC1), wherein the third power supply potential pattern (LVD3) and the third reference potential pattern (LVS3) are formed in the same wiring layer (WL7) under the multiple wiring layers (WL1-WL8), wherein the third power supply potential pattern (LVD3) and the third reference potential pattern (LVS3) extend in the same direction (X), being adjacent to each other in the top view.and wherein a path segment of a first power supply potential supply path (PVD1L) from the respective hump electrode (3BP) of the semiconductor chip (CHP1) to the respective contact pad pattern (2LD) of the wiring substrate (SUB1), which includes the first power supply potential pattern (LVD4), is assumed to be the first path segment (DVDL); a path segment of a first reference potential supply path (PVS1L) from the respective hump electrode (3BP) of the semiconductor chip (CHP1) to the respective contact pad pattern (2LD) of the wiring substrate (SUB1), which includes the first reference potential pattern (LVS4), is assumed to be the second path segment (DVSL); a path segment of a third power supply potential supply path (PVD1S) from the respective hump electrode (3BP) of the semiconductor chip (CHP1) to the respective contact pad pattern (2LD) of the wiring substrate (SUB1), which the third service provision potential pattern (LVD3) includes,a third path path (DVDS) is assumed, and a path path of a third reference potential supply path (PVS1S) from the respective hump electrode (3BP) of the semiconductor chip (CHP1) to the respective contact pad pattern (2LD) of the wiring substrate (SUB1), which includes the third reference potential pattern (LVS3), is assumed to be the fourth path path (DVSS), the first path path (DVDL) being longer than both the third path path (DVDS) and the fourth path path (DVSS), and the second path path (DVSL) being longer than both the third path path (DVDS) and the fourth path path (DVSS). Semiconductor device (PKG1) according to claim 12, wherein the wiring substrate (SUB1) comprises a second reference potential pattern (LVS2) that can supply a second reference potential (VS2) to a first circuit (CC1) that is not the first analog circuit (AC1), and wherein the second reference potential pattern (LVS2) is formed among the multiple wiring layers in the wiring substrate (SUB1) in a wiring layer that is adjacent to a wiring layer in which the third power supply potential pattern (LVD3) and the third reference potential pattern (LVS3) are formed, and overlaps with the third power supply potential pattern (LVD3) and the third reference potential pattern (LVS3). Semiconductor device (PKG1) according to claim 2, wherein the first analog circuit (AC1) is electrically connected to a fourth power supply potential pattern (LVD1) that can supply the first power supply potential (VD1) to the first analog circuit (AC1) and a fourth reference potential pattern (LVS1) that can supply the first reference potential (VS1) to the first analog circuit (AC1), wherein one of the fourth power supply potential pattern (LVD1) and the fourth reference potential pattern (LVS1) is provided in the first wiring layer (WL8), wherein another of the fourth power supply potential pattern (LVD1) and the fourth reference potential pattern (LVS1) is provided in the second wiring layer (WL7), wherein the fourth power supply potential pattern (LVD1) and the fourth reference potential pattern (LVS1) extend in the same direction (X) and overlap each other in the transparent top view.wherein a third pattern of the fourth power supply potential pattern (LVD1) and the fourth reference potential pattern (LVS1), formed in the first wiring layer (WL8), extends over a third width (WV4), the third width (WV4) being smaller than a separation distance (GLD) between adjacent contact pad patterns (2LD) across the third pattern in a third direction intersecting with a direction in which the third pattern extends, and wherein a path segment of a first power supply potential supply path (PVD1L) from the hump electrode (3BP) of the semiconductor chip (CHP1) to the respective contact pad pattern (2LD) of the wiring substrate (SUB1) encompassing the first power supply potential pattern (LVD4) is assumed to be the first path segment (DVDL),a path segment of a first reference potential supply path (PVS1L) from the respective hump electrode (3BP) of the semiconductor chip (CHP1) to the respective contact pad pattern (2LD) of the wiring substrate (SUB1), which includes the first reference potential pattern (LVS4), is assumed to be the second path segment (DVSL); a path segment of a fourth power supply potential supply path (PVD1M) from the respective hump electrode (3BP) of the semiconductor chip (CHP1) to the respective contact pad pattern (2LD) of the wiring substrate (SUB1), which includes the fourth power supply potential pattern (LVD1), is assumed to be the fifth path segment (DVDM); and a path segment of a fourth reference potential supply path (PVS1M) from the respective hump electrode (3BP) of the semiconductor chip (CHP1) to the respective contact pad pattern (2LD) of the wiring substrate (SUB1), which includes the fourth Reference potential pattern (LVS1) is included, which is assumed to be the sixth path segment (DVSM),The first path segment (DVDL) is longer than both the fifth path segment (DVDM) and the sixth path segment (DVSM), and the second path segment (DVSL) is longer than both the fifth path segment (DVDM) and the sixth path segment (DVSM). Semiconductor device (PKG1) according to claim 2, wherein a separation distance (GWL8) between the first pattern and a contact surface pattern (2LD) adjacent to the first pattern is longer than an interlayer distance (G78) between the first wiring layer (WL8) and the second wiring layer (WL7). Semiconductor device (PKG1) according to claim 1, wherein the first analog circuit (AC1) is further electrically connected to a first signal pattern (LSG) that can transmit an electrical signal (SG1) to the first analog circuit (AC1), and wherein a width of the first power supply potential pattern (LVD4) and a width of the first reference potential pattern (LVS4) are each greater than a width of the first signal pattern (LSG). Semiconductor device (PKG1) according to claim 1, wherein a width of the first power supply potential pattern (LVD4) and a width of the first reference potential pattern (LVS4) are each greater than a thickness of the first power supply potential pattern (LVD4) and a thickness of the first reference potential pattern (LVS4).

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