Method for manufacturing a superconducting integrated circuit

Abstract

A method for fabricating a superconducting integrated circuit on a substrate involves forming a first superconducting layer of a superconducting material over the substrate. A Josephson contact (JJ) layer stack with a JJ junction is formed over the first superconducting layer. The JJ layer stack is structured to form a JJ structure. The first superconducting layer is structured to form a structured first superconducting layer. A dielectric cover layer is formed over the JJ structure. The dielectric cover layer is structured to expose a top surface of the JJ structure. A second superconducting layer of a superconducting material is formed over the dielectric cover layer. The second superconducting layer is structured to form a structured second superconducting layer.

Description

Technical area

[0001] This disclosure relates generally to the field of superconducting integrated circuits and, in particular, to integration concepts for Josephson junctions on substrates. background

[0002] Electronic devices containing a superconducting integrated circuit are used in various fields of technology. For example, quantum computers, which operate with one or more superconducting quantum bits (qubits), are based on superconducting integrated circuits.

[0003] Quantum computing is a method that promises to solve certain tasks significantly faster than conventional computers. One approach to implementing circuits for such a computer is the creation of qubits with superconducting Josephson junctions and capacitors.

[0004] Superconducting integrated circuits with Josephson junctions are also used in single-flux quantum devices (SFQs) and traveling-wave parametric amplifiers (TWPAs).

[0005] Most manufacturing methods today use techniques such as shadow mask deposition and liftoff to realize these circuits. These processes have issues with reproducibility and defect density and generally do not allow for significant scaling in terms of dimensions and stacking.

[0006] WO 2018 / 093544 A1 describes a method for forming a superconducting structure based on a Josephson junction. In the method, a Josephson junction layer stack is formed over a base electrode, and the Josephson junction is etched out of the layer stack.

[0007] The invention is defined by the features of the independent claims. Embodiments and further developments are the subject of the dependent claims. Short description of the drawings

[0008] The elements in the drawings are not necessarily to scale. Like reference numerals indicate corresponding similar parts. The features of the various illustrated embodiments may be combined, provided they are not mutually exclusive, and / or they may be selectively omitted unless described as essential. The embodiments are illustrated in the drawings and are further described by way of example in the following description. The Fig. 1 to 5 are schematic cross-sectional views showing the steps of a method for manufacturing a superconducting integrated circuit on a substrate according to a first embodiment. The Fig. 6 to 8 are schematic cross-sectional views showing the steps of a method for manufacturing a superconducting integrated circuit on a substrate according to a second embodiment. The Fig. 9 to 18 are schematic cross-sectional views showing the steps of a method for manufacturing a superconducting integrated circuit on a substrate according to a third embodiment. Detailed description

[0009] The words "over" or "under" or similar words, when referring to a part, element, or layer of material that is shaped, attached, arranged, or placed "over" or "under" a surface, may be used herein to mean that the part, element, or layer of material is located "directly on" or "directly under," i.e., in direct contact with the implied surface (e.g., placed, shaped, arranged, placed, etc.). However, the word "over" or "under" or similar terms, when used to refer to a part, element, or layer of material that is shaped, attached, or placed "over" or "under" a surface, may also be used herein to mean that the part, element, or layer of material is located "indirectly on" or "indirectly under" the implied surface (e.g., placed, shaped, arranged, deposited, etc.).), wherein one or more additional parts, elements or layers are arranged between the surface in question and the part, element or layer of material.

[0010] The following description refers, by way of example, to methods for fabricating a superconducting integrated circuit containing a Josephson junction on a substrate. Superconducting integrated circuits (or devices) that use a Josephson junction are examples of superconducting quantum circuits (or devices) because the Josephson effect is based on a quantum mechanical tunneling process.

[0011] The methods can be used, for example, to manufacture quantum computers. However, the disclosure is not limited to methods for manufacturing quantum computing devices. Rather, the disclosure generally encompasses all methods for manufacturing superconducting integrated circuits that include a Josephson junction, i.e., superconducting Josephson junction quantum circuits.

[0012] In some examples, the superconducting integrated circuit may, for example, include or be a resonant circuit. A resonant circuit typically comprises (at least) a capacitor and an inductor. The resonant circuit may be a linear resonant circuit (e.g., a harmonic oscillator) or a nonlinear resonant circuit (e.g., an anharmonic oscillator). In quantum devices, such resonant circuits are also called quantum oscillators (QOs).

[0013] A well-known technique used in quantum computing, for example, is to use a Josephson junction to make an oscillating circuit nonlinear (or, in other words, to make the oscillator potential anharmonic). In quantum computers, anharmonic quantum oscillators are used to "form" qubits. In other words, a nonlinear oscillating circuit can "form" (or operate) a qubit. Qubits created by one or more (nonlinear) Josephson junctions in a (thus nonlinear) oscillating circuit are sometimes referred to in the scientific community as "Josephson qubits."

[0014] Further examples of superconducting Josephson junction quantum circuits are parametric Josephson or traveling-wave amplifiers (TWPAs). These devices offer high gain and quantum-limited noise. For example, for the construction of a large-scale multi-quantum processor with multiple qubits, qubit readout by multiplexing is desirable, which requires amplifiers with wide bandwidth, high gain, and low noise. Parametric traveling-wave amplifiers (TWPAs) offer such a capability.

[0015] Other examples of electronic devices containing a superconducting integrated circuit are single-flux quantum (SFQ) devices. These devices are transistor-like components that use voltage pulses generated by Josephson junctions in the superconducting electronic (quantum) circuit (instead of the voltage levels generated by transistors in semiconductor electronics) to encode, process, and transmit digital information. A superconducting integrated circuit containing a large number of SFQ devices enables the formation of (R)SFQ ((rapid) single flux quantum) logic.

[0016] As in Fig. 1, a substrate 110 is provided. The substrate 110 may, for example, comprise or be a sapphire substrate or a silicon substrate, in particular a highly resistive crystalline silicon substrate. The substrate 110 serves as a carrier for a superconducting integrated circuit to be constructed thereon. The substrate 110 may, for example, be unstructured or unprocessed. In particular, no integrated circuits or integrated components are formed on the substrate 110, for example.

[0017] A first superconducting layer 120 made of a superconducting material is formed over the substrate 110. The first superconducting layer may be an unstructured, continuous layer, which may, for example, be applied over the entire substrate 110.

[0018] The first superconducting layer 120 can be applied by a CVD (chemical vapor deposition) or PVD (physical vapor deposition) process, in particular by sputtering. The superconducting material is a material that can become superconducting at the operating temperature of the superconducting integrated circuit to be formed. The term "superconducting" therefore refers to the conductivity of the material at the operating temperature of the circuit. The superconducting material can contain or consist of, for example, Al, Nb, or Ta.

[0019] The first superconducting layer 120 can then be patterned to form a patterned first superconducting layer (also designated by reference numeral 120). The patterned first superconducting layer 120 contains structures 120_1, 120_2, 120_3 made of the superconducting material. The structures 120_1, 120_2, 120_3 can, for example, be electrically and / or structurally separated from each other.

[0020] The patterning of the first superconducting layer 120 can be performed, for example, by a patterning process using a photolithographic mask, a photoresist (not shown), and an etching process. Other patterning processes compatible with semiconductor manufacturing can also be used.

[0021] Subsequently, a first dielectric base layer 130 can be formed over the structured first superconducting layer 120. The first dielectric base layer 130 can be a continuous, unstructured layer of a dielectric material. The first dielectric base layer 130 can cover the entire substrate 110. The dielectric material can, for example, comprise or consist of silicon oxide or silicon nitride, or a combination (oxynitride) of these materials.

[0022] The first dielectric base layer 130 can then be patterned to form exposed regions 122_2, 122_3 of the patterned first superconducting layer 120 (or more precisely, the structures 120_2, 120_3 of the patterned first superconducting layer 120). The patterned first dielectric base layer 130 can partially or completely cover regions of the substrate 110 in which the superconducting material of the first superconducting layer 120 has been removed. Furthermore, the patterned first dielectric base layer 130 can partially cover at least some of the structures 120_1, 120_2, 120_3 of the patterned first superconducting layer 120.

[0023] The structuring of the first dielectric base layer 130 can be performed by structuring methods (e.g., lithography and etching), as already mentioned in connection with the structuring of the first superconducting layer 120. In other words, the first dielectric base layer 130 is opened at selected regions of the structures 122_2, 122_3 of the structured first conductive layer 120, so that at least a portion of the structures 122_2, 122_3 is exposed.

[0024] In Fig. 2, a Josephson junction layer stack 210 is formed over the first superconducting layer 120 (which in this embodiment is already structured into unconnected structures 120_1, 120_2, 120_3). The JJ layer stack 210 can be a continuous, unstructured layer stack formed in Fig. 2 is represented by the dashed-dotted line. The JJ layer stack 210 can, for example, cover the entire substrate 110.

[0025] The JJ layer stack 210 includes a JJ barrier layer (not shown). The JJ barrier layer is the functional layer of the JJ layer stack 210 that provides JJ tunneling.

[0026] The JJ layer stack 210 may, for example, comprise or be a three-layer stack of a superconducting / tunnel barrier / superconducting material. Possible three layers include, but are not limited to, Al / AlOx / Al, Nb / AlOx / Nb, or Ta / AlOx / Ta layer stacks. Barrier layers other than AlOx may also be used (e.g., MgOx, etc.), and various combinations of superconducting materials may also be used.

[0027] The JJ layer stack 210 may be deposited by sputtering or another suitable deposition process. Fig. 1 to 5, the JJ layer stack 210 may have a topography (ie, may not be planar) due to the previous patterning process(es).

[0028] As in Fig. 2, the JJ layer stack 210 is then patterned to form a JJ structure 212. In particular, the portions of the JJ layer stack 210 that overlie (overlap) the patterned first dielectric base layer 130 may be completely removed.

[0029] The patterning of the JJ layer stack 210 may include etching processes. For example, reactive ion etching (RIE) may be used for the metallic and dielectric etching of the JJ layer stack 210 to form the JJ structure 212. RIE is anisotropic and therefore suitable for forming the JJ structure 212 with (approximately) vertical sidewalls. As shown in Fig. 2, the JJ structure 212 is electrically contacted on its underside with a structure 120_2 of the structured first superconducting layer 120.

[0030] As in Fig. 3, a dielectric cap layer 330 is then formed over the JJ structure 212. The dielectric cap layer 330 may be an unpatterned, continuous layer, e.g., covering the entire substrate 110. The dielectric cap layer 330 may comprise or consist of one of the dielectric materials mentioned above in connection with the first dielectric base layer 130. The dielectric material of the dielectric cap layer 330 and the dielectric material of the first dielectric base layer 130 may be the same dielectric materials. In other examples, the dielectric material of the dielectric cap layer 330 and the dielectric material of the first dielectric base layer 130 may be different dielectric materials (and may therefore be selectively patterned).

[0031] As in Fig. 3, the dielectric cap layer 330 is then patterned a first time to expose a top surface of the JJ structure 212. In other words, the dielectric cap layer 330 is opened on top of the JJ structure 212.

[0032] Furthermore, the dielectric cap layer 330 and the first dielectric base layer 130 may be opened at one or more selected locations 340 above one or more structures 120_1, 120_2, 120_3 of the (structured) first superconducting layer 120. In the example of Fig. 3, a selected location 340 where the dielectric cap layer 330 and the first dielectric base layer 130 are opened is shown above the structure 120_1. In other examples (not shown), an opening may be created at locations where only the dielectric cap layer 330 or only the first dielectric base layer 130 is present.

[0033] The resulting structure may include regions on the patterned first superconducting layer 120 on which no dielectrics are located (here the structure 120_1 at location 340), regions covered by dielectrics with a thickness T1 determined by the dielectric cap layer 330, as shown, for example, at selected location 350 above the structure 120_3, and regions with thicker dielectrics on top, such as those formed by the dielectric cap layer 330 and the first dielectric base layer 130 with a total thickness T2 (with T2 > T1).

[0034] As described in more detail below, the opening at the selected location 340 can be used for contact formation (e.g., the formation of pads), the dielectric regions with a thickness T1 can be used for the formation of capacitors with a high area capacitance, and the dielectric regions with a thickness T2 can be used for the formation of capacitors with a lower area capacitance. In other words, the combination of the first dielectric base layer 130 and the dielectric cap layer 330 offers the possibility of having different area capacitances. This provides flexibility in the design of the superconducting integrated circuit. In particular, TWPAs can use capacitors with different capacitances in the superconducting integrated circuit.

[0035] As in Fig. As shown in Figure 4, a second superconducting layer 420 is formed from a superconducting material over the dielectric cap layer 330. The material of the second superconducting layer 420 may include or consist of one or more of the materials mentioned above for the first superconducting layer 120. The superconducting material of the first superconducting layer 120 and the superconducting material of the second superconducting layer 420 may, for example, be identical or different.

[0036] The second superconducting layer 420 is structured to form a structured second superconducting layer (also designated by reference numeral 420 below). Structuring the second superconducting layer 420, for example, forms the structures 420_1, 420_2, and 420_3. The structures 420_1, 420_2, and 420_3 can, for example, be structurally and / or electrically separated from one another.

[0037] A portion of the structured second superconducting layer 420, in this example, structure 420_1, can be arranged opposite structure 120_1 of the structured first superconducting layer 120, with the first dielectric base layer 130 and the dielectric cap layer 330 located therebetween. Since the thickness T2 can be selected to be relatively large, this arrangement can form a capacitor C1 with a low surface capacitance.

[0038] Another part of the patterned second superconducting layer 420, in this example, pattern 420_2, may form a contact to the top surface of the JJ structure 212. In other words, pattern 120_2 of the patterned first superconducting layer 120 and pattern 420_2 of the patterned second superconducting layer 420 may be used to contact the JJ structure 212 at the bottom and top, respectively.

[0039] The structure 420_2 can, for example, be further connected to the structure 120_1 of the structured first superconducting layer 120. For example, the structure 420_1 of the structured second superconducting layer 420 can overlie and fill the opening at the selected location 340 in the first dielectric base layer 130 and the dielectric cap layer 330. In this way, a via V is formed that connects a portion of the structured first superconducting layer 120 (e.g., the structure 120_1) and a portion of the structured second superconducting layer 420 (e.g., the structure 420_2).

[0040] A superconducting integrated circuit on substrate 110 may include or consist of the JJ structure 212, the via V, and the capacitor C1. As described above, the implementation of such a superconducting integrated circuit utilizes integration schemes that enable the formation of superconducting circuits including a JJ structure (e.g., a three-layer JJ structure) 212 using processes that are compatible with and scalable for semiconductor manufacturing.

[0041] Furthermore, at a selected location 350, a portion of the structured second superconducting layer (e.g., structure 420_3) may be arranged opposite a portion of the structured first superconducting layer 120 (e.g., structure 120_3), with the dielectric capping layer 330 having a thickness T1 disposed therebetween. This arrangement may form a capacitor C2 with a high surface capacitance (C2 > C1). The capacitance C2 of the capacitor C2 depends on the thickness T1 and the lateral size of the capacitor C2.

[0042] The capacitance C2 can be in the pF range, e.g., in a range between 1 pF and 100 pF, in particular between 10 pF and 50 pF. The capacitance of the capacitor C1 can be in the range of 10 fF, e.g., in a range between 5 fF and 500 fF, in particular between 10 fF and 100 fF.

[0043] The capacitor C2 may, for example, be electrically connected to (and thus form part of) the superconducting integrated circuit. In one example, the structure 120_2 of the patterned first superconducting layer 120 may be connected by a wire (not shown) to the structure 420_3 of the second superconducting layer 420. In other examples, the structures 120_2 and 120_3 may, for example, be continuous (i.e., connected to each other), so that a structure (corresponding to the structures 120_2 and 120_3) of the patterned first dielectric base layer 130 can simultaneously form a contact for the JJ structure 212 and a plate of the capacitor C2.

[0044] Subsequently, the entire assembly (substrate 110 with patterned superconducting layers 120, 420 and dielectric layer(s) 130 and 330) can be encapsulated with a passivation layer (not shown). In other examples, no passivation layer is applied.

[0045] As in Fig. 5, the dielectric capping layer 330 may be patterned a second time at the selected location 550. The second patterning of the dielectric capping layer 330 is performed after the second superconducting layer 420 has been patterned. As shown in Fig. As shown in Figure 5, the first dielectric base layer 130 can be opened simultaneously with the opening of the dielectric cover layer 330. In this way, a contact pad region of a contact pad P can be defined. The contact pad P enables the establishment of electrical contact with external circuits (not shown).

[0046] The superconducting integrated circuit may include further contact pads P. For example, the structure 120_1 and / or the structure 120_3 of the structured first superconducting layer 120 may also be connectable by similar contact pads (not shown) at other selected locations.

[0047] In the Fig. In the exemplary embodiment illustrated in Figures 1 to 5, the first dielectric base layer 130 is formed before the JJ layer stack 210 is formed over the patterned first superconducting layer 120. In other embodiments, the first dielectric base layer 130 may, for example, be formed after the JJ layer stack 210 has been formed over the first superconducting layer 120.

[0048] With reference to the Fig. 6 to 8, which show exemplary stages of a second embodiment of the fabrication of a superconducting integrated circuit, the first superconducting layer 120 of superconducting material is formed over the substrate 110, such as in connection with Fig. 1 described.

[0049] Subsequently, the JJ layer stack 210 is formed with a JJ barrier layer over the first superconducting layer 120. To avoid repetition, reference is made to the above description.

[0050] In the second embodiment, the JJ layer stack 210 can be deposited on the unpatterned first superconducting layer 120. The deposition of the first superconducting layer 120 and the JJ layer stack 210 can be performed in a single process step. Thus, no intermediate processes, such as the patterning of the first superconducting layer 120 and / or the deposition of a dielectric layer on the first superconducting layer 120 and / or the patterning of such a deposited dielectric layer, need to be performed prior to the patterning of the JJ layer stack 210. The JJ layer stack 210 can be planar.

[0051] As in Fig. As shown in Figure 7, the JJ layer stack 210 may be patterned to create the JJ structure 212 before the first superconducting layer 120 is patterned. The JJ structure 212 may be formed from the JJ layer stack 210 by patterning the JJ layer stack 210 by etching as described above, e.g., down to the tunnel barrier in the JJ layer stack 210.

[0052] Subsequently, the dielectric cap layer 330 can be formed over the JJ structure 212.

[0053] Subsequently, the first superconducting layer 120 is patterned. The patterning of the first superconducting layer 120 can be performed, for example, by opening the dielectric cover layer 330 at selected locations 710 and 720. In other words, the patterned dielectric cover layer 330 can be used as a mask layer for patterning the first superconducting layer 120, for example, by an etching process. In this way, the structures 120_2, 120_4, and 120_5 of the first superconducting layer 120 can be formed.

[0054] Subsequently, a further cover layer 830 made of a dielectric material is formed over the structured cover layer 330, the JJ structure 212 and the substrate 110, see Fig. 8.

[0055] The following manufacturing processes of the second embodiment may, for example, be similar or identical to those described above in connection with the Fig. 3 to 5, and reference is made to the above description to avoid repetition. In short, similar to Fig. 3, the cover layers 330, 830 can be opened over the JJ structure 212 and optionally over other parts of the structured first superconducting layer 120. For example, the cover layers 330, 830 can be opened similarly to Fig. 5 may be opened at a selected location 550 above the structure 120_4 to form a pad on the structure 120_4.

[0056] Structure 120_5 can, for example, be used to implement a resonator R that is capacitively coupled (reference symbol CC) to structure 120_4 (which may be provided with a contact pad). In this example, the capacitive coupling CC is achieved in the lateral dimension, i.e., structure 120_4 and structure 120_5 can form a lateral capacitor. The capacitance of this lateral capacitor depends, among other things, on the distance between structure 120_4 and structure 120_5, i.e., on the lateral dimension of the selected location 710.

[0057] The structure 120_5 (which may form a resonator R) may also be coupled to the structure 120_2 carrying the JJ structure 212 by lateral capacitive coupling CC. In other examples, the structure 120_5 may be coupled to the second superconducting layer 420 (see Fig. 4) be connected in the same way as in connection with the first embodiment ( Fig. 1 to 5). In other words, with reference to the Fig. 6 to 8, the second embodiment illustrated comprises the steps of structuring the cover layers 330, 830, applying the second superconducting layer 420, structuring the second superconducting layer 420 (see Fig. 4) and, if necessary, opening the cover layers 330, 830 at selected locations 550 (see Fig. 5) in the same manner as described above.

[0058] With reference to the Fig. 9 to 18, a third embodiment of a method for manufacturing a superconducting integrated circuit on a substrate 110 is described.

[0059] In this embodiment, a first superconducting layer 120 made of a superconducting material is formed over the substrate 110. As previously mentioned, the first superconducting layer 120 may be a continuous, unstructured layer.

[0060] Similar to what was already said in connection with Fig. 1, the first superconducting layer 120 is structured to form a structured first superconducting layer 120. For example, the structures 120_2, 120_4 and 120_5 may be as shown in Fig. 8 shown.

[0061] Subsequently, a first dielectric base layer 130 is formed over the structured first superconducting layer 120. In this regard, to avoid repetition, reference is made to the description in connection with Fig. 1. The material of the first dielectric base layer 130 can be any of the above-mentioned hard passivation materials, e.g., silicon nitride.

[0062] Subsequently, a second dielectric base layer (not shown) is formed over the first dielectric base layer 130. The dielectric material of the second dielectric base layer may be different from the dielectric material of the first dielectric base layer 130. The dielectric material of the first dielectric base layer 130 may be, for example, silicon nitride, and the material of the second dielectric base layer may be, for example, silicon oxide.

[0063] The second dielectric base layer can then be selectively thinned down to the first dielectric base layer 130 (e.g., polished back by chemical mechanical polishing (CMP)). In the regions where the superconducting material of the structured first superconducting layer 120 remains (e.g., structures 120_2, 120_4, 120_5), the first dielectric base layer 130 is exposed, while the gaps can be filled by plugs 1040 made of the dielectric material of the second dielectric base layer (see Fig. 10).

[0064] Subsequently, a third dielectric base layer 140 may be formed over the first dielectric base layer 130 and the plugs 1040 constructed from the second dielectric base layer. The material of the third dielectric base layer 140 may, for example, be the same dielectric material as the material of the first dielectric base layer 130. In some examples, a low-loss dielectric material such as silicon nitride is used.

[0065] The third dielectric base layer 140 may be an unstructured, continuous layer, which, for example, covers the entire surface of the Fig. 11 shown arrangement.

[0066] Subsequently, the first dielectric base layer 130 and the third dielectric base layer 140 (which may be made of the same material) may be formed as described in connection with Fig. 1. In this way, exposed regions of the structured first superconducting layer 120 can be formed (cf. exposed regions 122_2 and 122_3 in Fig. 1).

[0067] Subsequently, a JJ layer stack with a JJ barrier layer (cf. Fig. 2, reference numeral 210). The JJ layer stack ( Fig. 2, reference numeral 210) is then patterned to form the JJ structure 212.

[0068] Subsequently, a dielectric cap layer 330 may be formed over the device, as in Fig. 12. The dielectric cap layer 330 covers the JJ structure 212.

[0069] The dielectric cap layer 330 may then be opened a first time to expose a top surface of the JJ structure 212, as described in connection with Fig. 3. The opening of the dielectric cap layer 330 on top of the JJ structure 212 can be achieved by a special via etching process, e.g., by using RIE.

[0070] Alternatively, as in Fig. 13, the dielectric capping layer 330 may have a thickness equal to or greater than the thickness of the JJ structure 212. In this case, the (thick) dielectric capping layer 330 may be thinned (e.g., polished back by CMP) until the top of the JJ structure 212 is exposed (see Fig. 13). For example, the third dielectric base layer 140 may be omitted in this process.

[0071] The following methods can be performed in any of the previously described embodiments. Some of them have already been described in these embodiments, and reference is made to the above description to avoid repetition.

[0072] As in Fig. 14, a second superconducting layer 420 made of a superconducting material is formed over the dielectric cap layer 330. Prior to this, the dielectric layer(s) between the patterned first superconducting layer 120 and the second superconducting layer 420 may be opened to form a via contact V to the patterned first superconducting layer 120 (e.g., its structure 120_2). The second superconducting layer 420 may then be patterned to form a patterned second superconducting layer 420. For example, a region of the second superconducting layer 420 that overlaps the dielectric plugs 1040 may be removed.

[0073] Optionally, the dielectric plugs 1040 may then be removed to reduce the losses in the dielectric layer structure (e.g., consisting of the first dielectric base layer 130, the dielectric cap layer 330, and optionally the third dielectric base layer 140). This may be achieved by forming holes in the low-loss dielectric layer(s) 330, 140 above the dielectric plugs 1040 and by selectively removing the dielectric material of the dielectric plugs 1040 through these holes ( Fig. 15).

[0074] As in Fig. 15, the dielectric cap layer 330 and, for example, other low-loss dielectric layers, such as, for example, the first dielectric base layer 130 and optionally the third dielectric base layer 140, may be opened a second time to form a pad P of the superconducting integrated circuit, for example, on the structure 120_4 of the patterned first superconducting layer 120.

[0075] As in connection with the second embodiment ( Fig. 6 to 8), the structure 120_5 can form a resonator R that is capacitively coupled to the structure 120_4 and optionally to the structure 120_2 of the structured first superconducting layer 120 (CC). In Fig. 15, the reference symbol LLD refers to low-loss dielectric layers, which can be realized, for example, by dielectric layers 130, 330 and optionally 140 as described above.

[0076] As in Fig. As shown in Figure 16, prior to a contact pad opening of the low-loss dielectric layer(s) at P, a dielectric protection layer 1630 may be formed. The dielectric protection layer 1630 may, for example, be a continuous, unstructured layer that may cover the entire device. The dielectric protection layer 1630 (already mentioned) may cover the low-loss dielectric layer LLD and the structured second superconducting layer 420. The dielectric protection layer 1630 may be made of one of the aforementioned dielectric materials, in particular of a low-loss dielectric material such as silicon nitride.

[0077] In some examples, the dielectric protection layer 1630 may be planarized, e.g., by CMP. The planarized dielectric protection layer 1630 may then be used as a support for stacking to create stacked superconducting integrated circuits, and the process sequences described above may be repeated. This enables, e.g., multi-level integration of JJ structures 212 and other superconducting circuit elements above the Fig. 16 shown arrangement.

[0078] In some examples, a resistance element 1710 (see Fig. 17) into the superconducting integrated circuit. A possible method for integrating a resistance element is described in connection with Fig. 16. After planarizing the dielectric protection layer 1630, the dielectric protection layer 1630 may be opened at selected locations 1640, 1650 above the patterned second superconducting layer 420 (e.g., above its structure 420_2 and structure 420_1).

[0079] Subsequently, a metal layer that remains resistive at (cryogenic) operating temperatures can be deposited and patterned to create a resistive element 1710 with the desired resistance. The material of the resistive element 1710 (and thus of the metal layer from which the resistive element 1710 is constructed) can, for example, comprise copper or be made of copper. The resistive element 1710 can contact the structure 420_2 and the structure 420_1 of the patterned second superconducting layer 420 through the openings at selected locations 1640 and 1650, respectively. The integration of a resistive element 1710 enables the formation of a superconducting integrated circuit containing, for example, (R)SFQ logic.

[0080] As in Fig. 18, a further dielectric protective layer 1830 can then be applied over the Fig. 17 shown arrangement.

[0081] Subsequently, the dielectric layers (e.g., the low-loss dielectric layer LLD and optionally the dielectric protection layers 1630, 1830) may be opened to form a contact pad P over a part (e.g., the structure 120_4) of the structured first superconducting layer 120.

[0082] The following examples refer to further aspects of the revelation:

[0083] Example 1 is a method for fabricating a superconducting integrated circuit on a substrate, comprising forming a first superconducting layer made of a superconducting material over the substrate. A Josephson junction (JJ) layer stack having a JJ junction layer is formed over the first superconducting layer. The JJ layer stack is patterned to form a JJ structure. The first superconducting layer is patterned to form a patterned first superconducting layer. A dielectric cap layer is formed over the JJ structure. The dielectric cap layer is patterned a first time to expose a top surface of the JJ structure. A second superconducting layer made of a superconducting material is formed over the dielectric cap layer. The second superconducting layer is patterned to form a patterned second superconducting layer.

[0084] In Example 2, the subject matter of Example 1 in the first to third embodiments may optionally further comprise patterning the dielectric cap layer a second time after the second superconducting layer has been patterned.

[0085] In Example 3, the subject matter of Example 1 or 2 in the first to third embodiments may optionally include that the patterned first superconducting layer provides a first superconducting structure, that the patterned second superconducting layer provides a second superconducting structure, and that the second superconducting structure is connected to the JJ structure and the first superconducting structure.

[0086] In Example 4, the subject matter of any of the preceding examples in the first to third embodiments may optionally include that the patterned first superconducting layer and the patterned second superconducting layer are patterned to form a vertical capacitor with a dielectric capacitor material comprising the dielectric capping layer.

[0087] In Example 5, the subject matter of any of the preceding examples in the first to third embodiments may optionally include forming a first dielectric base layer over the patterned first superconducting layer.

[0088] In Example 6, the subject matter of Example 5 in the first to third embodiments may optionally further comprise patterning the first dielectric base layer to form exposed regions of the patterned first superconducting layer and forming the dielectric cap layer over the exposed regions.

[0089] In Example 7, the subject matter of Example 5 or 6 in the first and third embodiments may optionally include forming the first dielectric base layer before forming the JJ layer stack over the first superconducting layer.

[0090] In Example 8, the subject matter of Example 5 or 6 in the second embodiment may optionally include forming the first dielectric base layer after the JJ layer stack is formed over the first superconducting layer.

[0091] In Example 9, the subject matter of Example 8 in the second embodiment may include that the patterning of the JJ layer stack is performed before the first superconducting layer is patterned.

[0092] In Example 10, the subject matter of any of Examples 5 to 9 in the first to third embodiments can optionally include patterning the first dielectric base layer in the same patterning process used to pattern the dielectric cap layer.

[0093] In Example 11, the subject matter of any of Examples 5 to 10 in the third embodiment can optionally further comprise forming a second base dielectric layer over the first base dielectric layer, wherein the dielectric material of the second base dielectric layer is different from the dielectric material of the first base dielectric layer; and thinning the second base dielectric layer to expose the first base dielectric layer in regions over patterns of the patterned first superconducting layer.

[0094] In Example 12, the subject matter of Example 11 in the third embodiment may optionally include that the formation of the JJ layer stack and the patterning of the JJ layer stack are performed after the second dielectric base layer is formed.

[0095] In Example 13, the subject matter of Example 11 or 12 in the third embodiment can optionally include forming the dielectric capping layer over the second dielectric base layer after thinning the second dielectric base layer.

[0096] In Example 14, the subject matter of any of the preceding examples in the first to third embodiments can optionally include that the dielectric capping layer comprises silicon nitride.

[0097] Although specific embodiments have been shown and described herein, those skilled in the art will recognize that a variety of alternative and / or equivalent embodiments may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments described herein. Therefore, it is intended that this invention be limited only by the claims and their equivalents.

Claims

[1] A method of manufacturing a superconducting integrated circuit on a substrate (110), the method comprising: Forming a first superconducting layer (120) of a superconducting material over the substrate (110); Forming a Josephson junction (JJ) layer stack (210) with a JJ barrier layer over the first superconducting layer (120); Structuring the JJ layer stack (210) to form a JJ structure (212); Structuring the first superconducting layer (120) to form a structured first superconducting layer (120); Forming a dielectric cap layer (330) over the JJ structure (212); Patterning the dielectric cap layer (330) a first time to expose a top surface of the JJ structure (212); Forming a second superconducting layer (420) of a superconducting material over the dielectric cap layer (330); and Structuring the second superconducting layer (420) to form a structured second superconducting layer (420); and Structuring the dielectric cap layer (330) a second time after the second superconducting layer (420) has been structured. [2] The method of claim 1, wherein the patterned first superconducting layer (120) provides a first superconducting structure (120_1-3), the patterned second superconducting layer (420) provides a second superconducting structure (420_1-5), and wherein the second superconducting structure (420_1-5) is connected to the JJ structure (212) and the first superconducting structure (120_1-3). [3] A method of manufacturing a superconducting integrated circuit on a substrate (110), the method comprising: Forming a first superconducting layer (120) of a superconducting material over the substrate (110); Forming a Josephson junction (JJ) layer stack (210) with a JJ barrier layer over the first superconducting layer (120); Structuring the JJ layer stack (210) to form a JJ structure (212); Structuring the first superconducting layer (120) to form a structured first superconducting layer (120); Forming a dielectric cap layer (330) over the JJ structure (212); Patterning the dielectric cap layer (330) a first time to expose a top surface of the JJ structure (212); Forming a second superconducting layer (420) of a superconducting material over the dielectric cap layer (330); and Structuring the second superconducting layer (420) to form a structured second superconducting layer (420), wherein the structured first superconducting layer (120) and the structured second superconducting layer (420) are structured to form a vertical capacitor with a dielectric capacitor material comprising the dielectric capping layer (330). [4] A method according to any one of the preceding claims, wherein a first dielectric base layer (130) is formed over the patterned first superconducting layer (120). [5] A method of manufacturing a superconducting integrated circuit on a substrate (110), the method comprising: Forming a first superconducting layer (120) of a superconducting material over the substrate (110); Forming a Josephson junction (JJ) layer stack (210) with a JJ barrier layer over the first superconducting layer (120); Structuring the JJ layer stack (210) to form a JJ structure (212); Structuring the first superconducting layer (120) to form a structured first superconducting layer (120); Forming a dielectric cap layer (330) over the JJ structure (212); Patterning the dielectric cap layer (330) a first time to expose a top surface of the JJ structure (212); Forming a second superconducting layer (420) of a superconducting material over the dielectric cap layer (330); Structuring the second superconducting layer (420) to form a structured second superconducting layer (420); Structuring the first dielectric base layer (130) to form exposed regions of the structured first superconducting layer (120); and Forming the dielectric cover layer (330) over the exposed areas. [6] The method of claim 5, wherein the first dielectric base layer (130) is formed before the JJ layer stack (210) is formed over the first superconducting layer (120). [7] The method of claim 5, wherein the first dielectric base layer (130) is formed after the JJ layer stack (210) is formed over the first superconducting layer (120). [8] The method of claim 7, wherein the patterning of the JJ layer stack (210) is performed before the first superconducting layer (120) is patterned. [9] The method of any one of claims 4 to 8, wherein the first dielectric base layer (130) is patterned in the same patterning process used to pattern the dielectric cap layer (330). [10] A method according to any one of claims 4 to 9, further comprising: Forming a second dielectric base layer over the first dielectric base layer (130), wherein the dielectric material of the second dielectric base layer is different from the dielectric material of the first dielectric base layer (130); and Thinning the second dielectric base layer to expose the first dielectric base layer (130) in regions above structures of the structured first superconducting layer (120). [11] A method of manufacturing a superconducting integrated circuit on a substrate (110), the method comprising: Forming a first superconducting layer (120) of a superconducting material over the substrate (110); Forming a Josephson junction (JJ) layer stack (210) with a JJ barrier layer over the first superconducting layer (120); Structuring the JJ layer stack (210) to form a JJ structure (212); Structuring the first superconducting layer (120) to form a structured first superconducting layer (120); Forming a dielectric cap layer (330) over the JJ structure (212); Patterning the dielectric cap layer (330) a first time to expose a top surface of the JJ structure (212); Forming a second superconducting layer (420) of a superconducting material over the dielectric cap layer (330); and Structuring the second superconducting layer (420) to form a structured second superconducting layer (420), wherein the formation of the JJ layer stack (210) and the structuring of the JJ layer stack (210) occur after the formation of the second dielectric base layer. [12] The method of claim 11, wherein the dielectric cap layer (330) is formed over the second dielectric base layer after thinning the second dielectric base layer. [13] A method of manufacturing a superconducting integrated circuit on a substrate (110), the method comprising: Forming a first superconducting layer (120) of a superconducting material over the substrate (110); Forming a Josephson junction (JJ) layer stack (210) with a JJ barrier layer over the first superconducting layer (120); Structuring the JJ layer stack (210) to form a JJ structure (212); Structuring the first superconducting layer (120) to form a structured first superconducting layer (120); Forming a dielectric cap layer (330) over the JJ structure (212); Patterning the dielectric cap layer (330) a first time to expose a top surface of the JJ structure (212); Forming a second superconducting layer (420) of a superconducting material over the dielectric cap layer (330); Structuring the second superconducting layer (420) to form a structured second superconducting layer (420); Forming a second dielectric base layer over the first dielectric base layer (130), wherein the dielectric material of the second dielectric base layer is different from the dielectric material of the first dielectric base layer (130); and Thinning the second dielectric base layer to expose the first dielectric base layer (130) in regions over structures of the patterned first superconducting layer (120), wherein the dielectric cap layer (330) is formed over the second dielectric base layer after thinning the second dielectric base layer. [14] A method according to any one of the preceding claims, wherein the dielectric capping layer (330) comprises silicon nitride.

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