CELL STRUCTURE ON ECO-BASED, LAYOUT METHOD AND SYSTEM

Abstract

An IC structure comprises first to third n-wells aligned along a first direction in a semiconductor substrate, the first n-well being separated from the second and third n-wells by appropriate distances, a first plurality of active regions, gate structures and metal-like defined segments (MD segments) arranged over and electrically connected to the active regions located in the first well, a first tap structure arranged over and electrically connected to the second n-well, a second tap structure arranged over and electrically connected to the third n-well, and a first metal segment extending in the first direction over the first plurality of transistors and electrically connected to both the first and second tap structures.

Description

BACKGROUND

[0001] The ongoing trend toward miniaturization of integrated circuits (ICs) has led to ever smaller components that consume less power while still providing more functionality at higher speeds than previous technologies. This miniaturization has been achieved through design and manufacturing innovations combined with increasingly stringent specifications. Various electronic design automation (EDA) tools are used to create, revise, and verify semiconductor device designs, ensuring that all design and manufacturing specifications are met. Document DE 10 2017 125 036 A1 shows static memory circuits, sometimes also called SRAM circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Aspects of the present disclosure are best understood by reference to the following detailed description taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various elements are not drawn to scale. Indeed, the dimensions of various features / elements may be arbitrarily exaggerated or reduced for clarity of discussion. Fig. 1 is an illustration of a layout diagram of an IC and a corresponding IC structure in accordance with some embodiments. Fig. 2 is an illustration of a layout diagram of an IC and a corresponding IC structure in accordance with some embodiments. Fig. 3 is an illustration of a layout diagram of an IC and a corresponding IC structure in accordance with some embodiments. Fig. 4 is an illustration of a layout diagram of an IC and a corresponding IC structure in accordance with some embodiments. Fig. 5 is an illustration of a layout diagram of an IC and a corresponding IC structure in accordance with some embodiments. Fig. 6 is an illustration of a layout diagram of an IC and a corresponding IC structure in accordance with some embodiments. Fig. 7 is an illustration of a layout diagram of an IC and a corresponding IC structure in accordance with some embodiments. Fig. 8 is an illustration of a layout diagram of an IC and a corresponding IC structure in accordance with some embodiments. Fig. 9 is a flowchart of a method for generating an IC layout diagram in accordance with some embodiments. Fig. 10 is a block diagram of an IC design system in accordance with some embodiments. Fig. 11 is a block diagram of an integrated circuit (IC) manufacturing system and an associated IC manufacturing flow in accordance with some embodiments. DETAILED DESCRIPTION

[0003] The following disclosure presents many different embodiments, or examples, for implementing various features of the provided subject matter. Specific examples of components, values, acts, materials, arrangements, or the like are described below to simplify the present disclosure. For example, the formation of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are formed in direct contact with each other, but may also include embodiments in which additional elements may be formed between the first and second elements such that the first and second elements are not disposed in direct contact with each other. Furthermore, the present disclosure may repeat reference numbers and / or reference characters in the various examples.This repetition is for the purpose of simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0004] Furthermore, terms of spatial relationships, such as "beneath," "below," "low," "above," "upper," and the like, may be used herein for the purpose of more easily describing the relationship of one element depicted in the figures to another element(s). The terms of spatial relationships are intended to encompass various other orientations of the device during use or operation, in addition to the orientation depicted in the figures. The device may be arranged in a different orientation (rotated 90 degrees or in other orientations), and the terms of spatial relationships used herein may thus be interpreted accordingly.

[0005] In various embodiments, an integrated circuit (IC) structure, a layout diagram, and an IC design system are aligned to two types of standard cells: standard functional cells and standard spare cells, the latter referred to as engineering change order (ECO) cells. Standard functional cells are defined with specific internal arrangements of components to provide (in operation) corresponding conventional, subordinate functions to logic functions, such as, among others, an inverter, NAND, NOR, XOR, D-latch, a decoupling capacitor (DeCap), and-or inversion (AOI), or-and inversion (OAI), a multiplexer, a flip-flop, or the like.

[0006] ECO cells include ECO base cells and programmed ECO cells. A programmed ECO cell refers to an ECO base cell that has been programmed. Similar to a functional cell, an ECO base cell is defined with a specific arrangement of components. However, unlike a functional cell, an ECO base cell is not designed to provide a specific function. Unlike standard cells, which are operational (ready for use), an ECO base cell (which has not yet been programmed) is not operational (ready for use).

[0007] Given that ECO basic cells are spare cells, it is sufficient for the arrangement of an ECO basic cell that the ECO basic cell is capable of being "programmed" (redesigned), if necessary, to operate and provide one of the same conventional subordinate functions provided by a corresponding standard functional cell. In some embodiments, it is sufficient for the arrangement of each of the ECO basic cells that a particular ECO basic cell is capable of being "programmed" (redesigned) to provide one of the logic functions, such as an inverter, NAND, NOR, XOR, D-latch, a decoupling capacitor (DeCap), and-or inversion (AOI), or-and inversion (OAI), a multiplexer, a flip-flop, or the like.In some embodiments, an ECO base cell is programmed (redesigned) into a programmed ECO cell by changing one or more connections within at least one ECO base cell (intra-ECO base cell connections), such as metal-to-silicon contacts and / or metal-to-polysilicon contacts, or by making other metal layer changes with corresponding vias or contacts.

[0008] In some applications, electronic design automation (EDA) tools are used to select standard functional cells from standard cell libraries and insert the standard functional cells (if applicable) along with non-standard cells into an initial layout. EDA tools are also used to perform routing, which interconnects the standard functional cells and the non-standard cells using one or more metal layers and corresponding vias and contacts. EDA tools are further used to verify the routing. Depending on the verification results, the selection, placement, and routing of the standard and non-standard cells is revised. In at least some embodiments, the selection, placement, routing, and verification (SPRT) is repeated incrementally.Ultimately, the iterations of the SPRT process approach a final layout.

[0009] For a variety of reasons (e.g., a design change, an unacceptable timing error, an unacceptable electromigration error, or the like), it may be necessary to rework a nearly completed layout (or a layout that would otherwise have been considered final). In anticipation of circumstances in which the scope of such a rework would be relatively minor, and as a hedge against the need to restart the repetitive SPRT process (start from scratch), EDA tools are also used to insert one or more ECO base cells into the initial layout.

[0010] Because the ECO base cells are not operational, they are not connected to functional cells. If the nearly completed layout needs to be revised, one or more ECO base cells undergo "programming," which converts the one or more ECO base cells into one or more "programmed" ECO cells. The programmed ECO cells are then routed to be operationally connected to one or more standard functional cells.

[0011] In the various embodiments discussed below, ECO basic cells are capable of being arranged in one of several n-wells, wherein transistor main regions or transistor bodies are capable of operating at voltage levels that differ from those of the main regions of the transistors in neighboring n-wells, for example, transistors arranged in standard functional cells or other ECO cells. Compared to approaches in which ECO basic cells share n-wells with standard functional cells and other ECO cells, routing flexibility and design efficiency are thereby improved such that additional design activities, for example, repetition of the SPRT process or ECO cell adaptation, can be avoided.

[0012] As discussed above, the Fig. 1 - 8 depict IC layout diagrams and corresponding IC structures in accordance with some embodiments. The depictions in the Fig. 1-8 illustrate both the IC layout diagrams 100-800 and the corresponding IC structures 100-800 based at least in part on the IC layout diagrams 100-800, for example, in accordance with an IC manufacturing system and the associated IC manufacturing process 1100, which will be described below with reference to Fig. 11. In accordance with some embodiments, Fig. 9 is a flowchart of a method 900 for generating an IC layout diagram, for example, the IC layout diagram 100 - 800, and Fig. 10 is a block diagram of an IC design system 1000, for example, an EDA system 1000, configured to perform some or all of the operations of method 900.

[0013] As in Fig. 1, the IC layout diagram / structure 100 comprises n-well regions / n-wells NW1-NW3 arranged in a substrate SUB, examples of metal-like defined (MD) regions / segments MD (only one of which is indicated for clarity) extending in a Y direction, examples of via regions / via structures Vo (only one of which is indicated for clarity), and examples of first metal regions / metal segments M1 (only one of which is indicated for clarity) extending in an X direction perpendicular to the Y direction.

[0014] N-well regions / n-wells NW1 - NW3 are regions in an IC layout diagram, for example the IC layout diagram 100, which, in the manufacturing process according to the IC layout diagram / IC layout structure, define at least partially n-doped volumes within the substrate SUB.

[0015] The n-well regions / n-wells NW1 - NW3 are aligned along the X-direction, the n-well regions / n-wells NW1 and NW2 have a distance S1 in the X-direction, and the n-well regions / n-wells NW2 and NW3 have a distance S2 in the X-direction.

[0016] Each of the distances S1 and S2 is a distance greater than or equal to the distance specified by a minimum distance rule of the manufacturing process. In various embodiments, the distances S1 and S2 are equal to or different from each other.

[0017] In various embodiments, a distance S1 or S2 corresponds to a portion of the substrate SUB or an isolation region / an isolation structure, for example a volume of a dielectric material arranged between the respective n-well region / n-well pair NW1 / NW2 and / or NW2 / NW3.

[0018] Each of the n-well regions / wells NW1-MW3 comprises at least one instance of the MD region MD, a region in the IC layout diagram that overlaps the respective n-well region NW1-NW3, and at least partially defines a conductive MD segment MD disposed above and electrically connected to the underlying n-well NW1-NW3. During the manufacturing process, a bottom conductive layer, for example, a metal and / or a highly doped semiconductor material, comprises an MD segment MD, which in some embodiments is also referred to as a metal zero over oxide (MoOD) segment MD.

[0019] Each of the n-well regions / wells NW1-MW3 further includes at least one instance of a via region Vo, a region in the IC layout diagram that overlaps a respective instance of the MD region MD, and at least partially defines a via structure Vo disposed over and electrically connected to the underlying MD segment MD. A via structure Vo is a conductive volume configured to provide an electrical connection between the underlying element, for example, the MD segment MD, and an overlying element, for example, an instance of the metal segment M1 discussed below.

[0020] As in Fig. 1, combinations of instances of the MD region / MD segment MD and the via region / via structure Vo in each of the n-well regions / each of the n-wells NW1 - NW3 thus correspond to a tapping element / tapping structure Tap, which is configured to at least partially define electrical connections between the underlying n-well region / the underlying n-wells NW1 - NW3 and overlying instances of the metal region / metal segment M1.

[0021] A metal region M1 is a region in the IC layout diagram that overlaps one or more elements, including instances of the via region Vo, and at least partially defines a metal segment M1, for example, copper, disposed above and electrically connected to the respective underlying instances of the via structure Vo. In some embodiments, a bottom metal layer of a routing process, for example, an automatic placement and routing (APR) process, corresponding to the IC layout diagram comprises a metal segment M1, in some embodiments also referred to as a metal one segment M1.

[0022] In the Fig. 1, the n-well region NW2 has a function region arranged between two instances of the tap element Tap. The function region is a region in the IC layout diagram, for example, the IC layout diagram 100, in which one or more instances of an ECO basic cell ECO is / are arranged, as described below, for example, with reference to Fig. 2 - 8. The one or more instances of the ECO-Basis cell can be programmed as one or more functional components, for example, logic components.

[0023] The functional region comprises instances of the via region / via structure Vo, which correspond to electrical connections between the one or more functional components, and instances of the metal region / metal segment M1, overlapping / arranged above them, which are each electrically connected to the instances of the tapping element / tapping structure arranged in the n-well region / n-well NW2. The instances of the metal region / metal segment M1 are configured to be capable of operating the n-well region / n-well NW2 and the one or more instances of the ECO-Base cell (regardless of whether they have been programmed or not) at a first voltage level, for example, based on being routed through an overlying metal interconnect structure.

[0024] A separate instance of the metal region / metal segment M1 overlaps or is arranged above the instances of the tapping element / tapping structure Tap arranged in each of the n-well regions / n-wells NW1 and NW3, and overlaps or is arranged above the region Function, being configured to electrically connect the n-well regions / n-wells NW1 and NW3 to each other and at the same time to electrically isolate the n-well region / n-well NW2 from the n-well regions / n-wells NW1 and NW3. The instance of the metal region / metal segment M1 is configured such that it is capable of operating the n-well regions / n-wells NW1 and NW3 and all corresponding functional circuits at a second voltage level that differs from the first voltage level, for example, based on being routed through an overlying metal interconnect structure.

[0025] In the embodiment shown in Fig. 1, an IC layout diagram / structure 100 includes three additional instances of the metal region / metal segment M1 that are wider in the Y direction than the other instances of the metal region / metal segment M1. In various embodiments, a power distribution structure, e.g., a net configured to distribute a reference voltage level, e.g., ground, and one or more power supply voltage levels, e.g., VDD, within the IC layout diagram / structure 10, includes the additional instances of the metal region / metal segment M1.

[0026] In the embodiment which I Fig. As depicted in Figure 1, the functional area extends in the Y direction by a distance (a height) that corresponds to twice a distance dimension of the additional instances of the metal area / metal segment M1. In various embodiments, the functional area extends by a distance equal to the distance dimension or a multiple that is at least twice.

[0027] In the embodiment shown in Fig. As depicted in Figure 1, each of the n-well regions / each of the n-wells NW1-MW3 extends in the Y direction across the entire functional region. In some embodiments, one or more of the n-well regions / n-wells NW1-MW3 extend across a portion of the functional region, for example, across a distance corresponding to the pitch dimension.

[0028] With the configuration discussed above, the IC layout diagram / structure 100 is capable of including ECOS basic cells, for example, the ECO-base cells discussed below, arranged in the n-well region / n-well NW2, wherein portions of the transistor main portion or body are capable of operating at voltage levels different from those of the main portions of transistors in adjacent n-well regions / n-wells NW1 and NW3, for example, transistors that are components of standard functional cells or other ECO cells. Compared to approaches in which ECO basic cells share n-wells with standard functional cells and other ECO cells, routing flexibility and design efficiency are thereby improved such that additional design activities, for example, repeating the SPRT process or ECO cell adaptation, can be avoided.

[0029] Fig. 2 shows the IC layout diagram / the IC layout structure 200 together with the n-well regions / n-wells NW1 - NW3 arranged in the substrate SUB, instances of the MD regions / MD segments MD, the via regions / via structures Vo and first metal regions / metal segments M1, as well as the above-mentioned with respect to Fig. 1 discussed X-directions and Y-directions.

[0030] As in Fig. 2, a non-limiting example of the function region (not labeled for clarity) includes instances of the ECO Base cell arranged in two rows and two columns. In some embodiments, some or all of a row (indicated by the bold border) corresponds to a single instance of the ECO Base cell that is twice as wide in the x-direction as the remaining instances of the ECO Base cell.

[0031] The arrangement of the ECO cell, which is Fig. 2 is a non-limiting example provided for illustrative purposes. In various embodiments, an IC layout diagram / structure, e.g., IC layout diagram / structure 200, includes instances of the ECO base cell having other configurations, for example, where some or all of a column corresponds to a single instance of the ECO base cell that is twice as tall in the Y direction as the remaining instances of the ECO base cell.

[0032] In the embodiment shown in Fig. 2, the IC layout diagram / structure 200 comprises instances of the metal region / metal segment M1 extending in the X-direction and overlapping / arranged over the instances of the tap element / tap structure Tap disposed in each of the n-well regions / n-wells NW1, NW2, and NW3, and is configured to electrically interconnect the n-well regions / n-wells NW1, NW2, and NW3. The instances of the metal region / metal segment M1 are configured to operate the n-well regions / n-wells NW1, NW2, and NW3 and all corresponding ECO cells and / or functional circuits at a same voltage level, for example, based on being routed through an overlying metal interconnect structure.

[0033] The Fig. 1 and Fig. The embodiments depicted in Figure 2 represent alternative routing options, wherein one or more instances of the ECO-Base cell arranged in the n-well region / n-well NW2 are capable of operating at a voltage level that is either equal to or different from a voltage level applied to the n-well regions / n-wells NW1 and NW3. In accordance with having this routing flexibility, none of the embodiments discussed below Fig. 3 - 8 instances of the metal area / metal segment M1, which have a specific configuration.

[0034] Fig. 3 shows a simplified view of the IC layout diagram / structure 300, which includes the n-well regions / n-wells NW1-NW3 arranged in the substrate SUB, instances of the tap element / tap structure Tap and the cell ECO base, as well as the X-direction and the Y-direction, respectively, as discussed above.

[0035] Fig. 3 shows a non-limiting example, wherein the IC layout diagram / IC layout structure 300 includes four instances of the cell ECO base arranged in two rows and two columns. In some embodiments, each of the cell ECO base instances has the same orientation with respect to the X-direction and the Y-direction. In some embodiments, one or more instances of the cell ECO base are symmetrical to (mirrored with) one or more instances of the cell ECO base with respect to an X-axis or a Y-axis, for example, a boundary between one or more of the cell ECO base instances, as discussed in more detail below.

[0036] Fig. 4 shows a simplified view of the IC layout diagram / structure 400, which includes the n-well regions / n-wells NW1-NW3 arranged in the substrate SUB, four instances of the cell ECO base (only one instance being labeled for clarity), each of which includes instances of the MD region / MD segment MD and the via region / via structure Vo, as well as the X-direction and the Y-direction, each as discussed above.

[0037] Each of the instances of the ECO-Base cell also has instances of an active region / area AA, a gate region / structure G, a metal zero over poly (MoPO) region / metal zero over poly segment Mo, and a cut MD region CMD (where only a single instance of each is identified for clarity).

[0038] An active region, for example the active area AA, is a region in the IC layout diagram, for example a substrate region or an n-well region, for example the n-well region NW1 - NW3, which at least partially defines a volume in the respective substrate or the n-well, wherein various elements, for example transistor channels and / or source / drain elements, are formed by the manufacturing process in the respective IC structure.

[0039] A gate region, for example the gate region R, is a region in the IC layout diagram which at least partially defines a volume in the IC structure in question, wherein a gate electrode, in some embodiments also referred to as poly gate or poly, and a gate dielectric layer are formed by the manufacturing process.

[0040] A MoPO region, for example, the MoPO region Mo, is a region in the IC layout diagram that at least partially defines a conductive segment, for example, the MoPO segment Mo, which is arranged above and electrically connected to an underlying gate structure. During the manufacturing process, a MoPO segment Mo is arranged in the lowest conductive layer, for example, made of metal and / or highly doped semiconductor material.

[0041] A cut MD region is a region in the IC layout diagram that defines an area in the IC structure in question within which portions of the MD segments MD are removed after their formation in the manufacturing process, thereby electrically isolating them from each other.

[0042] The instances of the active area / area AA, the gate area / structure G, the MoPO area / segment Mo, the MD area / segment MD, the via area / structure Vo, and the cut MD area CMD in a particular instance of the ECO-Basis cell are arranged in a structure, wherein the ECO-Basis cell instance is capable of being programmed for a selectable cell function.

[0043] In various embodiments, each of the instances of the ECO-Base cell corresponds to the same structure or to a plurality of structures. In some embodiments, two structures are symmetrical to each other about an axis, for example, a boundary between the two structures.

[0044] In some embodiments, the instances correspond to the cell ECO-Base, which in Fig. 4, a first row in which a second structure is symmetrical to a first structure around a boundary extending in the Y direction, and a second row in which a third and a fourth structure are symmetrical to the first and second structure around a boundary extending in the X direction.

[0045] Each of the Fig. 5 and Fig. 7 shows a simplified view of a respective IC layout diagram / IC layout structure 500 and 600, respectively, comprising the n-well regions / n-wells NW1-NW3 arranged in the substrate SUB, six instances of the cell ECO-Base (only one instance being labeled for clarity), each of which includes instances of the active region / active area AA, the gate region / gate structure G, the MoPO region / MoPO segment Mo, the MD region / MD segment MD, the via region / via structure Vo, and the cut MD region CMD (which is not labeled for clarity), as well as the X-direction and the Y-direction, each as discussed above.

[0046] In various embodiments, the instances of the ECO base cell comprising the IC layout diagrams / IC layout structures 500 and 600 comprise the respective instances of the active area / area AA, the gate area / gate structure G, the MoPO area / MoPO segment Mo, the MD area / MD segment MD, the via area / via structure Vo, and the cut MD area CMD arranged in one or more structures, which in some embodiments have symmetry with respect to one or more axes.

[0047] Each of the Fig. 7 and Fig. 8 shows a simplified view of the respective IC layout diagram / IC layout structure 700 and 800, respectively, showing the n-well regions / n-wells NW1 - NW3 arranged in the substrate SUB and instances of the cell ECO base having various features / elements (not labeled for clarity).

[0048] The non-limiting example given in Fig. 7 has four instances of the ECO-Base cell arranged in the n-well region / n-well NW2, and the non-limiting example shown in Fig. 8, comprises a single instance of the ECO base cell arranged in the n-well region / n-well NW2, wherein the single instance is configured as a decoupling capacitive device.

[0049] By having the n-well region / n-well NW2 comprise the various instances of the ECO base cell, each of the IC layout diagrams / IC layout structures 300-800 is configured in accordance with the IC layout diagrams / IC layout structures 100 and 200, and is therefore capable of realizing the advantages discussed above with respect to the IC layout diagrams / IC layout structures 100 and 200.

[0050] Fig. 9 is a flow diagram of a method 900 for creating an IC layout diagram in accordance with some embodiments. In some embodiments, creating the IC layout diagram includes creating one or all of the one or more of the IC layout diagrams 100-800 described above with respect to the Fig. 1 - 8 were discussed.

[0051] In some embodiments, part or all of the method 900 is performed by a processor of a computer. In some embodiments, part or all of the method 900 is performed by a processor 1002 of the IC layout diagram generation system 1000, which is described below with reference to Fig. 10 is discussed.

[0052] In some embodiments, one or more of the operations of method 900 are a subset of operations of a method for forming an IC device. In some embodiments, one or more operations of method 900 are a subset of operations of an IC manufacturing flow, for example, the IC manufacturing flow described below with respect to a manufacturing system 1100 and Fig. 11 is discussed.

[0053] In some embodiments, the operations of method 900 are performed in the manner described in Fig. 9. In some embodiments, the operations of method 900 are performed simultaneously and / or in a different order than in Fig. 9. In some embodiments, one or more operations are performed before, between, during, and / or after performing one or more operations of method 900.

[0054] At operation 902, the first through third n-well regions are aligned along a first direction in an IC layout diagram. Aligning the first through third n-well regions includes separating the first n-well region from each of the second and third n-well regions by a distance that complies with at least one minimum well spacing rule.

[0055] In some embodiments, aligning the first to third n-well regions comprises aligning the n-well regions NW2, NW1 and NW3, wherein in accordance with one or more of the IC layout diagrams 100-800 described above with respect to the Fig. 1 - 8 have been discussed, the n-well region NW2 is separated from the n-well region NW1 by the distance S1, and the n-well region NW2 is separated from the n-well region NW3 by the distance S2.

[0056] In some embodiments, aligning the first to third n-well regions includes disposing a first tap via region in the second n-well region and disposing a second tap via region in the third n-well region. In some embodiments, aligning the first to third n-well regions includes disposing a third and a fourth tap via region in the first n-well region.

[0057] In some embodiments, arranging a tapping via region comprises arranging an instance of the tapping element Tap, which comprises an instance of the via region Vo, which comprises an instance of the via region described above with reference to the Fig. 1 and Fig. 2 discussed MD area MD overlaps.

[0058] At operation 904, a first ECO base cell is disposed in the first n-well region. In some embodiments, disposing the first ECO base cell in the first n-well region includes disposing the ECO base cell in the n-well region NW2, as described above with reference to the Fig. 1 - 8 discussed.

[0059] In some embodiments, arranging the first ECO basic cell in the first n-well region comprises arranging a plurality of ECO basic cells, including the first ECO basic cell in the first n-well region, for example, instances of the ECO basic cell in the n-well region NW2 in accordance with one or more of the Fig. 2 - 8.

[0060] At operation 906, the second and third n-well regions are electrically connected to each other. Electrically connecting the second and third n-well regions includes establishing a first electrical connection between the second and third n-well regions by overlapping both the first and second tap via regions with a first metal region extending in the first direction across the first n-well region.

[0061] In some embodiments, overlapping both the first and second tap via regions with the first metal region extending in the first direction over the first n-well region comprises overlapping the instances of the tap element Tap corresponding to the n-well regions NW1 and NW3 with an instance of the metal region M1 extending in the X-direction over the n-well region NW2, as described above with respect to the Fig. 1 and Fig. 2 discussed.

[0062] In some embodiments, electrically connecting the second and third n-well regions comprises establishing a second electrical connection between the third and fourth tap via regions by overlapping both the third and fourth tap via regions with a second metal region extending in the first direction across the first ECO base cell, for example, as described above with respect to Fig. 1 discussed.

[0063] In some embodiments, electrically connecting the second and third n-well regions comprises overlapping both the third and fourth tapping via regions with the first metal region, thereby establishing the first electrical connection between both the second and third n-well regions and the first n-well region, for example, as described above with respect to Fig. 2 discussed.

[0064] At operation 908, in some embodiments, the ECO base cell is configured as a functional cell. In some embodiments, configuring the ECO base cell as a functional cell includes adding and / or modifying one or more electrical connections within the functional cell, thereby configuring the ECO base cell to perform one or more logical or other functions.

[0065] In various embodiments, establishing the ECO base cell as a functional cell comprises establishing a subset of the or a plurality of ECO base cells as corresponding functional cells. In some embodiments, establishing the ECO base cell as a functional cell comprises establishing one or more instances of the ECO base cell described above with respect to the Fig. 1 - 8 have been discussed.

[0066] In some embodiments, establishing the ECO base cell as a functional cell includes performing one or more routing operations, for example, one or more APR operations. In some embodiments, establishing the ECO base cell as a functional cell includes routing a plurality of electrical signal paths to the functional cell.

[0067] In some embodiments, establishing the ECO base cell as a functional cell includes routing a first voltage distribution path to the first electrical connection, which is configured, for example, to distribute a first voltage level.

[0068] In some embodiments, setting up the ECO base cell as a functional cell includes routing a second voltage distribution path to the second electrical connection, which is configured, for example, to distribute a second voltage level different from the first voltage level.

[0069] At operation 910, in some embodiments, the IC layout diagram is stored in a storage device. In some embodiments, storing the IC layout diagram in the storage device includes storing the IC layout diagram in an IC layout diagram library, for example, layout diagram library 1009 of IC layout diagram creation system 1000, which is described below with respect to Fig. 10 is discussed.

[0070] In various embodiments, storing the IC layout diagram in the storage device comprises storing the IC layout diagram in a non-transitory, computer-readable memory or cell library, for example, a database, and / or comprises storing the IC layout diagram over a network. In some embodiments, storing the IC layout diagram in the storage device comprises storing the IC layout diagram over the network 1014 of the IC layout diagram creation system 1000, which is described below with reference to Fig. 10 is discussed.

[0071] At operation 912, in some embodiments, one or more manufacturing operations are performed based on the IC layout diagram. In some embodiments, performing one or more manufacturing operations includes performing one or more lithographic exposures based on the IC layout diagram. Performing one or more manufacturing operations, for example, one or more lithographic exposures, based on the IC layout diagram is described below with reference to Fig. 11 discussed.

[0072] By performing some or all of the acts of method 900, an IC layout diagram is created in which one or more instances of an ECO basic cell are arranged in a dedicated n-well region configured in accordance with IC layout diagrams 100 and 200, and is thereby able to realize the advantages discussed above with reference to IC layout diagrams / IC layout structures 100 and 200.

[0073] Fig. 10 is a block diagram of an electronic design automation (EDA) system 1000 in accordance with some embodiments.

[0074] In some embodiments, EDA system 1000 includes an APR system. Methods for designing layout diagrams described herein illustrate wire routing arrangements consistent with one or more embodiments and may be implemented, for example, using EDA system 1000, consistent with some embodiments.

[0075] In some embodiments, EDA system 1000 is a general-purpose computing device including a hardware processor 1002 and a non-transitory, computer-readable storage medium 1004. Storage medium 1004 is encoded with, i.e., stores, among other things, computer program code 1006, i.e., a set of executable instructions. Execution of instructions 1006 by hardware processor 1002 constitutes (at least in part) an EDA tool that implements some or all of the methods described herein in accordance with one or more embodiments (hereinafter referred to as the recited processes and / or methods).

[0076] The processor 1002 is electrically coupled to the computer-readable storage medium 1004 via a bus 1008. The processor 1002 is also electrically coupled to an I / O interface 1010 via the bus 1008. A network interface 1012 is also electrically connected to the processor 1002 via the bus 1008. The network interface 1012 is connected to a network 1014 such that the processor 1002 and the computer-readable storage medium 1004 are capable of connecting to external elements via the network 1014. The processor 1002 is configured to execute computer program code 1006 encoded in the computer-readable storage medium 1004 to cause the system 1000 to be usable to perform some or all of the recited processes and / or methods.In one or more embodiments, processor 1002 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application-specific integrated circuit (ASIC), and / or any suitable processing unit.

[0077] In one or more embodiments, the computer-readable storage medium 1004 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or corresponding device or apparatus). For example, the computer-readable storage medium 1004 comprises a semiconductor or solid-state memory, a magnetic tape, a removable computer diskette, a random access memory (RAM), a read-only memory (ROM), a magnetic hard disk, and / or an optical disk. In one or more embodiments that utilize optical disks, the computer-readable storage medium 1004 comprises a compact disc read-only memory (CD-ROM), a compact disc read / write (CD-R / W), and / or a digital video disc (DVD).

[0078] In one or more embodiments, storage medium 1004 stores computer program code 1006 configured to cause system 1000 (in which this embodiment represents (at least in part) the EDA tool) to be usable to perform a portion of, or all of, the recited processes and / or methods. In one or more embodiments, storage medium 1004 also stores information enabling a portion of, or all of, the recited processes and / or methods to be performed. In one or more embodiments, storage medium 1004 stores cell library 1007 of IC layout cells comprising cells as disclosed herein. In one or more embodiments, storage medium 1004 stores one or more layout diagrams 1009 corresponding to one or more of the layouts disclosed herein.

[0079] The EDA system 1000 includes the input / output (I / O) interface 1010. The I / O interface 1010 is connected to external circuitry. In one or more embodiments, the I / O interface 1010 includes a keyboard, keypad, mouse, tactile ball, touchscreen, and / or cursor direction keys for communicating information and commands to the processor 1002.

[0080] The EDA system 1000 also includes the network interface 1012, which is connected to the processor 1002. The network interface 1012 enables the system 1000 to communicate with the network 1014 to which one or more other computer systems are connected. The network interface 1012 includes wireless network interfaces, such as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired network interfaces, such as ETHERNET, USB, or IEEE-1364. In one or more embodiments, a portion of, or all of, the recited processes and / or methods are implemented in two or more systems 1000.

[0081] The system 1000 is configured to receive information through the I / O interface 1010. The information received through the I / O interface 1010 comprises one or more elements selected from the group consisting of instructions, data, design rules, libraries of standard cells, and / or other parameters for processing by the processor 1002. The information is transferred to the processor 1002 via the bus 1008. The EDA system 1000 is configured to receive information associated with a user interface (UI) through the I / O interface 1010. The information is stored in the computer-readable medium 1004 as UI 1042.

[0082] In some embodiments, a portion of, or all of, the recited processes and / or methods is implemented as a stand-alone software application for execution by a processor. In some embodiments, a portion of, or all of, the recited processes and / or methods is implemented as a software application that forms part of another software application. In some embodiments, a portion of, or all of, the recited processes and / or methods is implemented as a plug-in to a software application. In some embodiments, at least one of the recited processes and / or methods is implemented as a software application that forms a portion of an EDA tool. In some embodiments, a portion of, or all of the recited processes and / or methods is implemented as a software application used by EDA system 1000.In some embodiments, a layout plan having standard cells is generated using a tool such as VIRTUOSO® available from CADENCE DESIGN SYSTEMS, Inc., or another suitable layout creation tool.

[0083] In some embodiments, the processes are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of a non-transitory computer-readable recording medium include, but are not limited to, external / removable and / or internal / built-in storage or memory devices, for example, one or more members selected from the group consisting of an optical disk such as a DVD, a magnetic disk such as a hard disk, a semiconductor memory such as ROM, RAM, a memory card, and the like.

[0084] Fig. 11 is a block diagram of an integrated circuit (IC) manufacturing system 1100 and an IC manufacturing flow associated therewith, in accordance with some embodiments. In some embodiments, based on a layout diagram, at least (A) one or more semiconductor masks or (B) at least one component in a layer of a semiconductor integrated circuit are manufactured using the manufacturing system 1100.

[0085] In Fig. 11, the IC manufacturing system 1100 includes entities, such as a design house 1120, a mask house 1130, and an IC manufacturer / fabricator (“fab”) 1150, that cooperate with each other regarding design, development, and manufacturing cycles and / or services related to the fabrication of an IC device 1160. The entities in the system 1100 are interconnected by a communications network. In some embodiments, the communications network is a single network. In some embodiments, the communications network is a plurality of different networks, such as an intranet and the Internet. The communications network includes wired and / or wireless communications channels. Each of the entities interacts with one or more of the other entities and provides services to one or more of the other entities and / or receives services from one or more of the other entities.In some embodiments, two or more of the design house 1120, mask house 1130, and IC fabricator 1150 units are owned by a single larger company. In some embodiments, two or more of the design house 1120, mask house 1130, and IC fabricator 1150 units are co-located in a common facility and share common resources.

[0086] The design house (or design team) 1120 creates an IC design layout diagram 1122. The IC design layout diagram 1122 includes various geometric structures designed for an IC device 1160. The geometric structures correspond to structures of metal layers, oxide layers, or semiconductor layers that form the various components of the IC device 1160 to be manufactured. The various layers are combined to form various IC elements or IC features.For example, a portion of the IC design layout diagram 1122 includes various IC features or IC elements, such as an active area, a gate electrode, source and drain, metal lines or vias, an interlayer interconnect, and openings for bonding pads, to be formed in a semiconductor substrate (such as a silicon wafer), as well as various material layers disposed on the semiconductor substrate. The design house 1120 implements an appropriate design process to form the IC design layout diagram 1122. The design process includes one or more of the elements from the group comprising logical design, physical design, or arranging and routing. The IC design layout diagram 1122 is represented in one or more data files that include information about the geometric structures.For example, the IC design layout diagram 1122 may be expressed in a GDSII file format or a DFII file format.

[0087] The mask house 1130 includes data preparation 1132 and mask fabrication 1144. The mask house 1130 uses the IC design layout diagram 1122 to create one or more masks 1145, which are to be used to fabricate the various layers of the IC device 1160 in accordance with the IC design layout diagram 1122. The mask house 1130 performs mask data preparation 1132, in which the IC design layout diagram 1122 is translated into a representative data file (RDF). The mask data preparation 1132 provides the RDF to the mask fabrication 1144. The mask fabrication 1144 includes a mask writer. A mask writer converts the RDF into an image on a substrate, such as a mask (reticle) 1145 or a semiconductor wafer 1153.The design layout diagram 1122 is processed by the mask data preparation 1132 to conform to the particular characteristics of the mask writer and / or the requirements of the IC manufacturer 1150. In . Fig. 11, mask data preparation 1132 and mask fabrication 1144 are illustrated as separate elements. In some embodiments, mask data preparation 1132 and mask fabrication 1144 may be collectively referred to as mask data preparation.

[0088] In some embodiments, mask data preparation 1132 includes near-field optical correction (OPC), which uses lithography enhancement techniques to compensate for image defects, such as those resulting from diffraction, interference, other process effects, and the like. OPC adjusts the IC design layout diagram 1122. In some embodiments, mask data preparation 1132 includes further resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist functions, phase-shift masks, other suitable techniques, and the like, or combinations thereof. In some embodiments, reverse lithography technology (ILT) is also used, which treats OPC as a reverse imaging problem.

[0089] In some embodiments, mask data preparation 1132 includes a mask rule checker (MRC) that checks the IC design layout diagram 1122, which has undergone certain processes at the OPC, against a set of mask creation rules, which in turn include certain geometric and / or connection constraints to ensure sufficient margins, account for variations in semiconductor manufacturing processes, and the like. In some embodiments, the MRC modifies the IC design layout diagram 1122 to compensate for photolithographic conversion effects during mask fabrication 1144, which may undo some of the modifications performed by the OPC, and thus comply with the mask creation rules.

[0090] In some embodiments, mask data preparation 1132 includes a lithography process check (LPC) that simulates the processing that IC fabricator 1150 will implement to fabricate IC device 1160. LPC simulates this processing based on IC design layout diagram 1122 to create a simulated fabricated device, such as IC device 1160. The process parameters of the LPC simulation may include parameters related to various processes of the IC manufacturing cycle, parameters related to tools used to manufacture the IC, and / or other aspects of the manufacturing process. LPC considers various factors, such as aerial image contrast, depth of field (DOF), mask defect enhancement factor (MEEF), other suitable factors, and the like, or combinations thereof.In some embodiments, OPC and / or MRC are repeated after a simulated fabricated device has been created by the LPC if the shape of the simulated device is not sufficiently accurate to comply with the design rules to further refine the IC design layout diagram 1122.

[0091] It should be understood that the above description of mask data preparation 1132 has been simplified for clarity. In some embodiments, data preparation 1132 includes additional features / elements, such as a logic operation (LOP) to modify IC design layout diagram 1122 according to manufacturing rules. Furthermore, the processes performed on IC design layout diagram 1122 during data preparation 1132 can be performed in a variety of different orders.

[0092] After mask data preparation 1132 and during mask fabrication 1144, a mask 1145 or a group of masks 1145 is fabricated based on the modified IC design layout diagram 1122. In some embodiments, mask fabrication 1144 includes performing one or more lithographic exposures based on the IC design layout diagram 1122. In some embodiments, an electron beam (e-beam) or a multiple electron beam mechanism is used to form a pattern on a mask (photomask or reticle) 1145 based on the modified IC design layout diagram 1122. The mask 1145 can be formed using various technologies. In some embodiments, the mask 1145 is formed using a binary technology. In some embodiments, a mask pattern includes opaque regions and transparent regions.An irradiation beam, such as an ultraviolet (UV) ray, used to expose the image-sensitive material layer (e.g., photoresist) coated on a wafer is blocked by the opaque region and penetrates the transparent regions. In one example, a binary mask version of the mask 1145 includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated on the opaque regions of the binary mask. In another example, the mask 1145 is formed using phase-shifting technology. In a phase-shifting mask (PSM) version of the mask 1145, various features / elements in the structure formed on the phase-shifting mask are configured to have an appropriate phase difference to improve resolution and imaging quality.In various examples, the phase-shift mask may be a damped PSM or an alternating PSM. The mask(s) generated by mask fabrication 1144 are used in a variety of processes. For example, such a mask(s) are used in an ion implantation process to form various doped regions in semiconductor wafer 1153, in an etching process to form various etch regions in semiconductor wafer 1153, and / or in other suitable processes.

[0093] The IC fabricator 1150 is an IC manufacturing company that has one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, the IC fabricator 1150 is a semiconductor manufacturer. For example, one manufacturing facility may be available for the front-end manufacturing of a variety of IC products (front-end-of-line (FEOL) manufacturing), while a second manufacturing facility provides the back-end manufacturing for interconnecting and packaging the IC products (back-end-of-line (BEOL) manufacturing), and a third manufacturing facility provides other services to the manufacturing company.

[0094] The IC fabricator 1150 includes manufacturing tools 1152 configured to perform various manufacturing operations on the semiconductor wafer 1153 such that the IC device 1160 is manufactured in accordance with the mask(s), for example, the mask 1145. In various embodiments, the manufacturing tools 1152 include one or more of the tools from the group comprising a wafer stepper, an ion implanter, a photoresist coating device, a process chamber, for example, a CVD chamber or an LPCVD furnace, a CMP system, a plasma etching system, a wafer cleaning system, or other manufacturing facilities capable of performing one or more suitable manufacturing processes as discussed herein.

[0095] The IC fabricator 1150 uses mask(s) 1145 manufactured by the mask house 1130 to manufacture the IC device 1160. Thus, the IC fabricator 1150 at least indirectly uses the IC design layout diagram 1122 to manufacture the IC device 1160. In some embodiments, the semiconductor wafer 1153 is manufactured by the IC fabricator 1150 using the mask(s) 1145 to form the IC device 1160. In some embodiments, the IC fabrication includes performing one or more lithographic exposures, at least indirectly based on the IC design layout diagram 1122. The semiconductor wafer 1153 comprises a silicon substrate or other suitable substrate having material layers formed thereon.The semiconductor wafer 1153 further includes one or more different doped regions, dielectric elements, multilevel interconnects, and the like (which are formed in subsequent manufacturing steps).

[0096] In some embodiments, an IC structure includes first to third n-wells aligned along a first direction in a semiconductor substrate, the first n-well being separated from the second and third n-wells by respective distances, a first plurality of active regions, gate structures, and MD segments disposed over and electrically connected to the active regions disposed in the first well, a first tap structure disposed over and electrically connected to the second n-well, a second tap structure disposed over and electrically connected to the third n-well, and a first metal segment extending in the first direction and disposed over the first plurality of transistors and electrically connected to both the first and second tap structures.In some embodiments, the IC structure includes third and fourth tap structures disposed over and electrically connected to the first n-well, and a second metal segment extending in the first direction, wherein the second metal segment is disposed over and electrically connected to the third and fourth tap structures, respectively, and is electrically isolated from the first metal segment. In some embodiments, the first metal segment is configured to have a first voltage level, and the second metal segment is configured to have a second voltage level different from the first voltage level.In some embodiments, the IC structure includes third and fourth tap structures disposed over and electrically connected to the first n-well, the first metal segment being electrically connected to both the third and fourth tap structures. In some embodiments, the first plurality of active areas, gate structures, and MD segments comprise a first structure, and the IC structure includes a second plurality of active areas, gate structures, and MD segments disposed over and electrically connected to the active areas disposed in the first well and having the first structure.In some embodiments, the first plurality of active areas, gate structures, and MD segments comprise a first structure, the first IC structure comprises a second plurality of active areas, gate structures, and MD segments disposed over and electrically connected to the active areas disposed in the first well and having a second structure, and the second structure is symmetrical to the first structure about a first axis perpendicular to the first direction. In some embodiments, the IC structure comprises third and fourth pluralities of active areas, gate structures, and MD segments disposed over and electrically connected to the active areas disposed in the first well and having third and fourth structures, respectively, the third and fourth structures being symmetrical to the first and second structures about a second axis along the first direction.

[0097] In some embodiments, a method for creating an IC layout diagram comprises aligning first to third n-well regions along a first direction in the IC layout diagram, wherein the first n-well region is each separated from the second and third n-well regions by a distance corresponding to a minimum n-well spacing rule, respectively, arranging a first tap via region in the first n-well region, arranging a second tap via region in the third n-well region, arranging a first ECO basic cell in the first n-well region, establishing a first electrical connection between the second and third n-well regions by overlapping the first and second tap via regions with a metal region extending in the first direction over the first n-well region,and storing the IC layout diagram in a memory device. In some embodiments, the method comprises arranging a third and a fourth tap via region in the first n-well region and establishing a second electrical connection between the third and the fourth tap via region by overlapping both the third and the fourth tap via region with a second metal region extending in the first direction across the first ECO base cell. In some embodiments, the method comprises routing a first voltage distribution path to the first electrical connection and routing a second voltage distribution path to the second electrical connection, wherein the first and the second voltage distribution paths, respectively, are configured toseparate voltage levels. In some embodiments, the method comprises arranging a third and a fourth tapping via region in the first n-well region, wherein establishing the first electrical connection comprises overlapping both the third and the fourth tapping via region with the first metal region, thereby establishing the first electrical connection between the second and the third and the first n-well regions, respectively. In some embodiments, arranging the first ECO base cell in the first n-well region comprises arranging a second ECO base cell in the first n-well region adjacent to the first ECO base cell in the first direction. In some embodiments, arranging the first ECO base cell in the first n-well region comprises arranging a second ECO base cell in the first n-well region,which borders the first ECO basic cell in the first direction, wherein the first and second ECO basic cells are symmetrical to each other about a boundary between the first and second ECO basic cells, and arranging a third and a fourth ECO basic cell in the first n-well region, which borders the first and second ECO basic cells in the second direction, which is perpendicular to the first direction, wherein the first and third ECO basic cells are symmetrical to each other about a boundary between the first and third ECO basic cells, and the second and fourth ECO basic cells are symmetrical to each other about a boundary between the second and fourth ECO basic cells. In some embodiments, arranging the first ECO basic cell in the first n-well region comprises arranging a second and a third ECO basic cell in the first n-well region, which are oriented either in the first direction or in a second direction,which is perpendicular to the first direction, adjacent to the first ECO basic cell, and arranging third to fifth ECO basic cells in the first n-well region, which are adjacent to the first to third ECO basic cells in the other of the first and second directions, respectively. In some embodiments, the method comprises setting up the first ECO basic cell as a functional cell and routing a plurality of electrical signal paths to the ECO functional cell.

[0098] In some embodiments, an EDA system comprises a processor and a non-transitory, computer-readable storage medium comprising computer program code for one or more programs, wherein the non-transitory, computer-readable storage medium and the computer program code are configured with the processor to cause the processor to arrange a first tapped via region in a second n-well region of the first to third n-well regions of an IC layout diagram, wherein the first n-well region is separated from the second and third n-well regions, respectively, along a first direction by at least a distance that complies with a minimum n-well spacing rule, arrange a second tapped via region in the third n-well region, arrange a first ECO basic cell in the first n-well region,overlapping the first and second tap via regions, respectively, with a first metal region extending in the first direction across the first n-well region, thereby establishing a first electrical connection between the second and third n-well regions; routing a first voltage distribution path to the first electrical connection, wherein the first voltage distribution path is configured to distribute a first voltage level; and storing the IC layout diagram in a memory device. In some embodiments, the non-transitory computer-readable storage medium and the computer program code with the processor are configured to further cause the processor to arrange a third and a fourth tap via region in the first n-well region; connecting the third and fourth tap via regions, respectively, with a second metal region;which extends in the first direction over the first ECO base cell, thereby establishing a second electrical connection between the third and fourth tapping via regions, and routes a second voltage distribution path to the second electrical connection, wherein the second voltage distribution path is configured to distribute a second voltage level separate from the first voltage level. In some embodiments, the non-transitory computer-readable storage medium and the computer program code with the processor are configured to further cause the processor to arrange a third and a fourth tapping via region in the first n-well region, and to overlap both the third and fourth tapping via regions with the first metal region, respectively.whereby the first electrical connection is established between the second and third n-well regions, respectively, and the first n-well region. In some embodiments, the non-volatile computer-readable storage medium and the computer program code are configured with the processor to further cause the processor to establish the first ECO basic cell as a functional ECO cell and to route a plurality of electrical signal paths to the functional ECO cell. In some embodiments, the first ECO basic cell is a first ECO basic cell of a plurality of ECO basic cells, and the non-volatile computer-readable storage medium and the computer program code are configured with the processor to cause the processor to arrange the plurality of ECO basic cells comprising the first ECO basic cell in the first n-well region of the IC layout diagram.

Claims

[1] Integrated circuit structure (100, 200, 300, 400, 500, 600, 700, 800), hereinafter referred to as IC structure, comprising: first to third n-wells (NW1-NW3) which are aligned in a semiconductor substrate (SUB) along a first direction (X), wherein the first n-well (NW2) is separated from the second and third n-wells (NW1, NW3) by corresponding distances (S1, S2), respectively; a first plurality of active regions (AA), gate structures (G) and metal-like defined segments (MD) arranged over and electrically connected to the active regions (AA) arranged in the first n-well (NW2); a first tapping structure (Tap) arranged above the second n-well (NW1) and electrically connected thereto; a second tapping structure (Tap) arranged above the third n-well (NW3) and electrically connected thereto; a first metal segment (M1) extending in the first direction (X), disposed over a first number of transistors, and electrically connected to both the first and second tap structures (Tap); a third and a fourth tapping structure (Tap) arranged above the first n-well (NW2) and electrically connected thereto; and a second metal segment extending in the first direction (X), wherein the second metal segment is arranged over and electrically connected to both the third and fourth tapping structures (Tap), and is electrically insulated from the first metal segment (M1). [2] IC structure (100, 200, 300, 400, 500, 600, 700, 800) according to claim 1, wherein the first metal segment (M1) is arranged to have a first voltage level (VDD), and the second metal segment is configured to have a second voltage level (ground) which is different from the first voltage level (VDD). [3] IC structure (100, 200, 300, 400, 500, 600, 700, 800) according to one of claims 1 or 2, wherein the first plurality of active areas (AA), gate structures (G) and MD segments (MD) has a first structure, and the IC structure (100, 200, 300, 400, 500, 600, 700, 800) further comprises a second plurality of active regions (AA), gate structures (G) and MD segments (MD) which are arranged over and electrically connected to the active regions (AA) arranged in the first n-well (NW2), and comprise the first structure. [4] IC structure (100, 200, 300, 400, 500, 600, 700, 800) according to one of claims 1 or 2, wherein the first plurality of active areas (AA), gate structures (G) and MD segments (MD) has a first structure, the IC structure (100, 200, 300, 400, 500, 600, 700, 800) further comprises a second plurality of active regions (AA), gate structures (G) and MD segments (MD) arranged over and electrically connected to the active regions (AA) arranged in the first n-well (NW2), and having a second structure, and the second structure is symmetrical to the first structure about a first axis (Y) perpendicular to the first direction (X). [5] IC structure (100, 200, 300, 400, 500, 600, 700, 800) according to claim 4, further comprising: a third and a fourth plurality of active regions (AA), gate structures (G) and MD segments (MD) arranged above and electrically connected to the active regions (AA) arranged in the first n-well (NW2), and having a third and a fourth structure, respectively, wherein the third and fourth structures are symmetrical to the first and second structures about a second axis (X) along the first direction (X). [6] Method (900) for creating an integrated circuit layout diagram (100, 200, 300, 400, 500, 600, 700, 800), hereinafter referred to as IC layout diagram, the method (900) comprising: Aligning (902) first to third n-well regions (NW1-NW3) along a first direction (X) in the IC layout diagram (100, 200, 300, 400, 500, 600, 700, 800), wherein the first n-well region (NW2) is separated from the second and third n-well regions (NW1, NW3) by a distance (S1, S2) corresponding to a minimum n-well spacing rule; Arranging a first tapping via region (Tap) in the second n-well region (NW1); Arranging a second tapping via region (Tap) in the third n-well region (NW3); Arranging (904) a first engineering change order basic cell, hereinafter referred to as ECO basic cell, in the first n-well region (NW2); Producing (906) a first electrical connection between the second and third n-well regions (NW1, NW3) by overlapping both the first and second tapping via regions (Tap) with a first metal region (M1) extending in the first direction (X) over the first n-well region (NW2); Arranging a third and a fourth tapping via region (Tap) in the first n-well region (NW2); Establishing a second electrical connection between the third and fourth tapping via regions (tap) by overlapping both the third and fourth tapping via regions (tap) with a second metal region extending in the first direction (X) over the first ECO base cell; and Storing (910) the IC layout diagram (100, 200, 300, 400, 500, 600, 700, 800) in a storage device (1004). [7] The method (900) of claim 6, further comprising: Routing a first voltage distribution path to the first electrical connection; and Routing a second voltage distribution path to the second electrical connection, wherein the first and second voltage distribution paths are configured to distribute separate voltage levels. [8] The method (900) of any of claims 6 or 7, wherein arranging the first ECO basic cell in the first n-well region (NW2) further comprises arranging a second ECO basic cell in the first n-well region (NW2) adjacent to the first ECO basic cell in the first direction (X). [9] The method (900) of any one of claims 6 or 7, wherein arranging the first ECO basic cell in the first n-well region (NW2) further comprises: Arranging a second ECO basic cell in the first n-well region (NW2), adjacent to the first ECO basic cell in the first direction (X), wherein the first and second ECO basic cells are symmetrical to each other about a boundary between the first and second ECO basic cells; and Arranging a third and a fourth ECO basic cell in the first n-well region (NW2), in a second direction (Y) perpendicular to the first direction (X) adjacent to the first and the second ECO basic cell, wherein the first and the third ECO basic cell are symmetrical to each other about a boundary between the first and the third ECO basic cell, and the second and the fourth ECO basic cell are symmetrical to each other about a boundary between the second and the fourth ECO basic cell. [10] The method (900) of any one of claims 6 or 7, wherein arranging the first ECO basic cell in the first n-well region (NW2) further comprises: Arranging a second and a third ECO basic cell in the first n-well region (NW2), either in the first direction (X) or in a second direction (Y) perpendicular to the first direction (X) adjacent to the first ECO basic cell; and Arranging third to fifth ECO basic cells in the first n-well region (NW2), in the other of the first and second directions (X, Y) adjacent to the first to third ECO basic cells. [11] Method (900) according to one of claims 6 to 10, further comprising: Setting up (908) the first ECO base cell as a functional ECO cell; and Routing a plurality of electrical signal paths to the functional ECO cell. [12] Electronic design automation system, hereinafter referred to as EDA system, comprising: a processor (1002); and a non-transitory, computer-readable storage medium (1004) comprising computer program code (1006) for one or more programs, wherein the non-transitory, computer-readable storage medium (1004) and the computer program code (1006) are configured to interact with the processor (1002) to cause the processor (1002): disposing a first tapping via region (Tap) in a second n-well region (NW1) of first to third n-well regions (NW1-NW3) of an integrated circuit (IC) layout diagram (100, 200, 300, 400, 500, 600, 700, 800), wherein the first n-well region (NW2) is separated along a first direction (X) from the second and third n-well regions (NW1, NW3) by at least a distance (S1, S2) corresponding to a minimum n-well spacing rule; Arranging a second tapping via region (Tap) in the third n-well region (NW3); Arranging a first engineering change order basic cell, hereinafter referred to as ECO basic cell, in the first n-well region (NW2); Overlapping both the first and second tap via regions (Tap) with a first metal region (M1) extending in the first direction (X) over the first n-well region (NW2); thereby establishing a first electrical connection between the second and third n-well regions (NW3); Routing a first voltage distribution path to the first electrical connection, the first voltage distribution path configured to distribute a first voltage level (VDD); disposing a third and a fourth tapping via region (Tap) in the first n-well region (NW2); overlapping both the third and fourth tapping via regions (tap) with a second metal region extending in the first direction (X) over the first ECO base cell, thereby establishing a second electrical connection between the third and fourth tapping via regions (tap); and Routing a second voltage distribution path to the second electrical connection, wherein the second voltage distribution path is configured to distribute a second voltage level (ground) separate from the first voltage level (VDD); and Storing the IC layout diagram (100, 200, 300, 400, 500, 600, 700, 800) in a storage device (1004). [13] The EDA system (1000) of claim 12, wherein the non-transitory computer-readable storage medium (1004) and the computer program code (1006) are configured with the processor (1002) to cause the processor (1002) to further: sets up the first ECO base cell as a functional ECO cell; and routes a plurality of electrical signal paths to the functional ECO cell. [14] EDA system (1000) according to one of claims 12 or 13, wherein the first ECO base cell is a first ECO base cell of a plurality of ECO base cells, and the non-volatile, computer-readable storage medium (1004) and the computer program code (1006) are configured with the processor (1002) to cause the processor (1002) to further arrange the plurality of ECO basic cells comprising the first ECO basic cell in the first n-well region (NW2) of the IC layout diagram (100, 200, 300, 400, 500, 600, 700, 800).

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