ARRAY SUBSTATE AND DISPLAY PANEL

Abstract

The present application provides an array substrate and a display panel. The array substrate comprises a base, at least one pixel group arranged on the base, and three data line groups. Each pixel group comprises six subpixels spaced apart from one another along a first direction, each subpixel comprising at least one pixel electrode. Each data line group is associated with the pixel electrode of one of the subpixels, and the data line group is located on a side of the pixel electrode close to the base.Each of the data line groups comprises two data lines spaced apart from each other along the first direction, and the pixel electrode of each of the subpixels is electrically connected to one of the data lines; by arranging the data lines below the respective pixel electrodes in the present application, a DBS electrode can thus be omitted, thereby significantly increasing the aperture ratio of the subpixels to alleviate the problem of limited increase in aperture ratio in existing liquid crystal display panels.

Description

TECHNICAL AREA

[0001] The present application relates to the field of display technology, in particular an array substrate and a display panel. STATE OF THE ART

[0002] A liquid crystal display (LCD) panel is characterized by numerous advantages, including a thin form factor, low power consumption, and the absence of radiation. It finds widespread application and plays a dominant role in the field of flat panel displays. An LCD panel operates on the principle that liquid crystal molecules are sandwiched between a thin-film transistor (TFT) array substrate and a color filter (CF) substrate. A drive voltage is applied to these two substrates to control the rotation of the liquid crystal molecules, thereby refracting light rays from a backlight module and creating an image.

[0003] In a conventional liquid crystal display panel, a black matrix (BM) must be provided on one side of the color filter substrate to block light. When applied to a curved liquid crystal display panel, bending the panel causes a shift in the position of the BM, which in turn leads to light leakage and color deviation. To solve this problem, a design with less BM (DBS) can be used, in which the number of black matrices on data lines is reduced. That is, a DBS electrode is provided above a data line of the array substrate, located on the same layer as a pixel electrode, maintaining a state in which there is no voltage difference between the DBS electrode and a common electrode on the color filter substrate.Thus, the liquid crystal between the DBS electrode and the common electrode does not rotate and therefore exhibits a black state, blocking light instead of forming a black matrix. However, the presence of a DBS electrode limits the aperture ratio of a liquid crystal display panel. REVELATION OF THE INVENTION

[0004] The present application is based on the task of providing an array substrate and a display panel to alleviate the technical problem of limited increase in the aperture ratio in existing liquid crystal display panels.

[0005] According to the present application, the problem is solved by the following technical design: One embodiment of the present application provides an array substrate comprising the following: a base; at least one pixel group arranged on the base, each pixel group comprising six subpixels spaced apart from one another along a first direction, each of which comprises at least one pixel electrode; and three data line groups arranged on the base, each of the data line groups being assigned to the pixel electrode of one of the subpixels, and the data line group being located on a side of the pixel electrode close to the base; wherein each of the data line groups comprises two data lines spaced apart from each other along the first direction and the pixel electrode of each of the subpixels is electrically connected to one of the data lines.

[0006] In the array substrate according to the embodiment of the present application, it is provided that each of the pixel electrodes comprises a first main electrode extending along a second direction, to which the respective data line group is assigned.

[0007] In the array substrate according to the embodiment of the present application, it is provided that the orthogonal projection of the first main electrode onto the base covers the orthogonal projection of the associated data line group onto the base.

[0008] In the array substrate according to the embodiment of the present application, the first main electrode comprises a first subsection and a second subsection, wherein the first subsection is assigned to one of the data lines in the respective data line group and the second subsection is assigned to the other data line in the respective data line group.

[0009] In the array substrate according to the embodiment of the present application, the pixel electrode further comprises a second main electrode extending along the first direction, with which both the first subsection and the second subsection are electrically connected.

[0010] In the array substrate according to the embodiment of the present application, it is provided that the two data lines in the data line group each have the form of a polygon line.

[0011] In the array substrate according to the embodiment of the present application, each of the subpixels further comprises at least one transistor, wherein the pixel electrode of each of the subpixels is electrically connected to the associated transistor, and the transistor is electrically connected to the associated data line; wherein the transistors of some of the six subpixels are located on a first side of the pixel group and the transistors of the other subpixels are located on a second side of the pixel group, the first side being opposite the second side.

[0012] In the array substrate according to the embodiment of the present application, it is provided that the array substrate further comprises a first gate sensing line and a second gate sensing line extending along the first direction, wherein the first gate sensing line is electrically connected to the gates of the transistors of the first side and the second gate sensing line is electrically connected to the gates of the transistors of the second side.

[0013] In the array substrate according to the embodiment of the present application, the pixel group is provided in a plurality and the multiple pixel groups are spaced apart from each other along the second direction; wherein the array substrate further comprises a third gate scanning line extending along the first direction, wherein two adjacent pixel groups share the third gate scanning line.

[0014] In the array substrate according to the embodiment of the present application, it is provided that the array substrate further comprises several common electrode lines extending along the second direction, which are arranged on the same layer as the data lines, wherein the common electrode lines are assigned to the spaces between each two adjacent subpixels.

[0015] In the array substrate according to the embodiment of the present application, the six subpixels comprise two subpixels of the first color, two subpixels of the second color, and two subpixels of the third color; wherein one of the three data line groups is assigned to one of the two subpixels of the first color and the other two data line groups are assigned to the two subpixels of the second color, and wherein the two data lines in each of the data line groups are electrically connected to the pixel electrodes in the two subpixels of one and the same color.

[0016] In the array substrate according to the embodiment of the present application, it is provided that the polarities of the voltages on the two data lines are different in each of the data line groups.

[0017] In the array substrate according to the embodiment of the present application, the subpixels of the first color are blue subpixels, the subpixels of the second color are green subpixels, and the subpixels of the third color are red subpixels; wherein the three data line groups comprise a first data line group, a second data line group, and a third data line group, the first data line group being assigned to one of the two subpixels of the first color, and the second data line group and the third data line group being assigned to the two subpixels of the second color;wherein the two data lines in the first data line group are electrically connected to the pixel electrodes in the two subpixels of the second color, wherein the two data lines in the second data line group are electrically connected to the pixel electrodes in the two subpixels of the third color, and wherein the two data lines in the third data line group are electrically connected to the pixel electrodes in the two subpixels of the first color.;

[0018] In the array substrate according to the embodiment of the present application, it is provided that the subpixel of the first color and the subpixel of the second color are located between two adjacent subpixels of the third color, wherein the subpixel of the first color and the subpixel of the third color are located between two adjacent subpixels of the second color, wherein the subpixel of the second color and the subpixel of the third color are located between two adjacent subpixels of the first color, and wherein the subpixels of the first color, the subpixels of the second color and the subpixels of the third color are arranged successively spaced apart from each other in the first direction.

[0019] In the array substrate according to the embodiment of the present application, it is provided that the array substrate further comprises a fourth data line group, which is assigned to the other of the two subpixels of the first color, wherein the fourth data line group and the first data line group are identical.

[0020] One embodiment of the present application further provides a display panel. It comprises the array substrate according to one of the preceding embodiments.

[0021] Advantageous effects of the application: In the array substrate and the display panel according to the present application, the array substrate comprises a base, at least one pixel group arranged on the base, and three data line groups. Each pixel group comprises six subpixels spaced apart from one another along the first direction, each of which comprises at least one pixel electrode. Each of the data line groups is associated with the pixel electrode of one of the subpixels, and the data line group is located on a side of the pixel electrode close to the base.Each of the data line groups comprises two data lines spaced apart from each other along the first direction, and the pixel electrode of each of the subpixels is electrically connected to one of the data lines; by arranging the data lines below the respective pixel electrodes in the present application, a DBS electrode can thus be omitted, thereby significantly increasing the aperture ratio of the subpixels, thus solving the technical problem of limited increase in the aperture ratio in existing liquid crystal display panels. PRESENTATION OF THE REGISTRATION

[0022] To better illustrate the embodiments of the present invention or the prior art configurations, the accompanying drawings used to describe these embodiments or the prior art are briefly described below. It is understood that the following drawings represent only some embodiments of the invention and that it is possible for a person skilled in the art to derive further drawings from such drawings without inventive effort. These drawings show Fig. 1 a schematic top view of a pixel structure using a related technique; Fig. 2 a schematic structural top view of an array substrate according to an embodiment of the present application; Fig. 3 another schematic structural top view of the array substrate according to the embodiment of the present application; Fig. 4 a schematic structural detail drawing of a subpixel of first color according to Fig. 3; Fig. 5 another schematic structural detail drawing of the subpixel of the first color according to an embodiment of the present application; Fig. 6 a further schematic structural detail drawing of the subpixel of the first color according to the embodiment of the present application; Fig. 7 a further schematic structural top view of the array substrate according to the embodiment of the present application; Fig. 8 a schematic structural sectional view of a display panel according to an embodiment of the present application. SPECIFIC EXECUTION FORMS

[0023] The following are descriptions of individual embodiments with reference to the accompanying drawings, in order to illustrate certain feasible embodiments of the application as examples. Directional terms mentioned in the present application, such as "top," "bottom," "front," "back," "left," "right," "inside," "outside," "side surface," etc., are used only in relation to the respective directions in the accompanying drawings. Therefore, the directional terms used serve to describe and promote understanding of the application without limiting its scope. In the drawings, similarly designed units are identified by the same reference numeral. For better understanding and to facilitate description, the thicknesses of some layers and areas may be exaggerated in the accompanying drawings.This means that the dimensions and thicknesses of the individual components shown in the drawings are not necessarily to scale, and the application is by no means limited in this respect.

[0024] In view of the problem of limited increase in the aperture ratio of existing liquid crystal display panels, the inventor of the present application found in investigations that, due to the use of the design (Data BM less, DBS) in which the number of black matrices on data lines is reduced, in related technology a DBS electrode occupies part of the pixel space, thereby impairing the increase in the aperture ratio of the pixels.

[0025] It will be specifically addressed Fig. 1. The DBS electrode is located on the same layer as a pixel electrode PE. The DBS electrode covers an associated data line DL. The width of the DBS electrode is greater than the width of the data line DL. A common electrode CE is provided in the space between the DBS electrode and the pixel electrode PE, and part of the common electrode CE is further located below a main electrode of the pixel electrode PE. The common electrode CE is located on the same layer as a gate scanning line GL. The light shielding by the DBS electrode, in conjunction with the common electrode CE, results in a significantly reduced effective display area of ​​the liquid crystal display panel, thereby substantially lowering the aperture ratio. This, in turn, limits the possibility of increasing the aperture ratio of the liquid crystal display panel.

[0026] Therefore, the present application provides an array substrate and a display panel to solve the above problem of limited increase in aperture ratio.

[0027] It will be on Fig. Points 1 to 2 were indicated. Fig. Figure 2 shows a schematic structural top view of the array substrate according to an embodiment of the present application. It refers to Fig. 2. The array substrate 100 comprises a base 10, at least one pixel group 20 arranged on the base 10, and three data line groups 30. Each pixel group 20 comprises six subpixels spaced apart along a first direction X (for example, R1, G1, B1, R2, G2, and B2 in Fig. 2), each of which contains at least one pixel electrode 40 (for example, 40-1, 40-2, 40-3, 40-4, 40-5 and 40-6 in Fig. 2) comprises. Each of the data line groups 30 is assigned to the pixel electrode 40 of one of the subpixels, and the data line 30 is located on a side of the pixel electrode 40 close to the base 10. Each of the data line groups 30 comprises two data lines spaced apart from each other along the first direction X (for example, 31 and 32 in Fig. 2) and the pixel electrode 40 of each subpixel is electrically connected to one of the data lines. Each of the data lines extends along a second direction Y, which differs from the first direction X. Optionally, the first direction X is the horizontal direction and the second direction is the vertical direction. The first direction X is perpendicular to the second direction Y.

[0028] In the present embodiment, by arranging the data line groups 30 below the pixel electrodes 40 of the pixel group 20, the DBS electrode for light shielding of the data lines, as found in related technologies, can be omitted. This allows the pixel electrodes to be extended outwards to increase the area of ​​a subpixel aperture. Consequently, the aperture ratio of the subpixels can be significantly increased, thus solving the problem of limited aperture ratio increases in existing liquid crystal display panels.

[0029] Specifically, further details will be provided. Fig. 2. Pixel group 20 is arranged on base 10. Base 10 can be a rigid substrate or a flexible substrate; if base 10 is a rigid substrate, it can comprise a glass substrate or another hard substrate; if base 10 is a flexible substrate, it can comprise a polyimide thin film (polyimide, PI), an ultrathin glass thin film, or another flexible substrate.

[0030] Each pixel group 20 comprises six subpixels (for example, R1, G1, B1, R2, G2 and B2 in Fig. 2), the two subpixels of the first color (for example, B1 and B2 in Fig. 2), two subpixels of a second color (for example, G1 and G2 in Fig. 2) and two subpixels of a third color (for example, R1 and R2 in Fig. 2) comprise. The first color subpixel and the second color subpixel are located between two adjacent third color subpixels. For example, B1 and G1 are located between R1 and R2 in Fig. 2. The first color subpixel and the third color subpixel are located between two adjacent second color subpixels. For example, B1 and R2 are located between G1 and G2 in Fig. 2. The second color subpixel and the third color subpixel are located between two adjacent first color subpixels. For example, G2 and R2 are located between B1 and B2 in Fig. 2. That is, any three adjacent subpixels comprise a named subpixel of the first color, a named subpixel of the second color, and a named subpixel of the third color, so that any three adjacent subpixels can form a pixel.

[0031] The subpixels of the first color (for example, B1 and B2 in) are used in this process. Fig. 2) Blue subpixels, the subpixels of a second color (for example, G1 and G2 in Fig. 2) Green subpixels and the subpixels of the third color (for example, R1 and R2 in Fig. 2) Red subpixels. The blue subpixels can emit blue light. The green subpixels can emit green light. The red subpixels can emit red light. Since three adjacent subpixels comprise three colors, the pixel formed by three adjacent subpixels can emit light of different colors, thus enabling a color display.

[0032] Optionally, the subpixels of the first color, the subpixels of the second color, and the subpixels of the third color are arranged sequentially in the first direction X, spaced apart from each other. That is, the six subpixels are arranged in the first direction in the following order: subpixel of first color B2, subpixel of second color G2, subpixel of third color R2, subpixel of first color B1, subpixel of second color G1, and subpixel of third color R1, as shown in Fig. 2 shown, arranged.

[0033] The three data line groups 30 are also arranged on base 10 and assigned to some of the subpixels of pixel group 20. Each of the data line groups 30 comprises two data lines (for example, 31 and 32 in ). Fig. 2) Thus, the three data line groups 30 comprise six data lines, which are connected to the six subpixels of pixel group 20.

[0034] In detail, each subpixel comprises at least one pixel electrode 40, and each data line is electrically connected to the pixel electrode 40 of an associated subpixel. The data line is located on the side of the pixel electrode 40 closest to the base 10. That is, the data line is located between the respective pixel electrode 40 and the base 10. Thus, the data line group 30 associated with the data line is also located on the side of the respective pixel electrode 40 closest to the base 10. That is, the data group 30 is also located between the respective pixel electrode 40 and the base 10. Optionally, the material of the pixel electrode 40 includes indium tin oxide (ITO) and other transparent, electrically conductive materials.

[0035] The orthogonal projection of the data line group 30 onto the base 10 overlaps at least partially with the orthogonal projection of the associated pixel electrode 40 onto the base 10. Optionally, each of the pixel electrodes 40 includes a first main electrode 41 extending along a second direction Y, to which the respective data line group 30 is assigned. The orthogonal projection of the first main electrode 41 onto the base 10 overlaps at least partially with the orthogonal projection of the respective data line group 30 onto the base 10. The data line group 30 is assigned to the first main electrode 41.Thus, on the one hand, a DBS electrode for shielding the data line against light in a related technique can be omitted, so that the pixel electrode 40 is extended outwards to increase the area of ​​a pixel opening region and to increase the aperture ratio of the subpixels; on the other hand, the influence of the data line groups 30 on the light emission can be reduced or eliminated, since the area assigned to the first main electrode 41 is not transparent, which allows the aperture ratio of the subpixels to be increased further.

[0036] Each of the pixel electrodes 40 further comprises a second main electrode 42 extending along the first direction X, and branch electrodes 43 extending in various directions from the second main electrode 42 and / or the first main electrode 41. The second main electrode 42 intersects the first main electrode 41 and is oriented at a predetermined angle to it. For example, the second main electrode 42 runs perpendicular to the first main electrode 41 to divide the subpixel into four domains. The branch electrodes 43 are distributed within individual domains. Optionally, the pixel electrode 40 can also include a frame electrode 44 that surrounds the first main electrode 41, the second main electrode 42, and the branch electrodes 43 over half their circumference.

[0037] It should be noted that the drawings in the application only schematically depict some of the branch electrodes 43 of the pixel electrode 40. For example, in Fig. Two branch electrodes 43 per domain are shown, but the present application is by no means limited to this. The pixel electrode 40 according to the present application can also comprise more or fewer branch electrodes 43. Furthermore, embodiments of the application are described using the example of an embodiment in which each of the subpixels is subdivided into four domains. The present application is also not limited to this, and rather, alternatively, subpixels in the present application can each be subdivided into two domains, six domains, eight domains, etc.

[0038] Furthermore, one of the three data line groups 30 is assigned to one of the two subpixels of the first color and the other two data line groups 30 are assigned to the two subpixels of the second color.

[0039] In detail, the three data line groups 30 comprise a first data line group 30-1, a second data line group 30-2, and a third data line group 30-3. The first data line group 30-1 is assigned to one of the two subpixels of the first color, and the second data line group 30-2 and the third data line group 30-3 are assigned to the two subpixels of the second color. The two data lines in each of the data line groups are electrically connected to the pixel electrodes in the two subpixels of the same color in order to compensate for a coupling capacitor between subpixels and to improve longitudinal crosstalk and color deviation.

[0040] The two data lines in the first data line group 30-1 are electrically connected to the pixel electrodes in the two subpixels of the second color. The two data lines in the second data line group 30-2 are electrically connected to the pixel electrodes in the two subpixels of the third color. The two data lines in the third data line group 30-3 are electrically connected to the pixel electrodes in the two subpixels of the first color.

[0041] Optionally, the polarities of the voltages on the two data lines in each of the data line groups 30 are different to reduce coupling effects on the pixel voltage when a data signal changes and to lower the risk of longitudinal crosstalk. Specifically, the two data lines in each of the data line groups 30 are a first data line 31 and a second data line 32. The polarity of the voltage on the first data line 31 and the polarity of the voltage on the second data line 32 are different. For example, the voltage on the first data line 31 has a positive polarity and the voltage on the second data line 32 has a negative polarity; alternatively, the voltage on the first data line 31 has a negative polarity and the voltage on the second data line 32 has a positive polarity.

[0042] To better illustrate the connection between the data lines and the associated subpixels, one of the two subpixels of the same color is defined as 1 and the other as 2. For example, one of the two subpixels of the first color is B1 and the other subpixel of the first color is B2. Similarly, one of the two subpixels of the second color is G1 and the other subpixel of the second color is G2. One of the two subpixels of the third color is R1 and the other subpixel of the third color is R2. The six subpixels are arranged on base 10 along the first direction X in the following order: subpixel of first color B2, subpixel of second color G2, subpixel of third color R2, subpixel of first color B1, subpixel of second color G1, and subpixel of third color R1.

[0043] Furthermore, pixel electrodes 40, which are assigned to the individual subpixels, are defined. For example, the pixel electrode of the first color subpixel B2 is 40-6. The pixel electrode of the second color subpixel G2 is 40-5. The pixel electrode of the third color subpixel R2 is 40-4. The pixel electrode of the first color subpixel B1 is 40-3. The pixel electrode of the second color subpixel G1 is 40-2. The pixel electrode of the third color subpixel R1 is 40-1.

[0044] Each subpixel further comprises at least one transistor. The pixel electrode 40 of each subpixel is electrically connected to the associated transistor. In detail, each pixel electrode 40 further comprises a connecting electrode 45, and the pixel electrode 40 of each subpixel is electrically connected to the associated transistor via the connecting electrode 45. The transistor is also electrically connected to the associated data line. The transistors of some of the six subpixels are located on a first side of the pixel group 20, and the transistors of the other subpixels are located on a second side of the pixel group 20, with the first side facing the second side to equalize the aperture ratios of the individual subpixels, increase display uniformity, and avoid large deviations in the aperture ratios of the subpixels from one another due to the arrangement of the transistors on the same side of the pixel group 20.

[0045] Similarly, the transistor for each subpixel is defined. For example, the transistor for subpixel B2 (first color) is T6. The transistor for subpixel G2 (second color) is T4. The transistor for subpixel R2 (third color) is T2. The transistor for subpixel B1 (first color) is T5. The transistor for subpixel G1 (second color) is T3. The transistor for subpixel R1 (third color) is T1.

[0046] Each transistor comprises a gate, a source, and a drain. Using transistor T1 of the third color subpixel R1 as an example, transistor T1 comprises a gate GE, a source S1, and a drain D1. It is understood that each transistor also includes an active layer, which is not shown.

[0047] The array substrate 100 further comprises a first gate sensing line 51 and a second gate sensing line 52, extending along the first direction X. The first gate sensing line 51 is electrically connected to the gates of the transistors on the first side of pixel group 20, and the second gate sensing line 52 is electrically connected to the gates of the transistors on the second side of pixel group 20. For example, the first gate sensing line 51 is electrically connected to the gates of transistors T3, T4, T5, and T6, while the second gate sensing line 52 is electrically connected to the gates of transistors T1 and T2.

[0048] The following is based on reference to Fig. 2. The connection relationship between the pixel group 20 and the data line groups 30 was discussed in more detail.

[0049] It will be on Fig. 2. The pixel electrode 40-6 in the first color subpixel B2 is electrically connected to transistor T6, which is further electrically connected to the second data line 32 in the third data line group 30-3. The pixel electrode 40-3 in the first color subpixel B1 is electrically connected to transistor T5, which is further electrically connected to the first data line 31 in the third data line group 30-3. The pixel electrode 40-5 in the second color subpixel G2 is electrically connected to transistor T4, which is further electrically connected to the second data line 32 in the first data line group 30-1. The pixel electrode 40-2 in the second color subpixel G1 is electrically connected to transistor T3, which is further electrically connected to the first data line 31 in the first data line group 30-1.The pixel electrode 40-4 in the third color subpixel R2 is electrically connected to transistor T2, which is further electrically connected to the second data line 32 in the second data line group 30-2. The pixel electrode 40-1 in the third color subpixel R1 is electrically connected to transistor T1, which is further electrically connected to the first data line 31 in the second data line group 30-2.

[0050] One embodiment is made up of Fig. 1 to 4 can be taken from. Fig. Figure 3 shows another schematic structural top view of the array substrate according to the embodiment of the present application. Fig. Figure 4 shows a schematic structural detail drawing of the first color subpixel according to Fig. 3. In contrast to the embodiments described above, the array substrate 101 in the present embodiment is provided that the first main electrode 41 comprises a first subsection 411 and a second subsection 412, and both the first subsection 411 and the second subsection 412 are electrically connected to the second main electrode 42. The first subsection 411 is assigned to one of the data lines in the respective data line group 30, and the second subsection 412 is assigned to the other data line in the respective data line group 30, in order to optimize the interaction of the liquid crystal and to avoid dark streaks during alignment.

[0051] The details will be discussed on Fig. 3 and Fig. 4. In the case of the subpixels assigned to the respective data line groups 30, the first main electrode 41 of the pixel electrode comprises two parts. Using the example of pixel electrode 40-3 of the subpixel of first color B1, the subpixel of first color B1 is assigned to the first data line group 30-1. As in Fig. As shown in Figure 4, the first main electrode 41 comprises a first subsection 411 and a second subsection 412. The first subsection 411 is assigned to the first data line 31 in the first data line group 30-1. The second subsection 412 is assigned to the second data line 32 in the first data line group 30-1.

[0052] Furthermore, in the present embodiment, the array substrate 101 also comprises several common electrode lines 60 extending along the second direction Y, which are arranged on the same layer as the data line groups 30. That is, the common electrode lines 60 are arranged on the same layer as each of the data lines. Furthermore, the common electrode lines 60 are assigned to the spaces between each pair of adjacent subpixels. For example, the common electrode line 60 is located in Fig. 3 is assigned to the space between the third color subpixel R2 and the first color subpixel B1. Thus, in comparison to the pixel structure according to Fig. 1. During registration, by changing the position of the data lines, a common electrode CE, which is arranged in a related technique on the same layer as the gate scanning line GL, can be eliminated, thereby reducing the coupling effect for the common voltage when a data signal is changed, lowering the risk of crosstalk in the longitudinal direction and further increasing the image quality.

[0053] It should be noted that in the present application, "arrangement on the same layer" means that, during the manufacturing process, a membrane layer made of one and the same material is structured, thereby obtaining at least two different structures. Thus, the at least two structures are arranged on the same layer. In the present embodiment, for example, the data lines and the common electrode lines 60 are obtained by structuring one and the same electrically conductive membrane layer. Thus, the data lines and the common electrode lines 60 are arranged on the same layer.

[0054] It will continue on Fig. 3. Optionally, the array substrate 101 further comprises a fourth data line group 30-4, which is assigned to the other of the two first-color subpixels. For example, the fourth data line group 30-4 is assigned to first-color subpixel B2, and the first data line group 30-1 is assigned to first-color subpixel B1. The fourth data line group 30-4 and the first data line group 30-1 are identical in order to maintain a uniform opening of the two first-color subpixels and thus reduce color deviation. The data lines in the fourth data line group 30-4 are dummy signal lines and are not electrically connected to the subpixel. Further details can be found in the exemplary embodiments above, and repetition is omitted here.

[0055] To avoid dark streaks during alignment, in another embodiment the configurations according to Fig. 5 and Fig. 6 can be used. Fig. Figure 5 shows another schematic structural detail drawing of the subpixel of the first color according to an embodiment of the present application and Fig. Figure 6 shows a further schematic structural detail drawing of the subpixel of the first color according to the embodiment of the present application. It refers to Fig. 5. The orthogonal projection of the first main electrode 41 onto the base 10 covers the orthogonal projection of the associated data line group 30 onto the base 10. It is pointed out that Fig. 6. The two data lines in data line group 30 each have the form of a polygon line.

[0056] The following description is also given in detail using the example of pixel electrode 40-3 of the first color subpixel B1. The first color subpixel B1 is assigned to the first data line group 30-1. As in Fig. As shown in Figure 5, the orthogonal projection of the first main electrode 41 of the pixel electrode 40-3 onto the base 10 covers the orthogonal projection of the first data line group 30-1 onto the base 10. That is, the width of the first main electrode 41 is greater than the sum of the widths of the first data line 31 and the second data line 32 in the first data line group 30-1.

[0057] It will be on Fig. 6. The first main electrode 41 of the pixel electrode 40-3 comprises a first subsection 411 and a second subsection 412, which overlap in the second direction Y. That is, the first subsection 411 and the second subsection 412 are located on the same straight line. The first data line 31 in the first data line group 30-1 has the form of a polygon. Part of the first data line 31 is associated with the first subsection 411, and the other part is located between the first subsection 411 and the frame electrode 44. That is, part of the first data line 31 is covered by the first subsection 411, and the other part is not covered by the first subsection 411. Accordingly, the second data line 32 in the first data line group 30-1 also has the form of a polygon.Part of the second data line 32 is assigned to the second subsection 412, and the other part is located between the second subsection 412 and the frame electrode 44. That is, part of the second data line 32 is covered by the second subsection 412, and the other part is not. Further details can be found in the exemplary embodiments above, and repetition is omitted here.

[0058] One embodiment is made up of Fig. 1 to 7 can be found here. Fig. Figure 7 shows another schematic structural top view of the array substrate according to the embodiment of the present application. In contrast to the embodiments above, the array substrate 102 according to the present embodiment is provided that the pixel group 20 is provided in a plurality and the multiple pixel groups 20 are spaced apart from one another along the second direction Y; the array substrate 102 further comprises a third gate scanning line 53 extending along the first direction X, wherein two adjacent pixel groups 20 share the third gate scanning line 53 in order to reduce the number of gate scanning lines. Further details can be found in the embodiments above and are not repeated here.

[0059] Based on the same fundamental idea, one embodiment of the application also provides a display panel. It is displayed on Fig. 1 to 8 were indicated. Fig.Figure 8 shows a schematic structural sectional view of the display panel according to an embodiment of the present application. The display panel 1000 comprises the array substrate 100 according to one of the preceding embodiments. The display panel 1000 further comprises a color filter substrate 200, which is arranged opposite the array substrate 100, and liquid crystal molecules 300, which are arranged between the array substrate 100 and the color filter substrate 200.

[0060] The following can be seen from the above examples: The present application provides an array substrate and a display panel. The array substrate comprises a base, at least one pixel group arranged on the base, and three data line groups. Each pixel group comprises six subpixels spaced apart along the first direction, each subpixel comprising at least one pixel electrode. Each data line group is associated with the pixel electrode of one of the subpixels, and the data line group is located on a side of the pixel electrode close to the base.Each of the data line groups comprises two data lines spaced apart from each other along the first direction, and the pixel electrode of each of the subpixels is electrically connected to one of the data lines; by arranging the data lines below the respective pixel electrodes in the present application, a DBS electrode can thus be omitted, thereby significantly increasing the aperture ratio of the subpixels, thus solving the technical problem of limited increase in the aperture ratio in existing liquid crystal display panels.

[0061] The preceding exemplary embodiments describe individual embodiments with different focuses. For parts that are not explained in detail in a particular embodiment, reference can be made to the relevant descriptions in other embodiments.

[0062] The embodiments of the application have been presented in detail so far. The principle and embodiments of the application have been explained using concrete examples, and the description of the embodiments above serves only to support the understanding of the technical features of the application and its core ideas. It is understood by those skilled in the art in this field that modifications to the technical features described in the preceding embodiments or equivalent substitutions of some or all of the technical features contained therein are still possible. However, such modifications or substitutions do not result in the main ideas of the corresponding technical features deviating from the scope of the technical features of the individual embodiments of the present application.

Claims

[1] Array substrate, characterized by that it includes: a base; at least one pixel group arranged on the base, each pixel group comprising six subpixels spaced apart from one another along a first direction, each of which subpixels comprises at least one pixel electrode; and three data line groups arranged on the base, each of the data line groups being associated with the pixel electrode of one of the subpixels, the data line group being located on a side of the pixel electrode close to the base; wherein each of the data line groups comprises two data lines arranged spaced apart from each other along the first direction, and the pixel electrode of each of the subpixels is electrically connected to one of the data lines. [2] Array substrate according to claim 1, characterized bythat each of the pixel electrodes comprises a first main electrode extending along a second direction, to which the respective data line group is assigned. [3] Array substrate according to claim 2, characterized by that the orthogonal projection of the first main electrode onto the base covers the orthogonal projection of the associated data line group onto the base. [4] Array substrate according to claim 2, characterized by in that the first main electrode comprises a first subsection and a second subsection, wherein the first subsection is assigned to one of the data lines in the respective data line group and the second subsection is assigned to the other data line in the respective data line group. [5] Array substrate according to claim 4, characterized bythat the pixel electrode further comprises a second main electrode extending along the first direction, to which both the first subsection and the second subsection are electrically connected. [6] Array substrate according to claim 4, characterized by that the two data lines in the data line group each have the shape of a polygon line. [7] Array substrate according to claim 1, characterized by in that each of the subpixels further comprises at least one transistor, wherein the pixel electrode of each of the subpixels is electrically connected to the associated transistor, wherein the transistor is electrically connected to the associated data line; wherein the transistors of some of the six subpixels are located on a first side of the pixel group and the transistors of the other subpixels are located on a second side of the pixel group, wherein the first side is opposite the second side. [8] Array substrate according to claim 7, characterized by in that the array substrate further comprises a first gate scan line and a second gate scan line extending along the first direction, wherein the first gate scan line is electrically connected to the gates of the transistors of the first side and the second gate scan line is electrically connected to the gates of the transistors of the second side. [9] Array substrate according to claim 7, characterized by in that the pixel group is provided in a plurality, and the plurality of pixel groups are arranged spaced apart from each other along the second direction; wherein the array substrate further comprises a third gate scanning line extending along the first direction, wherein two adjacent pixel groups share the third gate scanning line. [10] Array substrate according to claim 1, characterized bythat the array substrate further comprises a plurality of common electrode lines extending along the second direction, which are arranged on the same layer as the data lines, wherein the common electrode lines are assigned to the spaces between each two adjacent subpixels. [11] Array substrate according to one of claims 1 to 10, characterized by that the six subpixels comprise two subpixels of first color, two subpixels of second color, and two subpixels of third color; wherein one of the three data line groups is assigned to one of the two subpixels of first color and the other two data line groups are assigned to the two subpixels of second color, and wherein the two data lines in each of the data line groups are electrically connected to the pixel electrodes in the two subpixels of one and the same color. [12] Array substrate according to claim 11, characterized bythat the polarities of the voltages on the two data lines in each of the data line groups are different. [13] Array substrate according to claim 11, characterized byin that the first-color subpixels are blue subpixels, the second-color subpixels are green subpixels, and the third-color subpixels are red subpixels; wherein the three data line groups comprise a first data line group, a second data line group, and a third data line group, the first data line group being assigned to one of the two first-color subpixels, and the second data line group and the third data line group being assigned to the two second-color subpixels; wherein the two data lines in the first data line group are electrically connected to the pixel electrodes in the two second-color subpixels, the two data lines in the second data line group are electrically connected to the pixel electrodes in the two third-color subpixels, and the two data lines in the third data line group are electrically connected to the pixel electrodes in the two first-color subpixels. [14] Array substrate according to claim 13, characterized by that the subpixel of the first color and the subpixel of the second color are located between two adjacent subpixels of the third color, wherein the subpixel of the first color and the subpixel of the third color are located between two adjacent subpixels of the second color, wherein the subpixel of the second color and the subpixel of the third color are located between two adjacent subpixels of the first color, and wherein the subpixels of the first color, the subpixels of the second color and the subpixels of the third color are arranged spaced from one another in the first direction. [15] Array substrate according to claim 13, characterized by that the array substrate further comprises a fourth data line group associated with the other of the two first color subpixels, wherein the fourth data line group and the first data line group are identical. [16] Display panel, characterized by that it comprises the array substrate according to one of claims 1 to 15.

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