Turn-on acceleration of current mirrors with high input current variation

Abstract

The invention relates to a current mirror with a MOS reference transistor (T1), the first terminal of which is connected to a reference potential (GND) and the control terminal and second terminal of which are connected to a reference voltage line (Vref). The turn-on accelerated current mirror comprises a current source transistor (T2), the first terminal of which is connected to the reference potential (GND) and the control terminal of which is connected to the reference voltage line (Vref). The MOS reference transistor (T1) diverts an input current (Iin) to the reference potential (GND) via its second terminal. The current source transistor (T2) diverts an output current (Iout) to the reference potential (GND) via its second terminal, which output current is proportional to the input current (Iin).The current mirror comprises a second current source transistor (T3), the first terminal of which is connected to the reference potential (GND) and the control terminal of which current source transistor (T3) is connected to the reference voltage line (Vref), and the second current source transistor (T3) diverts an output current (Iist) to the reference potential (GND) via its second terminal, which is proportional to the input current (Iin). The first switch (T4) is closed when the value of the output current (Iist) is less than the current value of the reference current (Iref) multiplied by a first positive numerical value greater than zero, and opened when the value of the output current (Iist) is greater than the current value of the reference current (Iref) multiplied by a second positive numerical value greater than zero.

Description

Field of the InventionThe invention is directed to power-on accelerated current mirrors.General IntroductionIn current mirrors from the prior art, currently different turn-on delays are tolerated or a plurality of current mirrors with different dimensions are used in order to be able to control the turn-on delay.Current mirrors which are capable of wide current range (e.g. 1mA... 100 mA) typically have too long start-up times at low currents due to the gate-source capacitance.However, the aim is to realize equal turn-on delay for all adjustable currents at the gate drivers of the current source transistors.The object is to provide a method for performing a processThe proposal is therefore based on the object of creating a solution which does not have the above disadvantages of the prior art and has further advantages. This object is achieved by the technical teaching of the independent claims. Further embodiments are optionally the subject matter of dependent claims.Solution of the ProblemIn the case of a turn-on-accelerated current mirror of the type described at the beginning, the object is achieved according to the proposal in that the reference line is drawn with the reference voltage V ref to a positive potential when an output current of an auxiliary current mirror is not yet drawing an electrical output current.For this purpose, after the switch-on accelerated current mirror has been switched on, the proposed device increases an injected, considerably higher primary current until an output-side current begins to flow.The document presented here refers to the attached Figure 1.The basic idea is to generate an output current I ist of this auxiliary current mirror by means of an auxiliary circuit as a function of the reference voltage V ref within the current mirror by means of an auxiliary current mirror and then to compare this with a reference current I ref. If the output current I ist of this auxiliary current mirror is too small in terms of absolute value compared to the current value of the reference current I ref the device according to the proposal can then conclude that the parasitic capacitances have not yet been sufficiently charged. By connecting the reference voltage line to the reference voltage V ref within the current mirror to the positive supply voltage line via a switch (T4), the device according to the invention can then rapidly recharge these parasitic capacitances. As a result, the reference voltage V ref increases and the magnitude of the output current I ist of the auxiliary current mirror increases. If the output current I ist of this auxiliary current mirror is sufficiently large or greater in terms of absolute value compared to the current value of the reference current I ref the device according to the proposal can then conclude that the parasitic capacitances are sufficiently charged. By isolating the reference voltage line with the reference voltage V ref within the current mirror from the positive supply voltage line by opening said switch (T4), the device according to the invention can then prevent an excessively high charge of the parasitic capacitances and an output current I out at the second terminal of the current mirror transistor T2 which is excessively high in terms of amount. The proposed device thus essentially performs the following steps:• Comparison of the current flowing on the output side with a reference current.• Activating a current-limited switch T4 if no output current I ist and thus no output current I out flows on the output side.• Deactivation of the current-limited switch T4 if an output current I ist and thus an output current I out flows on the output side.The document presented here thus discloses a turn-on accelerated current mirror. The turn-on accelerated current mirror preferably comprises a reference MOS transistor T1 having its first terminal connected to a reference potential (GND) and its control terminal connected to the reference voltage line V ref and a second terminal connected to a reference voltage line V ref. The second terminal of the MOS reference transistor T1 derives an input current I in with respect to the reference potential GND. The turn-on accelerated current mirror comprises a current source transistor T2 which is connected with a first terminal to the reference potential GND and which is connected with its control terminal to the reference voltage line V ref and which derives with its second terminal an output current I out against the reference potential GND which is proportional to the input current I in. In this case, the turn-on-accelerated current mirror comprises a second current source transistor T 3 which is connected by a first terminal to the reference potential GND and is connected by its control terminal to the reference voltage line V ref. The second current source transistor T 3 derives an output current I ist with a second terminal against the reference potential GND, which is proportional to the input current I in. The power-on accelerated current mirror preferably comprises a current comparator Icmp which compares the value of the output current I ist with the value of a reference current I ref. The turn-on accelerated current mirror preferably has a first switch T 4, which is configured to electrically connect a positive supply voltage line V bat to the reference voltage line V ref in the closed state and to electrically disconnect the positive supply voltage line V bat from the reference voltage line V ref in the open state. The switched-on accelerated current mirror is preferably configured to close the first switch T 4 between a positive supply voltage line V bat and the reference voltage line V ref when the current comparator Icmp determines a value of the output current I ist which is smaller than the current value of the reference current I ref multiplied by a first positive numerical value greater than zero. The turn-on accelerated current mirror is preferably configured to open the first switch T 4 between a positive supply voltage line V bat and the reference voltage line V ref when the current comparator Icmp determines a value of the output current I ist that is greater than the current value of the reference current I ref multiplied by a second positive numerical value greater than zero, wherein the first positive numerical value may be equal to the second positive numerical value.Instead of an electronically controlled electrical switch T 4, the device according to the invention can also use an electrically controlled resistor T 4 or a functionally equivalent device.In this case, the turn-on-accelerated current mirror preferably has a first switch T 4, which is configured to electrically connect a positive supply voltage line V bat to the reference voltage line V ref as an electrical resistor having a first electrical resistance value in the closed state and to electrically connect the positive supply voltage line V bat to the reference voltage line V ref as an electrical resistor having a second electrical resistance value in the open state, wherein the first electrical resistance value is typically smaller in magnitude than the second electrical resistance value.The switched-on accelerated current mirror is preferably configured to close the first switch T 4 between a positive supply voltage line V bat and the reference voltage line V ref when the current comparator Icmp determines a value of the output current I ist which is smaller than the current value of the reference current I ref multiplied by a first positive numerical value greater than zero. The turn-on accelerated current mirror is preferably configured to open the first switch T 4 between a positive supply voltage line V bat and the reference voltage line V ref when the current comparator Icmp determines a value of the output current I ist that is greater than the current value of the reference current I ref multiplied by a second positive numerical value greater than zero, wherein the first positive numerical value may be equal to the second positive numerical value.These apparatuses correspond to corresponding methods which likewise describe the document presented here:The document presented here thus discloses a method for accelerating the switching on of a current mirror, comprising the steps ofproviding a turn-on accelerated current mirror, wherein the current mirror comprises a reference MOS transistor T1 and wherein the reference MOS transistor T1 is connected by a first terminal to a reference potential GND and wherein the control terminal of the reference MOS transistor T1 is connected to the reference voltage line V ref and wherein the reference MOS transistor T1 is connected by a second terminal to a reference voltage line V ref and wherein the reference MOS transistor T1 derives by a second terminal an input current I in against the reference potential GND and wherein the current mirror comprises a current source transistor T2 and wherein the current source transistor T2 is connected by a first terminal to the reference potential GND and wherein the current source transistor T2 is connected to the reference potential GND its control terminal is connected to the reference voltage line V ref and the current source transistor T2 derives with a second terminal an output current I out to the reference potential GND, which is proportional to the input current I in ;providing a second current source transistor T3, wherein the second current source transistor (T3) has a first terminal connected to the reference potential GND, and wherein the second current source transistor T3 has its control terminal connected to the reference voltage line V ref ;deriving an output current I ist to the reference potential GND via a second terminal of the current source transistor T3, the output current I ist being proportional to the input current I in ;comparing the value of the output current I ist with the value of a reference current I ref, in particular by means of a current comparator Icmp, wherein the switch-on accelerated current mirror comprises a first switch T4 which is configured for the purpose of:;connecting a positive supply voltage line V bat to the reference voltage line V ref, when the value of the output current I ist is less than the current value of the reference current I ref multiplied by a first positive numerical value greater than zero;disconnecting the positive supply voltage line V bat from the reference voltage line V ref, when the value of the output current I ist is greater than the current value of the reference current I ref multiplied by a first positive numerical value greater than zero;The last two steps can also be realized by changing the resistance value of a switchable resistor. The method then alternatively comprises the steps of:connecting a positive supply voltage line V bat to the reference voltage line V ref by means of an electronic component (in particular first switch T4) with a first resistance value when the value of the output current I ist is less than the current value of the reference current I ref multiplied by a first positive numerical value greater than zero;connecting a positive supply voltage line V bat to the reference voltage line V ref by means of an electronic component (in particular first switch T4 with a second resistance value when the value of the output current I ist is greater than the current value of the reference current I ref multiplied by a first positive numerical value greater than zero, wherein the first resistance value is smaller in terms of amount than the second resistance value;Advantage Of the InventionSuch a turn-on-accelerated current mirror enables, at least in some implementations, the substantially faster establishment of the operational readiness of the current mirror. However, the advantages are not limited to this. Such a turn-on-accelerated current mirror typically avoids greater tolerances in the transient time of such a current mirror. Typical applications would be, for example, use in driver stages of motor drivers, use in gate drivers with current source characteristics, etc.List of the FiguresFIG. 1 shows the basic internal structure of the proposed turn-on-accelerated current mirror. For the purpose of description, the document presented herein refers to the foregoing description.DisclaimerThe above description is not intended to be exhaustive and does not limit this disclosure to the examples shown. Other variations to the disclosed examples may be understood and carried out by those of ordinary skill in the art from the drawings, disclosure, and claims. The indefinite articles "a" or "an" and their flexions do not exclude a plurality, while mentioning a certain number of elements does not exclude the possibility that more or fewer elements are present. A single unit may perform the functions of multiple elements mentioned in the disclosure, and conversely, multiple elements may perform the function of a unit. Numerous alternatives, equivalents, variations, and combinations are possible without departing from the scope of the present disclosure. Unless otherwise stated, all features of the present invention can be freely combined with each other. This relates to the entire document presented here. Unless otherwise indicated, the features described in the description of the figures can also be freely combined as features of the invention with the other features. A restriction of individual features of the exemplary embodiments to the combination with other features of the exemplary embodiments is expressly not provided in this case. In addition, physical features of the device can also be used as method features and method features can be used as physical features of the device. Such reformulation is thus automatically disclosed.In the foregoing detailed description, reference is made to the accompanying drawings. The examples in the specification and drawings should be considered as illustrative and are not to be considered as limiting to the specific example or element described. From the foregoing description and / or the drawings and / or the claims, several examples may be derived by altering, combining, or varying certain elements. Moreover, examples or elements that are not described literally may be derived by one of ordinary skill in the art from the description and / or drawings.

Claims

Turn-on accelerated current mirror comprising a reference MOS transistor (T1), wherein the reference MOS transistor (T1) is connected by a first terminal to a reference potential (GND) and wherein the control terminal of the reference MOS transistor (T1) is connected to the reference voltage line (V ref) and wherein the reference MOS transistor (T1) is connected by a second terminal to a reference voltage line (V ref) and wherein the reference MOS transistor (T1) derives by a second terminal an input current (I in) to the reference potential (GND), and comprising a current source transistor (T2), wherein the current source transistor (T2) is connected with a first terminal to the reference potential (GND), and wherein the current source transistor (T2) is connected with its control terminal to the reference voltage line (V ref) and wherein the current source transistor (T2) is configured to derive with a second terminal an output current (I out) against the reference potential (GND), which is proportional to the input current (I in), characterized in that the power-on accelerated current mirror comprises a second current source transistor (T3), and wherein the second current source transistor (T3) is connected by a first terminal to the reference potential (GND), and wherein the second current source transistor (T3) is connected by its control terminal to the reference voltage line (V ref) and wherein the second current source transistor (T3) is configured to derive by a second terminal an output current (I ist) to the reference potential (GND) which is proportional to the input current (I in) and wherein the power-on accelerated current mirror comprises a current comparator (Icmp) configured to derive, comparing the value of the output current (I ist) with the value of a reference current (I ref) and wherein the power-on accelerated current mirror comprises a first switch (T4) which is configured to electrically connect a positive supply voltage line (V bat) to the reference voltage line (V ref) in the closed state and to electrically disconnect the positive supply voltage line (V bat) from the reference voltage line (V ref) in the open state, and wherein the power-on accelerated current mirror is configured to, the first switch (T4) between a positive supply voltage line (V bat) and the reference voltage line (V ref) to close when the current comparator (Icmp) determines a value of the output current (I ist) which is smaller than the current value of the reference current (I ref) multiplied by a first positive numerical value greater than zero, and wherein the switched-on accelerated current mirror is configured to open the first switch (T4) between a positive supply voltage line (V bat) and the reference voltage line (V ref), when the current comparator (Icmp) determines a value of the output current (I ist) that is greater than the current value of the reference current (I ref) multiplied by a second positive numerical value greater than zero, wherein the first positive numerical value may be equal to the second positive numerical value.Turn-on accelerated current mirror comprising a reference MOS transistor (T1), wherein the reference MOS transistor (T1) is connected by a first terminal to a reference potential (GND) and wherein the control terminal of the reference MOS transistor (T1) is connected to the reference voltage line (V ref) and wherein the reference MOS transistor (T1) is connected by a second terminal to a reference voltage line (V ref) and wherein the reference MOS transistor (T1) is configured to derive by a second terminal an input current (I in) to the reference potential (GND), and comprising a current source transistor (T2), wherein the current source transistor (T2) is connected with a first terminal to the reference potential (GND), and wherein the current source transistor (T2) is connected with its control terminal to the reference voltage line (V ref) and wherein the current source transistor (T2) is configured to derive with a second terminal an output current (I out) against the reference potential (GND), which is proportional to the input current (I in), characterized in that the power-on accelerated current mirror comprises a second current source transistor (T3), and wherein the second current source transistor (T3) is connected by a first terminal to the reference potential (GND), and wherein the second current source transistor (T3) is connected by its control terminal to the reference voltage line (V ref) and wherein the second current source transistor (T3) is configured to derive by a second terminal an output current (I ist) to the reference potential (GND) which is proportional to the input current (I in) and wherein the power-on accelerated current mirror comprises a current comparator (Icmp) configured to derive, comparing the value of the output current (I ist) with the value of a reference current (I ref) and wherein the power-on accelerated current mirror has a first switch (T4) which is configured to electrically connect a positive supply voltage line (V bat) to the reference voltage line (V ref) as an electrical resistor having a first electrical resistance value in the closed state and to electrically connect the positive supply voltage line (V bat) to the reference voltage line (V ref) as an electrical resistor having a second electrical resistance value in the open state, wherein the first electrical resistance value 1 and wherein the power-on accelerated current mirror is configured to, the first switch (T4) between a positive supply voltage line (V bat) and the reference voltage line (V ref) to close when the current comparator (Icmp) determines a value of the output current (I ist) which is smaller than the current value of the reference current (I ref) multiplied by a first positive numerical value greater than zero, and wherein the switched-on accelerated current mirror is configured to open the first switch (T4) between a positive supply voltage line (V bat) and the reference voltage line (V ref), when the current comparator (Icmp) determines a value of the output current (I ist) that is greater than the current value of the reference current (I ref) multiplied by a second positive numerical value greater than zero, wherein the first positive numerical value may be equal to the second positive numerical value.Method for accelerating the switching on of a current mirror, comprising the steps of providing a current mirror, wherein the current mirror comprises a reference MOS transistor (T1), and wherein the reference MOS transistor (T1) is connected by a first terminal to a reference potential (GND), and wherein the control terminal of the reference MOS transistor (T1) is connected to the reference voltage line (V ref) and wherein the reference MOS transistor (T1) is connected by a second terminal to a reference voltage line (V ref) and wherein the reference MOS transistor (T1) derives by a second terminal an input current (I in) to the reference potential (GND), and wherein the current mirror comprises a current source transistor (T2), and wherein the current source transistor (T2) is connected with a first terminal to the reference potential (GND), and wherein the current source transistor (T2) is connected with its control terminal to the reference voltage line (V ref) and wherein the current source transistor (T2) derives with a second terminal an output current (I out) against the reference potential (GND), which is proportional to the input current (I in) ; providing a second current source transistor (T3), wherein the second current source transistor (T3) is connected with a first terminal to the reference potential (GND) and wherein the second current source transistor (T3) is connected with its control terminal to the reference voltage line (V ref) ; deriving an output current (I ist) to the reference potential (GND) via a second terminal of the current source transistor (T3), wherein the output current (I ist) is proportional to the input current (I in) ; comparing the value of the output current (I ist) with the value of a reference current (I ref), in particular by means of a current comparator (Icmp); connecting a positive supply voltage line (V bat) to the reference voltage line (V ref), when the value of the output current (I ist) is less than the current value of the reference current I ref multiplied by a first positive numerical value greater than zero; disconnecting the positive supply voltage line (V bat) from the reference voltage line (V ref), when the value of the output current (I ist) is greater than the current value of the reference current (I ref) multiplied by a first positive numerical value greater than zero.Method for accelerating the switching on of a current mirror, comprising the steps of providing a current mirror, wherein the current mirror comprises a reference MOS transistor (T1), and wherein the reference MOS transistor (T1) is connected by a first terminal to a reference potential (GND), and wherein the control terminal of the reference MOS transistor (T1) is connected to the reference voltage line (V ref) and wherein the reference MOS transistor (T1) is connected by a second terminal to a reference voltage line (V ref) and wherein the reference MOS transistor (T1) derives by a second terminal an input current (I in) to the reference potential (GND), and wherein the current mirror comprises a current source transistor (T2), and wherein the current source transistor (T2) is connected with a first terminal to the reference potential (GND), and wherein the current source transistor (T2) is connected with its control terminal to the reference voltage line (V ref) and wherein the current source transistor (T2) derives with a second terminal an output current (I out) against the reference potential (GND), which is proportional to the input current (I in) ; providing a second current source transistor (T3), wherein the second current source transistor (T3) is connected with a first terminal to the reference potential (GND) and wherein the second current source transistor (T3) is connected with its control terminal to the reference voltage line (V ref) ; deriving an output current (I ist) to the reference potential (GND) via a second terminal of the current source transistor (T3), wherein the output current (I ist) is proportional to the input current (I in) ; comparing the value of the output current (I ist) with the value of a reference current (I ref), in particular by means of a current comparator (Icmp); connecting a positive supply voltage line (V bat) to the reference voltage line (V ref) by means of an electronic component (in particular first switch (T4)) with a first resistance value when the value of the output current (I ist) is less than the current value of the reference current I ref multiplied by a first positive numerical value greater than zero; connecting a positive supply voltage line (V bat) to the reference voltage line (V ref) by means of an electronic component (in particular first switch (T4)) with a second resistance value if the value of the output current (I ist) is greater than the current value of the reference current (I ref) multiplied by a first positive numerical value greater than zero, wherein the first resistance value is smaller in terms of amount than the second resistance value.

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