METHOD FOR MANUFACTURING A DISPLAY DEVICE

Abstract

Method for manufacturing a display device (DSP), comprising: Preparing a substrate to be treated (SUB) in which a lower electrode (Leα), a rib (5) with an opening (APα) overlapping the lower electrode (Leα), and a partition (6) with a lower part (61) arranged on the rib (5) and an upper part (62) arranged on the lower part (61) and projecting from the side surfaces of the lower part (61) are formed over the substrate (10), Forming a first organic layer (OR11) covering the lower electrode (Leα) and a second organic layer (OR12) spaced apart from the first organic layer (OR11) and positioned on the upper part (62), Forming a first upper electrode (UE11) positioned on the first organic layer (OR11) and in contact with the lower part (61), and a second upper electrode (UE12) spaced apart from the first upper electrode (UE11) and positioned on the second organic layer (OR12), Forming a first transparent layer (TL11) positioned on the first upper electrode (UE11) and a second transparent layer (TL12) spaced apart from the first transparent layer (TL11) and positioned on the second upper electrode (UE12), Forming a first inorganic layer (IL11) positioned on the first transparent layer (TL11), and a second inorganic layer (IL12) spaced apart from the first inorganic layer (IL11) and positioned on the second transparent layer (TL12), Forming a sealing layer (SE10) positioned on top of the first inorganic layer (IL11) and the second inorganic layer (IL12) and covering the partition wall (6), Forming a resist (41) that covers the sealing layer (SE10) directly above the lower electrode (Leα) and covers part of the sealing layer (SE10) directly above the partition (6), Performing a dry etching using the resist (41) as a mask, removing the sealing layer (SE10) exposed by the resist (41), and Performing a wet set using the resist (41) as a mask by means of an acidic solution, and removing the second inorganic layer (IL12) exposed by the resist (41).

Description

AREA

[0001] The present invention relates to a method for manufacturing a display device. BACKGROUND

[0002] In recent years, display devices using an organic light-emitting diode (OLED) as the display element have become widely used. This display element comprises a pixel circuit including a thin-film transistor, a bottom electrode connected to the pixel circuit, an organic layer covering the bottom electrode, and a top electrode covering the organic layer. In addition to a light-emitting layer, the organic layer includes functional layers such as a hole transport layer and an electron transport layer.

[0003] Such display elements are easily degraded by moisture. Therefore, a technique for reliably sealing display elements is required.

[0004] Publication US 2020 / 0328378A1 describes an organic light-emitting display device comprising spaced-apart pixel electrodes on a substrate, an intermediate insulating layer with an auxiliary electrode, and subsequent, separately separated light-emitting intermediate layers, counter electrodes, and passivation layers.

[0005] US Patent 2020 / 0144544A1 describes an organic light-emitting display device comprising pixel electrodes, a pixel definition layer, intermediate layers, island-shaped counter electrodes, and protective layers, wherein a connecting layer above the protective layers electrically connects the counter electrodes. US Patent 2020 / 0212143A1 describes an organic light-emitting display device comprising a substrate, a pixel electrode, a pixel definition film, an intermediate layer, a counter electrode, and a passivation layer having a cover section and a projection extending away from the substrate, and covered by an encapsulation element. BRIEF EXPLANATION OF THE DRAWINGS Fig. Figure 1 shows a training example for a DSP display device. Fig. Figure 2 shows an example of the layout of the subpixels SP1, SP2, SP3. Fig. Figure 3 shows a schematic sectional view of the DSP display device along line III-III in Fig. 2. Fig. Figure 4 shows a training example for a display element 20. Fig. Figure 5 is a flowchart illustrating an example of a method for manufacturing the DSP display device. Fig. Figure 6 is a view illustrating the steps for preparing a substrate to be treated. Fig. Figure 7 is a view illustrating the steps for forming a first thin layer. Fig. Figure 8 is a view illustrating the steps to form a resist. Fig. Figure 9 is a view illustrating a first etching (dry etching) of the first thin layer. Fig. Figure 10 is a view illustrating a second etching (wet etching) of the first thin layer. Fig. Figure 11 is a view illustrating a third etching of the first thin layer. Fig. Figure 12 is a view illustrating the steps for removing the resist. Fig. Figure 13 is a view showing the results of Experiment 1. Fig. Figure 14 is a view showing the results of Experiment 2. DETAILED EXPLANATION

[0006] According to one embodiment, a method for manufacturing a display device comprises: Preparing a substrate to be treated, in which a lower electrode, a rib with an opening that overlaps the lower electrode, and a partition with a lower part arranged on the rib and an upper part arranged on the lower part and projecting from the side surfaces of the lower part are formed over the substrate. Forming a first organic layer covering the lower electrode and a second organic layer spaced apart from the first organic layer and positioned on the upper part, Forming a first upper electrode positioned on the first organic layer and in contact with the lower part, and a second upper electrode spaced apart from the first upper electrode and positioned on the second organic layer, Forming a first transparent layer positioned on the first upper electrode and a second transparent layer spaced apart from the first transparent layer and positioned on the second upper electrode, Forming a first inorganic layer positioned on top of the first transparent layer, and a second inorganic layer spaced apart from the first inorganic layer and positioned on top of the second transparent layer, Forming a sealing layer positioned on top of the first inorganic layer and the second inorganic layer, covering the partition wall, Forming a resist that covers the sealing layer directly above the lower electrode and covers part of the sealing layer directly above the partition wall, Performing a dry etching process using the resist as a mask, removing the sealing layer exposed by the resist, and Performing a wet set using the resist as a mask with an acidic solution, and removing the second inorganic layer exposed by the resist.

[0007] One embodiment will now be explained with reference to the drawings.

[0008] To further clarify the explanation, the drawings may also schematically show the width, thickness, shape, etc., of the individual parts in comparison to their actual form; however, this is merely an example. In the present description and the respective drawings, the components that perform the same or similar functions as those shown in the aforementioned drawings are marked with the same reference symbols, and overlapping detailed explanations may be omitted where necessary.

[0009] For ease of understanding, the drawings indicate mutually orthogonal X, Y, and Z axes where necessary. The direction along the X-axis is referred to as the first direction, the direction along the Y-axis as the second direction, and the direction along the Z-axis as the third direction. Viewing the components in the XY plane, defined by the first direction X and the second direction Y, is called a top view.

[0010] The display device of this embodiment is an organic electroluminescent display device equipped with an organic light-emitting diode (OLED) as the display element and can be installed in a television, a personal computer, on-board equipment, a tablet terminal, a smartphone, a mobile phone terminal, etc.

[0011] Fig. Figure 1 shows a training example for a DSP display device.

[0012] The display device DSP has a display area DA, on which images are displayed, and a border area SA around the display area DA, on an insulating substrate 10. The substrate 10 can be glass or a flexible resin film.

[0013] In the present embodiment, the substrate 10 has a rectangular shape in plan view. However, the shape of the substrate 10 in plan view is not limited to a rectangle, but can also take on other shapes, such as a square, circle, or oval.

[0014] The display area DA contains several pixels PX arranged in a matrix along the X and Y directions. Each pixel PX comprises several subpixels SP. For example, pixel PX might include a red subpixel SP1, a green subpixel SP2, and a blue subpixel SP3. Pixel PX can also include subpixels SP in other colors, such as white, or alternatively, subpixels SP1, SP2, and SP3.

[0015] The subpixel SP is equipped with a pixel circuit 1 and a display element 20, which is controlled by the pixel circuit 1. The pixel circuit 1 is equipped with a pixel switch 2, a driver transistor 3, and a capacitor 4. The pixel switch 2 and the driver transistor 3 are switching elements, which consist, for example, of thin-film transistors.

[0016] The gate electrode of pixel switch 2 is connected to a scanning line GL. One of the source and drain electrodes of pixel switch 2 is connected to a signal line SL, and the other is connected to the gate electrode of driver transistor 3 and capacitor 4. At driver transistor 3, one of the source and drain electrodes is connected to the power supply line PL and capacitor 4, and the other is connected to the anode of indicator element 20.

[0017] The design of pixel circuit 1 is not limited to the example shown in the drawings. Pixel circuit 1 can, for example, be equipped with more thin-film transistors and capacitors.

[0018] The display element 20 is an organic light-emitting diode (OLED) and can be referred to as an organic EL. For example, subpixel SP1 is equipped with a display element 20 that emits light in the red wavelength range, subpixel SP2 is equipped with a display element 20 that emits light in the green wavelength range, and subpixel SP3 is equipped with a display element 20 that emits light in the blue wavelength range.

[0019] Fig. Figure 2 shows an example of the layout of the subpixels SP1, SP2, SP3.

[0020] In the example of Fig. Subpixels SP1 and SP2 are aligned in the second direction Y. Furthermore, subpixels SP1 and SP2 are each aligned with subpixel SP3 in the first direction X.

[0021] If the subpixels SP1, SP2, and SP3 are arranged in such a layout, a row is formed in the display area DA in which the subpixels SP1 and SP2 are arranged alternately in the second direction Y, and a row is formed in which several subpixels SP3 are repeatedly arranged in the second direction Y. These rows are arranged alternately in the first direction X.

[0022] The layout of subpixels SP1, SP2, SP3 is not based on the example of Fig. 2 limited. As another example, the subpixels SP1, SP2, SP3 in each pixel PX can be arranged sequentially in the first direction X.

[0023] In the display area DA, a rib 5 and a partition 6 are arranged. Rib 5 has openings AP1, AP2, AP3 in the subpixels SP1, SP2, SP3. In the example of Fig. 2. The opening AP2 is larger than the opening AP1 and the opening AP3 is larger than the opening AP2.

[0024] In plan view, the partition 6 overlaps the rib 5. The partition 6 has several first partitions 6x extending in the first direction X and several second partitions 6y extending in the second direction Y. The multiple first partitions 6x are arranged between openings AP1 and AP2 adjacent in the second direction Y and between two openings AP3 adjacent in the second direction Y. The second partition 6y is arranged between openings AP1 and AP3 adjacent in the first direction X and between openings AP2 and AP3 adjacent in the first direction X.

[0025] In the example of Fig. The first partition 6x and the second partition 6y are connected. This results in partition 6 as a whole forming a grid that surrounds the openings AP1, AP2, and AP3. It can also be said that partition 6 has openings in subpixels SP1, SP2, and SP3, similar to rib 5.

[0026] Subpixel SP1 is provided with a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, each overlapping the aperture AP1. Subpixel SP2 is provided with a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, each overlapping the aperture AP2. Subpixel SP3 is provided with a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, each overlapping the aperture AP3.

[0027] In the example of Fig. Figure 2 shows the outer shapes of the lower electrodes LE1, LE2, LE3 with dotted lines, and the outer shapes of the organic layers OR1, OR2, OR3 and the upper electrodes UE1, UE2, UE3 with dashed lines. The respective circumferences of the lower electrodes LE1, LE2, LE3 overlap rib 5. The outer shape of the upper electrode UE1 substantially corresponds to the outer shape of the organic layer OR1, and the respective circumferences of the upper electrode UE1 and the organic layer OR1 overlap partition 6. The outer shape of the upper electrode UE2 substantially corresponds to the outer shape of the organic layer OR2, and the respective circumferences of the upper electrode UE2 and the organic layer OR2 overlap partition 6.The outer shape of the upper electrode UE3 essentially matches the outer shape of the organic layer OR3, and the respective circumferences of the upper electrode UE3 and the organic layer OR3 overlap the partition 6.

[0028] The lower electrode LE1, the upper electrode UE1, and the organic layer OR1 form the display element 20 of subpixel SP1. The lower electrode LE2, the upper electrode UE2, and the organic layer OR2 form the display element 20 of subpixel SP2. The lower electrode LE3, the upper electrode UE3, and the organic layer OR3 form the display element 20 of subpixel SP3. The lower electrodes LE1, LE2, and LE3 correspond, for example, to the anodes of display element 20. The upper electrodes UE1, UE2, and UE3 correspond to the cathodes or common electrodes of display element 20.

[0029] The lower electrode LE1 is connected via a contact hole CH1 to the pixel circuit 1 of the subpixel SP1 (see Fig. 1) connected. The lower electrode LE2 is connected to pixel circuit 1 of subpixel SP2 via a contact hole CH2. The lower electrode LE3 is connected to pixel circuit 1 of subpixel SP3 via a contact hole CH3.

[0030] Fig. Figure 3 shows a schematic sectional view of the DSP display device along line III-III in Fig. 2.

[0031] A circuit layer 11 is arranged on the substrate 10 described above. The circuit layer 11 comprises various circuits and lines, such as those in Fig. Figure 1 shows pixel circuit 1, the scanning line GL, the signal line SL, and the power supply line PL. The circuit layer 11 is covered with an insulating layer 12. The insulating layer 12 acts as a planarizing film, flattening the irregularities caused by the circuit layer 11.

[0032] The lower electrodes LE1, LE2, LE3 are arranged on the insulating layer (organic insulating layer) 12. The rib (inorganic insulating layer) 5 is arranged on the insulating layer 12 and the lower electrodes LE1, LE2, LE3. The ends of the lower electrodes LE1, LE2, LE3 are covered by the rib 5.

[0033] The partition 6 comprises a lower part (rod) 61, which is arranged on the rib 5, and an upper part (screen) 62, which covers the upper surface of the lower part 61. The upper part 62 is wider than the lower part 61. As a result, the two ends of the upper part 62 project beyond the side surfaces of the lower part 61. Fig. 3 beyond. This form of partition wall 6 can also be described as an overhang form.

[0034] The in Fig. The organic layer OR1 shown in Figure 2 comprises a first part OR1a and a second part OR1b, which are spaced apart from each other, as shown in Figure 2. Fig. Figure 3 shows the first part OR1a, which is in contact with the lower electrode LE1 through the opening AP1, covers the lower electrode LE1 and overlaps part of the rib 5. The second part OR1b is positioned on the upper part 62.

[0035] The in Fig. The upper electrode UE1 shown in section 2 further comprises a first part UE1a and a second part UE1b, which are spaced apart from each other as shown in Fig. Figure 3 shows the first part UE1a opposite the lower electrode LE1 and positioned on the first part OR1a. Furthermore, the first part UE1a is in contact with a side surface of the lower part 61. The second part UE1b is positioned above the partition 6 and on the second part OR1b.

[0036] The in Fig. The organic layer OR2 shown comprises a first part OR2a and a second part OR2b, which are spaced apart from each other, as shown in Fig. Figure 3 shows the first part OR2a in contact with the lower electrode LE2 through the opening AP2, covering the lower electrode LE2 and overlapping part of the rib 5. The second part OR2b is positioned on the upper part 62.

[0037] The in Fig. The upper electrode UE2 shown further comprises a first part UE2a and a second part UE2b, which are spaced apart from each other as shown in . Fig. Figure 3 shows the first part UE2a opposite the lower electrode LE2 and positioned on the first part OR2a. Furthermore, the first part UE2a is in contact with a side surface of the lower part 61. The second part UE2b is positioned above the partition 6 and on the second part OR2b.

[0038] The in Fig. The organic layer OR3 shown comprises a first part OR3a and a second part OR3b, which are spaced apart from each other, as shown in Fig. Figure 3 shows the first part OR3a in contact with the lower electrode LE3 through the opening AP3, covering the lower electrode LE3 and overlapping part of the rib 5. The second part OR3b is positioned on the upper part 62.

[0039] The in Fig. The upper electrode UE3 shown in section 2 further comprises a first part UE3a and a second part UE3b, which are spaced apart from each other as shown in Fig. Figure 3 shows the first part UE3a opposite the lower electrode LE3 and positioned on the first part OR3a. Furthermore, the first part UE3a is in contact with a side surface of the lower part 61. The second part UE3b is positioned above the partition 6 and on the second part OR3b.

[0040] In the Fig. The 3 illustrated example includes the subpixels SP1, SP2, SP3 cover layers (optical adjustment layers) CP1, CP2, CP3 for adjusting the optical properties of the light emitted by the light-emitting layers of the organic layers OR1, OR2, OR3.

[0041] The cover layer CP1 comprises a first part CP1a and a second part CP1b, which are spaced apart from each other. The first part CP1a is positioned at the opening AP1 and on top of the first part UE1a. The second part CP1b is positioned above the partition wall 6 and on top of the second part UE1b.

[0042] The cover layer CP2 comprises a first part CP2a and a second part CP2b, which are spaced apart from each other. The first part CP2a is positioned at the opening AP2 and on top of the first part UE2a. The second part CP2b is positioned above the partition wall 6 and on top of the second part UE2b.

[0043] The cover layer CP3 comprises a first part CP3a and a second part CP3b, which are spaced apart from each other. The first part CP3a is positioned at the opening AP3 and on top of the first part UE3a. The second part CP3b is positioned above the partition wall 6 and on top of the second part UE3b.

[0044] In subpixels SP1, SP2, and SP3, sealing layers SE1, SE2, and SE3 are arranged, respectively. Sealing layer SE1 completely covers every component of subpixel SP1, including the first part CP1a, partition 6, and the second part CP1b. Sealing layer SE2 completely covers every component of subpixel SP2, including the first part CP2a, partition 6, and the second part CP2b. Sealing layer SE3 completely covers every component of subpixel SP3, including the first part CP3a, partition 6, and the second part CP3b.

[0045] In the example of Fig. The second part OR1b, the second part UE1b, and the second part CP1b on partition wall 6 and the sealing layer SE1, as well as the second part OR3b, the second part UE3b, and the second part CP3b on partition wall 6 and the sealing layer SE3, are spaced apart from each other between subpixels SP1 and SP3. Furthermore, the second part OR2b, the second part UE2b, and the second part CP2b on partition wall 6 and the sealing layer SE2, as well as the second part OR3b, the second part UE3b, and the second part CP3b on partition wall 6 and the sealing layer SE3, are spaced apart from each other between subpixels SP2 and SP3.

[0046] The sealing layers SE1, SE2, SE3 are covered by a resin layer 13. The resin layer 13 is covered by the sealing layer 14. Furthermore, the sealing layer 14 is covered by a resin layer 15.

[0047] The insulating layer 12 is made of an organic material. The rib 5 and the sealing layers 14, SE1, SE2, SE3 are made of inorganic materials, such as silicon nitride (SiNx). The thickness of the rib 5, which is made of an inorganic material, is sufficiently small compared to the thickness of the partition 6 and the insulating layer 12. In one example, the thickness of the rib 5 is equal to or greater than 200 nm and equal to or less than 400 nm.

[0048] The lower part 61 of the partition 6 is made of an electrically conductive material. Both the lower part 61 and the upper part 62 of the partition 6 can be electrically conductive.

[0049] The lower electrodes LE1, LE2, LE3 can be made of a transparent, electrically conductive material such as ITO or have a laminated structure of a metallic material such as silver (Ag) and a transparent, electrically conductive material. The upper electrodes UE1, UE2, UE3 are made of a metallic material such as a magnesium-silver alloy (MgAg). The upper electrodes UE1, UE2, UE3 can also be made of a transparent, electrically conductive material such as ITO.

[0050] If the potential of the lower electrodes LE1, LE2, LE3 is relatively higher than that of the upper electrodes UE1, UE2, UE3, then the lower electrodes LE1, LE2, LE3 correspond to the anodes and the upper electrodes UE1, UE2, UE3 to the cathodes.

[0051] The organic layers OR1, OR2, and OR3 comprise several functional layers. The first part, OR1a, and the second part, OR1b, of organic layer OR1 comprise a light-emitting layer, EM1, which is composed of the same material. The first part, OR2a, and the second part, OR2b, of organic layer OR2 comprise a light-emitting layer, EM2, which is composed of the same material. The first part, OR3a, and the second part, OR3b, of organic layer OR3 comprise a light-emitting layer, EM3, which is composed of the same material. The light-emitting layers EM1, EM2, and EM3 are composed of materials that emit light in different wavelength ranges.

[0052] The cover layers CP1, CP2, and CP3 are formed, for example, by a multilayered body composed of several transparent thin films. This multilayered body can contain several thin films of inorganic materials and thin films of organic materials. These thin films also have different refractive indices. The materials of the thin films that make up the multilayered body differ from the materials of the upper electrodes UE1, UE2, and UE3, as well as from the materials of the sealing layers SE1, SE2, and SE3. The cover layers CP1, CP2, and CP3 can be omitted.

[0053] A common voltage is applied to the partition 6. This common voltage is applied to the first parts UE1a, UE2a, UE3a of each upper electrode, which are in contact with the side surfaces of the lower part 61. A pixel voltage is applied to the lower electrodes LE1, LE2, LE3 via the pixel circuits 1, each of which has the subpixels SP1, SP2, SP3.

[0054] When a potential difference is created between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer EM1 of the first part OR1a of the first organic layer OR1 emits light in the red wavelength range. When a potential difference is created between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer EM2 of the first part OR2a of the first organic layer OR2 emits light in the green wavelength range. When a potential difference is created between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer EM3 of the first part OR3a of the first organic layer OR3 emits light in the blue wavelength range.

[0055] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 can emit light of the same color (e.g., white). In this case, the DSP display device can be equipped with a color filter that converts the light emitted by the light-emitting layers into light of a color corresponding to subpixels SP1, SP2, and SP3. The DSP display device can further be equipped with a layer comprising quantum dots that are excited by the light emitted by the light-emitting layer to generate light of a color corresponding to subpixels SP1, SP2, and SP3.

[0056] Fig. Figure 4 shows a training example for a display element 20.

[0057] The in Fig. The lower electrode LE shown corresponds to the lower electrodes LE1, LE2, LE3 of the Fig. 3. The in Fig. The 4 depicted organic layer OR corresponds to the organic layers OR1, OR2, OR3 of Fig. 3. The in Fig. The upper electrode UE shown in section 4 corresponds to the upper electrodes UE1, UE2, UE3 of the diagram. Fig. 3.

[0058] The organic layer OR comprises a carrier-setting layer CA1, a light-emitting layer EM, and a carrier-setting layer CA2. Carrier-setting layer CA1 is positioned between the lower electrode LE and the light-emitting layer EM, and carrier-setting layer CA2 is positioned between the light-emitting layer EM and the upper electrode UE. Carrier-setting layers CA1 and CA2 contain several functional layers. The following discussion assumes that the lower electrode LE is the anode and the upper electrode UE is the cathode.

[0059] The support layer CA1 comprises a hole injection layer F11, a hole transport layer F12, an electron barrier layer F13, etc., as functional layers. The hole injection layer F11 is located on the lower electrode LE, the hole transport layer F12 is located on the hole injection layer F11, the electron barrier layer F13 is located on the hole transport layer F12, and the light-emitting layer EM is located on the electron barrier layer F13.

[0060] The support layer CA2 comprises a hole barrier layer F21, an electron transport layer F22, an electron injection layer F23, etc., as functional layers. The hole barrier layer F21 is located on the light-emitting layer EM, the electron transport layer F22 is located on the hole barrier layer F21, the electron injection layer F23 is located on the electron transport layer F22, and the upper electrode UE is located on the electron injection layer F23.

[0061] The carrier setting layers CA1, CA2 can, if necessary, include additional functional layers, such as carrier generation layers, in addition to the functional layers mentioned above, or at least one of the functional layers mentioned above can be omitted.

[0062] The in Fig. 4. The top layer CP shown corresponds to each of the top layers CP1, CP2, CP3 in Fig. 3. The top layer CP comprises a transparent layer (first layer) TL and an inorganic layer (second layer 2) IL. The transparent layer TL is located on the upper electrode UE, and the inorganic layer IL is located on top of the transparent layer TL. The transparent layer TL is a thin film, for example, made of an organic material, and has a high refractive index, meaning its refractive index is greater than that of the upper electrode UE. The inorganic layer IL is a transparent thin film, for example, made of lithium fluoride (LiF), and has a low refractive index, meaning its refractive index is lower than that of the transparent layer TL.

[0063] In the Fig. In the example shown in Figure 4, the cover layer CP is a two-layer stack consisting of the transparent layer TL and the inorganic layer IL; however, it can also consist of three or more layers. In the cover layer CP, the inorganic layer IL is positioned on the top layer and is in contact with the layers shown in Figure 4. Fig. The 3 shown sealing layers SE1, SE2, SE3 are in contact.

[0064] Next, an example of a method for manufacturing the DSP display device will be explained.

[0065] Fig. Figure 5 is a flowchart illustrating an example of a method for manufacturing the DSP display device.

[0066] The manufacturing process shown here is broadly classified into a step for preparing a substrate SUB to be treated, which serves as the basis for the subpixels SPα, SPβ, and SPγ (step ST1), and a step for forming the subpixel SPα (step ST2). After step ST2, a step for forming the subpixel SPβ follows, similar to the steps for forming the subpixel SPα, and then a step for forming the subpixel SPγ follows. The subpixels SPα, SPβ, and SPγ are one of the aforementioned subpixels SP1, SP2, and SP3.

[0067] In step ST2, a first thin layer 31 with a light-emitting layer EMα is formed on the substrate SUB to be treated (step ST21). In the steps for forming the first thin layer 31, an organic layer OR10 is first formed on the substrate SUB to be treated (step ST211). Then, an upper electrode UE10 is formed on the organic layer OR10 (step ST212). Then, a transparent layer TL10, forming a cover layer, is formed on the upper electrode UE10 (step ST213). Then, an inorganic layer IL10, forming a cover layer, is formed on the transparent layer TL10 (step ST214). Finally, a sealing layer SE10 is formed on the inorganic layer IL10 (step ST215).

[0068] Then, a resist 41 structured in a specific shape is formed on the first thin layer 31 (step ST22).

[0069] Next, a portion of the first thin layer 31 is removed by etching using resist 41 as a mask (step ST23). During the removal of this portion of the first thin layer 31, the sealing layer SE10 exposed by resist 41 is removed first (step ST231). Then, the inorganic layer IL10 exposed by resist 41 and the sealing layer SE10 is removed (step ST232). Next, the transparent layer TL10 exposed by resist 41, the sealing layer SE10, and the inorganic layer IL10 is removed (step ST233). Finally, the top electrode UE10 exposed by resist 41, the sealing layer SE10, the inorganic layer IL10, and the transparent layer TL10 is removed (step ST234). Then the organic layer OR10, which is exposed by the resist 41, the sealing layer SE10, the inorganic layer IL10, the transparent layer TL10 and the upper electrode UE10, is removed (step ST235).

[0070] Next, the resist 41 is removed (step ST24). This creates the subpixel SPα. The subpixel SPα is equipped with the display element 21, which has the first thin layer 31 in a specific shape.

[0071] The steps for forming the subpixel SPβ are similar to steps ST21 to ST24; however, in step ST21, a second thin layer 32 with the light-emitting layer EMβ is formed instead of the first thin layer 31. The subpixel SPβ is formed by structuring the second thin layer 32. The subpixel SPβ is equipped with the display element 22, which is formed by the second thin layer 32 in a specific shape. The representation of the second thin layer 32, the light-emitting layer EMβ, and the display element 22 is omitted here.

[0072] The steps for forming the subpixel SPγ are similar to steps ST21 to ST24; however, in step ST21, a third thin layer 33 with the light-emitting layer EMγ is formed instead of the first thin layer 31. The subpixel SPγ is formed by structuring the third thin layer 33. The subpixel SPγ is equipped with the display element 23, which incorporates the third thin layer 33 in a predefined shape. The representation of the third thin layer 33, the light-emitting layer EMγ, and the display element 23 is omitted here.

[0073] The light-emitting layer EMα, the light-emitting layer EMβ and the light-emitting layer EMγ are formed by materials that emit light in different wavelength ranges.

[0074] The following section explains steps ST1 and ST2 in detail.

[0075] First, in step ST1, as in Fig. Figure 6 shows a substrate SUB to be treated, in which the rib 5 is formed with a lower electrode LEα of subpixel SPα, a lower electrode LEβ of subpixel SPβ, a lower electrode LEγ of subpixel SPγ and openings APα, APβ, APγ which overlap each of the lower electrodes LEα, LEβ, LEγ, and the partition 6 with the lower part 61, which is arranged on the rib 5, and the upper part 62, which is arranged on the lower part 61 and projects from the side surfaces of the lower part 61, is formed above the substrate 10. Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11 to Fig. Figure 12 shows the substrate 10 and a circuit layer 11 below the insulating layer 12 is omitted.

[0076] Next, in step ST21, a first thin layer 31 is formed over the subpixel SPα, the subpixel SPβ and the subpixel SPγ, as shown in Fig. Figure 7 shows the steps for forming the first thin layer 31. These steps include forming the organic layer OR10, including the light-emitting layer EMα, on the substrate SUB to be treated (ST211); forming the upper electrode UE10 on the organic layer OR10 (ST212); forming the transparent layer TL10 on the upper electrode UE10 (ST213); forming the inorganic layer IL10 on the transparent layer TL10 (ST214); and forming the sealing layer SE10 on the inorganic layer IL10 (ST215). That is, in the example shown, the first thin layer 31 comprises the organic layer OR10, the upper electrode UE10, the transparent layer TL10, the inorganic layer IL10, and the sealing layer SE10.

[0077] The organic layer OR10 comprises a first organic layer OR11, a second organic layer OR12, a third organic layer OR13, a fourth organic layer OR14, and a fifth organic layer OR15. The first organic layer OR11, the second organic layer OR12, the third organic layer OR13, the fourth organic layer OR14, and the fifth organic layer OR15 each comprise a light-emitting layer EMα formed from the same material.

[0078] The first organic layer OR11 is formed such that it covers the lower electrode LEα. The second organic layer OR12 is spaced apart from the first organic layer OR11 and is positioned on the upper part 62 of the partition 6 between the lower electrode LEα and the lower electrode LEβ. The third organic layer OR13 is spaced apart from the second organic layer OR12 and is formed such that it covers the lower electrode LEβ. The fourth organic layer OR14 is spaced apart from the third organic layer OR13 and is positioned on the upper part 62 of the partition 6 between the lower electrode LEβ and the lower electrode LEγ. The fifth organic layer OR15 is spaced apart from the fourth organic layer OR14 and is formed such that it covers the lower electrode LEγ.

[0079] The upper electrode UE10 comprises a first upper electrode UE11, a second upper electrode UE12, a third upper electrode UE13, a fourth upper electrode UE14 and a fifth upper electrode UE15.

[0080] The first upper electrode UE11 is positioned on the first organic layer OR11 and is in contact with the lower part 61 of the partition 6 between the lower electrode LEα and the lower electrode LEβ. The second upper electrode UE12 is spaced apart from the first upper electrode UE11 and positioned on the second organic layer OR12 between the lower electrode LEα and the lower electrode LEβ. The third upper electrode UE13 is spaced apart from the second upper electrode UE12 and positioned on the third organic layer OR13. In the illustrated example, the third upper electrode UE13 is in contact with the lower part 61 of the partition 6 between the lower electrode LEα and the lower electrode LEβ and with the lower part 61 of the partition 6 between the lower electrode LEβ and the lower electrode LEγ, but it can also be in contact with either of the lower parts 61.The fourth upper electrode UE14 is spaced apart from the third upper electrode UE13 and is positioned on the fourth organic layer OR14 between the lower electrode LEβ and the lower electrode LEγ. The fifth upper electrode UE15 is spaced apart from the fourth upper electrode UE14, is positioned on the fifth organic layer OR15, and is in contact with the lower part 61 of the partition 6 between the lower electrode LEβ and the lower electrode LEγ.

[0081] The transparent layer TL10 comprises a first transparent layer TL11, a second transparent layer TL12, a third transparent layer TL13, a fourth transparent layer TL14 and a fifth transparent layer TL15.

[0082] The first transparent layer TL11 is positioned on the first upper electrode UE11. The second transparent layer TL12 is spaced apart from the first transparent layer TL11 and is positioned on the second upper electrode UE12. The third transparent layer TL13 is spaced apart from the second transparent layer TL12 and is positioned on the third upper electrode UE13. The fourth transparent layer TL14 is spaced apart from the third transparent layer TL13 and is positioned on the fourth upper electrode UE14. The fifth transparent layer TL15 is spaced apart from the fourth transparent layer TL14 and is positioned on the fifth upper electrode UE15.

[0083] The inorganic layer IL10 comprises a first inorganic layer IL11, a second inorganic layer IL12, a third inorganic layer IL13, a fourth inorganic layer IL14, and a fifth inorganic layer IL15. The first inorganic layer IL11, the second inorganic layer IL12, the third inorganic layer IL13, the fourth inorganic layer IL14, and the fifth inorganic layer IL15 are single-layer thin films composed of lithium fluoride. The thickness of the first inorganic layer IL11, the second inorganic layer IL12, the third inorganic layer IL13, the fourth inorganic layer IL14, and the fifth inorganic layer IL15 is between 20 nm and 200 nm.

[0084] The first inorganic layer IL11 is positioned on top of the first transparent layer TL11. The refractive index of the first inorganic layer IL11 is lower than the refractive index of the first transparent layer TL11.

[0085] The second inorganic layer IL12 is spaced apart from the first inorganic layer IL11 and is positioned on top of the second transparent layer TL12. The refractive index of the second inorganic layer IL12 is lower than the refractive index of the second transparent layer TL12.

[0086] The third inorganic layer IL13 is spaced apart from the second inorganic layer IL12 and is positioned on top of the third transparent layer TL13. The refractive index of the third inorganic layer IL13 is lower than the refractive index of the third transparent layer TL13.

[0087] The fourth inorganic layer IL14 is spaced apart from the third inorganic layer IL13 and is positioned on top of the fourth transparent layer TL14. The refractive index of the fourth inorganic layer IL14 is lower than the refractive index of the fourth transparent layer TL14.

[0088] The fifth inorganic layer IL15 is spaced apart from the fourth inorganic layer IL14 and is positioned on top of the fifth transparent layer TL15. The refractive index of the fifth inorganic layer IL15 is lower than the refractive index of the fifth transparent layer TL15.

[0089] The sealing layer SE10 is formed such that it covers the first inorganic layer IL11, the second inorganic layer IL12, the third inorganic layer IL13, the fourth inorganic layer IL14, the fifth inorganic layer IL15, and the partition 6. The sealing layer SE10 consists of silicon nitride, which is an inorganic material. The sealing layer SE10 covering the partition 6 is in contact with the lower region of the upper part 62 and the side surface of the lower part 61.

[0090] Then, in step ST22, a resist is applied to the SE10 sealing layer and this resist is structured as shown in Fig. Figure 8 illustrates this. The resist 41 formed by this structuring covers subpixel SPα. That is, the resist 41 is located directly above the lower electrode LEα, the first organic layer OR11, the first upper electrode UE11, the first transparent layer TL11, and the first inorganic layer IL11. The resist 41 further extends from subpixel SPα upwards of the partition 6. Directly above the partition 6 between subpixel SPα and subpixel SPβ, the resist 41 is located on the side of subpixel SPα (left side of the drawing) and exposes the sealing layer SE10 on the side of subpixel SPβ (right side of the drawing). In the illustrated example, the resist 41 exposes the sealing layer SE10 on subpixels SPβ and SPγ.

[0091] Then, in step ST231, as in Fig. Figure 9 shows a dry etching as the first etching of the first thin layer 31 using the resist 41 as a mask, and the sealing layer SE10 exposed by the resist 41 is removed.

[0092] In this dry etching process, the SE10 sealing layer of subpixels SPβ and SPγ is removed, exposing the third inorganic layer IL13 of subpixel SPβ and the fifth inorganic layer IL15 of subpixel SPγ. The SE10 sealing layer remains in subpixel SPα.

[0093] The lower part 61, upper part 62, and the second inorganic layer IL12 between subpixel SPα and subpixel SPβ are each covered by the sealing layer SE10 on the SPα side, while on the SPβ side they are exposed by the sealing layer SE10. The lower part 61, the upper part 62, and the fourth inorganic layer IL14 between subpixel SPβ and subpixel SPγ are exposed by the sealing layer SE10. The inorganic layer IL10 acts as an etch stop layer during the removal of the sealing layer SE10 by dry etching.

[0094] In this way, the sealing layer SE10 of the first thin layer 31 is formed by dry etching in such a way that it has a predetermined shape.

[0095] Then, in step ST232, as in Fig. Figure 10 shows a wet etching process as a second etching of the first thin layer 31 using resist 41 as a mask with an acidic solution, and the inorganic layer IL10 exposed by resist 41 is removed. The acidic solution is, for example, a solution of at least one organic acid from formic acid, acetic acid, propionic acid, and butanoic acid. Alternatively, the acidic solution is a solution of at least one inorganic acid from nitric acid and hydrochloric acid. In one example, acetic acid is used as the acidic solution. The acetic acid concentration is 0.01% or more, preferably, for example, 0.1% or more and 15% or less. The pH of the acidic solution is, for example, 2.5 or more and 3.6 or less. The basis for these numerical ranges is based on the results of Experiments 1 and 2, which are explained later.

[0096] Wet etching removes part of the second inorganic layer IL12 (on the side of subpixel SPβ), as well as the entirety of the third inorganic layer IL13, the entirety of the fourth inorganic layer IL14, and the entirety of the fifth inorganic layer IL15. Therefore, part of the second inorganic layer TL12 (on the side of subpixel SPβ) is exposed, along with the third inorganic layer TL13, the fourth inorganic layer TL14, and the fifth inorganic layer TL15. The first transparent layer TL11 remains in subpixel SPα.

[0097] Then, as in Fig. Figure 11 shows a third etching of the first thin layer 31 using the resist 41 as a mask. In this third etching, in step ST233, a portion of the second transparent layer TL12, the entire third transparent layer TL13, the entire fourth transparent layer TL14, and the entire fifth transparent layer TL15, exposed by the resist 41, are removed. Then, in step ST234, a portion of the second upper electrode UE12, the entire third upper electrode UE13, the entire fourth upper electrode UE14, and the entire fifth upper electrode UE15, exposed by the resist 41, are removed. Finally, in step ST235, a portion of the second organic layer OR12, the entire third organic layer OR13, the entire fourth organic layer OR14, and the entire fifth organic layer OR15, exposed by the resist 41, are removed.

[0098] This exposes the lower electrode LEβ in subpixel SPβ and the lower electrode LEγ in subpixel SPγ.

[0099] With respect to the partition 6 between subpixel SPα and subpixel SPβ, the second organic layer OR12, the second upper electrode UE12, the second transparent layer TL12, the second inorganic layer IL12, and the sealing layer SE10 remain directly above the upper part 62 on the side of subpixel SPα, while on the side of subpixel SPβ, the second organic layer OR12, the second upper electrode UE12, the second transparent layer TL12, the second inorganic layer IL12, and the sealing layer SE10 are removed. Therefore, the upper part 62 is exposed on the side of subpixel SPβ.

[0100] Rib 5 between subpixel SPα and subpixel SPβ is free on the side of subpixel SPβ.

[0101] With regard to the partition 6 between the subpixel SPβ and the subpixel SPγ, the lower part 61 and the upper part 62 are free.

[0102] Regarding rib 5 between subpixel SPβ and subpixel SPγ, the ribs on the side of subpixel SPβ and subpixel SPγ are each free.

[0103] Then, as in Fig. Figure 12 shows that in step ST24, resist 41 is removed. This exposes the sealing layer SE10 of subpixel SPα. Through these steps ST21 to ST24, the display element 21 is formed in subpixel SPα. The display element 21 is formed from the lower electrode LEα, the first organic layer OR11, the first upper electrode UE11, and the first cover layer CP11 (first transparent layer TL11 and first inorganic layer IL11). The display element 21 is covered by the sealing layer SE10.

[0104] The subpixel SPα in the above example is one of the subpixels in Fig. The two subpixels SP1, SP2, and SP3 shown. If, for example, subpixel SPα corresponds to subpixel SP1, then the lower electrode LEα corresponds to the lower electrode LE1, the first organic layer OR11 to the first part OR1a, the second organic layer OR12 to the second part OR1b, the light-emitting layer EMα to the first light-emitting layer EM1, the first upper electrode UE11 to the first part UE1a, the second upper electrode UE12 to the second part UE1b, the first cover layer CP11 (the first transparent layer TL11 and the first inorganic layer IL11) to the first part CP1a, the second cover layer CP12 (the second transparent layer TL12 and the second inorganic layer IL12) to the second part CP1b, and the sealing layer SE10 to the sealing layer SE1.

[0105] According to the present embodiment, a structuring technique can be established for the inorganic layer IL, which forms the cover layer CP. Acetic acid solution can be used as the acidic solution for removing the inorganic layer IL formed by lithium fluoride. Since the acidic solution has a uniform composition, concentration control is simple and environmental impact is low.

[0106] By safely removing the inorganic layer IL, which covers the subpixels SPβ and SPγ explained in the example above, the transparent layer TL, the upper electrode UE, and the organic layer OR can be removed. Therefore, display elements in the desired shapes can be formed in the other subpixels SPβ and SPγ in the subsequent subpixel formation steps.

[0107] Furthermore, in each subpixel, the upper electrode UE and the lower part 61 of the partition 6 can be securely electrically connected. Consequently, reliability can be increased.

[0108] Next, the inventor prepared acetic acid solutions with different concentrations (weight percent concentration) and, using these acetic acid solutions, conducted Experiment 1 to test whether lithium fluoride could be dissolved. In Experiment 1, the substrate to be treated is first prepared, in which a lithium fluoride layer is formed after the organic layer OR10 and the upper electrode UE10, which are described in relation to Fig. The lithium fluoride layer was formed as explained in section 7. The thickness of the lithium fluoride layer is approximately 80 nm. The immersion time of the substrate to be treated in the acetic acid solution was 2 minutes. Afterwards, it was checked whether the lithium fluoride layer remained or not, and whether or not damage had occurred due to the dissolution of the partition 6 by the acetic acid solution.

[0109] Fig. Figure 13 is a view showing the results of Experiment 1.

[0110] When using an acetic acid solution with a concentration of 0.01% (pH 3.6), part of the lithium fluoride layer remained, and no damage to the partition 6 was detected.

[0111] When using an acetic acid solution with a concentration of 0.1% (pH 3.4), no lithium fluoride layer remained and no damage to the partition 6 was detected.

[0112] When using an acetic acid solution with a concentration of 0.5% (pH 3.0), no lithium fluoride layer remained, and no damage to the partition 6 was detected.

[0113] When using an acetic acid solution with a concentration of 1% (pH 2.8), no lithium fluoride layer remained and no damage to the partition 6 was detected.

[0114] When using an acetic acid solution with a concentration of 2% (pH 2.7), no lithium fluoride layer remained and no damage to the partition 6 was detected.

[0115] When using an acetic acid solution with a concentration of 99.8% (pH 2.5), no lithium fluoride layer remained, and no damage to partition 6 was detected.

[0116] The inventor repeated the same experiment several times with the same concentrations of acetic acid solution and confirmed that the lithium fluoride layer could be stably dissolved when the concentration of the acetic acid solution was 0.1%. It was also confirmed that no damage to partition 6 occurred at a concentration of 99.8% acetic acid solution, even when the immersion time was extended to 10 minutes.

[0117] The dissolution of the lithium fluoride layer progresses as the immersion time of the substrate in the acetic acid solution is extended. Therefore, the entire lithium fluoride layer can be removed even at an acetic acid concentration of 0.01% if the immersion time is extended to more than 2 minutes.

[0118] Based on the results of Experiment 1, it was confirmed that the acetic acid solution is suitable as an acidic solution for safely removing the lithium fluoride layer and suppressing damage to the partition 6. It was also confirmed that the lithium fluoride layer can be removed when the acetic acid concentration is in the range of 0.01% or more (in the pH range of 3.6 or less), preferably when the acetic acid concentration is in the range above 0.01% (in the pH range below 3.6). According to the results of Experiment 1, the acetic acid concentration capable of removing the lithium fluoride layer is in the range of 0.01% or more and 99.8% or less, preferably in the range above 0.01% to 99.8% or less. The pH of the acidic solution capable of removing the lithium fluoride layer is in the range of 2.5 or more and 3.6 or less, preferably in the range of 2.5 or more and below 3.6.

[0119] Next, the inventor prepared acetic acid solutions with different concentrations (weight percent concentration) and conducted Experiment 2 to test whether lithium fluoride could be dissolved by changing the immersion time using these acetic acid solutions. In Experiment 2, the substrate to be treated is first prepared, in which a lithium fluoride layer is formed after the organic layer OR10 and the upper electrode UE10, which are described in relation to Fig. As explained in section 7, the lithium fluoride layer is formed. The thickness of the lithium fluoride layer is approximately 100 nm. Afterwards, it was checked whether the lithium fluoride layer remained or not.

[0120] Fig. Figure 14 is a view showing the results of Experiment 2.

[0121] When using an acetic acid solution with a concentration of 0.1%, a small amount of the lithium fluoride layer remained after an immersion time of 5 minutes, while no lithium fluoride layer remained after an immersion time of 10 and 15 minutes.

[0122] When using an acetic acid solution with a concentration of 0.5%, a small amount of the lithium fluoride layer remained after an exposure time of 5 minutes, while no lithium fluoride layer remained after an immersion time of 10 and 15 minutes.

[0123] When using an acetic acid solution with a concentration of 1%, a small amount of the lithium fluoride layer remained after an exposure time of 5 minutes, while no lithium fluoride layer remained after an immersion time of 10 and 15 minutes.

[0124] When using an acetic acid solution with a concentration of 2%, a small amount of the lithium fluoride layer remained after an exposure time of 5 minutes, while no lithium fluoride layer remained after an immersion time of 10 and 15 minutes.

[0125] When using an acetic acid solution with a concentration of 5%, a small amount of the lithium fluoride layer remained after an exposure time of 5 minutes, while no lithium fluoride layer remained after an immersion time of 10 and 15 minutes.

[0126] When using an acetic acid solution with a concentration of 10%, a small amount of the lithium fluoride layer remained after an exposure time of 5 minutes, while no lithium fluoride layer remained after an immersion time of 10 and 15 minutes.

[0127] When using an acetic acid solution with a concentration of 15%, a small amount of the lithium fluoride layer remained after an exposure time of 5 minutes, while no lithium fluoride layer remained after an immersion time of 10 and 15 minutes.

[0128] Based on the results of Experiment 2, it was confirmed that there is almost no difference in the dissolution rate of the lithium fluoride layer between acetic acid concentrations of 0.1% or more and 15% or less. The optimal immersion time for the reliable removal of the lithium fluoride layer is determined by its thickness. For example, if the thickness of the lithium fluoride layer is 100 nm, as in Experiment 2 above, the immersion time should be longer than 5 minutes, preferably longer than 10 minutes.

[0129] As explained above, according to the present embodiment it is possible to provide a method for manufacturing a display device that increases reliability and increases manufacturing yield.

Claims

[1] Method for manufacturing a display device (DSP), comprising: Preparing a substrate to be treated (SUB) in which a lower electrode (Leα), a rib (5) with an opening (APα) overlapping the lower electrode (Leα), and a partition (6) with a lower part (61) arranged on the rib (5) and an upper part (62) arranged on the lower part (61) and projecting from the side surfaces of the lower part (61) are formed over the substrate (10), Forming a first organic layer (OR11) covering the lower electrode (Leα) and a second organic layer (OR12) spaced apart from the first organic layer (OR11) and positioned on the upper part (62), Forming a first upper electrode (UE11) positioned on the first organic layer (OR11) and in contact with the lower part (61), and a second upper electrode (UE12) spaced apart from the first upper electrode (UE11) and positioned on the second organic layer (OR12), Forming a first transparent layer (TL11) positioned on the first upper electrode (UE11) and a second transparent layer (TL12) spaced apart from the first transparent layer (TL11) and positioned on the second upper electrode (UE12), Forming a first inorganic layer (IL11) positioned on the first transparent layer (TL11), and a second inorganic layer (IL12) spaced apart from the first inorganic layer (IL11) and positioned on the second transparent layer (TL12), Forming a sealing layer (SE10) positioned on top of the first inorganic layer (IL11) and the second inorganic layer (IL12) and covering the partition wall (6), Forming a resist (41) that covers the sealing layer (SE10) directly above the lower electrode (Leα) and covers part of the sealing layer (SE10) directly above the partition (6), Performing a dry etching using the resist (41) as a mask, removing the sealing layer (SE10) exposed by the resist (41), and Performing a wet set using the resist (41) as a mask by means of an acidic solution, and removing the second inorganic layer (IL12) exposed by the resist (41). [2] Method for manufacturing a display device (DSP) according to claim 1, wherein the first inorganic layer (IL11) and the second inorganic layer (IL12) are formed from lithium fluoride (LiF). [3] Method for manufacturing a display device (DSP) according to claim 2, wherein the thickness of the first inorganic layer (IL11) and the second inorganic layer (IL12) is 20 nm or more and 200 nm or less. [4] Method for manufacturing a display device (DSP) according to claim 2, wherein the refractive indices of the first inorganic layer (IL11) and the second inorganic layer (IL12) are smaller than the refractive indices of the first transparent layer (TL11) and the second transparent layer (TL12). [5] Method for manufacturing a display device (DSP) according to claim 1, wherein the acidic solution is a solution of at least one organic acid consisting of formic acid, acetic acid, propionic acid and butanoic acid. [6] Method for manufacturing a display device (DSP) according to claim 5, where the acidic solution is an acetic acid solution, and the acetic acid concentration is 0.01% or higher. [7] Method for manufacturing a display device (DSP) according to claim 6, wherein the acetic acid concentration is 0.1% or more and 15% or less. [8] Method for manufacturing a display device (DSP) according to claim 5, wherein the pH value of the acidic solution is 2.5 or more and 3.6 or less. [9] Method for manufacturing a display device (DSP) according to claim 1, wherein the acidic solution is a solution of at least one inorganic acid consisting of nitric acid and hydrochloric acid. [10] Method for manufacturing a display device (DSP) according to claim 1, wherein the first organic layer (OR11) and the second organic layer (OR12) comprise a light-emitting layer (EM) formed from the same material. [11] Method for manufacturing a display device (DSP) according to claim 1, further comprising: removing the second transparent layer (TL12) exposed by the resist (41) using the resist (41) as a mask. [12] Method for manufacturing a display device (DSP) according to claim 11, further comprising: removing the second upper electrode (UE12) exposed by the resist (41) using the resist (41) as a mask. [13] Method for manufacturing a display device (DSP) according to claim 12, further comprising: removing the second organic layer (OR12) exposed by the resist (41) using the resist (41) as a mask.

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