DISPLAY DEVICE

Abstract

Display device (DSP) equipped with: a substrate (10), a lower electrode (LE1, LE2, LE3) which is arranged above the substrate (10), a rib (5) having an opening (AP1, AP2, AP3) that overlaps the lower electrode (LE1, LE2, LE3), a partition (6) comprising a lower part (61) arranged on the rib (5) and an upper part (62) arranged on the lower part (61) and projecting from the side surface of the lower part (61), an organic layer (OR1, OR2, OR3) arranged on the lower electrode (LE1, LE2, LE3) in the opening (AP1, AP2, AP3) and comprising a light-emitting layer (EM1, EM2, EM3), and an upper electrode (UE1, UE2, UE3) which is arranged on the organic layer (OR1, OR2, OR3) and is in contact with the lower part (61) of the partition (6), a top layer (CP1, CP2, CP3) which is arranged on the upper electrode (UE1, UE2, UE3), and a sealing layer (SE1, SE2, SE3) that covers the top layer (CP1, CP2, CP3) and is in contact with the lower part (61) of the partition wall (6), wherein the organic layer (OR1, OR2, OR3) has a first end that is positioned on the rib (5) and a second end that is positioned on the rib (5) and lies on the side opposite the first end, where the thickness of the upper electrode (UE1, UE2, UE3) immediately at the second end is greater than the thickness of the upper electrode (UE1, UE2, UE3) immediately at the first end, wherein the sealing layer (SE1, SE2, SE3) covers the upper electrode (UE1, UE2, UE3) between the second end and the partition (6), wherein each of the organic layer (OR1, OR2, OR3), the upper electrode (UE1, UE2, UE3) and the cover layer (CP1, CP2, CP3) has a first part which is positioned below the upper part (62) of the partition (6) and a second part which is positioned above the upper part (62) and spaced apart from the first part, wherein the sealing layer (SE1, SE2, SE3) is in contact with the first part and the second part of the cover layer (CP1, CP2, CP3), wherein the second part of each of the organic layer (OR1, OR2, OR3), the upper electrode (UE1, UE2, UE3) and the cover layer (CP1, CP2, CP3) are formed as a stack, the stack exposes part of the upper surface of the upper part (62) of the partition (6).

Description

AREA

[0001] The embodiment of the present invention relates to a display device BACKGROUND

[0002] In recent years, display devices using an organic light-emitting diode (OLED) as the display element have become widely used. This display element comprises a pixel circuit including a thin-film transistor, a bottom electrode connected to the pixel circuit, an organic layer covering the bottom electrode, and a top electrode covering the organic layer. In addition to a light-emitting layer, the organic layer includes functional layers such as a hole transport layer and an electron transport layer.

[0003] The manufacturing process for such display elements requires techniques that suppress the reduction in reliability.

[0004] WO 2022 / 039 890 A1 describes subpixel circuits and methods for forming subpixel circuits that can be used in an organic light-emitting diode (OLED) display. The adjacent metal-containing overhang structures, which define each subpixel of the display's subpixel circuit, enable the subpixel circuit to be formed by evaporation deposition and remain in place after the subpixel circuit is formed. The metal-containing overhang structures define deposition angles, i.e., they create a shadowing effect during evaporation deposition.

[0005] US Patent 2012 / 0217516A1 describes a lighting device in which the luminescent element is protected from damage by external physical influences. The lighting device comprises a luminescent element formed on a first substrate and containing a first electrode layer, a luminescent layer, and a second electrode layer; a structural body formed on the first substrate; a second substrate facing the first substrate; and an adhesive layer arranged between the first and second substrates. BRIEF EXPLANATION OF THE DRAWINGS

[0006] It shows: Fig. 1. A training example for a DSP display device; FIG. 2 an embodiment of the layout of the subpixels SP1, SP2, SP3; Fig. 3 a schematic sectional view of the DSP display device along line III-III in Fig. 2; Fig. 4. A training example for a display element 20; Fig. 5 a schematic sectional view of the display device DSP along line AB in Fig. 2; Fig. 6 a schematic sectional view of the DSP display device along the CD line in Fig. 2; Fig. 7 a view to illustrate a vapor separation device EV; Fig. 8 A view to illustrate the vapor deposition direction D during the formation of the upper electrode in each subpixel; Fig. 9 A view to illustrate the transport direction TD during the formation of the upper electrode; Fig. 10 a view to illustrate a different transport direction TD during the formation of the upper electrode; Fig. 11. A view illustrating how the upper electrode is formed; Fig. 12 a flowchart illustrating an example of a method for manufacturing a DSP display device; Fig. 13 a view to illustrate step ST1; Fig. 14 a view to illustrate step ST21; Fig. 15 a view to illustrate step ST22; Fig. 16 a view to illustrate step ST23; and Fig. 17 a view to illustrate step ST24. DETAILED EXPLANATION

[0007] The purpose of the embodiment is to provide a display device and a method for manufacturing a display device that can suppress the reduction in reliability.

[0008] According to one embodiment, the display device is provided with: a substrate, a lower electrode arranged above the substrate, a rib having an opening that overlaps the lower electrode, a partition having a lower part arranged on the rib and an upper part arranged on the lower part and projecting from the side surface of the lower part, an organic layer arranged on the lower electrode in the opening and comprising a light-emitting layer, and an upper electrode arranged on the organic layer and in contact with the lower part of the partition, wherein the organic layer has a first end positioned on the rib and a second end positioned on the rib and located on the side facing away from the first end.where the thickness of the upper electrode immediately at the second end is greater than the thickness of the upper electrode immediately at the first end.

[0009] In a method for manufacturing a display device that is not according to the invention, the following steps are performed: preparing a processing substrate on which, above the substrate, a first lower electrode, a second lower electrode, a rib with a first opening overlapping the first lower electrode and a second opening overlapping the second lower electrode, and a partition with a lower part arranged on the rib between the first opening and the second opening, and an upper part arranged on the lower part and projecting from the side surface of the lower part are formed; forming an organic layer comprising a first light-emitting layer on the first lower electrode in the opening; forming a first upper electrode on the first organic layer; forming a second organic layer comprising a second light-emitting layer that differs from the first light-emitting layer.on the second lower electrode in the second opening, and forming a second upper electrode on the second organic layer, wherein in a vapor deposition device in which the first upper electrode and the second upper electrode are formed, the direction of expansion of the vapor deposition source is inclined to the normal of the substrate, an electrically conductive material is vapor-deposited onto the processing substrate while the processing substrate is transported in one direction, wherein the vapor deposition direction during the formation of the first upper electrode differs from the vapor deposition direction during the formation of the second upper electrode.

[0010] According to one embodiment, a display device can be provided that can suppress the reduction in reliability.

[0011] One embodiment will now be explained with reference to the drawings.

[0012] The disclosure is merely an example, and corresponding modifications that would be readily obvious to a person skilled in the art while maintaining the main purpose of the invention are naturally included in the scope of the present invention. To further clarify the explanation, the drawings may also schematically show the width, thickness, shape, etc., of the individual parts in comparison to their actual form; however, this is merely an example and does not restrict the interpretation of the present invention. In this description and the respective drawings, the components that perform the same or similar functions as those shown in the aforementioned drawings are designated with the same reference numerals, and overlapping detailed explanations may be omitted as appropriate.

[0013] For ease of understanding, the drawings indicate mutually orthogonal X, Y, and Z axes as needed. The direction along the X-axis is referred to as the first direction, the direction along the Y-axis as the second direction, and the direction along the Z-axis as the third direction. Viewing the various elements parallel to the third direction, Z, is referred to as the top view.

[0014] The display device of this embodiment is an organic electroluminescent display device equipped with an organic light-emitting diode (OLED) as the display element and can be installed in a television, a personal computer, on-board equipment, a tablet terminal, a smartphone, a mobile phone terminal, etc.

[0015] Fig. 1. A training example for a DSP display device.

[0016] The display device DSP has a display area DA, on which images are displayed, and a border area SA around the display area DA, on an insulating substrate 10. The substrate 10 can be glass or a flexible resin film.

[0017] In the present embodiment, the substrate 10 has a rectangular shape in plan view. However, the shape of the substrate 10 in plan view is not limited to a rectangle, but can also take on other shapes, such as a square, circle, or oval.

[0018] The display area DA contains several pixels PX arranged in a matrix along the X and Y directions. Each pixel PX comprises several subpixels SP. For example, pixel PX might include red subpixel SP1, blue subpixel SP2, and green subpixel SP3. Pixel PX can also include subpixels SP in other colors, such as white, or alternatively, subpixels SP1, SP2, and SP3.

[0019] The subpixel SP is equipped with a pixel circuit 1 and a display element 20, which is controlled by the pixel circuit 1. The pixel circuit 1 is equipped with a pixel switch 2, a driver transistor 3, and a capacitor 4. The pixel switch 2 and the driver transistor 3 are switching elements, which consist, for example, of thin-film transistors.

[0020] The gate electrode of pixel switch 2 is connected to a scanning line GL. One of the source and drain electrodes of pixel switch 2 is connected to a signal line SL, and the other is connected to the gate electrode of driver transistor 3 and capacitor 4. At driver transistor 3, one of the source and drain electrodes is connected to the power supply line PL and capacitor 4, and the other is connected to the anode of indicator element 20.

[0021] The design of pixel circuit 1 is not limited to the example shown in the drawings. Pixel circuit 1 can, for example, be equipped with more thin-film transistors and capacitors.

[0022] The display element 20 is an organic light-emitting diode (OLED) and can be referred to as an organic EL. For example, subpixel SP1 is equipped with a display element 20 that emits light in the red wavelength range, subpixel SP2 with a display element 20 that emits light in the blue wavelength range, and subpixel SP3 with a display element 20 that emits light in the green wavelength range.

[0023] Fig. 2 an example of the layout of the subpixels SP1, SP2, SP3.

[0024] In the example of Fig. Subpixels SP1 and SP3 are aligned in the second direction Y. Furthermore, subpixels SP1 and SP3 are each aligned with subpixel SP2 in the first direction X.

[0025] If the subpixels SP1, SP2, and SP3 have such a layout, a row is formed in the display area DA in which the subpixels SP1 and SP3 are arranged alternately in the second direction Y, and a row is formed in which several subpixels SP2 are repeatedly arranged in the second direction Y. These rows are arranged alternately in the first direction X.

[0026] The layout of subpixels SP1, SP2, SP3 is not based on the example of Fig. 2 limited. As another example, the subpixels SP1, SP2, SP3 in each pixel PX can be arranged sequentially in the first direction X.

[0027] In the display area DA, a rib 5 and a partition 6 are arranged. Rib 5 has openings AP1, AP2, AP3 in the subpixels SP1, SP2, SP3. In the example of Fig. 2. The opening AP3 is larger than the opening AP1 and the opening AP2 is larger than the opening AP3.

[0028] In plan view, the partition 6 overlaps the rib 5. The partition 6 has several first partitions 6x extending in the first direction X and several second partitions 6y extending in the second direction Y. The multiple first partitions 6x are arranged between the openings AP1 and AP3, which are adjacent in the second direction Y, and between two openings AP2, which are adjacent in the second direction Y. The second partitions 6y are arranged between the openings AP1 and AP2, which are adjacent in the first direction X, and between the openings AP2 and AP3, which are adjacent in the first direction X.

[0029] In the example of Fig. The first partition 6x and the second partition 6y are connected. This results in partition 6 as a whole forming a grid that surrounds the openings AP1, AP2, and AP3. It can also be said that partition 6 has openings in subpixels SP1, SP2, and SP3, similar to rib 5.

[0030] Subpixel SP1 is provided with a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, each overlapping the aperture AP1. Subpixel SP2 is provided with a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, each overlapping the aperture AP2. Subpixel SP3 is provided with a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, each overlapping the aperture AP3.

[0031] In the example of Fig. Figure 2 shows the outer shapes of the lower electrodes LE1, LE2, LE3 with dotted lines, and the outer shapes of the organic layers OR1, OR2, OR3 and the upper electrodes UE1, UE2, UE3 are shown with dashed lines. The respective circumferences of the lower electrodes LE1, LE2, LE3 overlap rib 5. The outer shape of the upper electrode UE1 essentially corresponds to the outer shape of the organic layer OR1, and the respective circumferences of the upper electrode UE1 and the organic layer OR1 overlap partition 6.

[0032] The outer shape of the upper electrode UE2 essentially corresponds to the outer shape of the organic layer OR2, and the respective circumferences of the upper electrode UE2 and the organic layer OR2 overlap the partition 6. The outer shape of the upper electrode UE3 essentially corresponds to the outer shape of the organic layer OR3, and the respective circumferences of the upper electrode UE3 and the organic layer OR3 overlap the partition 6.

[0033] The lower electrode LE1, the upper electrode UE1, and the organic layer OR1 form the display element 20 of subpixel SP1. The lower electrode LE2, the upper electrode UE2, and the organic layer OR2 form the display element 20 of subpixel SP2. The lower electrode LE3, the upper electrode UE3, and the organic layer OR3 form the display element 20 of subpixel SP3. The lower electrodes LE1, LE2, and LE3 correspond, for example, to the anodes of display element 20. The upper electrodes UE1, UE2, and UE3 correspond to the cathodes or common electrodes of display element 20.

[0034] The lower electrode LE1 is connected via a contact hole CH1 to the pixel circuit 1 of the subpixel SP1 (see Fig. 1) connected. The lower electrode LE2 is connected to pixel circuit 1 of subpixel SP2 via a contact hole CH2. The lower electrode LE3 is connected to pixel circuit 1 of subpixel SP3 via a contact hole CH3.

[0035] Fig. 3 a schematic sectional view of the DSP display device along line III-III in Fig. 2.

[0036] A circuit layer 11 is arranged on the substrate 10 described above. The circuit layer 11 comprises various circuits and lines, such as those in Fig. Figure 1 shows pixel circuit 1, the scanning line GL, the signal line SL, and the power supply line PL. The circuit layer 11 is covered with an insulating layer 12. The insulating layer 12 acts as a planarizing film, flattening the irregularities caused by the circuit layer 11.

[0037] The lower electrodes LE1, LE2, LE3 are arranged on the insulating layer 12. The rib 5 is arranged on the insulating layer 12 and the lower electrodes LE1, LE2, LE3. The ends of the lower electrodes LE1, LE2, LE3 are covered by the rib 5. That is, the ends of the lower electrodes LE1, LE2, LE3 are arranged between the insulating layer 12 and the rib 5. Between the adjacent lower electrodes LE1, LE2, LE3, the insulating layer 12 is covered by the rib 5.

[0038] The partition 6 comprises a lower part (rod) 61, which is arranged on the rib 5, and an upper part (screen) 62, which is arranged on the lower part 61. The lower part 61 of the partition 6, shown on the left side of the drawing, is positioned between the openings AP1 and AP2. The lower part 61 of the partition 6, shown on the right side of the drawing, is positioned between the openings AP2 and AP3. The upper part 62 is wider than the lower part 61. As a result, the two ends of the upper part 62 project beyond the side surfaces of the lower part 61. Fig. 3. This form of partition 6 can also be called an overhang form. The part of the upper part 62 that projects beyond the lower part 61 can simply be called a projection.

[0039] The in Fig. The organic layer OR1 shown in Figure 2 comprises a first part OR1a and a second part OR1b, which are spaced apart from each other, as shown in Figure 2. Fig. Figure 3 shows the first part OR1a in contact with the lower electrode LE1 through the opening AP1, covering the lower electrode LE1 and overlapping part of the rib 5. The second part OR1b is arranged on the upper part 62.

[0040] The in Fig. The upper electrode UE1 shown in section 2 further comprises a first part UE1a and a second part UE1b, which are spaced apart from each other as shown in Fig. Figure 3 shows the first part UE1a opposite the lower electrode LE1 and positioned on the first part OR1a. Furthermore, the first part UE1a is in contact with a side surface of the lower part 61. The second part UE1b is positioned above the partition 6 and positioned on the second part OR1b.

[0041] The first part OR1a and the first part UE1a are positioned below the upper part 62.

[0042] The in Fig. The organic layer OR2 shown comprises a first part OR2a and a second part OR2b, which are spaced apart from each other, as shown in Fig. Figure 3 shows the first part OR2a in contact with the lower electrode LE2 through the opening AP2, covering the lower electrode LE2 and overlapping part of the rib 5. The second part OR2b is arranged on the upper part 62.

[0043] The in Fig. The upper electrode UE2 shown further comprises a first part UE2a and a second part UE2b, which are spaced apart from each other as shown in . Fig. Figure 3 shows the first part UE2a opposite the lower electrode LE2 and arranged on the first part OR2a. Furthermore, the first part UE2a is in contact with a side surface of the lower part 61. The second part UE2b is positioned above the partition 6 and arranged on the second part OR2b.

[0044] The first part OR2a and the first part UE2a are positioned below the upper part 62.

[0045] The in Fig. The organic layer OR3 shown comprises a first part OR3a and a second part OR3b, which are spaced apart from each other, as shown in Fig. Figure 3 shows the first part OR3a in contact with the lower electrode LE3 through the opening AP3, covering the lower electrode LE3 and overlapping part of the rib 5. The second part OR3b is arranged on the upper part 62.

[0046] The in Fig. The upper electrode UE3 shown in section 2 further comprises a first part UE3a and a second part UE3b, which are spaced apart from each other as shown in Fig. Figure 3 shows the first part UE3a opposite the lower electrode LE3 and arranged on the first part OR3a. Furthermore, the first part UE3a is in contact with a side surface of the lower part 61. The second part UE3b is positioned above the partition 6 and arranged on the second part OR3b.

[0047] The first part OR3a and the first part UE3a are positioned below the upper part 62.

[0048] In the Fig. The 3 illustrated example includes the subpixels SP1, SP2, SP3 cover layers (optical adjustment layers) CP1, CP2, CP3 for adjusting the optical properties of the light emitted by the light-emitting layers of the organic layers OR1, OR2, OR3.

[0049] The cover layer CP1 comprises a first part CP1a and a second part CP1b, which are spaced apart from each other. The first part CP1a is positioned in the opening AP1, below the upper part 62, and arranged on top of the first part UE1a. The second part CP1b is positioned above the partition wall 6 and arranged on top of the second part UE1b.

[0050] The cover layer CP2 comprises a first part CP2a and a second part CP2b, which are spaced apart from each other. The first part CP2a is positioned in the opening AP2, below the upper part 62, and arranged on the first part UE2a. The second part CP2b is positioned above the partition wall 6 and arranged on the second part UE2b.

[0051] The cover layer CP3 comprises a first part CP3a and a second part CP3b, which are spaced apart from each other. The first part CP3a is positioned in the opening AP3, below the upper part 62, and arranged on top of the first part UE3a. The second part CP3b is positioned above the partition wall 6 and arranged on top of the second part UE3b.

[0052] In the subpixels SP1, SP2, SP3, sealing layers SE1, SE2, SE3 are each arranged.

[0053] The sealing layer SE1 is in contact with the first part CP1a, the lower part 61 and the upper part 62 of the partition 6, and the second part CP1b, and continuously covers each element of the subpixel SP1. In the example shown, the sealing layer SE1 has a closed cavity V1 below the upper part 62 of the partition 6 (below the projection 621). The cavity V1 is spaced apart from the partition 6. This cavity V1 is surrounded by a portion of the sealing layer SE1 that is in contact with the side surface of the lower part 61 of the partition 6, a portion that is in contact with the bottom surface of the upper part 62 of the partition 6, and a portion that is in contact with the first part CP1a. The cavity V1 is formed along the entire perimeter of the partition 6 surrounding the opening AP1, but may also partially disappear. Furthermore, the cavity V1 is completely closed.

[0054] The sealing layer SE2 is in contact with the first part CP2a, the lower part 61 and the upper part 62 of the partition 6, and the second part CP2b, and continuously covers each element of the subpixel SP2. The sealing layer SE2 has a closed cavity V2 below the upper part 62 of the partition 6 (below the projection 622). The cavity V2 is positioned across the partition 6, which is shown on the left side of the drawing, on the side facing away from the cavity V1. The cavity V2 is formed along the entire perimeter of the partition 6, which surrounds the opening AP2, but may also partially disappear. Furthermore, the cavity V2 is completely closed.

[0055] The sealing layer SE3 is in contact with the first part CP3a, the lower part 61 and the upper part 62 of the partition 6, and the second part CP3b, and continuously covers each element of the subpixel SP3. The sealing layer SE3 has a closed cavity V3 below the upper part 62 of the partition 6 (below the projection 623). The cavity V3 is positioned across the partition 6, which is shown on the right side of the drawing, on the side facing away from the cavity V2. The cavity V3 is formed along the entire perimeter of the partition 6, which surrounds the opening AP3, but may also partially disappear. Furthermore, the cavity V3 is completely closed.

[0056] The sealing layers SE1, SE2, SE3 are covered by a protective layer 13.

[0057] In the example of Fig. 3 is on the partition 6 between the subpixels SP1, SP2 the second part OR1b of the organic layer OR1 is spaced from the second part OR2b of the organic layer OR2, the second part UE1b of the upper electrode UE1 is spaced from the second part UE2b of the upper electrode UE2, the second part CP1b of the cover layer CP1 is spaced from the second part CP2b of the cover layer CP2, and the sealing layer SE1 is spaced from the sealing layer SE2.

[0058] The protective layer 13 is arranged between the second part OR1b and the second part OR2b, between the second part UE1b and the second part UE2b, between the second part CP1b and the second part CP2b, and between the sealing layer SE1 and the sealing layer SE2, respectively.

[0059] On the partition 6 between subpixels SP2 and SP3, the second part OR2b of the organic layer OR2 is spaced from the second part OR3b of the organic layer OR3, the second part UE2b of the upper electrode UE2 is spaced from the second part UE3b of the upper electrode UE3, the second part CP2b of the top layer CP2 is spaced from the second part CP3b of the top layer CP3, and the sealing layer SE2 is spaced from the sealing layer SE3. The protective layer 13 is positioned between the second part OR2b and the second part OR3b, between the second part UE2b and the second part UE3b, between the second part CP2b and the second part CP3b, and between the sealing layer SE2 and the sealing layer SE3, respectively.

[0060] Insulation layer 12 is an organic insulation layer. Rib 5 and sealing layers SE1, SE2, SE3 are inorganic insulation layers.

[0061] The sealing layers SE1, SE2, SE3, for example, consist of the same inorganic insulating material.

[0062] Rib 5 is made of silicon nitride (SiNx), an example of an inorganic insulating material. Rib 5 can consist of a single layer of silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3), other inorganic insulating materials. Rib 5 can also consist of a stack of at least two layers made of silicon nitride, silicon oxide, silicon oxynitride, and aluminum oxide.

[0063] The sealing layers SE1, SE2, and SE3 consist of silicon nitride (SiNx), an example of an inorganic insulating material. These sealing layers can also consist of a single layer of silicon oxide (SiOx), silicon oxynitride (SiON), or aluminum oxide (Al2O3), other inorganic insulating materials. Alternatively, they can be stacked with a combination of at least two layers of silicon nitride, silicon oxide, silicon oxynitride, or aluminum oxide. Therefore, the sealing layers SE1, SE2, and SE3 can be made of the same material as rib 5.

[0064] The lower part 61 of the partition 6 consists of an electrically conductive material and is electrically connected to the first parts UE1a, UE2a, UE3a of each upper electrode. Both parts of the lower part 61 and the upper part 62 of the partition 6 can be electrically conductive.

[0065] The thickness T5 of rib 5 is sufficiently small compared to the thickness of the partition 6 and the insulating layer 12. For example, the thickness T5 of rib 5 is equal to or greater than 200 nm and equal to or less than 400 nm.

[0066] Immediately above the lower electrode LE1, which overlaps the opening AP1, the sealing layer SE1 has a thickness T1. Immediately above the lower electrode LE2, which overlaps the opening AP2, the sealing layer SE2 has a thickness T2. Immediately above the lower electrode LE3, which overlaps the opening AP3, the sealing layer SE3 has a thickness T3. The thicknesses T1, T2, and T3 are essentially the same.

[0067] The thickness T61 of the lower part 61 of the partition 6 (from the upper surface of the rib 5 to the lower surface of the upper part 62) is greater than the thickness T5 of the rib 5.

[0068] The lower electrodes LE1, LE2, LE3 can be made of a transparent, electrically conductive material such as ITO or have a laminated structure of a metallic material such as silver (Ag) and a transparent, electrically conductive material. The upper electrodes UE1, UE2, UE3 consist of a metallic material, e.g., an alloy of magnesium and silver (MgAg). The upper electrodes UE1, UE2, UE3 can be made of a transparent, electrically conductive material such as ITO.

[0069] If the potential of the lower electrodes LE1, LE2, LE3 is relatively higher than that of the upper electrodes UE1, UE2, UE3, then the lower electrodes LE1, LE2, LE3 correspond to the anodes and the upper electrodes UE1, UE2, UE3 to the cathodes.

[0070] The organic layers OR1, OR2, and OR3 comprise several functional layers. The first part, OR1a, and the second part, OR1b, of organic layer OR1 comprise a light-emitting layer EM1, which is composed of the same material. The first part, OR2a, and the second part, OR2b, of organic layer OR2 comprise a light-emitting layer EM2, which is composed of the same material. The light-emitting layer EM2 is composed of a different material than the light-emitting layer EM1. The first part, OR3a, and the second part, OR3b, of organic layer OR3 comprise a light-emitting layer EM3, which is composed of the same material. The light-emitting layer EM3 is composed of a different material than the light-emitting layers EM1 and EM2.The material from which the light-emitting layer EM1 is made, the material from which the light-emitting layer EM2 is made, and the material from which the light-emitting layer EM3 is made are materials that emit light in different wavelength ranges.

[0071] The cover layers CP1, CP2, and CP3 are formed, for example, by a multilayer consisting of several transparent thin films. This multilayer can contain several thin films made of inorganic materials and thin films made of organic materials. These thin films also have different refractive indices. The materials of the thin films that make up the multilayer differ from the materials of the upper electrodes UE1, UE2, and UE3, as well as from the materials of the sealing layers SE1, SE2, and SE3. The cover layers CP1, CP2, and CP3 can be omitted.

[0072] The protective layer 13 is formed from a multilayer of transparent thin films and includes, for example, thin films made of inorganic materials and thin films made of organic materials.

[0073] A common voltage is applied to the partition 6. This common voltage is applied to the first parts UE1a, UE2a, UE3a of each upper electrode, which are in contact with the side surfaces of the lower part 61. A pixel voltage is applied to the lower electrodes LE1, LE2, LE3 via the pixel circuits 1, each of which has the subpixels SP1, SP2, SP3.

[0074] When a potential difference is created between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer EM1 of the first part OR1a of the first organic layer OR1 emits light in the red wavelength range. When a potential difference is created between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer EM2 of the first part OR2a of the organic layer OR2 emits light in the blue wavelength range. When a potential difference is created between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer EM3 of the first part OR3a of the organic layer OR3 emits light in the green wavelength range.

[0075] As another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 can emit light of the same color (e.g., white). In this case, the DSP display device can be equipped with a color filter that converts the light emitted by the light-emitting layers into light of a color corresponding to subpixels SP1, SP2, and SP3. The DSP display device can further be equipped with a layer comprising quantum dots that are excited by the light emitted by the light-emitting layer to generate light of a color corresponding to subpixels SP1, SP2, and SP3.

[0076] Fig. 4. A training example for a display element 20.

[0077] The in Fig. The lower electrode LE shown corresponds to the lower electrodes LE1, LE2, LE3 of the Fig. 3. The in Fig. The 4 depicted organic layer OR corresponds to the organic layers OR1, OR2, OR3 of Fig. 3. The in Fig. The upper electrode UE shown in section 4 corresponds to the upper electrodes UE1, UE2, UE3 of the diagram. Fig. 3.

[0078] The organic layer OR comprises a carrier-setting layer CA1, a light-emitting layer EM, and a carrier-setting layer CA2. Carrier-setting layer CA1 is positioned between the lower electrode LE and the light-emitting layer EM, and carrier-setting layer CA2 is positioned between the light-emitting layer EM and the upper electrode UE. Carrier-setting layers CA1 and CA2 contain several functional layers. The following discussion assumes that the lower electrode LE is the anode and the upper electrode UE is the cathode.

[0079] The support layer CA1 comprises a hole injection layer F11, a hole transport layer F12, an electron barrier layer F13, etc., as functional layers. The hole injection layer F11 is located on the lower electrode LE, the hole transport layer F12 is located on the hole injection layer F11, the electron barrier layer F13 is located on the hole transport layer F12, and the light-emitting layer EM is located on the electron barrier layer F13.

[0080] The support layer CA2 comprises a hole barrier layer F21, an electron transport layer F22, an electron injection layer F23, etc., as functional layers. The hole barrier layer F21 is located on the light-emitting layer EM, the electron transport layer F22 is located on the hole barrier layer F21, the electron injection layer F23 is located on the electron transport layer F22, and the upper electrode UE is located on the electron injection layer F23.

[0081] The carrier setting layers CA1, CA2 can, if necessary, include additional functional layers, such as carrier generation layers, in addition to the functional layers mentioned above, or at least one of the functional layers mentioned above can be omitted.

[0082] Fig. 5 a schematic sectional view of the display device DSP along line AB in Fig. 2. The in Fig. Figure 5 shows a sectional view comprising several SP2 subpixels arranged in the second direction, Y. The representation of the substrate, circuit layer, and protection layer, which are shown in Fig. The numbers shown in point 3 are omitted.

[0083] The subpixel SP2, positioned in the center of the drawing, is considered. The first part OR2a of the organic layer OR2 has an end P11 along the second direction Y and an end P12 on the opposite side of end P11. Ends P11 and P12 are positioned on rib 5 and spaced from the lower part 61 of partition 6. Ends P11 and P12 are positioned directly below the upper part 62 of partition 6. Furthermore, ends P11 and P12 are located directly below the cavity V2 formed in the sealing layer SE2.

[0084] In the first part UE2a of the upper electrode UE2, the thickness T12 immediately at end P12 is greater than the thickness T11 immediately at end P11 (T12 > T11). The first part UE2a is also in contact with the lower part 61 of the partition 6, which is opposite end P12 in the second direction Y. The first part UE2a may or may not be in contact with the lower part 61 opposite end P11 in the second direction Y. The contact area between the lower part 61 opposite end P12 and the first part UE2a is larger than the contact area between the lower part 61 opposite end P11 and the first part UE2a.

[0085] The sealing layer SE2 covers the first part CP2a and the second part CP2b of the top layer CP2. Between the end P12 and the partition wall 6, the first part UE2a of the first part CP2a of the top layer CP2 is exposed and covered by the sealing layer SE2.

[0086] The second part OR2b of the organic layer OR2, the second part UE2b of the upper electrode UE2 and the second part CP2b of the cover layer CP2 are formed as stacks and arranged over the entire upper surface 62A of the upper part 62 of the partition 6.

[0087] In subpixel SP2, located on the right side of the drawing, the first part OR2a of the organic layer OR2 also has an end point P13. Directly at end point P13, the thickness of the first part UE2a of the upper electrode UE2 is equal to the thickness T11 immediately at end point P11 and smaller than the thickness T12, which is not further explained.

[0088] In the Fig. In the example shown, end P11 corresponds to the first end and end P12 to the second end.

[0089] Fig. 6 a schematic sectional view of the DSP display device along the CD line in Fig. 2. The in Fig. Figure 6 shows a sectional view comprising subpixels SP1 and SP3, which are arranged alternately in the second direction Y. The representation of the substrate, circuit layer, and protection layer, which are shown in Fig. The numbers shown in point 3 are omitted.

[0090] The subpixel SP1, positioned on the left side of the drawing, is considered. The first part OR1a of the organic layer OR1 has an end P21 along the second direction Y and an end P22 on the opposite side of end P21. Ends P21 and P22 are positioned on rib 5 and spaced from the lower part 61 of the partition 6. Ends P21 and P22 are positioned directly below the upper part 62 of the partition 6. Furthermore, ends P21 and P22 are positioned directly below the cavity V1 formed in the sealing layer SE1.

[0091] In the first part UE1a of the upper electrode UE1, the thickness T22 immediately at end P22 is greater than the thickness T21 immediately at end P21 (T22 > T21). The first part UE1a is in contact with the lower part 61 of the partition 6, which is opposite end P22 in the second direction Y. The first part UE1a may or may not be in contact with the lower part 61 opposite end P21 in the second direction Y. The contact area between the lower part 61 opposite end P22 and the first part UE1a is larger than the contact area between the lower part 61 opposite end P21 and the first part UE1a.

[0092] The sealing layer SE1 covers the first part CP1a and the second part CP1b of the top layer CP1. Between the end P22 and the partition wall 6, the first part UE1a of the first part CP1a of the top layer CP1 is exposed and covered by the sealing layer SE1.

[0093] The second part OR1b of the organic layer OR1, the second part UE1b of the upper electrode UE1 and the second part CP1b of the cover layer CP1 are formed as stacks and expose part of the upper surface 62A of the upper part 62 of the partition 6.

[0094] The subpixel SP3, positioned on the right side of the drawing, is considered. The first part OR3a of the organic layer OR3 has an end P23 along the second direction Y and an end P24 on the opposite side of end P23. Ends P23 and P24 are positioned on rib 5 and spaced from the lower part 61 of partition 6. Ends P23 and P24 are positioned directly below the upper part 62 of partition 6. Furthermore, ends P23 and P24 are positioned directly below the cavity V3 formed in the sealing layer SE3.

[0095] In the first part UE3a of the upper electrode UE3, the thickness immediately at end P23 is greater than the thickness immediately at end P24. The first part UE3a is in contact with the lower part 61 of the partition 6, which is opposite end P23 in the second direction Y. The first part UE3a may or may not be in contact with the lower part 61 opposite end P24 in the second direction Y. The contact area between the lower part 61 opposite end P23 and the first part UE3a is larger than the contact area between the lower part 61 opposite end P24 and the first part UE3a.

[0096] Between the end P23 and the partition wall 6, the first part UE3a of the first part CP3a of the cover layer CP3 is exposed and covered by the sealing layer SE3.

[0097] The second part OR3b of the organic layer OR3, the second part UE3b of the upper electrode UE3 and the second part CP3b of the cover layer CP3 are formed as stacks and expose part of the upper surface 62A of the upper part 62 of the partition 6.

[0098] In the Fig. In the example shown in Figure 6, when subpixel SP1 is considered, end P21 corresponds to the first end and end P22 to the second end. When subpixel SP3 is considered, end P23 corresponds to the second end and end P24 to the first end.

[0099] Next, a vapor separation device EV for forming the upper electrode will be explained.

[0100] Fig. 7 a view to illustrate a vapor separation device EV.

[0101] The vapor separation device EV is equipped with a transport mechanism 100 and a vapor separation source 110.

[0102] The transport mechanism 100 transports the processing substrate SUB. The processing substrate SUB is a substrate 10 on which a circuit layer 11, the insulating layer 12, the lower electrode LE, the rib 5, the partition 6, and the organic layer OR are formed. The transport direction TD of the processing substrate SUB through the transport mechanism 100 is indicated by an arrow in the drawing.

[0103] The vapor source 110 emits a material M to form the upper electrode. The direction of expansion of the vapor source 110 is inclined to the normal of the substrate 10, as indicated by the dashed line in the drawing. The direction of expansion here is, for example, the direction in which a sleeve 120 expands, regulating the emission direction of the electrically conductive material M. The angle θ between the normal of the substrate 10 and the direction of expansion of the vapor source 110 is, for example, between 5° and 40°. The vapor emission direction D of the electrically conductive material M through the vapor source 110 is indicated in the drawing by an arrow. The vapor emission direction D is a direction from the bottom 111 of the vapor source 110 to the opening 112 of the vapor source 110. The vapor emission direction D is opposite to the transport direction TD.

[0104] In such a vapor deposition device EV, the vapor deposition source 110 is fixed, and the material M is vapor-deposited onto the processing substrate SUB while the processing substrate SUB is transported in one direction. This forms an upper electrode on the organic layer OR. The electrically conductive material M is an alloy of magnesium and silver.

[0105] Fig. 8 A view illustrating the vapor deposition direction D during the formation of the upper electrode in each subpixel.

[0106] In subpixel SP1, the opening AP1 of rib 5 overlaps the lower electrode LE1, and the organic layer OR1 forms on the lower electrode LE1 within the opening AP1. The vapor deposition direction D1 during the formation of the upper electrode UE1 on the organic layer OR1 is indicated by the arrow in the drawing.

[0107] In subpixel SP2, the opening AP2 of rib 5 overlaps the lower electrode LE2, and the organic layer OR2 forms on the lower electrode LE2 within the opening AP2. The vapor deposition direction D1 during the formation of the upper electrode UE2 on the organic layer OR2 is the same direction as the vapor deposition direction D1 during the formation of the upper electrode UE1 in subpixel SP1, as indicated by the arrow in the drawing.

[0108] In subpixel SP3, the opening AP3 of rib 5 overlaps the lower electrode LE3, and the organic layer OR3 forms on the lower electrode LE3 within the opening AP3. The vapor deposition direction D2 during the formation of the upper electrode UE3 on the organic layer OR3 differs from the vapor deposition direction D1 during the formation of the upper electrode UE1 in subpixel SP1, as indicated by the arrow in the diagram.

[0109] These vapor separation directions D1 and D2 are essentially parallel to the direction (second direction Y) in which the lower electrode LE1 and the lower electrode LE3 are aligned, and are opposite to each other.

[0110] Fig. 9 A view to illustrate the transport direction TD during the formation of the upper electrode.

[0111] The illustrated example shows the transport direction TD of the processing substrate SUB during the formation of the upper electrode UE1 of subpixel SP1 or the upper electrode UE2 of subpixel SP2. The processing substrate SUB has one end SUBA along the transport direction TD and the other end SUBB on the opposite side from the first end SUBA. In the illustrated example, the processing substrate SUB is introduced into the vapor deposition device EV with the first end SUBA as its leading end. In the vapor deposition device EV, a conductive material M emitted by the vapor deposition source 110 is vapor-deposited while the processing substrate SUB is transported with the first end SUBA as its leading end.

[0112] Fig. 10 A view to illustrate a different transport direction TD during the formation of the upper electrode.

[0113] The illustrated example shows the transport direction TD of the processing substrate SUB during the formation of the upper electrode UE3 of the subpixel SP3. If, for example, the upper electrode UE3 is formed after the formation of the upper electrode UE1 or UE2, the processing substrate SUB is transported with one end SUBA as the leading end, then rotated 180° in the plane of the substrate before the formation of the upper electrode UE3, and introduced into the vapor deposition device EV with the other end SUBB as the leading end. In the vapor deposition device EV, the conductive material M emitted by the vapor deposition source 110 is vapor-deposited, while the processing substrate SUB is transported with the other end SUBB as the leading end.

[0114] In this way, the transport direction of the processing substrate SUB during the formation of the upper electrode UE1 or UE2 is different from the transport direction of the processing substrate SUB during the formation of the upper electrode UE3.

[0115] Fig. 11 A view to illustrate how the upper electrode is formed.

[0116] In the upper level of Fig. Figure 11 shows the processing substrate SUB before the formation of the upper electrode (before introduction into the vapor separation device).

[0117] In the lower level of Fig. Figure 11 shows the processing substrate SUB after the formation of the upper electrode UE. The tip of the arrow indicating the transport direction TD corresponds to the trailing end of the arrow indicating the vapor separation direction D, and vice versa.

[0118] The electrically conductive material M emitted by the vapor separation source 110 is shielded by the partition 6 on the side of the trailing end of the vapor separation direction D, while on the tip side of the vapor separation direction D it bypasses the lower part 61 of the partition 6. Therefore, when considering the upper electrode UE of a subpixel, it becomes thicker on the tip side of the vapor separation direction D and thinner on the side of the trailing end of the vapor separation direction D. On the tip side of the

[0119] In vapor deposition direction D, the upper electrode UE is securely in contact with the lower part 61 of the partition 6, and the two are electrically connected. Therefore, compared to the case where the expansion direction of the vapor deposition source 110 is parallel to the normal of the substrate 10, a poor electrical connection between the upper electrode UE and the lower part 61 is suppressed. On the tip side of vapor deposition direction D, more electrically conductive material M surrounds the lower part 61, thus increasing the contact area between the upper electrode UE and the lower part 61 and reducing the contact resistance. Consequently, a reduction in reliability can be suppressed.

[0120] In the Fig. In examples 7 to 11, the opening AP1 corresponds to the first opening, the opening AP3 to the second opening, the lower electrode LE1 to the first lower electrode, the lower electrode LE3 to the second lower electrode, the organic layer OR1 to the first organic layer, the organic layer OR3 to the second organic layer, the light-emitting layer EM1 to the first light-emitting layer, the light-emitting layer EM3 to the second light-emitting layer, the upper electrode UE1 to the first upper electrode, the upper electrode UE3 to the second upper electrode, the cover layer CP1 to the first cover layer, the cover layer CP3 to the second cover layer, the sealing layer SE1 to the first sealing layer, and the sealing layer SE3 to the second sealing layer.

[0121] The in Fig. 7, Fig. 9, Fig. 10 and Fig. The example shown in Figure 11 for the vapor separation device EV corresponds to a case in which the vapor separation surface of the processing substrate SUB is arranged above the substrate 10 (with the front facing upwards) and the vapor separation source 110 is configured to emit the electrically conductive material M downwards. However, the vapor separation device EV is not limited to this configuration. For example, the vapor separation device EV can be configured such that the vapor separation surface of the processing substrate SUB is arranged below the substrate 10 (with the front facing downwards) and the vapor separation source 110 emits the electrically conductive material M upwards. Furthermore, the vapor separation device EV can be configured such that the processing substrate SUB is transported in a vertically upright position and the vapor separation source 110 emits the material M laterally.

[0122] Next, an example of a method for manufacturing the DSP display device will be explained.

[0123] Fig. 12. A flowchart illustrating an example of a method for manufacturing a DSP display device.

[0124] The manufacturing process described here comprises, broadly speaking, a step for preparing the processing substrate SUB, which serves as the basis for subpixels SPα, SPβ, and SPγ (step ST1), a step for forming subpixel SPα (step ST2), a step for forming subpixel SPβ (step ST3), and a step for forming subpixel SPγ (step ST4). The subpixels SPα, SPβ, and SPγ are one of the aforementioned subpixels SP1, SP2, and SP3.

[0125] In step ST1, a processing substrate SUB is first prepared, with the lower electrodes LEα, LEβ, LEγ, rib 5 and the partition 6 being formed on the substrate 10. As in Fig. As shown in Figure 3, the circuit layer 11 and the insulating layer 12 are also formed between the substrate 10 and the lower electrodes LEα, LEβ, LEγ.

[0126] In step ST2, a first thin film 31 with a light-emitting layer EMα is formed on the processing substrate SUB (step ST21). Then, a first resist 41, structured in a predetermined shape, is formed on the first thin film 31 (step ST22). Next, a portion of the first thin film 31 is removed by etching using the first resist 41 as a mask (step ST23). The first resist 41 is then removed (step ST24). This creates the subpixel SPα. The subpixel SPα is equipped with the display element 21, which has the first thin film 31 in a specific shape.

[0127] In step ST3, a second thin film 32, comprising the light-emitting layer EMβ, is first formed on the processing substrate SUB (step ST31). Then, a second resist 42, structured in a predetermined shape, is formed on the second thin film 32 (step ST32). Next, a portion of the second thin film 32 is removed by etching using the second resist 42 as a mask (step ST33). The second resist 42 is then removed (step ST34). This creates the subpixel SPβ. The subpixel SPβ is equipped with the display element 22, which has the second thin film 32 in a specific shape.

[0128] In step ST4, a third thin film 33, comprising the light-emitting layer EMγ, is first formed on the processing substrate SUB (step ST41). Then, a third resist 43, structured in a predetermined shape, is formed on the third thin film 33 (step ST42). Next, a portion of the third thin film 33 is removed by etching using the third resist 43 as a mask (step ST43). The third resist 43 is then removed (step ST44). This creates the subpixel SPγ. The subpixel SPγ is equipped with the display element 23, which has the third thin film 33 in a predetermined shape.

[0129] The light-emitting layer EMα, the light-emitting layer EMβ and the light-emitting layer EMγ are formed by materials that emit light in different wavelength ranges.

[0130] The detailed representation of the second thin film 32, the light-emitting layer EMβ, the indicator element 22, the third thin film 33, the light-emitting layer EMγ and the indicator element 23 is omitted.

[0131] Steps ST1 and ST2 are described below with reference to Fig. Explained in sections 13 to 17. Each in the Fig. The section shown in sections 13 to 17 corresponds, for example, to a section along line III-III in Fig. 2.

[0132] First, in step ST1, the processing substrate SUB is prepared, as shown in Fig. Figure 13 illustrates the process for preparing the processing substrate SUB, which comprises the following steps: forming the circuit layer 11 on the substrate 10, forming the insulating layer 12 on the circuit layer 11, forming the lower electrode LEα of subpixel SPα, the lower electrode LEβ of subpixel SPβ, and the lower electrode LEγ of subpixel SPγ on the insulating layer 12, forming the rib 5 with openings APα, APβ, APγ, each overlapping the lower electrodes LEα, LEβ, LEγ, and forming the partition 6 with the lower part 61 located on the rib 5 and the upper part 62 located on the lower part 61 and projecting from the side surface of the lower part 61. Fig. Figures 14 to 17 omit the representation of the substrate 10 and the circuit layer 11 below the insulating layer 12.

[0133] Subsequently, in step ST21, a first thin film 31 is formed over the subpixel SPα, the subpixel SPβ and the subpixel SPγ, as shown in Fig. Figure 14 illustrates the process for forming the first thin film 31, comprising the following steps: forming an organic layer OR10 with a light-emitting layer EMα on the processing substrate SUB, forming an upper electrode UE10 on the organic layer OR10, forming a top layer CP10 on the upper electrode UE10, and forming a sealing layer SE10 on the top layer CP10. In the illustrated example, the first thin film 31 comprises the organic layer OR10, the upper electrode UE10, the top layer CP10, and the sealing layer SE10. The steps for producing the upper electrode UE10 are described with reference to the Fig. The vapor separation device EV described in sections 7 to 11 was carried out.

[0134] The organic layer OR10 comprises an organic layer OR11, an organic layer OR12, an organic layer OR13, an organic layer OR14, and an organic layer OR15. The organic layers OR11, OR12, OR13, OR14, and OR15 each comprise the light-emitting layer EMα.

[0135] The organic layer OR11 is formed such that it covers the lower electrode LEα. The organic layer OR12 is spaced apart from the organic layer OR11 and is positioned on the upper part 62 of the partition 6 between the lower electrode LEα and the lower electrode LEβ. The organic layer OR13 is formed such that it is spaced apart from the organic layer OR12 and covers the lower electrode LEβ. The organic layer OR14 is spaced apart from the organic layer OR13 and is positioned on the upper part 62 of the partition 6 between the lower electrode LEβ and the lower electrode LEγ. The organic layer OR15 is formed such that it is spaced apart from the organic layer OR14 and covers the lower electrode LEγ.

[0136] The upper electrode UE10 includes an upper electrode UE11, an upper electrode UE12, an upper electrode UE13, an upper electrode UE14 and an upper electrode UE15.

[0137] The upper electrode UE11 is positioned on the organic layer OR11 and is in contact with the lower part 61 of the partition 6 between the lower electrode LEα and the lower electrode LEβ. The upper electrode UE12 is spaced apart from the upper electrode UE11 and is positioned on the organic layer OR12 between the lower electrode LEα and the lower electrode LEβ. The upper electrode UE13 is spaced apart from the upper electrode UE12 and is positioned on the organic layer OR13. In the illustrated example, the upper electrode UE13 is in contact with the lower part 61 of the partition 6 between the lower electrode LEα and the lower electrode LEβ and in contact with the lower part 61 of the partition 6 between the lower electrode LEβ and the lower electrode LEγ, but can also be in contact with either of the lower parts 61.The upper electrode UE14 is spaced apart from the upper electrode UE13 and is positioned on the organic layer OR14 between the lower electrode LEβ and the lower electrode LEγ. The upper electrode UE15 is spaced apart from the upper electrode UE14, is positioned on the organic layer OR15, and is in contact with the lower part 61 of the partition 6 between the lower electrode LEβ and the lower electrode LEγ.

[0138] The CP10 top layer includes a CP11 top layer, a CP12 top layer, a CP13 top layer, a CP14 top layer and a CP15 top layer.

[0139] The top layer CP11 is positioned on the upper electrode UE11. The top layer CP12 is spaced away from the top layer CP11 and positioned on the upper electrode UE12. The top layer CP13 is spaced away from the top layer CP12 and positioned on the upper electrode UE13. The top layer CP14 is spaced away from the top layer CP13 and positioned on the upper electrode UE14. The top layer CP15 is spaced away from the top layer CP14 and positioned on the upper electrode UE15.

[0140] The sealing layer SE10 is formed such that it covers the cover layer CP11, the cover layer CP12, the cover layer CP13, the cover layer CP14, the cover layer CP15, and the partition wall 6. The sealing layer SE10 covering the partition wall 6 is in contact with the lower region of the upper part 62 and the side surface of the lower part 61. The sealing layer SE10 has a cavity Vα facing the subpixel SPα of the partition wall 6, a cavity Vβ facing the subpixel SPβ of the partition wall 6, and a cavity Vγ facing the subpixel SPγ of the partition wall 6.

[0141] Subsequently, in step ST22, a first Resist 41 is formed on the sealing layer SE10, as shown in Fig. Figure 15 shows the first resist 41 covering subpixel SPα. That is, the first resist 41 is located directly on the lower electrode LEα, the organic layer OR11, the upper electrode UE11, and the cover layer CP11. The first resist 41 extends from subpixel SPα upwards along the partition 6. Between subpixel SPα and subpixel SPβ, the first resist 41 is located on the side of subpixel SPα (left in the drawing) and exposes the sealing layer SE10 on the side of subpixel SPβ (right in the drawing). In the illustrated example, the first resist 41 exposes the sealing layer SE10 on subpixels SPβ and SPγ.

[0142] Then, in step ST23, as in Fig. Figure 16 shows that etching was carried out using the first resist 41 as a mask to remove part of the first thin layer 31.

[0143] First, the sealing layer SE10, exposed by the first Resist 41, is removed. Then, the top layer CP10, exposed by the first Resist 41 and the sealing layer SE10, is removed. Next, the upper electrode UE10, exposed by the first Resist 41, the sealing layer SE10, and the top layer CP10, is removed. Finally, the organic layer OR10, exposed by the first Resist 41, the sealing layer SE10, the top layer CP10, and the upper electrode UE10, is removed.

[0144] This exposes the lower electrode LEβ in subpixel SPβ and the lower electrode LEγ in subpixel SPγ. At the partition 6 between subpixel SPα and subpixel SPβ, the organic layer OR12, the upper electrode UE12, the cover layer CP12, and the sealing layer SE10 remain on the upper part 62 on the side of subpixel SPα, while the organic layer OR12, the upper electrode UE12, the cover layer CP12, and the sealing layer SE10 on the side of subpixel SPβ are removed. Therefore, the partition 6 is exposed on the side of subpixel SPβ.

[0145] The partition wall 6 between subpixel SPβ and subpixel SPγ is also exposed.

[0146] Then the first resist 41 is removed in step ST24, as shown in Fig. Figure 17 shows that this exposes the sealing layer SE10 of subpixel SPα. Steps ST21 to ST24 form the display element 21 in subpixel SPα. The display element 21 consists of the lower electrode LEα, the organic layer OR11 with the light-emitting layer EMα, the upper electrode UE11, and the cover layer CP11. The display element 21 is further covered by the sealing layer SE10.

[0147] On the partition 6 between subpixel SPα and subpixel SPβ, a stack is formed consisting of the organic layer OR12 with the light-emitting layer EMα, the upper electrode UE12, and the cover layer CP12, and the stack is covered with the sealing layer SE10. Additionally, the portion of partition 6 on the side of subpixel SPα is covered with the sealing layer SE10.

[0148] The subpixel SPα in the above example is one of the subpixels in Fig.The subpixels SP1, SP2, and SP3 shown in Figure 2 correspond to the following subpixels: SPα, SP1 ...

[0149] As explained above, according to the present embodiment it is possible to provide a display device and a method for manufacturing the display device that can suppress the reduction in reliability and improve manufacturing yield.

Claims

[1] Display device (DSP) equipped with: a substrate (10), a lower electrode (LE1, LE2, LE3) which is arranged above the substrate (10), a rib (5) having an opening (AP1, AP2, AP3) that overlaps the lower electrode (LE1, LE2, LE3), a partition (6) comprising a lower part (61) arranged on the rib (5) and an upper part (62) arranged on the lower part (61) and projecting from the side surface of the lower part (61), an organic layer (OR1, OR2, OR3) arranged on the lower electrode (LE1, LE2, LE3) in the opening (AP1, AP2, AP3) and comprising a light-emitting layer (EM1, EM2, EM3), and an upper electrode (UE1, UE2, UE3) which is arranged on the organic layer (OR1, OR2, OR3) and is in contact with the lower part (61) of the partition (6), a top layer (CP1, CP2, CP3) which is arranged on the upper electrode (UE1, UE2, UE3), and a sealing layer (SE1, SE2, SE3) that covers the top layer (CP1, CP2, CP3) and is in contact with the lower part (61) of the partition wall (6), wherein the organic layer (OR1, OR2, OR3) has a first end that is positioned on the rib (5) and a second end that is positioned on the rib (5) and lies on the side opposite the first end, where the thickness of the upper electrode (UE1, UE2, UE3) immediately at the second end is greater than the thickness of the upper electrode (UE1, UE2, UE3) immediately at the first end, wherein the sealing layer (SE1, SE2, SE3) covers the upper electrode (UE1, UE2, UE3) between the second end and the partition (6), wherein each of the organic layer (OR1, OR2, OR3), the upper electrode (UE1, UE2, UE3) and the cover layer (CP1, CP2, CP3) has a first part which is positioned below the upper part (62) of the partition (6) and a second part which is positioned above the upper part (62) and spaced apart from the first part, wherein the sealing layer (SE1, SE2, SE3) is in contact with the first part and the second part of the cover layer (CP1, CP2, CP3), wherein the second part of each of the organic layer (OR1, OR2, OR3), the upper electrode (UE1, UE2, UE3) and the cover layer (CP1, CP2, CP3) are formed as a stack, the stack exposes part of the upper surface of the upper part (62) of the partition (6). [2] Display device (DSP) according to claim 1, wherein the lower part of the partition (6) consists of an electrically conductive material, wherein a contact area between the lower part (61) opposite the second end and the upper electrode (UE1, UE2, UE3) is larger than the contact area between the lower part (61) opposite the first end and the upper electrode (UE1, UE2, UE3). [3] Display device (DSP) according to claim 1, wherein the first end and the second end are positioned directly below the upper part (62) of the partition (6). [4] Display device (DSP) according to claim 1, wherein the sealing layer (SE1, SE2, SE3) has a cavity (V1, V2, V3) which is closed below the upper part (62) of the partition wall (6), and the first end and the second end are positioned directly below the cavity (V1, V2, V3). [5] Display device (DSP) according to claim 1, wherein the sealing layer (SE1, SE2, SE3) consists of an inorganic insulating material. [6] Display device (DSP) according to claim 1, wherein the sealing layer (SE1, SE2, SE3) consists of silicon nitride. [7] Display device (DSP) according to claim 1, wherein the rib (5) consists of an inorganic insulating material. [8] Display device (DSP) according to claim 1, wherein the rib (5) is made of silicon nitride. [9] Display device (DSP) according to claim 1, wherein the rib (5) is made of silicon oxynitride.

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