Power semiconductor device with a solder leakage prevention layer and method for its manufacture

Abstract

Power semiconductor device (200, 300, 400), comprising: a die carrier (110), a power semiconductor chip (120) arranged on the die carrier (110), the power semiconductor chip (120) comprising a first side (121) and an opposing second side (122), the first side (121) facing away from the die carrier (110) and comprising a first power terminal (123) with a Cu layer (150), and the second side (122) comprising a second power terminal (124) electrically coupled to the die carrier (110), a contact clip (130) electrically coupled to the Cu layer (150) of the first power terminal (123) by a solder joint (160), and a structured cover layer (140) on the first side (121) of the Power semiconductor chips (120) are arranged, wherein the cover layer (140) surrounds the first power terminal (123) on at least one lateral side,wherein the cover layer (140) is arranged above the Cu layer (150) and the cover layer (140) consists of Al2O3 or SiO2, and an imide layer (180) which is arranged on the first side (121) of the power semiconductor chip (120) at least partially under the Cu layer (150) and is arranged along a circumference of the first power terminal (123).

Description

TECHNICAL FIELD

[0001] The invention relates to a power semiconductor component having a cover layer designed to prevent solder from escaping from a power terminal, and to a method for producing such a power semiconductor component. BACKGROUND

[0002] A power semiconductor device, for example a power semiconductor package, may comprise, for example, a power semiconductor chip attached to a die carrier such that a first side of the power semiconductor chip faces away from the die carrier and a second side faces the die carrier. Furthermore, a contact clip may be coupled to a power terminal on the first side of the power semiconductor chip. The contact clip may, for example, electrically connect the power terminal to an external contact or to another die carrier of the power semiconductor device. However, there may be a risk that solder leakage may occur during manufacture of the power semiconductor device when coupling the contact clip to the power terminal.Such solder leakage can, for example, cause pad contamination and / or electrical short circuits, and can therefore reduce the yield of a lot of usable devices. Improved power semiconductor devices and improved methods for manufacturing power semiconductor devices can help solve these and other problems. SUMMARY

[0003] Various aspects relate to a power semiconductor device, comprising: a die carrier; a power semiconductor chip arranged on the die carrier, the power semiconductor chip comprising a first side and an opposite second side, the first side facing away from the die carrier and comprising a first power terminal having a Cu layer, and the second side comprising a second power terminal electrically coupled to the die carrier by a solder connection; a contact clip electrically coupled to the Cu layer of the first power terminal by a solder connection; and a structured cap layer arranged on the first side of the power semiconductor chip, the cap layer surrounding the first power terminal on at least one lateral side, the cap layer being arranged above the Cu layer, the cap layer being made of Al2O3 or SiO2.

[0004] Various aspects relate to a method for manufacturing a power semiconductor device, the method comprising: providing a die carrier; arranging a power semiconductor chip on the die carrier, the power semiconductor chip comprising a first side and an opposite second side, the first side facing away from the die carrier and comprising a first power terminal with a Cu layer, and the second side comprising a second power terminal; depositing a cap layer consisting of Al2O3 or SiO2 on the first side of the power semiconductor chip over the Cu layer; structuring the cap layer such that the cap layer surrounds the first power terminal on at least one lateral side; electrically coupling the second power terminal to the die carrier; and soldering a contact clip to the Cu layer of the first power terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] The accompanying drawings illustrate examples and, together with the description, serve to explain principles of the invention. Other examples and many of the intended advantages of the invention will be readily apparent from the following detailed description. The elements of the drawings are not necessarily to scale. Identical reference numerals designate corresponding similar parts. Fig. 1A and Fig. 1B show a top view ( Fig. 1A) and a sectional view ( Fig. 1B) a power semiconductor device comprising a structured cover layer. Fig. 2 shows a sectional view of another power semiconductor device, wherein the cover layer is arranged exclusively over a Cu layer of a first power terminal. Fig. 3 shows a sectional view of another power semiconductor device comprising the cap layer and also comprising a polymer ring arranged around the first power terminal. Fig. 4 shows a plan view of another power semiconductor device comprising metal finger structures arranged beneath the cap layer. Fig. 5A to Fig. 5D show a power semiconductor device at various stages of fabrication according to an exemplary method of fabricating a power semiconductor device. Fig. 6 is a flowchart of an exemplary method for manufacturing a power semiconductor device. DETAILED DESCRIPTION

[0006] In the following detailed description, well-known structures and elements are shown in schematic form to facilitate the description of one or more aspects of the invention. In this regard, directional terminology such as "top," "bottom," "left," "right," "upper," "lower," etc., is used with reference to the orientation of the described figure. Since components of the invention can be positioned in a number of different orientations, the directional terminology is used for illustrative purposes only. It is understood that other examples may be used and structural or logical changes may be made.

[0007] Additionally, while a particular feature or aspect of an example may be disclosed with respect to only one of several implementations, such feature or aspect may be combined with one or more other features or aspects of the other implementations as may be desired and advantageous for a given or particular application, unless expressly stated or technically limited otherwise. Furthermore, to the extent that the terms "include," "having," "with," or other variations thereof are used either in the detailed description or in the claims, such terms are intended to be inclusive in a manner similar to the term "comprising." The terms "coupled" and "connected" may be used together with derivatives thereof.It is understood that these terms can be used to indicate that two elements cooperate or interact with each other, whether or not they are in direct physical or electrical contact; intermediate elements or layers may be provided between the "bonded," "attached," or "connected" elements. However, it is also possible for the "bonded," "attached," or "connected" elements to be in direct contact with each other. Furthermore, the term "exemplary" is intended merely as an example and not as the best or optimal.

[0008] The examples of a power semiconductor device described below may use various types of semiconductor dies or circuits integrated into the semiconductor dies, including AC / DC or DC / DC converter circuits, inverter circuits, power MOS transistors, power Schottky diodes, JFETs (Junction Gate Field Effect Transistors), bipolar power transistors, power integrated circuits, etc.

[0009] The semiconductor die(s) may include terminals (or electrodes) that allow for electrical contact to be made with the integrated circuits contained within the semiconductor die(s). The terminals may include one or more electrode metal layers deposited on the semiconductor material of the semiconductor die(s). The electrode metal layers may be fabricated with any desired geometric shape and material composition. For example, they may comprise or consist of a material selected from the group consisting of Cu, Ni, NiSn, Au, Ag, Pt, and Pd.

[0010] An efficient power semiconductor device and an efficient method for manufacturing a power semiconductor device can, for example, reduce material consumption, ohmic losses, chemical waste, etc., and can therefore enable energy and / or resource savings. Improved power semiconductor devices and improved methods for manufacturing a power semiconductor device, as specified in this description, can therefore at least indirectly contribute to green technology solutions, i.e., climate-friendly solutions that provide mitigation of energy and / or resource use.

[0011] Fig. 1A and Fig. 1B shows a power semiconductor device 100 comprising a die carrier 110, a power semiconductor chip 120, a contact clip 130, and a patterned cap layer 140. Fig. 1A shows a plan view of the power semiconductor device 100 and Fig. Figure 1B shows a sectional view along the line BB' in Fig. 1A.

[0012] The power semiconductor device 100 may, for example, be a power semiconductor package or a part of a power semiconductor package. A power semiconductor package may, for example, include a power semiconductor chip arranged on a die carrier, an encapsulation body encapsulating the power semiconductor chip, and external contacts electrically coupled to the power semiconductor chip.

[0013] The power semiconductor device 100 may be configured to operate with a high electrical voltage and / or a high electrical current. The power semiconductor device 100 may provide any suitable electrical circuit, or the power semiconductor device 100 may be part of any suitable electrical circuit. Examples of such electrical circuits include converter circuits, inverter circuits, half-bridge circuits, full-bridge circuits, etc.

[0014] The die carrier 110 may comprise or consist of a suitable metal or metal alloy. For example, the die carrier 110 may comprise or consist of Cu. According to one example, the die carrier 110 is a leadframe part. In this case, the power semiconductor device 100 may, for example, comprise further components that are parts of the same leadframe as the die carrier 110, for example, external contacts.

[0015] The power semiconductor chip 120 is arranged on the die carrier 110. The power semiconductor chip 120 can, in particular, be arranged above a top side of the die carrier 110. A bottom side of the die carrier 110, which is opposite the top side, can be exposed, for example, by an encapsulation body (not shown) of the power semiconductor device 100. The bottom side of the die carrier 110 can, for example, be configured to be coupled to a heat sink and / or to an application board.

[0016] The power semiconductor chip 120 comprises a first side 121 and an opposite second side 122. The first side 121 faces away from the die carrier 110 and the first side 121 comprises a first power terminal 123 with a Cu layer 150. According to one example, the first power terminal 123 may comprise one or more additional metal layers (in Fig. 1B not shown), for example, a Ti layer and / or a W layer and / or an Al layer. The one or more additional metal layers may be arranged between the Cu layer 150 and the semiconductor material of the power semiconductor chip 120.

[0017] The first power terminal 123 may, for example, be a source terminal, a drain terminal, an emitter terminal, or a collector terminal. The second side 122 of the power semiconductor chip 120 includes a second power terminal 124 electrically coupled to the die carrier 110. The second power terminal 124 may, for example, be coupled to the die carrier 110 via a second solder connection. The second power terminal 124 may, for example, be a source terminal, a drain terminal, an emitter terminal, or a collector terminal. According to one example, the first power terminal 123 is a source terminal and the second power terminal 124 is a drain terminal, and according to another example, it is vice versa.

[0018] The contact clip 130 is electrically coupled to the Cu layer 150 of the first power terminal 123 by a solder joint 160 (it should be noted that the solder joint 160 in Fig. 1A is not shown to show the Cu layer 150). The contact clip 130 may be arranged above the power semiconductor chip 120 and above the die carrier 110. The contact clip 130 may comprise or consist of any suitable metal or metal alloy, for example, Cu. According to one example, the contact clip 130 is a lead frame part, in particular a part of a different lead frame than the die carrier 110.

[0019] The contact clip 130 may, for example, be configured to provide an electrical connection between the first power terminal 123 of the power semiconductor chip 120 and an external contact of the power semiconductor device 100. For this purpose, a distal end of the contact clip 130 may be coupled to the external contact via, for example, a further solder connection (wherein the distal end of the contact clip 130 extends beyond a periphery of the die carrier 110).

[0020] The capping layer 140 is arranged on the first side 121 of the power semiconductor chip 120. According to one example, the capping layer 140 is arranged only on the first side 121 and not on the second side 122 of the power semiconductor chip 120. The capping layer 140 is a structured layer, which means that the capping layer 140 has a predefined shape, with only a portion of the first side 121 being covered by the capping layer 140. The capping layer 140 may, for example, cover between about 5% and about 95% of the first side 121. The lower limit of this range may also be about 10%, about 20%, about 30%, or about 40%, and the upper limit may also be about 90%, about 80%, about 70%, about 60%, or about 50%.

[0021] The cover layer 140 surrounds the first power terminal 123 on at least one lateral side. This may mean that the cover layer 140 is arranged along a portion or all of at least one of the lateral sides of the first power terminal 123. For example, the cover layer 140 may be arranged along a first lateral side 123_1 of the first power terminal 123, but not along one or more of a second lateral side 123_2, a third lateral side 123_3, and a fourth lateral side 123_4. According to another example, the cover layer 140 may be arranged along two of the lateral sides 123_1 to 123_4, or along three of the lateral sides 123_1 to 123_4, or along all four of the lateral sides 123_1 to 123_4. In particular, the cover layer 140 can completely surround the first power terminal 123 on all lateral sides 123_1 to 123_4.A perimeter of the first power terminal 123 may be defined by the cover layer 140 in the sense that the first power terminal 123 is exposed from the cover layer 140 only within the perimeter.

[0022] The cover layer 140 is arranged over the Cu layer 150 of the first power terminal 123. In other words, the cover layer 140 can be arranged (directly) over the Cu layer 150 and can cover a portion, e.g., an outer portion, of the Cu layer 150. In the Fig. In the example shown in Figure 1B, the capping layer 140 is also arranged directly over the semiconductor material of the power semiconductor chip 120. However, it is also possible for the capping layer 140 to be arranged only over the Cu layer 150, or the capping layer 140 may be arranged over the Cu layer 150 and over one or more additional layers, e.g., a hard passivation layer, over the semiconductor material.

[0023] The cap layer 140 is made of Al2O3 and / or SiO2. For example, the cap layer 140 may consist solely of Al2O3, excluding unavoidable impurities, or the cap layer 140 may consist solely of SiO2, excluding unavoidable impurities. According to another example, the cap layer 140 may include an Al2O3 layer and a SiO2 layer. The cap layer 140 may be formed, for example, using a suitable atomic layer deposition (ALD) process or a suitable chemical vapor deposition (CVD) process.

[0024] The cover layer 140 is configured to prevent liquid solder material from escaping from the periphery of the first power terminal 123. In other words, the cover layer 140 can act as a barrier for liquid solder material during the manufacture of the power semiconductor device 100, in particular during the manufacture of the solder connection 160, and ensure that no liquid solder material comes into contact with other parts of the first side 121, with the exception of the first power terminal 123. The material of the cover layer 140 can, in particular, be configured to be non-wettable by liquid solder material.

[0025] Furthermore, the cap layer 140 may also prevent oxidation of the Cu layer 150 to prevent delamination of an encapsulation material from the power semiconductor chip 120.

[0026] According to one example, the solder joint 160 comprises a Pb-free solder material. According to another example, the solder joint 160 comprises a solder material that includes Pb. The solder material of the solder joint 160 may, for example, include or consist of Sn.

[0027] According to one example, the power semiconductor device 100 comprises one or more further terminals 170 arranged laterally adjacent to the first power terminal 123 on the first side 121 of the power semiconductor chip 120. The one or more further terminals 170 may, for example, comprise a control terminal, e.g., a gate terminal, and / or a sensing terminal, e.g., a source sensing terminal or a temperature sensing terminal.

[0028] According to one example, the one or more further terminals 170 are not surrounded by the cap layer 140. It may not be necessary to surround the further terminals 170 with the cap layer 140 because bond wires are coupled to the further terminals 170 instead of contact clips, and therefore there is no risk of solder leakage.

[0029] According to one example, the power semiconductor device 100 further comprises a polymer layer 180. The polymer layer 180 may, for example, comprise or consist of an imide. The polymer layer 180 may substantially surround the first power terminal 123. The Cu layer 150 may, for example, be arranged at least partially over the polymer layer 180. The cap layer 140 may, for example, be arranged at least partially over the polymer layer 180. The polymer layer 180 may, for example, cover those portions of the first side 121 of the power semiconductor chip 120 that are not part of the first power terminal 123 or the further terminals 170.

[0030] Fig. 2 shows a sectional view of a power semiconductor device 200, which may be similar or identical to the power semiconductor device 100, except for the differences described below.

[0031] In the power semiconductor device 200, the cap layer 140 is arranged only (directly) above the Cu layer 150. In particular, the cap layer 140 is not in contact with the polymer layer 180. Furthermore, the Cu layer 150, in particular an outer portion of the Cu layer 150, is arranged above the polymer layer 180.

[0032] As in Fig. As shown in Figure 2, only an inner portion of the Cu layer 150 is exposed from the cap layer 140 and may be wetted by liquid solder material to form the solder joint 160. It should be noted that in both the power semiconductor device 100 and the power semiconductor device 200, the cap layer 140, and not the polymer layer 180, is configured to act as a solder stop.

[0033] Fig. 3 shows a sectional view of another power semiconductor device 300, which may be similar or identical to the power semiconductor device 100 or 200, except for the differences described below.

[0034] In the power semiconductor device 300, the polymer layer 180 is structured such that a polymer ring 180' surrounds the first power terminal 123. The polymer ring 180' can, for example, be arranged along the circumference of the first power terminal 123. Due to the polymer ring 180', the first power terminal 123 has a topology that includes a raised ring structure. This raised ring structure can, for example, assist in the correct alignment of the contact clip 130 on a droplet of liquid solder material during the manufacture of the power semiconductor device 300.

[0035] Fig. 4 shows a plan view of another power semiconductor device 400, which may be similar or identical to one of the power semiconductor devices 100 to 300, except for the differences described below.

[0036] The power semiconductor device 400 includes at least one metal finger structure 410 extending from a point outside the perimeter of the first power terminal 123 to a point inside the perimeter. For example, the one or more metal finger structures 410 may extend from one or more of the further terminals 170 to a point inside the perimeter of the first power terminal 123. Furthermore, the metal finger structures 410 are arranged on the first side 121 of the power semiconductor chip 120 beneath the Cu layer 150. The one or more metal finger structures 410 may, for example, be configured for voltage sensing and / or temperature sensing and / or may be configured as electrical contacts between a gate terminal and the first power terminal 123.

[0037] According to one example, the power semiconductor device 400 includes the polymer ring 180'. In this case, the polymer ring 180' may have an opening at the metal finger structures 180'.

[0038] The metal finger structures may comprise or consist of any suitable metal. According to one example, the metal finger structures comprise or consist of Al, Cu, Ti, or W.

[0039] Fig. 5A to Fig. 5D show the power semiconductor device 100 at various stages of fabrication according to an exemplary method of fabricating a power semiconductor device.

[0040] As in Fig. 5A, the power semiconductor chip 120 is provided. A Cu layer is deposited on the first side 121 of the power semiconductor chip 120. According to one example, forming the Cu layer 150 of the first power terminal 123 also includes patterning the deposited Cu layer. According to one example, the deposited Cu layer may also be patterned to provide the further terminal(s) 170.

[0041] As in Fig. As shown in Figure 5B, a cap layer is deposited on the first side 121 of the power semiconductor chip 120, in particular on the Cu layer 150. Furthermore, a patterning process is performed on the deposited cap layer to form the patterned cap layer 140. The cap layer 140 may, for example, consist of Al2O3 and / or SiO2, and the deposition of the cap layer may, for example, comprise using a suitable conformal coating process such as ALD or CVD. Patterning the deposited cap layer may, for example, comprise suitable photolithography processes and etching processes followed by resist stripping and cleaning processes. The etching process may, for example, be performed using hydrofluoric acid.

[0042] According to one example, the capping layer is deposited such that the structured capping layer 140 has a thickness in the range of approximately 4 nm to approximately 50 nm, wherein the thickness is measured perpendicular to the first side 121 of the power semiconductor chip 120. The lower limit of this range may also be approximately 5 nm, approximately 6 nm, approximately 7 nm, approximately 8 nm, or approximately 10 nm, and the upper limit may also be approximately 40 nm, approximately 30 nm, approximately 20 nm, or approximately 15 nm. According to one example, the structured capping layer 140 has a minimum width or a maximum width w in the range of approximately 200 µm to approximately 500 µm around the circumference of the first power terminal 123, wherein the width w is measured parallel to the first side 121 of the power semiconductor chip 120. The lower limit of this range may also be about 250 µm, about 300 µm or about 350 µm and the upper limit may also be about 450 µm or about 400 µm.

[0043] As in Fig. 5C, the die carrier 110 is provided, and the power semiconductor chip 120 is coupled to the die carrier 110. This may, for example, include soldering the second side 122 of the power semiconductor chip 120 to the die carrier 110. Instead of soldering, it is also possible, for example, to use a sintering process or an adhesive bonding process using conductive adhesive.

[0044] As in Fig. 5D, the contact clip 130 is provided and soldered to the Cu layer 150 of the first power terminal 123 via the solder connection 160 (compare Fig. 1B). During the soldering process, the cap layer 140 prevents solder from escaping from the first power terminal 123. The cap layer 140 may also prevent oxidation of the covered portion of the Cu layer 150. This may, for example, prevent or at least mitigate delamination problems between the Cu layer 150 and a molding compound encapsulating the power semiconductor chip 120.

[0045] According to one example, manufacturing the power semiconductor device 100 may include a further process of encapsulating the power semiconductor chip 120 with an encapsulation body. This may, for example, include molding over the power semiconductor chip 120. The cap layer 140 may be completely encapsulated by the encapsulation body. The contact clip 130 may be partially or completely encapsulated by the encapsulation body.

[0046] Fig.6 is a flowchart of an exemplary method 600 for manufacturing a power semiconductor device. The method 600 may be used, for example, to manufacture any of the power semiconductor devices 100-400.

[0047] The method 600 comprises, at 601, a process for providing a die carrier, at 602, a process for arranging a power semiconductor chip on the die carrier, wherein the power semiconductor chip comprises a first side and an opposite second side, wherein the first side faces away from the die carrier and comprises a first power terminal with a Cu layer, and wherein the second side comprises a second power terminal, at 603, a process for depositing a cap layer consisting of Al2O3 or SiO2 on the first side of the power semiconductor chip over the Cu layer, at 604, a process for structuring the cap layer such that the cap layer surrounds the first power terminal on at least one lateral side, at 605, a process for electrically coupling the second power terminal to the die carrier, and at 606, a process for soldering a contact clip to the Cu layer of the first power terminal.wherein the cover layer is designed to prevent leakage of liquid solder material from a periphery of the first power terminal., Examples

[0048] In the following, the power semiconductor device and the method for manufacturing a power semiconductor device will be further explained using specific examples.

[0049] Example 1 is a power semiconductor device comprising: a die carrier; a power semiconductor chip arranged on the die carrier, the power semiconductor chip comprising a first side and an opposite second side, the first side facing away from the die carrier and comprising a first power terminal having a Cu layer, and the second side comprising a second power terminal electrically coupled to the die carrier by a solder connection; a contact clip electrically coupled to the Cu layer of the first power terminal by a solder connection; and a structured cap layer arranged on the first side of the power semiconductor chip, the cap layer surrounding the first power terminal on at least one lateral side, the cap layer being arranged over the Cu layer, the cap layer being made of Al2O3 or SiO2.

[0050] Example 2 is the power semiconductor device of Example 1, wherein the cover layer (140) comprises an opening that is larger than the contact clip, and wherein the solder connection is arranged within the opening.

[0051] Example 3 is the power semiconductor device of Example 1, wherein the cap layer is configured to prevent leakage of liquid solder material from a periphery of the first power terminal.

[0052] Example 4 is the power semiconductor device according to Examples 1 to 3, further comprising: an imide ring arranged on the first side of the power semiconductor chip under the Cu layer and arranged along a circumference of the first power terminal.

[0053] Example 5 is the power semiconductor device according to Examples 1 to 4, wherein the opening is located within the imide ring (180').

[0054] Example 6 is the power semiconductor device of Example 4, further comprising: one or more metal finger structures extending from a point outside the perimeter of the first power terminal to a point inside the perimeter, the metal finger structures being arranged on the first side of the power semiconductor chip under the Cu layer, the imide ring having an opening at the metal finger structures.

[0055] Example 7 is the power semiconductor device according to any one of the preceding examples, further comprising: at least one control or sense terminal arranged on the first side of the power semiconductor chip laterally adjacent to the first power terminal, wherein the cap layer separates the first power terminal from the control or sense terminal.

[0056] Example 8 is the power semiconductor device according to any one of the preceding examples, wherein the cap layer has a width of at least 200 µm around the perimeter of the first power terminal, the width being measured parallel to the first side of the power semiconductor chip.

[0057] Example 9 is the power semiconductor device according to any one of the preceding examples, wherein the cap layer has a thickness in the range of 4 nm to 50 nm, the thickness being measured perpendicular to the first side of the power semiconductor chip.

[0058] Example 10 is the power semiconductor device according to any one of the preceding examples, wherein the solder joint comprises a Pb-free solder material.

[0059] Example 11 is the power semiconductor device of any preceding example, wherein the first power terminal is a source terminal, the second power terminal is a drain terminal, and the contact clip electrically connects the first power terminal to an external contact of the power semiconductor device.

[0060] Example 12 is the power semiconductor device of any preceding example, wherein the cap layer surrounds the first power terminal on all lateral sides such that the cap layer defines the perimeter of the first power terminal.

[0061] Example 13 is a method of manufacturing a power semiconductor device, the method comprising: providing a die carrier; arranging a power semiconductor chip on the die carrier, the power semiconductor chip comprising a first side and an opposite second side, the first side facing away from the die carrier and comprising a first power terminal with a Cu layer, and the second side comprising a second power terminal; depositing a cap layer consisting of Al2O3 or SiO2 on the first side of the power semiconductor chip over the Cu layer; patterning the cap layer such that the cap layer surrounds the first power terminal on at least one lateral side; electrically coupling the second power terminal to the die carrier; and soldering a contact clip to the Cu layer of the first power terminal.

[0062] Example 14 is the method of Example 13, wherein the cover layer is configured to prevent leakage of liquid solder material from a periphery of the first power terminal.

[0063] Example 15 is the method of Example 13 or 14, wherein depositing the capping layer comprises using an atomic layer deposition process or a chemical vapor deposition process to deposit the capping layer.

[0064] Example 16 is the method of examples 13 to 115, wherein patterning the cap layer comprises depositing the cap layer over the first power terminal and then at least partially removing the cap layer over the first power terminal.

[0065] Example 17 is the method of any one of Examples 13 to 16, wherein patterning the cap layer comprises using a photolithography process to remove the cap layer over specific portions of the first side of the power semiconductor chip.

[0066] Example 18 is the process of Example 15 or 16, wherein the topcoat is removed using hydrofluoric acid.

[0067] Example 19 is the method of any one of Examples 13 to 18, further comprising: disposing an imide ring on the first side of the power semiconductor chip under the Cu layer and along the perimeter of the first power terminal.

[0068] Example 20 is the method of any one of Examples 13 to 19, wherein the first side of the power semiconductor chip further comprises at least one control or sense terminal arranged laterally adjacent to the first power terminal, and wherein the cap layer is deposited over the control or sense terminal and subsequently removed over the control or sense terminal.

[0069] Example 21 is the process of any one of Examples 13 to 20, wherein the cap layer is deposited to a thickness in the range of 4 nm to 50 nm.

[0070] Example 22 is the method of any one of Examples 13 to 21, wherein the cover layer is patterned such that the cover layer surrounds the first power terminal on all lateral sides and such that the cover layer defines the perimeter of the first power terminal.

[0071] Example 23 is an apparatus comprising means for performing the method according to any one of claims 13 to 22.

[0072] While the invention has been illustrated and described with respect to one or more implementations, changes and / or modifications may be made to the illustrated examples without departing from the spirit and scope of the appended claims. In particular, with respect to the various functions performed by the above-described components or structures (assemblies, devices, circuits, systems, etc.), the terms (including any reference to a "means") used to describe such components are intended, unless otherwise indicated, to correspond to any component or structure that performs the specified function of the described component (e.g., that is functionally equivalent), even if it is not structurally equivalent to the disclosed structure that performs the function in the exemplary implementations of the invention illustrated herein.

Claims

[1] A power semiconductor device (100) comprising: a die carrier (110), a power semiconductor chip (120) arranged on the die carrier (110), wherein the power semiconductor chip (120) comprises a first side (121) and an opposite second side (122), wherein the first side (121) faces away from the die carrier (110) and comprises a first power terminal (123) with a Cu layer (150), and wherein the second side (122) comprises a second power terminal (124) electrically coupled to the die carrier (110), a contact clip (130) which is electrically coupled to the Cu layer (150) of the first power terminal (123) by a solder connection (160), and a structured cover layer (140) arranged on the first side (121) of the power semiconductor chip (120), wherein the cover layer (140) surrounds the first power terminal (123) on at least one lateral side, wherein the cover layer (140) is arranged above the Cu layer (150) and the cover layer (140) consists of Al2O3 or SiO2. [2] The power semiconductor device (300) of claim 1, wherein the cover layer (140) comprises an opening larger than the contact clip, and wherein the solder connection is disposed within the opening. [3] The power semiconductor device (300) according to claim 1 or 2, further comprising: an imide ring (180') arranged on the first side (121) of the power semiconductor chip (120) under the Cu layer (150) and arranged along a circumference of the first power terminal (123). [4] The power semiconductor device (400) of claim 3, wherein the opening is located within the imide ring (180'). [5] The power semiconductor device (400) according to claim 3 or 4, further comprising: one or more metal finger structures (410) extending from a point outside the perimeter of the first power terminal (123) to a point inside the perimeter, wherein the metal finger structures (410) are arranged on the first side (121) of the power semiconductor chip (120) under the Cu layer (150), wherein the imide ring (180') has an opening on the metal finger structures (410). [6] Power semiconductor device (100) according to one of the preceding claims, further comprising: at least one control or sensing terminal (170) arranged on the first side (121) of the power semiconductor chip (120) laterally adjacent to the first power terminal (123), wherein the cover layer (140) separates the first power terminal (123) from the control or sensing terminal (170). [7] Power semiconductor device (100) according to one of the preceding claims, wherein the cover layer (140) has a width of at least 200 µm around the circumference of the first power terminal (123), the width being measured parallel to the first side (121) of the power semiconductor chip (120). [8] Power semiconductor device (100) according to one of the preceding claims, wherein the cover layer (140) has a thickness in the range of 4 nm to 50 nm, the thickness being measured perpendicular to the first side (121) of the power semiconductor chip (120). [9] Power semiconductor device (100) according to one of the preceding claims, wherein the solder joint (160) comprises a Pb-free solder material. [10] The power semiconductor device (100) according to any one of the preceding claims, wherein the first power terminal (123) is a source terminal, the second power terminal (124) is a drain terminal, and the contact clip (130) electrically connects the first power terminal (123) to an external contact of the power semiconductor device (100). [11] Power semiconductor device (100) according to one of the preceding claims, wherein the cover layer (140) surrounds the first power terminal (123) on all lateral sides, so that the cover layer (140) defines the perimeter of the first power terminal (123). [12] A method (600) for manufacturing a power semiconductor device, the method comprising: Providing (601) a die carrier, Arranging (602) a power semiconductor chip on the die carrier, wherein the power semiconductor chip comprises a first side and an opposite second side, wherein the first side faces away from the die carrier and comprises a first power terminal with a Cu layer and wherein the second side comprises a second power terminal, Depositing (603) a cover layer consisting of Al2O3 or SiO2 on the first side of the power semiconductor chip over the Cu layer, Structuring (604) the cover layer so that the cover layer surrounds the first power terminal on at least one lateral side, electrically coupling (605) the second power terminal to the die carrier, and Soldering (606) a contact clip to the Cu layer of the first power terminal. [13] The method (600) of claim 12, wherein depositing (603) the capping layer comprises using an atomic layer deposition process or a chemical vapor deposition process to deposit the capping layer. [14] The method (600) of claim 12 or 13, wherein structuring (604) the cover layer comprises depositing the cover layer over the first power terminal and then at least partially removing the cover layer over the first power terminal. [15] The method (600) of any one of claims 12 to 14, wherein patterning (604) the capping layer comprises using a photolithography process to remove the capping layer over specific portions of the first side of the power semiconductor chip. [16] The method (600) of claim 14 or 15, wherein the cover layer is removed using hydrofluoric acid. [17] Method (600) according to one of claims 12 to 16, further comprising: Arranging an imide ring on the first side of the power semiconductor chip under the Cu layer and along the circumference of the first power terminal. [18] The method (600) of any one of claims 12 to 17, wherein the first side of the power semiconductor chip further comprises at least one control or sense terminal arranged laterally adjacent to the first power terminal, and wherein the cap layer is deposited over the control or sense terminal and subsequently removed over the control or sense terminal. [19] The method (600) according to any one of claims 12 to 18, wherein the cover layer is deposited (603) to a thickness in the range of 4 nm to 50 nm. [20] The method (600) of any one of claims 12 to 19, wherein the cover layer is structured (604) such that the cover layer surrounds the first power terminal on all lateral sides and such that the cover layer defines the perimeter of the first power terminal.