A silicon carbide power semiconductor device of trench gate structure and a method of manufacturing the same

Abstract

The application discloses a trench gate structure silicon carbide power semiconductor device and a preparation method thereof. The device adopts a trench gate structure, hexagonal boron nitride as a first gate dielectric buffer layer, alpha-Bi2SeO5 two-dimensional ferroelectric material as a second gate dielectric layer, both of which together form a silicon carbide gate dielectric layer, and TiN as a gate electrode. At the same time, the bottom of the trench gate adopts a new structure, which uses a deep P well region to wrap the corners on both sides of the bottom of the trench, and the rest of the bottom area not covered by the deep P well region is covered by a current spreading layer (CSL) for further optimizing the current spreading capability. The device prepared by the application has the advantages of excellent gate dielectric stability, outstanding withstand voltage capability, good conduction characteristics, excellent interface quality and the like, and is suitable for high-voltage and high-power power electronic application fields.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor power device technology, specifically relating to a silicon carbide power semiconductor device with a trench gate structure and its fabrication method. Background Technology

[0002] Silicon carbide (SiC), with its wide bandgap (~3.2 eV), high breakdown electric field, good thermal conductivity, and high-temperature operating characteristics, is suitable for fabricating high-voltage, high-power semiconductor devices. These properties enable SiC-based power semiconductor devices to withstand high-temperature and high-voltage operating environments. In recent years, trench gate structures have shown significant advantages over traditional planar gate structures and have been widely used in high-voltage, high-power SiC power MOSFET devices. This is because SiC power MOSFET devices with trench gate structures can shorten the channel length, enhance the gate's control over the channel, and reduce the device's specific on-resistance. They also reduce chip area and increase integration density, driving the miniaturization and high-voltage development of SiC power devices. However, trench-gate SiC power devices still have some technical shortcomings: on the one hand, traditional gate dielectric materials (such as SiO2 and Al2O3) have high interface state densities with SiC substrates, resulting in generally low gate dielectric reliability and a high risk of gate leakage, making them unsuitable for the long-term high-voltage, high-power operation requirements; on the other hand, electric field concentration is prone to occur at the bottom corners of the trench, which can easily reduce the device's withstand voltage and decrease its reliability.

[0003] To address the aforementioned issues, several optimization attempts have been undertaken within the industry. For gate dielectric reliability, researchers have employed methods such as doping modification and interface passivation to improve the performance of traditional gate dielectrics, but achieving a balance between high dielectric constant, low interface states, and high-temperature stability remains challenging. Regarding the issues of electric field concentration at the trench bottom and the imbalance between breakdown voltage and conduction characteristics, improvements are often made through methods such as rounding trench corners and injecting a P-type shielding layer beneath the trench. However, rounding trench corners is technically difficult to control, resulting in limited improvement in electric field concentration. While the P-type shielding layer can alleviate electric field distortion at the trench bottom, it increases the JFET resistance, leading to higher on-resistance. These methods fail to effectively balance breakdown voltage and conduction characteristics, offering limited optimization and failing to adequately meet the comprehensive performance requirements of high-voltage, high-power power electronics. Therefore, it is necessary to propose a new structural design to address these shortcomings. Summary of the Invention

[0004] The present invention provides a trench gate structure silicon carbide power semiconductor device and its fabrication method, which can at least solve one of the technical problems in the background art.

[0005] To achieve the above objectives, the present invention adopts the following technical solution: A silicon carbide power semiconductor device with a trench gate structure, the device comprising: a drain, a substrate, and an N-drift region sequentially stacked along a longitudinal direction; A current spreading layer is provided on the side of the N-drift region away from the substrate, and a trench is formed above the current spreading layer, with a composite gate structure provided in the trench. The composite gate structure, from the inside to the outside along the inner wall of the trench, includes: a first gate dielectric layer h-BN, a second gate dielectric layer α-Bi2SeO5, and a TiN gate electrode; A deep P-well region is provided above the current extension layer, which extends to the corner of the trench and fits seamlessly with the corner of the trench. The current spreading layer is attached to the bottom of the trench; the N+ region is formed outside the deep P-well region by ion implantation, forming a PN junction with the deep P-well region; An interlayer dielectric (ILD) of SiO2 is deposited above the gate structure of the semiconductor device to form an insulating protection on the device surface; the device is provided with a source metal electrode, which makes ohmic contact with the N+ region and the deep P well region.

[0006] Furthermore, the SiO2ILD layer described in this invention is an interlayer dielectric layer with a thickness ranging from 0.5 to 1 μm, which isolates the electrode structures on the device surface and provides support for the source and gate contact holes.

[0007] Furthermore, the current spreading layer of the present invention has a thickness ranging from 1.5 to 3.0 μm and a doping concentration ranging from 5 × 10⁻⁶. 16 ~8×10 16 cm -3 It is used to buffer and shield the electric field at the bottom of the trench gate, suppress the concentration of electric field at the bottom of the trench, protect the gate dielectric at the bottom of the trench gate, and at the same time achieve uniform current spread and reduce the on-resistance of the device.

[0008] Furthermore, the CSL current extension layer of the present invention has a depth range of 2.0–4.0 μm for the deep P-well region and a P-type doping concentration range of 1 × 10⁻⁶. 18 ~5×10 19 cm -3 There is no gap at the joint where it meets the corner of the groove.

[0009] Furthermore, in the composite gate structure of the present invention, the thickness of the first gate dielectric layer h-BN ranges from 5 to 15 nm, and the thickness of the second gate dielectric layer α-Bi2SeO5 ranges from 10 to 25 nm. The thickness of the TiN gate electrode ranges from 1.5 to 2.5 μm and is compatible with the α-Bi₂SeO₅ gate dielectric interface.

[0010] Furthermore, in this invention, the doping concentration range of the N+ region is 1 × 10⁻⁶. 20 ~5×10 20cm -3 The depth range is 0.3–0.8 μm; The substrate is an N-type silicon carbide substrate with a resistivity ranging from 0.008 to 0.015 Ω. cm; The doping concentration range of the N-drift region is 1×10⁻⁶. 15 ~5×10 15 cm -3 The thickness ranges from 5 to 15 μm.

[0011] On another front, a method for fabricating a silicon carbide power semiconductor device with a trench gate structure includes the following steps: S1. Select an N-type silicon carbide substrate; S2. An N-drift region is prepared on one side of an N-type silicon carbide substrate using chemical vapor phase epitaxy. S3. A film is formed on the surface of the N drift region by chemical vapor deposition, and then a CSL current extension layer is prepared by photolithography and plasma etching. S4. An epitaxial layer is formed on the outside of the CSL current-extended layer by epitaxial growth method; S5. A deep P-well region was prepared on the surface of the epitaxial layer by high-temperature ion implantation combined with annealing. S6. Trenches are etched in the deep P-well region using photolithography and inductively coupled plasma etching. S7. A first gate dielectric layer h-BN and a second gate dielectric layer α-Bi2SeO5 are sequentially deposited on the inner wall of the trench using atomic layer deposition to construct a stacked gate dielectric layer. S8. A TiN gate electrode is deposited inside the stacked gate dielectric layer by magnetron sputtering. S9. An N+ region was prepared outside the deep P-well region using a high-temperature ion implantation combined with annealing method. S10. A SiO2ILD layer is deposited above the gate structure using plasma-enhanced chemical vapor deposition. S11. A Ti / Al composite source metal layer is prepared on the surface of the deep P-well region by electron beam evaporation and coated on the outside of the SiO2ILD layer. S12. A drain metal layer is prepared on the back side of the substrate using electron beam evaporation to form a drain, thus completing the pre-fabrication of the semiconductor device. The pre-fabricated device is then placed in an argon protective atmosphere for heat treatment to optimize the interface states and doping activation of each layer.

[0012] In step S12, the temperature is kept at 1350℃ for 90 minutes to optimize the interface states and doping activation of each layer and eliminate the stress generated during the process.

[0013] As can be seen from the above technical solution, the beneficial effects of the present invention compared to the prior art are: 1. The present invention achieves shielding of the concentrated electric field at the trench corner and uniform current spread by a composite structure in which the deep P-well region is bonded to the trench corner and the CSL current spread layer is bonded to the bottom of the trench, thereby reducing the on-resistance of the device and effectively preventing the gate dielectric layer from breaking down and degrading due to electric field concentration and excessive stress, thus greatly improving the long-term reliability of the device and the gate dielectric withstand voltage. 2. The stacked gate dielectric structure composed of h-BN and α-Bi2SeO5, combined with TiN gate electrode, has the advantages of high dielectric constant, low leakage current and low interface state density. Compared with a single gate dielectric layer, it significantly improves gate control efficiency and reduces gate leakage capacitance and switching loss. 3. The deep P-well region optimizes the internal electric field distribution of the device, and together with the N-drift region, it further improves the reverse breakdown voltage capability of the device. At the same time, the current spreading layer (CSL) reduces the on-resistance of the device, achieving a balanced improvement in the breakdown voltage and conduction performance of the device. 4. The fabrication method of this invention is highly compatible with existing SiC-MOSFET fabrication processes and can be used for industrial production. The novel trench-gate structure silicon carbide power semiconductor device produced can be applied in the field of high-voltage and high-frequency power electronic devices. Attached Figure Description

[0014] Figure 1 This is a schematic diagram of the structure of a silicon carbide power semiconductor device with a trench gate structure disclosed in this invention. Figure 2 This is a flowchart of a method for fabricating a novel trench gate structure silicon carbide power semiconductor device disclosed in this invention; Figure 3 This is a structural diagram corresponding to step S1 in the fabrication method of a trench gate structure silicon carbide power semiconductor device disclosed in this invention; Figure 4 This is a structural diagram corresponding to step S2 in the fabrication method of a trench gate structure silicon carbide power semiconductor device disclosed in this invention; Figure 5 This is a structural diagram corresponding to step S3 in the fabrication method of a trench gate structure silicon carbide power semiconductor device disclosed in this invention; Figure 6 This is a structural diagram corresponding to step S6 in the method for fabricating a trench gate structure silicon carbide power semiconductor device disclosed in this invention. Figure 7 This is a structural diagram corresponding to step S7 in the fabrication method of a trench gate structure silicon carbide power semiconductor device disclosed in this invention. Figure 8 This is a structural diagram corresponding to step S8 in the method for fabricating a trench gate structure silicon carbide power semiconductor device disclosed in this invention. Figure 9 This is a structural diagram corresponding to step S9 in the fabrication method of a trench gate structure silicon carbide power semiconductor device disclosed in this invention. Figure 10 This is a structural diagram corresponding to step S10 in the method for fabricating a trench gate structure silicon carbide power semiconductor device disclosed in this invention. Figure 11 This is a structural diagram corresponding to step S11 in the fabrication method of a trench gate structure silicon carbide power semiconductor device disclosed in this invention; Figure 12 This is a structural diagram corresponding to step S12 in the fabrication method of a trench gate structure silicon carbide power semiconductor device disclosed in this invention; Figure 13 These are transfer characteristic curves of Embodiment 1, Embodiment 2, and the comparative example of the trench gate SiC-MOSFET described in this invention; Figure 14 These are breakdown characteristic curves of the devices in Embodiments 1 and 2 of this invention and the comparative example.

[0015] Labeling: 1. Substrate; 2. N-drift region; 3. CSL current spread layer; 4. Deep P-well region; 5. First gate dielectric layer; 6. Second gate dielectric layer; 7. TiN gate electrode; 8. N+ region; 9. IDL interlayer dielectric layer; 10. Source; 11. Drain. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments.

[0017] like Figure 1 As shown, the present invention provides a silicon carbide power semiconductor device with a trench gate structure, the semiconductor device comprising: a drain 11, a substrate 1, and an N-drift region 2 stacked sequentially along the longitudinal direction; A CSL current spreading layer 3 is provided on the side of the N drift region 2 away from the substrate. A trench is formed above the CSL current spreading layer 3, and a composite gate structure is provided in the trench. The composite gate structure includes, from the inside to the outside, the following components along the inner wall of the trench: a first gate dielectric layer 5, a second gate dielectric layer 6, and a TiN gate electrode 7. The first gate dielectric layer 5 uses h-BN material, and the second gate dielectric layer 6 uses α-Bi2SeO5 material. A deep P-well region 4 is provided above the CSL current extension layer 3. The deep P-well region 4 extends to the corner of the trench and fits seamlessly with the corner of the trench to shield the concentrated electric field at the corner of the trench. CSL current spreading layer 3 is attached to the bottom of the trench to further optimize the current spreading capability; N+ region 8 is formed outside deep P well region 4 by ion implantation process, forming a PN junction with deep P well region 4; A SiO2ILD interlayer dielectric layer 9 is deposited above the gate structure of the semiconductor device to form an insulating protection for the device surface; the device has a source 10, which makes ohmic contact with the N+ region 8 and the deep P-well region 4.

[0018] Among them, the SiO2ILD interlayer dielectric layer 9, with a thickness ranging from 0.5 to 1 μm, is used to provide insulation protection for the device surface, isolate the electrode structures on the device surface, avoid short circuits between electrodes, and provide support for the source and gate contact holes, ensuring electrode contact stability and improving the overall insulation reliability of the device.

[0019] CSL current spreading layer 3 has a thickness ranging from 1.5 to 3.0 μm and a doping concentration ranging from 5 × 10⁻⁶. 16 ~8×10 16 cm -3 It is used to buffer and shield the electric field at the bottom of the trench gate, suppress the concentration of electric field at the bottom of the trench, protect the gate dielectric at the bottom of the trench gate, and at the same time achieve uniform current spread and reduce the on-resistance of the device.

[0020] The depth of the deep P-well region 4 ranges from 2.0 to 4.0 μm, and the P-type doping concentration ranges from 1 × 10⁻⁶. 18 ~5×10 19 cm -3 There are no gaps at the joint with the corner of the trench, ensuring complete shielding of the electric field at the corner.

[0021] The thickness of the first gate dielectric layer 5 ranges from 5 to 15 nm, and the thickness of the second gate dielectric layer 6 ranges from 10 to 25 nm. The first gate dielectric layer 5 uses h-BN material, and the second gate dielectric layer 6 uses α-Bi2SeO5 material. The first gate dielectric layer 5 and the second gate dielectric layer 6 form a stacked gate dielectric structure, which has both high dielectric constant and low leakage current characteristics.

[0022] The thickness of the TiN gate electrode 7 ranges from 1.5 to 2.5 μm. The work function of this electrode matches the device channel, exhibits excellent high-temperature stability and good conductivity, and is compatible with the α-Bi2SeO5 gate dielectric interface. The process is mature and feasible, improving the gate control stability and overall device reliability.

[0023] The doping concentration range of N+ region 8 is 1×10⁸. 20 ~5×10 20 cm -3With a depth range of 0.3–0.8 μm, it is used to optimize conductive channels and reduce resistance.

[0024] Substrate 1 is an N-type silicon carbide substrate with a resistivity ranging from 0.008 to 0.015 Ω. cm; the doping concentration range of the N drift region 2 is 1×10 cm. 15 ~5×10 15 cm -3 With a thickness ranging from 5 to 15 μm, it ensures the reverse withstand voltage capability of the device.

[0025] Taking a SiC-MOSFET device with a protective structure as an example, which is applicable to conventional high-voltage power electronics scenarios, the semiconductor device includes: a drain 11, a substrate 1, and an N-drift region 2 stacked sequentially along the longitudinal direction. Among them, substrate 1 is an N-type silicon carbide substrate with a resistivity of 0.01 Ω·cm, which ensures the conduction efficiency of drain current; N-drift region 2 is located on the side of the substrate away from the drain 11, and has a doping concentration of 2 × 10⁻⁶. 15 cm -3 With a thickness of 8μm, the reverse breakdown voltage and on-resistance of the device are balanced by reasonably controlling the doping concentration and thickness. A CSL current spreading layer 3 is provided on the side of the N-drift region 2 away from the substrate 1. The CSL current spreading layer 3 is a silicon carbide-based current spreading layer with a thickness of 1.8 μm and a doping concentration of 5.5 × 10⁻⁶. 16 cm -3 ; A deep P-well region 4 is provided above the CSL current extension layer 3. Trenches are etched in the deep P-well region 4. The depth and width of the trenches are set according to conventional high voltage requirements. The CSL current spreading layer 3 is closely attached to the bottom of the trench to achieve a uniform current spreading effect and further reduce the on-resistance of the device.

[0026] A composite gate structure is provided in the trench, and the composite gate structure includes, from the inside to the outside, a first gate dielectric layer 5, a second gate dielectric layer 6, and a TiN gate electrode 7 along the inner wall of the trench. The first gate dielectric layer 5 uses h-BN material, and the second gate dielectric layer 6 uses α-Bi2SeO5 material. The thickness of the first gate dielectric layer 5 is 8nm, and the thickness of the second gate dielectric layer 6 is 15nm. h-BN and α-Bi2SeO5 form a stacked gate dielectric structure, which has both high dielectric constant and low leakage current characteristics, effectively improving the reliability of the gate dielectric. The TiN gate electrode 7 has a thickness of 1.5 μm. This electrode has excellent high-temperature stability, good conductivity, and is compatible with the α-Bi2SeO5 gate dielectric interface, which can improve the gate control stability and the overall reliability of the device.

[0027] The deep P-well region 4 above the CSL current extension layer 3 extends to the corner of the trench and fits seamlessly with the corner, with no gaps at the fit, ensuring complete shielding of the corner electric field. Among them, the depth of deep P-well region 4 is 2.5 μm, and the P-type doping concentration is 3 × 10⁻⁶. 18 cm -3 Its core function is to shield the concentrated electric field at the corner of the trench, protect the gate dielectric layer at the corner of the trench, and prevent the gate dielectric from breaking down due to the concentrated electric field.

[0028] The N+ region 8 is formed outside the deep P-well region 4 via ion implantation, forming a PN junction with the deep P-well region 4. The source 10 achieves ohmic contact with the N+ region 8 and part of the deep P-well region 4. The doping concentration of the N+ region 8 is 2 × 10⁻⁶. 20 cm -3 With a depth of 0.4μm, it can optimize the conductive channels of the device, further reduce the on-resistance, and improve the current conduction efficiency.

[0029] A SiO2 ILD interlayer dielectric layer 9 with a fixed thickness of 0.5 μm is deposited above the gate structure of the device to form an insulating protection layer. Source contact holes and gate contact holes are formed on the ILD interlayer dielectric layer 9 to ensure good contact between the source electrode 10, the TiN gate electrode 7 and the internal structure. The drain electrode 11 is located on the back side of the substrate and is formed by preparing a metal layer through evaporation to achieve good ohmic contact with the N-type silicon carbide substrate 1. The device is subjected to high-temperature annealing treatment at 1200-1500℃ to optimize the interface states and doping activation of each layer and ensure overall performance stability.

[0030] Taking a SiC-MOSFET device with a protective structure as an example 2, which is suitable for high-voltage power electronics applications, its structure is basically the same as that of Example 1, the difference being that the parameters of each layer are adapted to the high-voltage requirements, as detailed below: The substrate selected is an N-type silicon carbide substrate 1 with a resistivity of 0.01 Ω·cm; The N-drift region 2 is located on the side of substrate 1 away from the drain 11, and has a doping concentration of 1×10⁻⁶. 15 cm -3 With a thickness of 12μm, by reducing the doping concentration and increasing the thickness, the reverse breakdown voltage capability of the device is significantly improved, making it suitable for high breakdown voltage applications. A CSL current spreading layer 3 is provided on the side of the N-drift region 2 away from the substrate 1. The CSL current spreading layer 3 is a silicon carbide-based current spreading layer with a thickness of 2.8 μm and a doping concentration of 7 × 10⁻⁶. 16cm -3 Further optimize current expansion capability; A deep P-well region 4 is provided above the CSL current extension layer 3. Trenches are etched in the deep P-well region 4. The depth and width of the trenches are set according to conventional high voltage requirements. The CSL current spreading layer 3 is tightly attached to the bottom of the trench, achieving a uniform current spreading effect and further reducing the on-resistance of the device.

[0031] A composite gate structure is provided in the trench, and the composite gate structure includes, from the inside to the outside, a first gate dielectric layer 5, a second gate dielectric layer 6, and a TiN gate electrode 7 along the inner wall of the trench. The first gate dielectric layer 5 has a thickness of 12nm, and the second gate dielectric layer 6 has a thickness of 22nm, which is suitable for high voltage withstand scenarios. The first gate dielectric layer 5 uses h-BN material, and the second gate dielectric layer 6 uses α-Bi2SeO5 material. h-BN and α-Bi2SeO5 form a stacked gate dielectric structure, which has both high dielectric constant and low leakage current characteristics, effectively improving the reliability of the gate dielectric. The TiN gate electrode 7 has a thickness of 2μm, which increases the electrode thickness and ensures the reliability of gate control under high voltage conditions. The electrode has excellent high temperature stability, good conductivity, and is compatible with the α-Bi2SeO5 gate dielectric interface, which can improve the stability of gate control and the overall reliability of the device.

[0032] The deep P-well region 4 above the CSL current extension layer 3 extends to the corner of the trench and fits seamlessly with the corner, with no gaps at the fit, ensuring complete shielding of the corner electric field. The deep P-well region 4 has a depth of 3.5 μm and a P-type doping concentration of 4 × 10⁻⁶. 19 cm -3 By increasing the depth and doping concentration, the shielding effect of the electric field at the corner of the trench is enhanced, avoiding gate dielectric breakdown caused by the concentration of electric field at the corner under high voltage conditions; the trench depth and width are adapted to high voltage requirements. The N+ region 8 is formed outside the deep P-well region 4 via ion implantation, forming a PN junction with the deep P-well region 4. The source 10 achieves ohmic contact with the N+ region 8 and part of the deep P-well region 4. The doping concentration of the N+ region 8 is 4 × 10⁻⁶. 20 cm -3 With a depth of 0.6μm, it can optimize the conductive channels of the device, further reduce the on-resistance, and improve the current conduction efficiency.

[0033] A SiO2 ILD interlayer dielectric layer 9 with a fixed thickness of 1 μm is deposited above the gate structure of the device to ensure insulation protection under high voltage conditions. Source contact holes and gate contact holes are formed on the ILD interlayer dielectric layer 9 to ensure good contact between the source electrode 10, the TiN gate electrode 7 and the internal structure. The drain electrode 11 is located on the back side of the substrate 1 and is formed by preparing a metal layer through evaporation to achieve good ohmic contact with the N-type silicon carbide substrate 1. The device is subjected to high-temperature annealing treatment at 1200-1500℃ to optimize the interface states and doping activation of each layer and ensure overall performance stability.

[0034] like Figure 2 As shown, this embodiment provides a method for fabricating a silicon carbide power semiconductor device with a trench gate structure as described in Embodiment 1 using a SiC-MOSFET device with a protective structure. The specific steps are as follows: S1. Select an N-type silicon carbide substrate 1; An N-type SiC substrate with a resistivity of 0.01 Ω·cm was selected to ensure that the substrate quality met the requirements for device fabrication. Its structure is as follows. Figure 3 As shown.

[0035] S2. An N-drift region 2 is prepared on one side of an N-type silicon carbide substrate 1 using chemical vapor phase epitaxy. The epitaxial growth temperature was 1600℃, the growth time was 120 min, and the doping concentration of N drift region 2 was controlled to be 2×10⁻⁶. 15 cm -3 With a thickness of 8 μm, the uniformity and stability of the N drift region 2 are ensured. Its structure is as follows: Figure 4 As shown.

[0036] S3. A film is formed on the surface of the N drift region 2 by chemical vapor deposition, and then the CSL current extension layer 3 is prepared by photolithography and plasma etching. The process parameters in this step are as follows: deposition temperature is 1500℃, deposition time is 90 min, CSL current extension layer 3 thickness is controlled at 1.8 μm, and doping concentration is 5.5 × 10⁻⁶. 16 cm -3 To ensure a tight fit between the CSL current spreading layer 3 and the N drift region 2, achieving uniform current spreading, its structure is as follows: Figure 5 As shown.

[0037] S4. An epitaxial layer is formed on the outside of the CSL current extension layer 3 by epitaxial growth method; The epitaxial growth temperature was 1600℃ and the growth time was 80 min.

[0038] S5. A deep P-well region 4 was prepared on the surface of the epitaxial layer by high-temperature ion implantation combined with annealing. The implantation temperature for high-temperature ion implantation is 650℃, and the implantation dose is 5×10⁻⁶.18 cm -2 The annealing temperature was 1600℃, the annealing time was 45 min, the depth of the deep P-well region 4 was controlled to be 2.5 μm, and the P-type doping concentration was 3 × 10⁻⁶. 18 cm -3 .

[0039] S6. Trenches are etched in the deep P-well region 4 using photolithography and inductively coupled plasma etching. The trench depth and width are set according to the voltage withstand requirements of conventional high-voltage devices. After etching, the inner wall of the trench is polished to ensure a smooth inner wall that fits the bottom of the CSL current extension layer 3. Its structure is as follows: Figure 6 As shown.

[0040] S7. The first gate dielectric layer 5 and the second gate dielectric layer 6 are sequentially deposited on the inner wall of the trench using atomic layer deposition to construct a stacked gate dielectric layer. The first gate dielectric layer 5 uses h-BN material, and the second gate dielectric layer 6 uses α-Bi2SeO5 material. The first gate dielectric layer 5 is deposited at a temperature of 300℃ for 30 minutes, with a thickness of 8nm, to ensure uniform layer thickness and close adhesion to the inner wall of the trench. The second gate dielectric layer 6 is deposited at a temperature of 300℃ for 60 minutes, with a controlled thickness of 15 nm. Together with the first gate dielectric layer 5, it forms a stacked gate dielectric structure, as shown in the figure. Figure 7 As shown.

[0041] S8. A TiN gate electrode 7 is deposited inside the stacked gate dielectric layer by magnetron sputtering. The sputtering power was 200W, the deposition temperature was 350℃, and the deposition time was 40min. The thickness of the TiN gate electrode 7 was controlled to be 1.5μm. The trench was filled to form a complete composite gate structure, as shown in the figure. Figure 8 As shown.

[0042] S9. An N+ region 8 is fabricated outside the deep P-well region 4 of the device by high-temperature ion implantation combined with annealing. The implantation temperature for high-temperature ion implantation is 700℃, and the implantation dose is 3×10⁻⁶. 20 cm -2 The annealing temperature was 1550℃, the annealing time was 35 min, and the depth of the N+ region 8 was controlled to be 0.4 μm. Its structure is as follows: Figure 9 As shown.

[0043] S10. A SiO2ILD interlayer dielectric layer 9 is deposited above the gate structure of the device using plasma-enhanced chemical vapor deposition. During deposition, the SiH4 to O2 gas ratio was controlled at 1:3, the deposition temperature at 300℃, the deposition time at 80 min, and the thickness controlled at 0.5 μm to form an insulating protection layer. Then, source and gate contact holes were formed using photolithography and ICP etching at 250℃ for 20 min to ensure precise alignment of the contact holes with the N+ region 8 and the TiN gate electrode 7, completing the contact hole fabrication. The structure is shown below. Figure 10 As shown.

[0044] S11. A Ti / Al composite metal layer is prepared on the surface of the device as the top metal source 10 by electron beam evaporation. The evaporation temperature was 280℃, and the evaporation time was 50 min to ensure good ohmic contact between the source electrode 10, the N+ region 8, and the deep P-well region 4. Its structure is as follows: Figure 11 As shown.

[0045] S12. A metal layer is prepared on the back side of the substrate to form the drain electrode 11 by electron beam evaporation, thus completing the pre-fabrication of the semiconductor device. The pre-fabricated device is then placed in an argon protective atmosphere for heat treatment to optimize the interface states and doping activation of each layer. The evaporation temperature was 300℃, and the evaporation time was 60 min to achieve good ohmic contact between the drain 11 and the N-type silicon carbide substrate 1. The holding temperature was 1350℃, and the holding time was 90 min to optimize the interface states and doping activation of each layer and eliminate stress generated during the process. Its structure is as follows: Figure 12 As shown, the silicon carbide power semiconductor device with the trench gate structure described in Example 1 was finally obtained.

[0046] The device fabricated in this embodiment uses hexagonal boron nitride as the first gate dielectric buffer layer and α-Bi₂SeO₅ two-dimensional ferroelectric material as the second gate dielectric layer, together forming a silicon carbide gate dielectric layer, with TiN as the gate electrode. Simultaneously, a novel structure is adopted at the bottom of the trench gate, utilizing a deep P-well region to wrap the two corners of the trench bottom, while the remaining bottom area not covered by the deep P-well region is covered by a CSL current spreading layer to further optimize current spreading capability. The device fabricated by this invention has advantages such as excellent gate dielectric stability, outstanding withstand voltage, good conduction characteristics, and excellent interface quality, making it suitable for high-voltage, high-power power electronics applications.

[0047] The 1.2kV trench-gate SiC-MOSFET structure and fabrication method of this application differ from those of Examples 1 and 2. The difference lies in that this comparative example uses a typical structure and supporting fabrication process of a commercially available 1.2kV trench-gate SiC-MOSFET. To verify the technical effect of this invention, the devices of Examples 1 and 2 and this comparative example were subjected to electrical performance tests under the same test conditions. The test indicators included core electrical parameters such as the threshold voltage and breakdown voltage of the devices. The obtained test data are as follows: Figure 13 , Figure 14 As shown.

[0048] Figure 13 The graphs show the transfer characteristic curves of the devices in Embodiments 1 and 2 of the present invention and the comparative example; where the horizontal axis represents the gate-source voltage VGS and the vertical axis represents the drain current ID; the test conditions are under the driving condition of drain-source voltage VDS=10V, and it can be concluded that the embodiments of the present invention have completed the optimization of the threshold voltage compared with the comparative example.

[0049] Figure 14 The graph shows the breakdown characteristic curves of the devices in Embodiments 1, 2 and the comparative example of the present invention. The horizontal axis represents the drain-source voltage VDS and the vertical axis represents the drain current ID. The test condition is that the gate-source voltage VGS = 0V. As can be seen from the graph, the breakdown voltage of the devices in each embodiment of the present invention is significantly higher than that of the comparative example device. This indicates that the structure described in the present invention can effectively improve the phenomenon of electric field concentration inside the device and significantly improve the reverse withstand voltage capability and operational reliability of the device.

[0050] In summary, by comparing the transfer characteristics, breakdown characteristics, and specific on-resistance of Embodiments 1 and 2 with those of this application, it is clear that compared to conventional 1.2kV trench gate SiC-MOSFETs, this invention achieves improved device withstand voltage through optimized structural design and fabrication process, while maintaining the specific on-resistance within a reasonable range without a significant increase. In particular, Embodiment 1 successfully reduced the device threshold voltage from approximately 4.5V to approximately 3.9V and effectively controlled leakage current, achieving threshold voltage optimization without sacrificing device output characteristics. This fully demonstrates the innovation and practicality of this invention in device structural design.

[0051] The device fabricated in this embodiment uses hexagonal boron nitride as the first gate dielectric buffer layer and α-Bi₂SeO₅ two-dimensional ferroelectric material as the second gate dielectric layer, together forming a silicon carbide gate dielectric layer, with TiN as the gate electrode. Simultaneously, a novel structure is adopted at the bottom of the trench gate, utilizing a deep P-well region to wrap the two corners of the trench bottom, while the remaining bottom area not covered by the deep P-well region is covered by a CSL current spreading layer to further optimize current spreading capability. The device fabricated by this invention has advantages such as excellent gate dielectric stability, outstanding withstand voltage, good conduction characteristics, and excellent interface quality, making it suitable for high-voltage, high-power power electronics applications.

[0052] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0053] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0054] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A silicon carbide power semiconductor device with a trench gate structure, characterized in that, The device includes: a drain (11), a substrate (1), and an N-drift region (2) stacked sequentially along the longitudinal direction. The N-drift region (2) has a CSL current extension layer (3) on the side away from the substrate. A trench is formed above the CSL current extension layer (3), and a composite gate structure is formed in the trench. The composite gate structure includes, from the inside to the outside, the following components along the inner wall of the trench: a first gate dielectric layer (5), a second gate dielectric layer (6), and a TiN gate electrode (7). The first gate dielectric layer (5) uses h-BN material, and the second gate dielectric layer (6) uses α-Bi2SeO5 material. A deep P-well region (4) is provided above the CSL current extension layer (3), and the deep P-well region (4) extends to the corner of the trench and fits seamlessly with the corner of the trench; The CSL current extension layer (3) is attached to the bottom of the trench; the N+ region (8) is formed outside the deep P well region (4) by ion implantation process, and forms a PN junction with the deep P well region (4); A SiO2ILD interlayer dielectric layer (9) is deposited above the gate structure of the semiconductor device to form an insulating protection on the device surface; the device is provided with a source (10), and the source (10) makes ohmic contact with the N+ region (8) and the deep P well region (4).

2. The silicon carbide power semiconductor device with trench gate structure according to claim 1, characterized in that, The SiO2ILD interlayer dielectric layer (9) has a thickness ranging from 0.5 to 1 μm, which isolates the electrode structures on the device surface and provides support for the source and gate contact holes.

3. The silicon carbide power semiconductor device with a trench gate structure according to claim 2, characterized in that, The CSL current extension layer (3) has a thickness ranging from 1.5 to 3.0 μm and a doping concentration ranging from 5 × 10⁻⁶. 16 ~8×10 16 cm -3 .

4. The silicon carbide power semiconductor device with trench gate structure according to claim 1, characterized in that, The depth of the deep P-well region (4) ranges from 2.0 to 4.0 μm, and the P-type doping concentration ranges from 1 × 10⁻⁶. 18 ~5×10 19 cm -3 There is no gap at the joint where it meets the corner of the groove.

5. The silicon carbide power semiconductor device with trench gate structure according to claim 1, characterized in that: In the composite gate structure, the thickness of the first gate dielectric layer (5) ranges from 5 to 15 nm, and the thickness of the second gate dielectric layer (6) ranges from 10 to 25 nm. The thickness of the TiN gate electrode (7) ranges from 1.5 to 2.5 μm and is compatible with the α-Bi2SeO5 gate dielectric interface.

6. The silicon carbide power semiconductor device with a trench gate structure according to claim 1, characterized in that, The doping concentration range of the N+ region (8) is 1×10⁻⁶. 20 ~5×10 20 cm -3 The depth range is 0.3–0.8 μm; The substrate is an N-type silicon carbide substrate with a resistivity ranging from 0.008 to 0.015 Ω. cm; The doping concentration range of the N-drift region (2) is 1×10 15 ~5×10 15 cm -3 The thickness ranges from 5 to 15 μm.

7. A method for fabricating a silicon carbide power semiconductor device with a trench gate structure, used to fabricate a silicon carbide power semiconductor device with a trench gate structure as described in any one of claims 1-6, characterized in that, The method includes the following steps: S1. Select an N-type silicon carbide substrate (1). S2. An N-drift region (2) is prepared on one side of an N-type silicon carbide substrate (1) by chemical vapor phase epitaxy. S3. A film is formed on the surface of the N drift region (2) by chemical vapor deposition, and then a CSL current extension layer (3) is prepared by photolithography and plasma etching. S4. An epitaxial layer is formed on the outside of the CSL current-extended layer by epitaxial growth method; S5. A deep P-well region was prepared on the surface of the epitaxial layer by high-temperature ion implantation combined with annealing (4). S6. Trenches are etched in the deep P-well region (4) using photolithography and inductively coupled plasma etching. S7. A first gate dielectric layer (5) and a second gate dielectric layer (6) are sequentially deposited on the inner wall of the trench using atomic layer deposition to construct a stacked gate dielectric layer. S8. A TiN gate electrode is deposited inside the stacked gate dielectric layer by magnetron sputtering (7). S9. An N+ region (8) was prepared outside the deep P-well region (4) by high-temperature ion implantation combined with annealing. S10. A SiO2ILD interlayer dielectric layer is deposited above the gate structure using plasma-enhanced chemical vapor deposition (9). S11. A Ti / Al composite metal layer is prepared on the surface of the deep P-well region (4) by electron beam evaporation as a source electrode (10) and coated on the outside of the SiO2ILD interlayer dielectric layer (9). S12. A metal layer is prepared on the back side of the substrate to form a drain electrode (11) by electron beam evaporation to complete the pre-fabrication of the semiconductor device. The pre-fabricated device is then placed in an argon protective atmosphere for heat treatment to optimize the interface states and doping activation of each layer.

8. The method for fabricating a silicon carbide power semiconductor device with a trench gate structure according to claim 7, characterized in that, Step S12 involves holding the temperature at 1350℃ for 90 minutes to optimize the interface states and doping activation of each layer and eliminate stress generated during the process.

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