Semiconductor Device and Method for Manufacturing a Semiconductor Device

Abstract

A semiconductor device (10) comprising: an oxide insulating layer (120); an oxide semiconductor layer (140) over the oxide insulating layer (120); a gate electrode (160) above the oxide semiconductor layer (140); a gate insulating layer (150) between the oxide semiconductor layer (140) and the gate electrode (160); and a first insulating layer (165A) covering the oxide semiconductor layer (140) and the gate electrode (160), a second insulating layer (170A) over the first insulating layer (165A), wherein the first insulating layer (165A) is an oxide, and the second insulating layer (170A) is a nitride, wherein the semiconductor device (10) is subdivided into a first area (A1) that overlaps the gate electrode (160), . a second area (A2) that does not overlap the gate electrode (160) and overlaps the oxide semiconductor layer (140), and a third area (A3) that does not overlap the gate electrode (160) and the oxide semiconductor layer (140), a thickness of the gate insulating layer (150) in the first region (A1) is 200 nm or more, the gate electrode (160) touches the first insulating layer in the first area (A1), the oxide semiconductor layer (140) touches the first insulating layer in the second area (A2), a quantity of impurities contained in the oxide semiconductor layer (140) of the second region (A2) is greater than a quantity of impurities contained in the oxide semiconductor layer (140) in the first region (A1), and a quantity of impurities contained in the oxide insulating layer (120) in the third area (A3) is greater than a quantity of impurities contained in the oxide insulating layer (120) in the second area (A2), and wherein in the third area (A3), impurities are contained in the oxide insulating layer (120) and the first insulating layer, and a contamination profile in a thickness direction of the oxide insulating layer (120), the first insulating layer and the second insulating layer comprises a first peak and a second peak, wherein the first peak is located in the oxide insulating layer (120) and the second peak is located in the first insulating layer.

Description

[Technical area]

[0001] One embodiment of the present invention relates to a semiconductor device which uses an oxide semiconductor for a channel, and to a method for manufacturing the semiconductor device. [Background art]

[0002] In recent years, a semiconductor device has been developed that uses an oxide semiconductor instead of silicon semiconductors such as amorphous silicon, low-temperature polysilicon, and single-crystal silicon for one channel (e.g., patent literature 1 to 6). The semiconductor device containing such an oxide semiconductor can be fabricated with a simple structure and a low-temperature process, similar to a thin-film transistor containing amorphous silicon. It is known that the semiconductor device containing the oxide semiconductor exhibits a higher field-effect mobility than the semiconductor device containing amorphous silicon. Furthermore, patent literature 7 discloses a transistor with an oxide semiconductor film whose electrical stability is to be improved by reducing oxygen defects.The technical teaching consists of selectively creating regions with different oxygen diffusion properties within an insulating layer by introducing impurities such as phosphorus or boron. These so-called "oxygen-blocking regions" control the oxygen flow to and from the oxide semiconductor film in order to stabilize its properties. Patent reference 8 discloses a top-gate transistor with an oxide semiconductor, designed for improved reliability and stable electrical properties. The technical teaching describes a multilayer structure in which a first oxide semiconductor film forms the channel and a second oxide semiconductor film with a higher carrier density is arranged above the gate insulator. [List of citations][Patent literature] [Patent Literature 1] JP 2021-141338 A [Patent Literature 2] JP 2014-099601 A [Patent Literature 3] JP 2021-153196 A [Patent Literature 4] JP 2018-006730 A [Patent Literature 5] JP 2016-184771 A [Patent Literature 6] JP ​​2021-108405 A [Patent literature 7] US 2015 / 041 803 A1 [Patent literature 8] US 2016 / 343 868 A1 [Summary of the Invention][Technical Problem]

[0003] In oxide semiconductors, charge carriers are generated when hydrogen binds to oxygen defects. In a semiconductor device, this mechanism can be used to create a source region and a drain region, which are areas of low resistance, by forming oxygen defects in an oxide semiconductor layer and supplying hydrogen to these defects. Conversely, if hydrogen diffuses into a channel region of the oxide semiconductor layer, the channel properties of the semiconductor device deteriorate. Specifically, hydrogen diffusion into the channel region CH alters the threshold voltage in the electrical properties of the semiconductor device, leading to increased threshold voltage fluctuation and a decrease in the device's fabrication yield.Therefore, the use of an oxide layer that contains excessive amounts of oxygen and is able to trap hydrogen, as an insulating layer in contact with the oxide semiconductor layer, makes it possible to suppress the penetration of hydrogen into the channel area.

[0004] However, since the oxide layer containing excess oxygen acts as an electron trap, the reliability of the semiconductor device containing such an oxide layer is significantly reduced. To prevent this deterioration in reliability, there is therefore a need for a semiconductor device capable of supplying hydrogen to the source and drain regions of the oxide semiconductor layer and preventing hydrogen from entering the channel region of the oxide semiconductor layer.

[0005] One object of the embodiment of the present invention is to provide a semiconductor device comprising a hydrogen-trapping region that prevents hydrogen from entering a channel region. [Solution for Problems]

[0006] To solve the problem, a semiconductor device with the features of claim 1 and a method for manufacturing a semiconductor device with the features of claims 18 and 19 are provided. Advantageous embodiments are described in the dependent claims. [Brief description of the drawings] Fig. Figure 1 is a cross-sectional view showing the outline of a semiconductor device. Fig. Figure 2 is a top view showing the outline of a semiconductor device. Fig. Figure 3 is a schematic, partially enlarged cross-sectional view showing a configuration of a semiconductor device. Fig. Figure 4 is a diagram showing profiles of impurity concentrations in a first region up to a third region in a semiconductor device. Fig. Figure 5 is a flowchart showing a process for manufacturing a semiconductor device. Fig. Figure 6 is a cross-sectional view showing a method for manufacturing a semiconductor device. Fig. Figure 7 is a cross-sectional view showing a method for manufacturing a semiconductor device. Fig. Figure 8 is a cross-sectional view showing a method for manufacturing a semiconductor device. Fig. Figure 9 is a cross-sectional view showing a method for manufacturing a semiconductor device. Fig. Figure 10 is a cross-sectional view showing a method for manufacturing a semiconductor device. Fig. Figure 11 is a cross-sectional view showing a method for manufacturing a semiconductor device. Fig. Figure 12 is a cross-sectional view showing a method for manufacturing a semiconductor device. Fig. Figure 13 is a cross-sectional view showing a method for manufacturing a semiconductor device. Fig. Figure 14 is a schematic cross-sectional view illustrating a hydrogen capture function in the second and third regions of a semiconductor device. Fig. Figure 15 is a schematic cross-sectional view illustrating a hydrogen capture function in the second and third regions of a semiconductor device. Fig. Figure 16 is a schematic cross-sectional view illustrating the effects of hydrogen capture, and a diagram showing the electrical properties of a semiconductor device. Fig. Figure 17 is a cross-sectional view showing an outline of a semiconductor device according to an embodiment of the present invention. Fig. Figure 18 is a schematic, partially enlarged cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention. Fig. Figure 19 is a diagram showing profiles of impurity concentrations in a first region to a third region in a semiconductor device according to the embodiment of the present invention. Fig. Figure 20 is a flowchart showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. Fig. Figure 21 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. Fig. Figure 22 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. Fig. Figure 23 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. Fig. Figure 24 is a schematic, partially enlarged cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention. Fig. Figure 25 is a diagram showing profiles of impurity concentrations in a first region to a third region in a semiconductor device according to the embodiment of the present invention. Fig. Figure 26 is a flowchart showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. Fig. Figure 27 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. Fig. Figure 28 is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. [Description of the embodiments]

[0007] Embodiments of the present invention are described below with reference to the drawings. The following disclosure is merely an example. A configuration that a person skilled in the art can easily imagine by modifying the configuration of the embodiment accordingly, while retaining the core of the invention, is of course included within the scope of the present invention. For the sake of clarity, the drawings may be presented schematically with regard to widths, thicknesses, shapes, and the like of the respective sections in comparison to actual embodiments. However, the shape shown is merely an example and does not limit the interpretation of the present invention.In this specification and each of the drawings, the same symbols are assigned to the same components as previously described with reference to the preceding drawings, and a detailed description thereof may be omitted if necessary.

[0008] In embodiments of the present invention, a direction from a substrate to an oxide semiconductor layer is referred to as "on" or "above." Conversely, a direction from the oxide semiconductor layer to the substrate is referred to as "below" or "below." As described above, for the sake of simplicity, the expressions "above" or "below" may be used for clarification, but, for example, a vertical relationship between the substrate and the oxide semiconductor layer may be arranged in a different direction than that shown in the drawing. In the following description, for example, the expression "the oxide semiconductor layer on the substrate" describes only the vertical relationship between the substrate and the oxide semiconductor layer as described above, and other elements may be arranged between the substrate and the oxide semiconductor layer.Top or bottom refers to a stacking order in a structure where multiple layers are stacked. When expressed as a pixel electrode above a transistor, it can be a positional relationship where the transistor and the pixel electrode do not overlap in a top view. Conversely, when expressed as a pixel electrode vertically above a transistor, it signifies a positional relationship where the transistor and the pixel electrode overlap in a top view.

[0009] In this description, the terms "film" and "layer" can optionally be interchanged.

[0010] "Display device" refers to a structure configured to display an image using electro-optical layers. For example, the term "display device" may refer to a display panel containing the electro-optical layer, or it may refer to a structure in which other optical elements (e.g., polarizing element, backlight, touch panel, etc.) are attached to a display cell. The "electro-optical layer" may include a liquid crystal layer, an electroluminescent (EL) layer, an electrochromic (EC) layer, and an electrophoretic layer, provided there is no technical contradiction.Although the embodiments described later are illustrated by way of example using the liquid crystal display device with a liquid crystal layer and an organic EL display device with an organic EL layer as the display device, the structure of the present embodiment can therefore be applied to a display device including the other electro-optical layers described above.

[0011] The expressions “α includes A, B, or C”, “α includes one of A, B, and C”, and “α includes one selected from a group consisting of A, B, and C” do not preclude the case that α includes multiple combinations of A to C, unless otherwise specified. Furthermore, these expressions do not preclude the case that α contains other elements.

[0012] Furthermore, the following embodiments can be combined with each other, provided there is no technical contradiction. [1. First embodiment]

[0013] A semiconductor device according to an embodiment of the present invention is described with reference to Fig. 1, Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12, Fig. 13, Fig. 14, Fig. 15 to Fig. 16 described. For example, a semiconductor device of the embodiment described below can be used in addition to a transistor used in a display device in an integrated circuit (IC) such as a microprocessor unit (MPU) or a memory circuit. [1-1. Configuration of the semiconductor device 10]

[0014] A configuration of a semiconductor device 10 according to an embodiment of the present invention is described with reference to Fig. 1 and Fig. 2 described. Fig. Figure 1 is a cross-sectional view showing an outline of a semiconductor device according to an embodiment of the present invention. Fig. Figure 2 is a top view showing an outline of a semiconductor device according to an embodiment of the present invention.

[0015] As in Fig. In Figure 1, the semiconductor device 10 is arranged over a substrate 100. The semiconductor device 10 comprises a light-shielding layer 105, a nitride insulating layer 110 and an oxide insulating layer 120, a metal oxide layer 130, an oxide semiconductor layer 140, a gate insulating layer 150, a gate electrode 160, insulating layers 170 and 180, a source electrode 201, and a drain electrode 203. If the source electrode 201 and the drain electrode 203 are not specifically distinguished from each other, they can be referred to as the source-drain electrode 200.

[0016] The light-shielding layer 105 is arranged on the substrate 100. The nitride insulating layer 110 and the oxide insulating layer 120 are arranged on the substrate 100 and the light-shielding layer 105, respectively. The nitride insulating layer 110 covers a top surface and an end section of the light-shielding layer 105. The oxide semiconductor layer 140 is arranged on the oxide insulating layer 120. The oxide semiconductor layer 140 is structured. A portion of the oxide insulating layer 120 extends outside the pattern of the oxide semiconductor layer 140, overcoming end sections of the oxide semiconductor layer 140.

[0017] Although the present embodiment shows an exemplary configuration in which the oxide insulating layer 120 and the oxide semiconductor layer 140 are in contact with each other, the configuration is not limited to this. For example, a metal oxide layer can be arranged between the oxide insulating layer 120 and the oxide semiconductor layer 140. The metal oxide layer can be, for example, a metal oxide containing aluminum as its main component. Aluminum oxide, in particular, can be used as the metal oxide layer.

[0018] The gate electrode 160 faces the oxide semiconductor layer 140 above the oxide semiconductor layer 140. The gate insulating layer 150 is arranged between the oxide semiconductor layer 140 and the gate electrode 160. The gate insulating layer 150 is in contact with the oxide semiconductor layer 140. A surface in contact with the gate insulating layer 150, beneath the main surfaces of the oxide semiconductor layer 140, is an upper surface 141. A surface in contact with the oxide insulating layer 120, beneath the main surfaces of the oxide semiconductor layer 140, is a lower surface 142. An area between the upper surface 141 and the lower surface 142 is a side surface 143.

[0019] A pattern end of the gate insulating layer 150 is approximately the same as a pattern end of the gate electrode 160. That is, in a top view, the pattern of the gate insulating layer 150 is essentially identical to the pattern of the gate electrode 160.

[0020] Insulating layer 170 is arranged on top of the gate insulating layer 150 and the gate electrode 160. Insulating layer 170 covers the gate electrode 160. Insulating layer 170 can be referred to as the "first insulating layer". Insulating layer 180 is arranged on top of insulating layer 170. Openings 171 and 173 are arranged in insulating layers 170 and 180, extending to the oxide semiconductor layer 140. The source electrode 201 is arranged inside opening 171. The source electrode 201 is in contact with the oxide semiconductor layer 140 at the bottom of opening 171. The drain electrode 203 is arranged inside opening 173. The drain electrode 203 is in contact with the oxide semiconductor layer 140 at the bottom of opening 173.

[0021] The light-shielding layer 105 serves to block light incident on the oxide semiconductor layer 140 from one side of the substrate 100. The nitride insulating layer 110 acts as a barrier film, shielding impurities that diffuse from the substrate 100 towards the oxide semiconductor layer 140. The light-shielding layer 105 can function as the bottom gate of the semiconductor device 10. In this case, the nitride insulating layer 110 and the oxide insulating layer 120 function as gate insulating layers for the bottom gate.

[0022] The operation of the semiconductor device 10 is primarily controlled by a voltage applied to the gate electrode 160. If the light-shielding layer 105 acts as the lower gate, an auxiliary voltage is applied to the light-shielding layer 105. However, a voltage similar to that applied to the gate electrode 160 can also be applied to the light-shielding layer 105. Conversely, if the light-shielding layer 105 is used simply as a light-shielding film, no specific voltage is applied to it, and its potential can remain unaffected. Alternatively, the light-shielding layer 105 can act as an insulator.

[0023] The semiconductor device 10 is divided into a first region A1, a second region A2, and a third region A3 based on the patterns of the gate electrode 160 and the oxide semiconductor layer 140. The first region A1 is a region that overlaps the gate electrode 160 in a top view. The second region A2 is a region that does not overlap the gate electrode 160 but does overlap the oxide semiconductor layer 140 in a top view. The third region A3 is a region that does not overlap either the gate electrode 160 or the oxide semiconductor layer 140 in a top view.

[0024] In other words, in the first region A1, the oxide semiconductor layer 140 is covered by the gate insulating layer 150. Conversely, in the second region A2, the oxide semiconductor layer 140 is exposed to the gate insulating layer 150, as the gate insulating layer 150 is not located on top of the oxide semiconductor layer 140. Therefore, in the second region A2, the oxide semiconductor layer 140 is in contact with the insulating layer 170. Similarly, in the third region A3, the oxide insulating layer 120 is in contact with the insulating layer 170. In the first region A1, the gate electrode 160 is in contact with the insulating layer 170.

[0025] The thickness of the gate insulating layer 150 in the first region A1 is 200 nm or more. The thickness of the gate insulating layer 150 in the first region A1 can be 250 nm or more, or 300 nm or more.

[0026] The oxide semiconductor layer 140 is subdivided into a source region S, a drain region D, and a channel region CH based on the pattern of the gate electrode 160. The source region S and the drain region D are regions corresponding to the second region A2. The channel region CH is a region corresponding to the first region A1. In a top view, an end section in the channel region CH coincides with an end section of the gate electrode 160. The oxide semiconductor layer 140 in the channel region CH exhibits semiconductor properties. Each of the oxide semiconductor layers 140 in the source region S and the drain region D exhibits conductive properties. That is, the carrier concentrations of the oxide semiconductor layer 140 in the source region S and the drain region D are higher than the carrier concentration of the oxide semiconductor layer 140 in the channel region CH. The source electrode 201 and the drain electrode 203 contact the oxide semiconductor layer 140 in the source region S and the drain region D, respectively.in the drain region D and are electrically connected to the oxide semiconductor layer 140. The oxide semiconductor layer 140 can be a single-layer structure or a stacked structure.

[0027] Although a top-gate transistor, in which the gate electrode 160 is arranged above the oxide semiconductor layer 140, is shown as an exemplary semiconductor device 10 in the present embodiment, the semiconductor device 10 is not limited to this configuration. For example, the semiconductor device 10 can be a dual-gate transistor, as described above, in which the light-shielding layer 105 also functions as a gate in addition to the gate electrode 160. Alternatively, the semiconductor device 10 can be a bottom-gate transistor in which the light-shielding layer 105 primarily functions as a gate. The above configurations are merely embodiments, and the present invention is not limited to them.

[0028] In a Fig. In the direction D1 shown, the width of the light-shielding layer 105 is greater than the width of the gate electrode 160. Direction D1 connects the source electrode 201 and the drain electrode 203 and defines a channel length L of the semiconductor device 10. Specifically, the length in direction D1 in the region (channel region CH) where the oxide semiconductor layer 140 overlaps the gate electrode 160 is the channel length L, and the width in direction D2 in channel region CH is the channel width W. The light-shielding layer 105 and the gate electrode 160 extend in direction D2.

[0029] In Fig. Although Figure 2 shows a configuration in which the source-drain electrode 200 does not overlap the light-shielding layer 105 and the gate electrode 160 in a top view, the configuration is not limited to this configuration. For example, the source-drain electrode 200 may overlap the light-shielding layer 105 and / or the gate electrode 160 in a top view. The above configuration is merely one embodiment, and the present invention is not limited to the above configuration. [1-2. Material of each component of the semiconductor device 10].

[0030] Substrate 100 is a rigid, transmissive substrate, such as a glass substrate, a quartz substrate, a sapphire substrate, or the like. If substrate 100 needs to be flexible, a resin-containing substrate is used, such as a polyimide substrate, an acrylic substrate, a siloxane substrate, or a fluorinated resin substrate. When a resin-containing substrate is used as substrate 100, impurities can be introduced into the resin to improve the thermal resistance of substrate 100. In particular, if the semiconductor device 10 is a top-emission display, impurities that reduce the light transmittance of substrate 100 can be used, since the substrate 100 does not need to be transparent.In the event that the semiconductor device 10 is used for an integrated circuit which is not a display device, a substrate without light transmission can be used, for example a semiconductor substrate such as a silicon substrate, a silicon carbide substrate, a compound semiconductor substrate or a conductive substrate. For example, a stainless steel substrate is used as substrate 100.

[0031] Common metallic materials are used for the light-shielding layer 105, the gate electrode 160, and the source-drain electrode 200. For example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof are used. The materials described above can be used in a single layer or in a stacked layer as the light-shielding layer 105, gate electrode 160, and source-drain electrode 200. A material other than the metallic materials described above can be used as the light-shielding layer 105 if conductivity is not required. For example, a black matrix such as a black resin can be used as the light-shielding layer 105. The light-shielding layer 105 can be a single-layer structure or a stacked structure.For example, the light-shielding layer 105 can be a stacked structure consisting of a red color filter, a green color filter and a blue color filter.

[0032] Common insulating materials are used as nitride insulating layer 110, oxide insulating layer 120, and insulating layers 170 and 180. For example, inorganic insulating layers such as silicon dioxide (SiOx), silicon oxynitride (SiOxNy), aluminum oxide (AlOx), and aluminum oxynitride (AlOxNy) are used as oxide insulating layer 120 and insulating layer 180. Inorganic insulating layers such as silicon nitride (SiNx), silicon nitride oxide (SiNxOy), aluminum nitride (AlNx), and aluminum nitride oxide (AlOxOy) are used as nitride insulating layer 110 and insulating layer 170. However, an inorganic insulating layer such as silicon dioxide (SiOx), silicon oxynitride (SiOxNy), aluminum oxide (AlOx), or aluminum oxynitride (AlOxNy) can also be used as insulating layer 170. An inorganic insulating layer such as silicon nitride (SiNx), silicon nitride oxide (SiNxOy), aluminum nitride (AlNx) and aluminum nitride oxide (AINxOy) can be used as insulating layer 180.

[0033] Of the insulating layers described above, the oxygen-containing insulating layer is used as gate insulating layer 150. For example, an inorganic insulating layer such as silicon dioxide (SiOx), silicon oxynitride (SiOxNy), aluminum oxide (AlOx), and aluminum oxynitride (AlOxNy) is used as gate insulating layer 150.

[0034] The oxide insulating layer 120 is an insulating layer that releases oxygen through heat treatment. That is, the oxide insulating layer 120 is an oxide insulating layer containing excess oxygen. For example, the temperature of the heat treatment at which the oxide insulating layer 120 releases oxygen is 600 °C or less, 500 °C or less, 450 °C or less, or 400 °C or less. This means that, for example, the oxide insulating layer 120 releases oxygen at a heat treatment temperature performed in a manufacturing process of the semiconductor device 10 when a glass substrate is used as the substrate 100. Similarly, an insulating layer with the function of releasing oxygen through heat treatment can be used for at least one of the insulating layers 170 and 180.

[0035] A few-defect insulating layers are used as the gate insulating layer 150. For example, when comparing the oxygen composition ratio in the gate insulating layer 150 with the oxygen composition ratio in an insulating layer (hereinafter referred to as "another insulating layer") that has a similar composition to the gate insulating layer 150, the oxygen composition ratio in the gate insulating layer 150 is closer to the stoichiometric ratio with respect to the insulating layer than the oxygen composition ratio in that other insulating layer.In particular, when silicon dioxide (SiOx) is used for both the gate insulating layer 150 and the insulating layer 180, the oxygen composition in the silicon dioxide used as the gate insulating layer 150 is close to the stoichiometric ratio of silicon dioxide compared to the oxygen composition in the silicon dioxide used as the insulating layer 180. For example, a layer can be used as the gate insulating layer 150 in which no defects are observed when evaluated by electron spin resonance (ESR).

[0036] The SiOxNy and AlOxNy compounds described above are a silicon compound and an aluminum compound, respectively, containing nitrogen (N) in a ratio (x > y) that is smaller than that of oxygen (O). SiNxOy and AINxOy are a silicon compound and an aluminum compound, respectively, containing oxygen in a ratio (x > y) that is smaller than that of nitrogen.

[0037] A metal oxide with semiconductor properties can be used as the oxide semiconductor layer 140.

[0038] Although a detailed procedure for the fabrication of the oxide semiconductor layer 140 will be described later, the oxide semiconductor layer 140 can be formed using a sputtering process. The composition of the oxide semiconductor layer 140 formed by the sputtering process depends on the composition of a sputtering target. In this case, the composition of the metal element of the oxide semiconductor layer 140 can be specified based on the composition of the metal element of the sputtering target.

[0039] In the case where the oxide semiconductor layer 140 has a polycrystalline structure, its composition can be specified using X-ray diffraction (XRD). Specifically, the composition of the metal element in the oxide semiconductor layer can be determined based on the crystal structure and lattice constant of the oxide semiconductor layer obtained by the XRD method. Furthermore, the composition of the metal element in the oxide semiconductor layer 140 can also be identified using X-ray fluorescence analysis, electron probe microanalyzer (EPMA) analysis, or similar methods. However, the oxygen element present in the oxide semiconductor layer 140 may not be specified by these methods, as the oxygen element varies depending on the sputtering process conditions.

[0040] As described above, the oxide semiconductor layer 140 can have an amorphous structure or a polycrystalline structure.

[0041] As described above, in the case where a metal oxide layer is arranged between the oxide insulating layer 120 and the oxide semiconductor layer 140, a metal oxide containing aluminum as its main component is used as the metal oxide layer. For example, an inorganic insulating layer such as aluminum oxide (AlOx), aluminum oxynitride (AlOxNy), and aluminum nitride oxide (AlOxOy) is used as the metal oxide layer. The phrase "metal oxide layer containing aluminum as its main component" means that the proportion of aluminum in the metal oxide layer is 1% or more of the total amount of the metal oxide layer. The proportion of aluminum in the metal oxide layer can be 5% or more and 70% or less, 10% or more and 60% or less, or 30% or more and 50% or less of the total amount of the metal oxide layer. The ratio can be a mass ratio or a weight ratio. [1-3. Configuration of the hydrogen-capturing region]

[0042] A hydrogen-trapping region is formed in the oxide insulating layer 120. Therefore, a configuration of the hydrogen-trapping region formed in the oxide insulating layer 120 is determined with reference to Fig. 3 and Fig. 4 described. Fig. Figure 3 is a schematic, partially enlarged cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention. In particular, it shows Fig. 3 an enlarged cross-sectional view of an area P in Fig. 1. Although the in Fig. Since the area P shown in Figure 3 is located near the drain area D, the area near the source area S also has the same configuration as area P.

[0043] The oxide insulating layer 120 is divided into the first region A1, the second region A2, and the third region A3. The insulating oxide layer 120 in each region is described as insulating oxide layer 120-1, 120-2, and 120-3, respectively. Oxide insulating layers 120-1 and 120-2 are in contact with the oxide semiconductor layer 140. Oxide insulating layer 120-3 is in contact with the insulating layer 170.

[0044] Although details will be described later, the oxide semiconductor layer 140 is formed in the source region S and the drain region D by ion implantation of impurities using the gate electrode 160 as a mask. Examples of impurities used include boron (B), phosphorus (P), argon (Ar), nitrogen (N), or the like. This ion implantation creates oxygen defects in the oxide semiconductor layer 140 in the source region S and the drain region D. The resistance of the oxide semiconductor layer 140 in the source region S and the drain region D is reduced by the trapping of hydrogen in the oxygen defects created. Since, for example, a silicon nitride layer contains more hydrogen than a silicon oxide layer, using silicon nitride as an insulating layer 170 can reduce the resistance of the oxide semiconductor layer 140 in the source region S and the drain region D.

[0045] Although details will be described later, the ion implantation is performed in a state where the gate insulating layer 150 is removed by etching, exposing the oxide semiconductor layer 140 in the second region A2 and the oxide insulating layer 120 in the third region A3. In the second region A2, the ion-implanted impurities reach the oxide insulating layer 120 via the oxide semiconductor layer 140. Similarly, in the third region A3, the ion-implanted impurities are introduced into the exposed oxide insulating layer 120. Therefore, a dangling bond defect DB is created in the oxide insulating layer 120 in both the second region A2 and the third region A3.

[0046] In the first region A1, impurities are ion-implanted using the gate electrode 160 as a mask. Therefore, no impurities are implanted into the gate insulating layer 150 and the oxide insulating layer 120-1 in the first region A1, and the dangling bond defect DB is not generated in these insulating layers. On the other hand, as described above, the dangling bond defect DB is generated in the oxide insulating layers 120-2 and 120-3. For example, if silicon oxide is used as the oxide insulating layer 120, the silicon dangling bond defect DB is formed in the oxide insulating layers 120-2 and 120-3.

[0047] The dangling bond defect DB formed in the oxide insulating layer 120 traps hydrogen. That is, in the semiconductor device 10, the oxide insulating layers 120-2 and 120-3 act as a hydrogen-trapping region. Therefore, for example, hydrogen that diffuses from the insulating layer 170 at the time of deposition is trapped in the dangling bond defect DB in the oxide insulating layers 120-2 and 120-3, thus preventing hydrogen from penetrating the oxide semiconductor layer 140 in the channel region CH. Therefore, in the state after the formation of the insulating layer 170, the hydrogen concentrations in the oxide insulating layers 120-2 and 120-3 are higher than the hydrogen concentration in the oxide insulating layer 120-1.

[0048] Since the dangling bond defect DB is formed by ion implantation, the oxide insulating layers 120-2 and 120-3 contain impurities introduced by ion implantation. The distribution of the amount of dangling bond defects DB formed in the oxide insulating layers 120-2 and 120-3 corresponds to a concentration profile of the impurity contained therein. That is, the position and amount of the dangling bond defect DB can be adjusted by adapting the impurity profile obtained through ion implantation.

[0049] Although details will be described later, it is effective to form the dangling bond defect DB in the oxide insulating layer 120 to suppress the occurrence of an abnormality in the electrical properties of the semiconductor device 10 due to the penetration of hydrogen into the oxide semiconductor layer in the channel region CH. Therefore, impurities must be implanted to reach the oxide insulating layer 120.

[0050] For example, in the case of the semiconductor device where the gate insulating layer 150 must withstand high voltages, the thickness of the gate insulating layer 150 must be 200 nm or more. On the other hand, if the impurity is caused to reach the oxide insulating layer 120 by ion implantation, the thickness of the insulating layer through which the impurity passes by ion implantation must be less than 150 nm, due to a limitation imposed by the accelerating voltage of the ion implantation device. Although details will be described later, to meet these requirements, in the present embodiment, impurities are ion-implanted in a state in which the gate insulating layer 150 is removed from the oxide semiconductor layer 140 in the second region A2 and from the oxide insulating layer 120 in the third region A3.

[0051] Fig. Figure 4 is a diagram showing profiles of defect concentrations in the first region A1 to the third region A3 in a semiconductor device according to the embodiment of the present invention. The vertical axes of each of the three in Fig. 4 indicates the concentration of impurities per unit volume (concentration [ / cm³]). 3 The horizontal axes indicate the layer name in the depth direction. "UC" on the horizontal axis corresponds to the oxide insulating layer 120 and the nitride insulating layer 110. "OS" corresponds to the oxide semiconductor layer 140. "GI" corresponds to the gate insulating layer 150. "GL" corresponds to the gate electrode 160. "PAS" corresponds to the insulating layer 170.

[0052] As in Fig. As shown in Figure 4, the impurity concentration profile in the first region A1 exhibits a peak at the gate electrode 160 (GL). Therefore, in the depth direction of the first region A1, the amount of impurities contained at a predetermined position of the gate electrode 160 is greater than any amount of impurities contained at a predetermined position of the gate insulating layer 150, at a predetermined position of the oxide semiconductor layer 140, and at a predetermined position of the oxide insulating layer 120. The "depth direction" above refers to the thickness direction of each layer. The metal material exhibits a high stopping effect against impurities introduced by ion implantation. When the metal material is used as the gate electrode 160, the impurities are blocked by the gate electrode 160 and do not reach the gate insulating layer 150 (GI).Therefore, the dangling bond defect DB is not formed in the gate insulating layer 150 and the oxide insulating layer 120 in the first region A1 due to the introduction of impurities. However, the impurities can reach the gate insulating layer 150 as long as the electrical properties of the semiconductor device 10 are not affected.

[0053] In the second region A2, the impurity concentration profile exhibits peaks in the oxide semiconductor layer 140 (OS). Therefore, at the depth of the second region A2, the amount of impurities contained in the predetermined position of the oxide semiconductor layer 140 is greater than the amount of impurities contained in the predetermined position of the oxide insulating layer 120. Since the purpose of introducing impurities is to reduce the resistance of the oxide semiconductor layer 140 in the source region S and the drain region D, the ion implantation condition is adjusted to exhibit the concentration profile described above. The amount of impurities contained in the oxide semiconductor layer 140 in the second region A2 is greater than the amount of impurities contained in the oxide semiconductor layer 140 in the first region A1.Likewise, the amount of impurities contained in the oxide insulating layer 120 (UC) in the second area A2 is greater than the amount of impurities contained in the oxide insulating layer 120 in the first area A1.

[0054] As described above, impurities are also introduced into the oxide insulating layer 120 in the second area A2. Therefore, the dangling bond defect DB, which is associated with the introduction of impurities, is formed in the oxide insulating layer 120-2 (see Fig. 3).

[0055] In the third region A3, the impurity concentration profile exhibits a peak in the oxide insulating layer 120. In the third region A3, the oxide semiconductor layer 140 is not located on top of the oxide insulating layer 120. This results in the peak of the concentration profile being located in the oxide insulating layer 120 in the third region A3, instead of in the oxide semiconductor layer 140 in the second region A2. That is, the amount of impurities contained in the oxide insulating layer 120 in the third region A3 is greater than the amount of impurities contained in the oxide insulating layer 120 in the first region A1, and greater than the amount of impurities contained in the oxide insulating layer 120 in the second region A2.

[0056] According to the impurity concentration profile described above, the dangling bond defect DB associated with the introduction of the impurity is formed in the oxide insulating layer 120-3 (see Fig. 3) Since, as described above, the peak of the concentration profile in the oxide insulating layer 120 is present in the third region A3, the amount of free bond defect DB present in the oxide insulating layer 120 in the third region A3 is greater than the amount of dangling bond defect DB present in the oxide insulating layer 120 in the second region A2. Therefore, the oxide insulating layer 120 in the third region A3 can trap more hydrogen than the oxide insulating layer 120 in the second region A2.

[0057] In the present embodiment, in the depth direction of the third region A3, the amount of impurities contained at a predetermined position in the oxide insulating layer 120 is 1 × 10 16 / cm 3or more, 1 × 10 17 / cm 3 or more or 1 × 10 18 / cm 3 or more. The predetermined position can be a peak position of the concentration profile or a position corresponding to an interface between the oxide insulating layer 120 and the insulating layer 170. Alternatively, the predetermined position can be a position shifted by a predetermined depth from a position corresponding to the interface in the direction of the oxide insulating layer 120.

[0058] In the present embodiment, a configuration is illustrated in which the amount of impurities contained in the oxide insulating layer 120 in the third region A3 is greater than the amount of impurities contained in the oxide insulating layer 120 in the second region A2; however, the configuration is not limited to this configuration. Similarly, while the present embodiment illustrates an exemplary configuration in which the peak of the impurity concentration profile is present in the third region A3 within the oxide insulating layer 120, the configuration is not limited to this configuration. For example, in the depth direction of the third region A3, the concentration of impurities may be highest at the upper surface of the oxide insulating layer 120 (the surface corresponding to the interface between the oxide insulating layer 120 and the insulating layer 170).

[0059] Referring to Fig. In section 2, channel region CH corresponds to the first region A1, source region S and drain region D correspond to the second region A2, and regions other than channel region CH, source region S, and drain region D correspond to the third region CH. That is, channel region CH is located between the second region A2 and surrounded by the third region A3. Therefore, for example, hydrogen diffusing from insulating layer 170 at the time of deposition is trapped by the dangling bond defect DB, which is formed in the oxide insulating layer 120 located in the second region A2 and the third region A3 surrounding channel region CH. This makes it possible to suppress the penetration of hydrogen into the oxide semiconductor layer 140 in channel region CH. [1-4. Method for manufacturing a semiconductor device 10]

[0060] A method for manufacturing a semiconductor device 10 according to an embodiment of the present invention is described with reference to Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12 to Fig. 13 described. Fig. Figure 5 is a flowchart showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12 to Fig. Figure 13 shows cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0061] As in Fig. 5 and Fig. As shown in Figure 6, the light shield 105 is formed on the substrate 100 as a bottom gate, and the nitride insulating layer 110 and the oxide insulating layer 120 are formed on the light shield 105 (“Formation of the insulating layer / light shield layer” in step S1001 of Figure 6). Fig. 5) Silicon nitride is formed as the nitride insulating layer 110, for example. Silicon oxide is formed as the oxide insulating layer 120, for example. The nitride insulating layers 110 and the oxide insulating layer 120 are deposited by a CVD (Chemical Vapor Deposition) process. For example, the thickness of the nitride insulating layer 110 is 50 nm or more and 500 nm or less, or 150 nm or more and 300 nm or less. The thickness of the oxide insulating layer 120 is 50 nm or more and 500 nm or less, or 150 nm or more and 300 nm or less.

[0062] By using silicon nitride as the nitride insulating layer 110, the nitride insulating layer 110 can block impurities that diffuse, for example, from the substrate 100 towards the oxide semiconductor layer 140. The silicon oxide used as the oxide insulating layer 120 is silicon oxide with the physical property of releasing oxygen upon heat treatment.

[0063] As in Fig. 5 and Fig. As shown in Figure 7, the oxide semiconductor layer 140 is formed on the oxide insulating layer 120 (“OS film formation” in step S1002 of Fig. 5) In this process, the gate insulating layer 140 is formed over the substrate 100. The oxide semiconductor layer 140 is deposited by a sputtering process or an atomic layer deposition (ALD) process.

[0064] In the case where the metal oxide layer, which contains aluminium as the main component, is arranged between the oxide insulating layer 120 and the oxide semiconductor layer 140, the metal oxide layer is also deposited by the sputtering process or an atomic layer deposition process in the same procedure as described above.

[0065] For example, the thickness of the oxide semiconductor layer 140 is 10 nm or more and 100 nm or less, 15 nm or more and 70 nm or less, or 20 nm or more and 40 nm or less. In the present embodiment, the thickness of the oxide semiconductor layer 140 is 30 nm. The oxide semiconductor layer 140 is amorphous before the heat treatment (OS annealing) described later.

[0066] For example, if the oxide semiconductor layer 140 is deposited by the sputtering process, the oxide semiconductor layer 140 is deposited in a state in which the temperature of the object to be deposited (the substrate 100 and the structures formed on it) is controlled.

[0067] When deposition on the object to be deposited is carried out by sputtering, ions generated in the plasma and atoms reflected from a sputtering target collide with the object. Therefore, the temperature of the object to be deposited increases during the deposition process. To control the temperature of the object to be deposited, as described above, deposition can be performed while the object is being cooled. For example, the object to be deposited can be cooled from a surface opposite a surface to be deposited, so that the temperature of the deposited surface of the object to be deposited (hereafter referred to as the "deposition temperature") is 100°C or less, 70°C or less, 50°C or less, or 30°C or less.An oxygen partial pressure under the deposition conditions of the oxide semiconductor layer 140 is 2% or more and 20% or less, 3% or more and 15% or less, or 3% or more and 10% or less.

[0068] As in Fig. 5 and Fig. As shown in Figure 8, a pattern of the oxide semiconductor layer 140 is formed (“Forming the OS pattern” in step S1003 of Figure 8). Fig. 5) Although not shown, a resist mask is formed on the oxide semiconductor layer 140, and the oxide semiconductor layer 140 is etched using the resist mask. Wet etching or dry etching can be used to etch the oxide semiconductor layer 140. Wet etching can involve etching using an acidic etchant. Examples of suitable etchants include oxalic acid, PAN, sulfuric acid, hydrogen peroxide, or hydrofluoric acid.

[0069] The pattern of the oxide semiconductor layer 140 is formed and then a heat treatment (OS annealing) is carried out on the oxide semiconductor layer 140 (“annealing OS” in step S1004 of Fig. 5) In OS annealing, the oxide semiconductor layer 140 is held at a predetermined target temperature for a predetermined time. The predetermined target temperature is 300 °C or more and 500 °C or less, or 350 °C or more and 450 °C or less. The holding time at the target temperature is 15 minutes or more and 120 minutes or less, or 30 minutes or more and 60 minutes or less. In the present embodiment, the oxide semiconductor layer 140 is crystallized by OS annealing. However, crystallization of the oxide semiconductor layer 140 by OS annealing is not strictly necessary.

[0070] As in Fig. 5 and Fig. As shown in Figure 9, the gate insulating layer 150 is deposited on the oxide semiconductor layer 140 (“formation of GI” in step S1005 of Fig. 5) For example, silicon dioxide is formed as the gate insulating layer 150. The gate insulating layer 150 is formed by the CVD process. For example, the gate insulating layer 150 can be deposited at a deposition temperature of 350 °C or higher to form an insulating layer with few defects, as described above as the gate insulating layer 150. For example, the thickness of the gate insulating layer 150 is 200 nm or more and 500 nm or less, 200 nm or more and 400 nm or less, or 250 nm or more and 350 nm or less. An oxygen implantation process can be performed on the upper part of the gate insulating layer 150 after the gate insulating layer 150 has been deposited.

[0071] A heat treatment (oxidation annealing) to supply oxygen to the oxide semiconductor layer 140 is carried out in a state in which the gate insulating layer 150 is deposited on the oxide semiconductor layer 140 and the metal oxide layer 190 is deposited on the gate insulating layer 150 (“annealing to oxidation” in step S1006 of Fig. 5) During the process from the deposition of the oxide semiconductor layer 140 to the deposition of the gate insulating layer 150 on the oxide semiconductor layer 140, a large number of oxygen defects 140 occur on the top surface 141 and the side surface 143 of the oxide semiconductor layer. Oxygen released from the oxide insulating layers 120 and the gate insulating layer 150 is supplied to the oxide semiconductor layer 140 by the oxidation annealing described above, and the oxygen defects are repaired. If the process of implanting oxygen into the gate insulating layer 150 is not carried out, the oxidation annealing can be performed in a state where an insulating layer can release oxygen through heat treatment.

[0072] To increase the amount of oxygen supplied from the gate insulating layer 150 to the oxide semiconductor layer 140, a metal oxide layer containing aluminum as its main component can be formed on the gate insulating layer 150 by sputtering. Oxidation annealing can then be performed in this state. The use of aluminum oxide, which has a high barrier property, as the metal oxide layer prevents the oxygen, which is implanted into the gate insulating layer 150 during oxidation annealing, from diffusing outwards. The oxygen implanted into the gate insulating layer 150 is efficiently supplied to the oxide semiconductor layer 140 through the formation of the metal oxide layer and subsequent oxidation annealing.

[0073] As in Fig. 5 and Fig. As shown in Figure 10, the gate electrode 160 is deposited and the gate electrode 160 and the gate insulating layer 150 are integrally etched (“Forming GE and Etching GI” in step S1007 of Figure 1000). Fig. 5) The gate electrode 160 is deposited by sputtering or atomic layer deposition and patterned by photolithography. Both the gate electrode 160 and the gate insulating layer 150 are patterned by photolithography. The gate electrode 160 and the gate insulating layer 150 can be etched in the same process (under the same conditions), or each can be etched in a different process (under different conditions). That is, the etching of the gate insulating layer 150 can be performed by over-etching within the etching process for the gate electrode 160, or by etching that differs from the etching process for the gate electrode 160, using the gate electrode 160 as a mask after etching the gate electrode 160.

[0074] As in Fig. As shown in Figure 11, the oxide semiconductor layer 140 in the second region A2 is exposed, and the oxide insulating layer 120 in the third region A3 is exposed by structuring the gate electrode 160 and the gate insulating layer 150. In this state, impurities are ion-implanted into the exposed oxide insulating layer 120 and the exposed oxide semiconductor layer 140 (“implantation of foreign ions” in step S1008 of Figure 11). Fig. 5) In particular, impurities are implanted into the exposed oxide insulating layer 120 and the exposed oxide semiconductor layer 140 using the gate electrode 160 as a mask.

[0075] For example, elements such as boron (B), phosphorus (P), argon (Ar), or nitrogen (N) are implanted into the oxide insulating layer 120 and the oxide semiconductor layer 140 by ion implantation. In the oxide semiconductor layer 140, in the second region A2, which does not overlap the gate electrode 160, oxygen defects are created by ion implantation. The resistance of the oxide semiconductor layer 140 in the second region A2 is reduced by the trapping of hydrogen in the created oxygen defects. Conversely, no impurities are implanted in the oxide semiconductor layer 140 in the first region A1, which overlaps the gate electrode 160, so no oxygen defects are created and the resistance in the first region A1 is not reduced. Through the above steps, the channel region CH is formed in the oxide semiconductor layer 140 in the first region A1, and the source region S and the drain region D are formed in the oxide semiconductor layer 140 in the second region A2.

[0076] The dangling bond defect DB is generated in the oxide insulating layer 120 in the second region A2 and in the third region A3 by ion implantation. The location and extent of the dangling bond defect DB can be controlled by adjusting the process parameters (e.g., dose, acceleration voltage, plasma power, etc.) of the ion implantation. For example, the dose is 1 × 10 14 / cm 2 or more, 5 × 10 14 / cm 2 or more or 1 x 10 15 / cm 2 or more. For example, the accelerating voltage is greater than 10 keV, 15 keV or more, or 20 keV or more.

[0077] As in Fig. 5 and Fig. As shown in Figure 12, the insulating layers 170 and 180 are deposited as interlayer films on the gate insulating layer 150 and the gate electrode 160 (interlayer film formation in step S1009 of Figure 12). Fig. 5) The insulating layers 170 and 180 are deposited by the CVD process. For example, a silicon nitride layer is formed as insulating layer 170 and a silicon oxide layer as insulating layer 180. The materials used as insulating layers 170 and 180 are not limited to those mentioned above. The thickness of insulating layer 170 is 50 nm or more and 500 nm or less. The thickness of insulating layer 180 is 50 nm or more and 500 nm or less.

[0078] As in Fig. 5 and Fig. As shown in Figure 12, the openings 171 and 173 are formed in the insulating layers 170 and 180 (“opening of the contact hole” in step S1010 of Figure 12). Fig. 5) The oxide semiconductor layer 140 in the source region S is exposed through the opening 171. The oxide semiconductor layer 140 in the drain region D is exposed through the opening 173. The semiconductor device 10 according to Fig. 1 is completed by forming the source-drain electrode 200 on the oxide semiconductor layer 140 exposed through the openings 171 and 173 and on the insulating layer 180 (“SD Formation” in step S1011 of Fig. 5). [1-5. Hydrogen capture in Dangling Bond Defect DB]

[0079] Referring to Fig. 4, Fig. 5 and Fig. 14. In step S1008, the ion implantation also implants impurities into the oxide insulating layer 120 (UC) in the second region A2 and the third region A3. This ion implantation of impurities creates the dangling bond defect DB in the oxide insulating layer 120 in the second region A2 and the third region A3. In other words, the oxide insulating layer 120 contains impurities such as boron (B), phosphorus (P), argon (Ar), or nitrogen (N). In the present embodiment, as described above, the amount of impurities contained in the oxide insulating layer 120 in the third region A3 is greater than the amount of impurities contained in the oxide insulating layer 120 in the second region A2. Fig. Figure 14 schematically shows the Dangling Bond defect DB that is formed in the oxide insulating layer 120 in the case that the impurities are introduced as described above.

[0080] For the insulating layer 170 to function effectively as a barrier against impurities diffusing in from above, it is preferably a dense film with few defects. To obtain such an insulating layer 170, it must be deposited at a high temperature. For example, when the silicon nitride layer is formed as the insulating layer 170 at a high temperature, it contains a large amount of hydrogen. Consequently, a significant amount of hydrogen diffuses from the insulating layer 170 to the oxide insulating layer 120 and the oxide semiconductor layer 140 due to the deposition temperature. Therefore, hydrogen diffuses not only into the oxide semiconductor layer 140 in the source region S and the drain region D, but also into the semiconductor layer 140 in the channel region CH through the oxide insulating layer 120 if the hydrogen-trapping region is not formed within the oxide insulating layer 120.

[0081] In step S1008, in the case where the Fig. 14 Dangling bond defect DB shown in the oxide insulating layer 120 is formed, as shown in Fig. As shown in Figure 15, hydrogen H, which diffuses from the insulating layer 170 at the time of deposition, is trapped by the dangling bond defect DB (“◯” is overlaid “×”). Therefore, in step S1009, it is possible to prevent the hydrogen H, which diffuses from the insulating layer 170 at the time of deposition or after deposition, from penetrating the oxide semiconductor layer 140 in the channel region CH. Thus, a film containing a large amount of hydrogen can be used as the insulating layer 170, enabling the insulating layer 170 to be realized with a high impurity blocking function. Furthermore, the resistance of the oxide semiconductor layer 140 in the source region S and in the drain region D can be sufficiently reduced.

[0082] In the present embodiment, the amount of hydrogen H trapped in the oxide insulating layer 120 in the third region A3 is greater than the amount of hydrogen H trapped in the oxide insulating layer 120 in the second region A2, based on the distribution of the dangling bond defect DB in the oxide insulating layer 120.

[0083] Fig. Figure 16 is a schematic cross-sectional view illustrating the effects of hydrogen trapping, and a diagram showing the electrical properties of a semiconductor device according to an embodiment of the present invention. Fig. Figure 16 shows a result (300) of the investigation into the influence of the location (layer) where the hydrogen trap is formed on the electrical properties. Figure 310 in Fig. The electrical properties shown in Figure 16 illustrate the case where the hydrogen trap is not formed (relatively few) in both the oxide insulating layer 120 and the gate insulating layer 150. The in Fig. The electrical properties designated 16 by 320 are electrical properties for the case where the hydrogen trap is formed only in the gate insulating layer 150. Those designated by 330 in Fig. The electrical properties shown in Figure 16 represent the case where the hydrogen trap is formed only in the oxide insulating layer 120.

[0084] The hydrogen trap described above is not formed by ion implantation of impurities, as in the present embodiment, but by pseudo-adjustment of the film formation conditions of each insulating layer. In the configuration of Fig. 16 Silicon oxide layers are used as oxide insulating layer 120 and gate insulating layer 150. It is known that when a silicon oxide layer is formed under conditions with excessive oxygen content, the silicon oxide layer contains many hydrogen traps. That is, under the in Fig. Under the condition specified in section 16 with 320, a silicon oxide layer containing excess oxygen is used as the gate insulating layer 150. In the Fig. In state 16, labelled 330, a silicon oxide layer containing excess oxygen is used as an oxide insulating layer 120. The configuration of Fig. 16 is the same as the configuration of Fig. 1.

[0085] Like 310 in Fig. Figure 16 shows that if the hydrogen trap is not formed in both the oxide insulating layer 120 and the gate insulating layer 150, bumps in the electrical properties are confirmed. It is known that bumps in the electrical properties are generated when hydrogen penetrates the oxide semiconductor layer 140 in the channel region CH at the time of deposition of the insulating layer film 170. As in Figure 320 in Fig. As shown in Figure 16, the bumps in the electrical properties are not improved if the hydrogen trap is formed only in the gate insulating layer 150. On the other hand, as shown in Figure 330, Fig. As shown in Figure 16, if the hydrogen trap is formed only in the oxide insulating layer 120, the bumps in the electrical properties are reduced. These results demonstrate that it is essential to form the hydrogen trap in the oxide insulating layer 120 to suppress hydrogen from penetrating the oxide semiconductor layer 140 in the channel region CH at the time of deposition of the insulating layer 170.

[0086] In the present embodiment, as shown in Fig. 2, Fig. 4 and Fig. As shown in Figure 14, many dangling bond defects DB are formed in the oxide insulating layer 120 in the third region A3, which surrounds the channel region CH. According to this configuration, it is possible to suppress the penetration of hydrogen into the oxide semiconductor layer 140 in the channel region CH. This makes it possible to obtain the semiconductor device 10 with electrical properties in which the bumps are suppressed. [2. Second embodiment]

[0087] A semiconductor device according to an embodiment of the present invention is described with reference to Fig. 17, Fig. 18, Fig. 19, Fig. 20, Fig. 21, Fig. 22 to Fig. 23. A semiconductor device 10A according to the present embodiment is similar to the semiconductor device 10 according to the first embodiment, but differs from the semiconductor device 10 in that an oxide insulating layer 165A is arranged between an oxide semiconductor layer 140A and an insulating layer 170A. In the following description, a description of the same configuration as that of the semiconductor device 10 according to the first embodiment can be omitted by adding the letter “A” after the reference numerals shown in the drawings according to the first embodiment. [2-1. Configuration of the semiconductor device 10A]

[0088] A configuration of the semiconductor device 10A according to an embodiment of the present invention is described with reference to Fig. 17 described. Fig. Figure 17 is a cross-sectional view showing the outline of a semiconductor device according to an embodiment of the present invention. Since a top view of the semiconductor device 10A is the same as that shown in Figure 17, the following applies: Fig. In the top view shown in section 2, descriptions are omitted.

[0089] As in Fig. As shown in Figure 17, the semiconductor device 10A comprises, in addition to an oxide light-shielding layer 105A, the oxide insulating layer 165A, a nitride insulating layer 110A, an oxide insulating layer 120A, the oxide semiconductor layer 140A, a gate insulating layer 150A, a gate electrode 160A, insulating layers 170A and 180A, and a source-drain electrode 200A. The oxide insulating layer 165A can be referred to as the "first insulating layer." In this case, the insulating layer 170A is referred to as the "second insulating layer." As described above, a nitride insulating layer is used as insulating layer 170A.

[0090] The oxide insulating layer 165A covers the oxide semiconductor layer 140A and the gate electrode 160A. Specifically, the oxide insulating layer 165A is located between the first gate electrode 160A and the insulating layer 170A in the first region A1, between the oxide semiconductor layer 140A and the insulating layer 170A in the second region A2, and between the oxide insulating layer 120A and the insulating layer 170A in the third region A3. The thickness of the oxide insulating layer 165A is 50 nm or more, or 100 nm or more. [2-2. Configuration of the hydrogen capture region]

[0091] Fig. Figure 18 is a schematic, partially enlarged cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention. As in Fig. As shown in Figure 18, the oxide insulating layers 165A in the first region A1, in the second region A2, and in the third region A3 are described as oxide insulating layers 165A-1, 165A-2, and 165A-3, respectively. Oxide insulating layer 165A-1 is in contact with the gate electrode 160A and the insulating layer 170A. Oxide insulating layer 165A-2 is in contact with the oxide semiconductor layer 140A and the insulating layer 170A. Oxide insulating layer 165A-3 is in contact with oxide insulating layer 120A-3 and the insulating layer 170A.

[0092] Although details will be described later, in the present embodiment ion implantation is performed at least twice. Similar to the first embodiment ( Fig. 11) The first ion implantation is performed in the state where the gate insulating layer 150A has been removed by etching and the oxide semiconductor layer 140A in the second region A2 and the oxide insulating layer 120A in the third region A3 are exposed. The second ion implantation is performed in the state where the oxide insulating layer 165A has been formed after the first ion implantation. The dangling bond defect DB is created in the oxide insulating layer 120A by the first implantation as described in Fig. 3. The dangling bond defect DB is generated in the oxide insulating layer 165A by the second ion implantation, as shown in Fig. 18 shown. However, the Dangling Bond defect DB can be generated by the second ion implantation in the oxide insulating layer 120A in the second area A2 and in the third area A3.

[0093] The dangling bond defect DB formed in oxide insulating layers 120A and 165A traps hydrogen. In other words, in semiconductor device 10A, oxide insulating layers 120A-2 and 120A-3 and oxide insulating layers 165A-1, 165A-2, and 165A-3 act as the hydrogen-trapping region. Since these insulating layers function as the hydrogen-trapping region, hydrogen diffusing from insulating layer 170A, for example, at the time of deposition, is trapped in the dangling bond defect DB formed in oxide insulating layers 120A-2 and 120A-3 and oxide insulating layers 165A-1, 165A-2, and 165A-3. This makes it possible to suppress the penetration of hydrogen into the oxide semiconductor layer 140A in the channel area CH.Therefore, in the state after the formation of the insulating layer 170A, the hydrogen concentrations of the oxide insulating layers 120A-2 and 120A-3 and the oxide insulating layers 165A-1, 165A-2 and 165A-3 are higher than the hydrogen concentration of the oxide insulating layer 120A-1.

[0094] Since the dangling bond defect (DB) is formed by ion implantation, the oxide insulating layers 120A-2 and 120A-3, as well as the oxide insulating layers 165A-1, 165A-2, and 165A-3, contain impurities introduced by ion implantation. The distribution of the amounts of dangling bond defects (DB) formed in these insulating layers corresponds to the concentration profiles of the impurities contained therein. That is, the position and amount of the dangling bond defect (DB) can be adjusted by modifying the impurity profile obtained through ion implantation.

[0095] Fig. Figure 19 is a diagram showing profiles of defect concentrations in the first region A1 to the third region A3 in a semiconductor device according to an embodiment of the present invention. The vertical axis of each of the three in Fig. 19 indicates the concentration of impurities per unit volume (concentration [ / cm³]). 3 The horizontal axis indicates the layer name in the depth direction. "UC" on the horizontal axis corresponds to the oxide insulating layer 120A and the nitride insulating layer 110A. "OS" corresponds to the oxide semiconductor layer 140A. "GI" corresponds to the gate insulating layer 150A. "GL" corresponds to the gate electrode 160A. "PAS1" corresponds to the oxide insulating layer 165A. "PAS2" corresponds to the insulating layer 170A.

[0096] As in Fig. As shown in Figure 19, the impurity concentration profile in the first region A1 exhibits two peaks (P3 and P4). Peak P4 is present in the gate electrode 160A (GL). Peak P3 is present in the oxide insulating layer 165A (PAS1). This means that in the first region A1, impurities are present in both the gate electrode 160A and the oxide insulating layer 165A. Therefore, the dangling bond defect DB associated with the introduction of impurities is formed in the oxide insulating layer 165A on the gate electrode 160A. On the other hand, the insulating layer 170A (PAS2) in the first region A1 contains virtually no impurities.In the depth direction in the first region A1, the amount of impurities contained at a predetermined position of both the gate electrode 160A and the oxide insulating layer 165A is greater than the amount of impurities contained at a predetermined position of the gate insulating layer 150A, the amount of impurities contained at a predetermined position of the oxide semiconductor layer 140A, and the amount of impurities contained at a predetermined position of the oxide insulating layer 120A.

[0097] In the second region A2, the impurity concentration profile exhibits two peaks (P5 and P6). Peak P6 is present in the oxide semiconductor layer 140A (OS). The impurity concentration profile associated with peak P6 extends to the oxide insulating layer 120A (UC). Peak P5 is present in the oxide insulating layer 165A (PAS1). This means that in the second region A2, impurities are present in the oxide insulating layer 120A, the oxide semiconductor layer 140A, and the oxide insulating layer 165A. In contrast, the insulating layer 170A in the second region A2 contains virtually no impurities. In the second area A2, the amount of impurities contained in the predetermined positions of both the oxide semiconductor layer 140A and the oxide insulating layer 165A is greater than the amount of impurities contained in the predetermined position of the oxide insulating layer 120A.

[0098] As described above, in the second area A2, impurities are introduced into the oxide insulating layer 120A and the oxide insulating layer 165A. Therefore, the dangling bond defect DB associated with the introduction of impurities is formed in the oxide insulating layer 120A and the oxide insulating layer 165A.

[0099] In the third region A3, the impurity concentration profile exhibits two peaks (P1 and P2). Peak P2 is present in oxide insulating layer 120A (UC). Peak P1 is present in oxide insulating layer 165A (PAS1). This means that in the third region A3, impurities are present in both oxide insulating layer 120A and oxide insulating layer 165A. In contrast, insulating layer 170A in the third region A3 contains virtually no impurities. In the third region A3, oxide semiconductor layer 140A is not located on top of oxide insulating layer 120A. Consequently, instead of the peak of the concentration profile in oxide semiconductor layer 140A in the second region A2, peak P2 of the concentration profile is present in oxide insulating layer 120A in the third region A3.This means that the amount of impurities contained in the oxide insulating layer 120A in the third area A3 is greater than the amount of impurities contained in the oxide insulating layer 120A in the first area A1, and greater than the amount of impurities contained in the oxide insulating layer 120A in the second area A2.

[0100] According to the impurity concentration profile described above, the dangling bond defect DB associated with the introduction of impurities forms in oxide insulating layer 120A and oxide insulating layer 165A. Since, as described above, the peak P2 of the concentration profile is present in oxide insulating layer 120A in the third region A3, the amount of dangling bond defect DB present in oxide insulating layer 120A in the third region A3 is greater than the amount of dangling bond defect DB present in oxide insulating layer 120A in the second region A2. Therefore, oxide insulating layer 120A in the third region A3 can trap more hydrogen than oxide insulating layer 120A in the second region A2.

[0101] Since the peaks P1, P3, and P5 of the concentration profiles are present in the oxide insulating layer 165A from the first region A1 to the third region A3, a similar degree of dangling bond defects DB is formed in the oxide insulating layer 165A in these regions. The dangling bond defect DB present in the oxide insulating layer 165A can trap hydrogen from the insulating layer 170A. Since the thickness of the oxide insulating layer 165A is 50 nm or more, a significant effect is achieved by trapping hydrogen from the insulating layer 170A. Since the thickness of the oxide insulating layer 165A is 100 nm or more, the effects described above are even more significant.

[0102] In the present embodiment, in the depth direction in the third region A3, the amount of impurities contained at a predetermined position in the oxide insulating layer 120A is 1 × 10 16 / cm 3 or more, 1 × 10 17 / cm 3or more or 1 × 10 18 / cm 3 or more. The predetermined position can be a peak position of the density profile or a position corresponding to an interface between oxide insulating layer 120A and oxide insulating layer 165A. Similarly, in the depth direction, in the third region A3, the amount of impurities contained at a predetermined position in oxide insulating layer 165A is 1 × 10 16 / cm 3 or more, 1 × 10 17 / cm 3 or more or 1 × 10 18 / cm 3 or more. The specified position can be a position of peak P1 of the concentration profile or a position corresponding to an interface between the oxide insulating layer 165A and the insulating layer 170A. [2-3. Method for manufacturing the semiconductor device 10A]

[0103] A method for manufacturing the semiconductor device 10A according to an embodiment of the present invention is described with reference to Fig. 20, Fig. 21, Fig. 22 to Fig. 23 described. Fig. Figure 20 is a flowchart showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. Fig. 21, Fig. 22 to Fig. Figure 23 shows cross-sectional views illustrating a method for manufacturing a semiconductor device according to an embodiment of the present invention. Since steps S1001 to S1008 in Fig. 20 are the same as steps S1001 to S1008 as in Fig. 5 and Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10 to Fig. 11. Descriptions are omitted.

[0104] Similar to Fig. 11, after the impurities were ion-implanted into the exposed oxide insulating layer 120A and the exposed oxide semiconductor layer 140A, as in Fig. As shown in Figure 21, the oxide insulating layer 165A is deposited on the oxide insulating layer 120A, the oxide semiconductor layer 140A and the gate electrode 160A (“formation of the insulating layer” in step S1020 of Fig. 20). The oxide insulating layer 165A is formed by a CVD process. For example, a silicon oxide layer is formed as the oxide insulating layer 165A. However, the material used as the oxide insulating layer 165A is not limited to the above. The thickness of the oxide insulating layer 165A is 50 nm or more and 150 nm or less.

[0105] As in Fig. 20 and Fig. As shown in Figure 22, impurities are ion-implanted into the oxide insulating layer 165A (“Implanting foreign ions” in step S1021 of Figure 22). Fig. 20). In the present embodiment, impurities are implanted such that a peak in the concentration profile of the impurities is present in the oxide insulating layer 165A. For example, elements such as boron (B), phosphorus (P), argon (Ar), or nitrogen (N) are implanted into the oxide insulating layer 165A by ion implantation. The dangling bond defect DB is generated in the oxide insulating layer 165A in the first region A1 to the third region A3 by ion implantation. The position and amount of the dangling bond defect DB can be controlled by adjusting the process parameters (e.g., dose, acceleration voltage, plasma power, and the like) of the ion implantation. For example, the dose is 1 × 10 14 / cm 2 or more, 5 × 10 14 / cm 2 or more or 1 × 10 15 / cm 2or more. For example, if the element to be implanted is boron (B), the accelerating voltage is 10 keV or more and 50 keV or less. However, the peak of the concentration profile may not be present in the oxide insulating layer 165A.

[0106] As in Fig. 20 and Fig. As shown in Figure 23, the insulating layers 170A and 180A are formed on the oxide insulating layer 165A as interlayer films (“interlayer film film formation” in step S1009 of Figure 23). Fig. 20), and openings 171A and 173A are formed in the insulating layers 170A and 180A (“opening of the contact hole” in step S1010 of Fig. 20). Formation of the source-drain electrode 200A on the oxide semiconductor layer 140A and the insulating layer 180A exposed through openings 171A and 173A (“SD Formation” in step S1011 of Fig. 20) completes the in Fig. Semiconductor device 10A shown in 17.

[0107] In the present embodiment, as in Fig. 18 and Fig. As shown in Figure 19, the dangling bond defect DB is formed not only in oxide insulating layer 120A but also in oxide insulating layer 165A, thus making it possible to suppress the penetration of hydrogen into the oxide semiconductor layer 140A in the channel region CH. This allows the semiconductor device 10A to be obtained with electrical properties in which bumps are suppressed. [3. Third embodiment]

[0108] A semiconductor device according to an embodiment of the present invention is described with reference to Fig. 24, Fig. 25, Fig. 26, Fig. 27 to Fig. 28. The semiconductor device 10B according to the present embodiment is similar to the semiconductor device 10A according to the second embodiment, but differs from the semiconductor device 10A in the concentration profile of the impurity introduced by ion implantation. In the following description, a description of the same configuration as that of the semiconductor device 10A according to the second embodiment can be omitted by adding the letter “B” instead of the letter “A” after the reference numerals shown in the drawings. [3-1. Configuration of semiconductor device 10B]

[0109] One configuration of the semiconductor device 10B in the present embodiment is the same as the configuration of the one in Fig. The semiconductor device 10A shown in Figure 17 is described. However, the film quality of the oxide insulating layer 165B in semiconductor device 10B differs from that of the oxide insulating layer 165A in semiconductor device 10A. Since the configuration of semiconductor device 10B is otherwise the same as that of semiconductor device 10A, further descriptions are omitted. [3-2. Configuration of the hydrogen capture region]

[0110] Fig. Figure 24 is a schematic, partially enlarged cross-sectional view showing a configuration of a semiconductor device according to an embodiment of the present invention. Although details are described later, the dangling bond defect DB formed in oxide insulating layer 120B and oxide insulating layer 165B, which is shown in Fig. Figure 24 shows that it is produced by ion implantation after formation of the oxide insulating layer 165B.

[0111] Fig. Figure 25 is a diagram showing the impurity concentration profile from the first region A1 to the third region A3 in a semiconductor device according to the embodiment of the present invention. The vertical axis of each of the three regions in Fig. 25 indicates the concentration of impurities per unit volume (concentration [ / cm³]). 3 The horizontal axis indicates the layer name in the depth direction. "UC" on the horizontal axis corresponds to the oxide insulating layer 120B and the nitride insulating layer 110B. "OS" corresponds to an oxide semiconductor layer 140B. "GI" corresponds to a gate insulating layer 150B. "GL" corresponds to a gate electrode 160B. "PAS1" corresponds to the oxide insulating layer 165B. "PAS2" corresponds to the insulating layer 170B.

[0112] As in Fig. As shown in Figure 25, in the first region A1, impurities are contained in the gate electrode 160B (GL) and the oxide insulating layer 165B (PAS1), and the concentration profile of the impurities exhibits a peak in the gate electrode 160B. Therefore, in the depth direction of the first region A1, the amount of impurities contained in the predetermined positions of both the gate electrode 160B and the oxide insulating layer 165B is greater than the amount of impurities contained in the predetermined position of the gate insulating layer 150B, the amount of impurities contained in the predetermined position of the oxide semiconductor layer 140B, and the amount of impurities contained in the oxide insulating layer 120B.

[0113] In the second region A2, impurities are present in the oxide insulating layer 120B (UC), the oxide semiconductor layer 140B (OS), and the oxide insulating layer 165B, with the impurity concentration profile exhibiting a peak in the oxide semiconductor layer 140B. Therefore, in the depth direction of the second region A2, the amount of impurities present at the predetermined position of the oxide semiconductor layer 140B is greater than the amount of impurities present at the predetermined position of the oxide insulating layer 120B and greater than the amount of impurities present at the predetermined position of the oxide insulating layer 165B.

[0114] As described above, in the second area A2, impurities are introduced into oxide insulating layer 120B and oxide insulating layer 165B. Therefore, the dangling bond defect DB associated with the introduction of impurities is formed in oxide insulating layer 120B and oxide insulating layer 165B.

[0115] In the third region A3, impurities are present in the oxide insulating layer 120B and the insulating layer 165B, and the concentration profile of the impurities exhibits a peak in the oxide insulating layer 120B (UC). In the third region A3, the oxide semiconductor layer 140B is not located on top of the oxide insulating layer 120B. Consequently, instead of the peak in the concentration profile in the oxide semiconductor layer 140B in the second region A2, the peak in the concentration profile is found in the oxide insulating layer 120B in the third region A3. This means that the amount of impurities contained in the oxide insulating layer 120B in the third area A3 is greater than the amount of impurities contained in the oxide insulating layer 120B in the first area A1, and greater than the amount of impurities contained in the oxide insulating layer 120B in the second area A2.

[0116] According to the impurity concentration profile described above, the dangling bond defect (DB) associated with impurity introduction is formed in oxide insulating layer 120B and oxide insulating layer 165B. As described above, in the third region A3, since the peak of the concentration profile is in oxide insulating layer 120B, the amount of dangling bond defects (DB) present in oxide insulating layer 120B in the third region A3 is greater than the amount of dangling bond defects (DB) present in oxide insulating layer 120B in the second region A2. Therefore, oxide insulating layer 120B in the third region A3 can trap more hydrogen than oxide insulating layer 120B in the second region A2. Since the thickness of the oxide insulating layer 165B is 50 nm or more, a remarkable effect is achieved by trapping hydrogen from the insulating layer 170B.Since the thickness of the oxide insulating layer 165B is 100 nm or more, the effects described above are even more remarkable.

[0117] In the present embodiment, as described above, although one configuration has been shown by way of example in which the concentration profile of the impurity has a peak in the gate electrode 160B in the first region A1, the concentration profile has a peak in the oxide semiconductor layer 140B in the second region A2 and the concentration profile has a peak in the oxide insulating layer 120B in the third region A3, the configuration is not limited to this configuration.

[0118] For example, if the thickness of the oxide semiconductor layer 140B is relatively small, the concentration profile in the second region A2 may exhibit a peak in the oxide insulating layer 120B or near the interface between the oxide semiconductor layer 140B and the oxide insulating layer 120B. Conversely, if the thickness of the oxide insulating layer 165B is relatively large, the concentration profile may exhibit a peak in the oxide insulating layer 165B or near the interface between the oxide insulating layer 165B and the lower layer of the oxide insulating layer 165B in the first region A1 to the third region A3. The lower layer of the oxide insulating layer 165B is the gate electrode 160B in the first region A1, the oxide semiconductor layer 140B in the second region A2, and the oxide insulating layer 120B in the third region A3.

[0119] In the present embodiment, in the depth direction of the third region A3, the amount of impurities contained at a predetermined position in the oxide insulating layer 120B is 1 × 10 16 / cm 3 or more, 1 × 10 17 / cm 3 or more or 1 x 10 18 / cm 3 or more. The predetermined position can be the peak position of the concentration profile or a position corresponding to an interface between oxide insulating layer 120B and oxide insulating layer 165B. Alternatively, the predetermined position can be a position shifted by a predetermined depth from a position corresponding to the interface in the direction of oxide insulating layer 120B. [3-3. Method for manufacturing the semiconductor device 10B]

[0120] A method for manufacturing the semiconductor device 10B according to an embodiment of the present invention is described with reference to Fig. 26, Fig. 27 to Fig. 28 described. Fig. Figure 26 is a flowchart showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. Fig. 27 to Fig. Figures 28 are cross-sectional views showing a method for manufacturing a semiconductor device according to an embodiment of the present invention. Since steps S1001 to S1007 in Fig. 26 are the same steps S1001 to S1007 as those in Fig. 5 and Fig. 6, Fig. 7, Fig. 8, Fig. 9 to Fig. 10, so descriptions will be omitted.

[0121] Similar to Fig. As shown in Figure 10, the gate electrode 160B is deposited and the gate electrode 160B and the gate insulating layer 150B are etched simultaneously, and then, as shown in Figure 10, the following steps are taken: Fig. Figure 27 shows the oxide insulating layer 165B being deposited on the oxide insulating layer 120B, the oxide semiconductor layer 140B and the gate electrode 160B (“forming the insulating layer” in step S1020 of Fig. 26). The oxide insulating layer 165B is formed by a CVD process. For example, a silicon oxide layer is formed as the oxide insulating layer 165B. An insulating layer with a relatively low hydrogen content is used as the oxide insulating layer 165B. For example, the hydrogen content of the oxide insulating layer 165B is 1 × 10 21 cm -3 or less.

[0122] When a silicon oxide layer is used as an oxide insulating layer 165B, the silicon oxide layer is formed under a condition in which the ratio of silane (SiH4) to nitrous oxide (N2O) is relatively small. For example, under this condition, [N2O / SiH4] is 30 or less.

[0123] In the event that the contamination can reach the oxide insulating layer 120B via ion implantation, there is a limitation due to the accelerating voltage of the ion implantation device. Therefore, the thickness of the oxide insulating layer 165B is less than 150 nm.

[0124] As in Fig. 26 and Fig. As shown in Figure 28, impurities are ion-implanted into the oxide insulating layer 165B (“Implanting foreign ions” in step S1021 of Figure 28). Fig. 26) In the present embodiment, impurities are implanted such that the peak of the impurity concentration profile is present in the oxide semiconductor layer 140B (second region A2) and the oxide insulating layer 120B (third region A3), which is located beneath the oxide insulating layer 165B. For example, elements such as boron (B), phosphorus (P), argon (Ar), or nitrogen (N) are implanted by ion implantation into the oxide semiconductor layer 140B and the oxide insulating layer 120B via the oxide insulating layer 165B. The dangling bond defect DB is created by ion implantation in the oxide insulating layer 120B in the second region A2, the oxide insulating layer 120B in the third region A3, and the oxide insulating layer 165B in the first to third regions A1. The position and quantity of the dangling bond defect DB can be controlled by adjusting the process parameters (e.g. dose quantity, acceleration voltage, plasma power, and the like) of the ion implantation.For example, the dose is 1 × 10. 14 / cm 2 or more, 5 × 10 14 / cm 2 or more or 1 × 10 15 / cm 2 or more. For example, if the element to be implanted is boron (B), the accelerating voltage is 10 keV or more and 50 keV or less.

[0125] Following the above ion implantation, the insulating layers 170B and 180B are deposited as interlayer films on the oxide insulating layer 165B (interlayer film film formation in step S1009 of Fig. 26) and openings 171B and 173B are formed in the insulating layers 170B and 180B (“opening of the contact hole” in step S1010 of Fig. 26). Forming a source-drain electrode 200B on the oxide semiconductor layer 140B and the insulating layer 180B, exposed through the openings 171B and 173B (“SD Formation” in step S1011 of Fig. 26), completes the semiconductor device 10B similar to that of Fig. 17.

[0126] In the present embodiment, as in Fig. 24 and Fig.As shown in Figure 25, the dangling bond defect DB is formed in the oxide insulating layer 165B in addition to the oxide insulating layer 120B, thus suppressing the penetration of hydrogen into the oxide semiconductor layer 140B in the channel region CH. This makes it possible to obtain the semiconductor device 10B with electrical properties in which bumps are suppressed. Furthermore, since the insulating layer with a relatively low hydrogen content is used as the oxide insulating layer 165B in the present embodiment, it is possible to suppress the penetration of hydrogen into the oxide semiconductor layer 140B in the channel region CH at the time of deposition of the oxide insulating layer 165B. Moreover, the dangling bond defect DB can be formed in both the oxide insulating layer 120B and the oxide insulating layer 165B by ion implantation.

[0127] Each of the embodiments described above as embodiments of the present invention can be appropriately combined and implemented, provided that no contradiction arises. [List of reference symbols] 10 Semiconductor device, 100 substrate, 105 Light shielding layer, 110 Nitride insulating layer, 120 oxide insulating layer, 140 oxide semiconductor layer, 141 Top side, 142 Underside, 143 side surface area, 150 gate insulation layers, 160 Gate electrode, 165A Oxide insulating layer, 170 insulating layer, 171 Opening, 173 Opening, 180 insulating layer, 200 Source-Drain Electrode, 201 Source electrode, 203 Drain electrode, A1 first area, A2 second area, A3 third area, CH Canal area D Drain area, DB Dangling Bond defect, S Source area

Claims

A semiconductor device (10) comprising: an oxide insulating layer (120); an oxide semiconductor layer (140) over the oxide insulating layer (120); a gate electrode (160) over the oxide semiconductor layer (140); a gate insulating layer (150) between the oxide semiconductor layer (140) and the gate electrode (160); and a first insulating layer (165A) covering the oxide semiconductor layer (140) and the gate electrode (160); a second insulating layer (170A) over the first insulating layer (165A), wherein the first insulating layer (165A) is an oxide, and the second insulating layer (170A) is a nitride, wherein the semiconductor device (10) is subdivided into a first region (A1) overlapping the gate electrode (160). a second area (A2) that does not overlap the gate electrode (160) and overlaps the oxide semiconductor layer (140), and a third area (A3) that does not overlap the gate electrode (160) and the oxide semiconductor layer (140),a thickness of the gate insulating layer (150) in the first region (A1) is 200 nm or more, the gate electrode (160) contacts the first insulating layer in the first region (A1), the oxide semiconductor layer (140) contacts the first insulating layer in the second region (A2), an amount of impurities contained in the oxide semiconductor layer (140) of the second region (A2) is greater than an amount of impurities contained in the oxide semiconductor layer (140) in the first region (A1), and an amount of impurities contained in the oxide insulating layer (120) in the third region (A3) is greater than an amount of impurities contained in the oxide insulating layer (120) in the second region (A2), and wherein in the third region (A3), impurities are contained in the oxide insulating layer (120) and the first insulating layer, and a Contamination profile in one thickness direction of the oxide insulating layer (120),the first insulating layer and the second insulating layer comprise a first peak and a second peak, wherein the first peak is located in the oxide insulating layer (120) and the second peak is located in the first insulating layer. Semiconductor device (10) according to claim 1, wherein, in the first region (A1), impurities are contained in the gate electrode (160) and the first insulating layer, and an impurity profile in a thickness direction of the gate electrode (160) and the first insulating layer comprises a third peak and a fourth peak, and the third peak is present in the gate electrode (160), and the fourth peak is present in the first insulating layer. Semiconductor device (10) according to claim 2, wherein, in the second region (A2), impurities are contained in the oxide insulating layer (120), the oxide semiconductor layer (140) and the first insulating layer, an impurity profile in a thickness direction of the oxide insulating layer (120), the oxide semiconductor layer (140), the first insulating layer and the second insulating layer comprises a fifth peak and a sixth peak, the fifth peak is present in the oxide semiconductor layer (140) and the sixth peak is present in the first insulating layer Semiconductor device (10) according to one of claims 1 to 3, wherein the first insulating layer contacts the oxide insulating layer (120) in the third region (A3). Semiconductor device (10) according to any one of claims 1 to 4, wherein the thickness of the first insulating layer is 50 nm or more. Semiconductor device (10) according to any one of claims 1 to 4, wherein the thickness of the first insulating layer is 100 nm or more. Semiconductor device (10) according to any one of claims 1 to 4, wherein the thickness of the first insulating layer is less than 150 nm. Method for manufacturing a semiconductor device (10) comprising: forming a first oxide insulating layer (120); forming an oxide semiconductor layer (140) over the first oxide insulating layer.(120);Exposing the first oxide insulating layer (120) by forming a pattern of the oxide semiconductor layer (140) over the first oxide insulating layer (120);Forming a gate insulating layer (150) over the oxide semiconductor layer (140);Forming a gate electrode (160) over the gate insulating layer (150);Exposing the oxide semiconductor layer (140) and the first oxide insulating layer (120) by forming a pattern of the gate insulating layer (150) and the gate electrode (160) over the oxide semiconductor layer (140);Implanting an impurity into the exposed oxide semiconductor layer (140) and the first oxide insulating layer (120);Forming a second oxide insulating layer over each of the first oxide insulating layer (120), the oxide semiconductor layer (140), and the gate electrode. (160); Implanting an impurity into the second oxide insulating layer; and forming a nitride insulating layer over the second oxide insulating layer. Method for fabricating a semiconductor device (10), comprising: forming a first oxide insulating layer (120); forming an oxide semiconductor layer (140) over the first oxide insulating layer (120); exposing the first oxide insulating layer (120) by forming a pattern of the oxide semiconductor layer (140) over the first oxide insulating layer (120); forming a gate insulating layer (150) over the oxide semiconductor layer (140); forming a gate electrode (160) over the gate insulating layer (150); exposing the oxide semiconductor layer (140) and the first oxide insulating layer (120) by forming a pattern of the gate insulating layer (150) and the gate electrode (160) over the oxide semiconductor layer (140); forming a second oxide insulating layer having a hydrogen content of 1 × 10²¹ cm⁻³ or less over the first oxide insulating layer (120), the oxide semiconductor layer (140) and the gate electrode (160);Implanting an impurity into the oxide semiconductor layer (140), the first oxide insulating layer (120) and the second oxide insulating layer; and forming a nitride insulating layer over the second oxide insulating layer.

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