Semiconductor component with an insulation structure and method for manufacturing the semiconductor component

Abstract

A semiconductor device comprises: a silicon layer with a thickness ranging from 2 µm to 200 µm between a front and a back side of the silicon layer; a first device region and a second device region laterally isolated from each other within the silicon layer by an insulating structure extending from the front to the back side of the silicon layer; a first insulating layer on the front side of the silicon layer; a first structured metallization on the first insulating layer; a second insulating layer on the back side of the silicon layer; and a second structured metallization on the second insulating layer. The first structured metallization provides lateral electrical routing along the front side of the silicon layer. The second structured metallization provides lateral electrical routing along the back side of the silicon layer.Additional embodiments of semiconductor devices and methods for manufacturing the semiconductor devices are also described.

Description

BACKGROUND

[0001] For high-voltage integrated devices (e.g., 20 V or higher), such as a diode, an LDMOS (laterally diffused metal-oxide-semiconductor), etc., the device must be optimized for the intended application. For example, robustness, low on-resistance, high breakdown voltage, etc., may require optimization. To optimize parameters such as robustness, resistance, and breakdown voltage, the potential and fields within the device must be controlled for all operating conditions. Existing solutions include field-guiding elements such as field plates over silicon, stepped implantation schemes, p / n compensation structures, and the like. All of these solutions contribute to producing an efficient high-voltage integrated device, but further efficiency gains can be realized by improving the device design. SUMMARY

[0002] According to one embodiment of a semiconductor device, the semiconductor device comprises: a silicon layer with a thickness in a range of 2 µm to 200 µm between a front side and a back side of the silicon layer; a first device region and a second device region, which are laterally insulated from one another in the silicon layer by an insulation structure extending from the front side to the back side of the silicon layer; a first insulation layer on the front side of the silicon layer; a first patterned metallization on the first insulation layer; a second insulation layer on the back side of the silicon layer;and a second patterned metallization on the second insulation layer, wherein the first patterned metallization provides lateral electrical routing along the front side of the silicon layer, wherein the second patterned metallization provides lateral electrical routing along the back side of the silicon layer;

[0003] According to one embodiment of a method for manufacturing a semiconductor device, the method comprises: forming a silicon layer with a thickness in a range of 2 µm to 200 µm between a front side and a back side of the silicon layer; forming a first device region and a second device region that are laterally insulated from each other in the silicon layer by an insulation structure extending from the front side to the back side of the silicon layer; forming a first insulation layer on the front side of the silicon layer; forming a first patterned metallization on the first insulation layer; forming a second insulation layer on the back side of the silicon layer;and forming a second patterned metallization on the second insulation layer, wherein the first patterned metallization provides lateral electrical routing along the front side of the silicon layer, wherein the second patterned metallization provides lateral electrical routing along the back side of the silicon layer;

[0004] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and upon viewing the accompanying drawings. SHORT DESCRIPTION OF THE CHARACTERS

[0005] The elements of the drawings are not necessarily to scale relative to one another. Like reference numerals indicate corresponding similar parts. The features of the various illustrated embodiments may be combined, provided they are not mutually exclusive. Embodiments are illustrated in the drawings and described in detail in the following description. Fig. 1 illustrates a cross-sectional view of a portion of a semiconductor device having a patterned front side metallization and a patterned back side metallization, according to an embodiment. Fig. 2 illustrates a cross-sectional view of a portion of the semiconductor device during a mask backside implantation process according to one embodiment. Fig. 3 illustrates a cross-sectional view of a portion of the semiconductor device during a mask backside implantation process according to one embodiment. Fig. 4A to Fig. 4C illustrate cross-sectional views of a portion of the semiconductor device during a portion of the manufacturing process according to one embodiment. Fig. 5A and Fig. 5B illustrate cross-sectional views of a portion of the semiconductor device during a portion of the manufacturing process according to one embodiment. Fig. 6A to Fig. 6C illustrate cross-sectional views of a portion of the semiconductor device during formation of the patterned backside metallization according to one embodiment. Fig. 7 to Fig. 9 illustrate respective cross-sectional views of a portion of the semiconductor device according to additional embodiments. Fig. 10A illustrates a plan view and Fig. Figure 10B illustrates a corresponding cross-sectional view along the line shown in Fig. 10A is labeled AA', of a part of the semiconductor device according to an embodiment. Fig. 11A illustrates a plan view and Fig. Figure 11B illustrates a corresponding cross-sectional view along the line shown in Fig. 11A is labeled BB', of a part of the semiconductor device according to an embodiment. Fig. 12A illustrates a plan view and Fig. Figure 12B illustrates a corresponding cross-sectional view along the line shown in Fig. 12A is designated CC', of a part of the semiconductor device according to an embodiment. Fig. 13 illustrates a partial top view of the silicon layer of the semiconductor device according to another embodiment. DETAILED DESCRIPTION

[0006] The described embodiments provide a semiconductor device and methods for manufacturing the semiconductor device. The semiconductor device includes a silicon layer with a thickness in a range of 2 µm to 200 µm between the front and back sides of the silicon layer. Two or more device regions are laterally insulated from each other in the silicon layer by an isolation structure extending from the front side to the back side of the silicon layer. A patterned metallization is arranged on both sides of the silicon layer. The patterned front side metallization provides lateral electrical routing along the front side of the silicon layer. The patterned back side metallization provides lateral electrical routing along the back side of the silicon layer.The isolation structure and / or a silicon via may be used to provide vertical electrical routing between the patterned front side metallization and the patterned back side metallization.

[0007] The semiconductor device described herein enables power and / or signal routing along both the front and back surfaces of the device and enables back-gating for front-side devices. The semiconductor device also enables vertical devices with power and / or signal routing across the back surface and selective contacts to, for example, a lead frame at the bottom of the device for electrical and thermal connection. With the patterned back-side metallization and using a conductive trench / plug, a bias voltage (back-gating) can be capacitively applied to a lateral high voltage (e.g., 20 V or higher) or a power device (e.g., 1 A or higher) at the front surface. The back bias voltage can enhance device functionality, e.g.,by reducing leakage current, increasing the forward bias inrush current, enabling better transient operation, reducing cross-coupling from other components, etc. Furthermore, controlled backside bias also enables stacking of high-voltage devices for higher voltages without redesigning the device. In the case of SOI (silicon-on-insulator) technology, capacitive coupling from the front side to the back side enables the transfer of information across the back side. Capacitance or leakage sensing can be enabled for in-situ detection of backside oxide failure.

[0008] Next, embodiments of the semiconductor device and associated manufacturing methods will be described with reference to the figures.

[0009] Fig. 1 illustrates a cross-sectional view of a portion of a semiconductor device according to an embodiment. The semiconductor device includes a silicon layer 100 having a thickness T_Si in the depth direction (z-direction in Fig. 1) in a range of 2 µm (micrometers) to 200 µm between a front side 102 and a back side 104 of the silicon layer 100. In one embodiment, the silicon layer 100 is realized by forming one or more devices, such as one or more power diodes, one or more high-voltage transistors, a gate driver for a power transistor, etc., in a bulk silicon wafer or in one or more epitaxial layers grown on a bulk silicon wafer, and then grinding the back side of the bulk silicon wafer to the final thickness T_Si. The resulting silicon layer 100 is thicker (e.g., T_Si = 2 µm to 200 µm) than typical SOI device layers, which typically have a thickness in the nanometer (nm) range. The silicon layer 100 may instead be a standard SOI device layer formed by SIMOX (isolation by oxygen implantation, wafer bonding, etc.).) and has a thickness T_Si of less than 10 µm. The silicon layer 100 can be doped n-type or p-type.

[0010] A first device region 106 and a second device region 108 are laterally isolated from each other in the silicon layer 100 by an isolation structure 110 extending from the front side 102 to the back side 104 of the silicon layer 100. Depending on the target application, the same device type or different device types may be formed in the first and second device regions 106, 108, exemplary embodiments of which will be described in more detail later. The semiconductor device may include more than two device regions 106, 108, which are laterally isolated from each other in the silicon layer 100 by an isolation structure 110.

[0011] The semiconductor device also includes a first (front-side) insulation layer 112 on the front side 102 of the silicon layer 100 and a first (front-side) patterned metallization 114 on the front-side insulation layer 112. A second (back-side) insulation layer 116 is located on the back side 104 of the silicon layer 100, and a second (back-side) patterned metallization 118 is located on the back-side insulation layer 116. The front-side and back-side insulation layers 112, 116 may, for example, be deposited oxides. However, any suitable type of dielectric material (e.g., SiO2, SiN4, etc.) may be used as the front-side and back-side insulation layers 112, 116. The front and back metallizations 114, 118 may include a single metallic layer or a stack of metallic layers 120.The front and back metallizations 114, 118 may include one or more vias 122 extending through the respective insulation layer 112, 116 and connected to one or more metallic layers 120, e.g., in the case of a Cu damascene structure.

[0012] The patterned front-side metallization 114 provides lateral electrical routing along the front side 102 of the silicon layer 100. For example, the patterned front-side metallization 114 may laterally route power and / or signals between the device regions 106, 108 at the front side 102 of the silicon layer 100. The patterned back-side metallization 118 similarly provides lateral electrical routing along the back side 104 of the silicon layer 100. For example, the patterned back-side metallization 118 may laterally route power and / or signals to one or more of the device regions 106, 108 at the back side 104 of the silicon layer 100. Separately or in combination, the patterned back-side metallization 118 may apply a back bias voltage to one or more of the device regions 106, 108 at the back side 104 of the silicon layer 100.Separately or in combination, the patterned backside metallization 118 may provide capacitive coupling to one or more of the device regions 106, 108 on the backside 104 of the silicon layer 100.

[0013] In one embodiment, the isolation structure 110, which extends from the front side 102 to the back side 104 of the silicon layer 100, provides vertical electrical routing between the patterned front side metallization 114 and the patterned back side metallization 118. For example, the isolation structure 110 may include an electrically conductive material 124 laterally separated from the silicon layer 100 by a dielectric material and / or a pn junction 126. In this example, the electrically conductive material 124 provides vertical electrical routing between the patterned front side metallization 114 and the patterned back side metallization 118. The electrically conductive material 124 is made of an electrically conductive material such as polysilicon and / or a metal or metal stack.

[0014] In the case of a dielectric material as the insulating material 126, the dielectric material may line each sidewall of a trench, which is then filled with the electrically conductive material forming the electrically conductive material 124. The dielectric material may be SiOx, SiN, HfOx, AlxOy (e.g., Al2O3), TEOS (tetraethoxysilane), etc., or a layer stack of two or more of these or similar dielectric materials. The trench is etched into the silicon layer 100 before the silicon layer 100 is thinned to the target / final thickness T_Si. The dielectric material lines the sidewalls and the bottom of the trench. Later, the silicon layer 100 is thinned from the backside 104 until the target thickness T_Si is reached.The thinning process may expose the electrically conductive material forming the electrically conductive material 124 at the bottom of the trench, enabling vertical electrical routing between the front side 102 and the back side 104 of the silicon layer 100. In other cases, the electrically conductive material 124 may remain covered by the dielectric material at the bottom of the trench.

[0015] In the case of a pn junction as the insulating material 126, the pn junction is a boundary or interface between two types of semiconductor materials within the silicon layer 100. For example, the silicon layer 100 may be p-type or n-type near the insulating structure 110, and an intermediate region of the opposite conductivity type may directly border the electrically conductive material 124. The region of the opposite conductivity type directly bordering the electrically conductive material 124 may be formed by ion implantation or out-diffusion of n-type dopants in a p-type substrate or p-type dopants in an n-type substrate.

[0016] In another embodiment, a through-silicon via (TSV) 128 provides vertical electrical routing between the patterned front-side metallization 114 and the patterned back-side metallization 118. The TSV 128 is in Fig. 1 as a dashed rectangle to provide an unobstructed view of the isolation structure 110. The TSV 128 is formed after the silicon layer 100 has been thinned to the target / final thickness T_Si by deep etching through the thinned silicon layer 100, lining the via with an insulating liner, opening the liner at the bottom, filling the lined via with a metal or metal alloy, and connecting the metal or metal alloy to the adjacent patterned metallization 114 on the front side 102 of the silicon layer 100 and to the adjacent patterned metallization 118 on the back side 104 of the silicon layer 100. The electrically conductive material 124 and the corresponding insulating material 126 are in Fig. 1 as extending from a bottom surface of the patterned front-side metallization 114 to a top surface of the patterned back-side metallization 118. This is the case for the TSV 128, which is formed after the front-side and back-side insulation layers 112, 116 have been formed.

[0017] For the isolation structure 110, at least the insulation material 126 terminates at the front side 102 and the back side 104 of the silicon layer 100, since the isolation structure 110 is formed before the silicon layer 100 is thinned to the final thickness T_Si. The electrically conductive material 124 may or may not be covered by the corresponding insulation material 126 at the back side 104 of the silicon layer 100, depending on the design and function of the isolation structure 110. If the isolation structure 110 is only provided for the lateral isolation of adjacent device regions 106, 108, then the electrically conductive material 124 may be covered by the insulation material 126 at the back side 104 of the silicon layer 100.However, if the isolation structure 110 is also used for vertical electrical routing between the patterned front side metallization 114 and the patterned back side metallization 118, then the electrically conductive material 124 is exposed (i.e., not covered) by the isolation material 126 at the back side 104 of the silicon layer 100.

[0018] Depending on the material type used to form the electrically conductive material 124 in the isolation structure 110, the TSV 128 may have a lower electrical resistance than the isolation structure 110. Nevertheless, the isolation structure 110 may be used to provide vertical electrical routing between the front side 102 and the back side 104 of the silicon layer 100 if the electrically conductive material 124 is exposed at the bottom of the trench defining the isolation structure 110.In either case, the vertical routing capability provided by the isolation structure 110 and / or the TSV 128 can route power across the patterned metallizations 114, 118 on the front and back sides 102, 104 of the silicon layer 100, thereby enabling vertical devices, power / signal routing across the back side 104, selective contact to a substrate such as a lead frame on the back side 104 for electrical and / or thermal connection, etc.

[0019] The number of isolation structures 110 included in the semiconductor device depends on the number of device regions 106, 108 requiring lateral isolation. The semiconductor device may include one or more TSVs 128 or no TSVs 128, depending on whether vertical electrical routing is required between the patterned front-side metallization 114 and the patterned back-side metallization 118 and whether the isolation structure(s) 110 is / are used to provide the vertical routing.

[0020] As in Fig. 1, the patterned backside metallization 118 may contact the silicon layer 100 at the backside 104 through openings 130 in the backside insulation layer 116. For example, the patterned backside metallization 118 may contact the first and second device regions 106, 108 at the backside 104 of the silicon layer 100 or only one of the device regions 106, 108 at the backside 104. One or more islands or segments of the patterned backside metallization 118 that contact the silicon layer 100 at the backside 104 may be vertically electrically connected to the patterned frontside metallization 114 through the isolation structure 110 or the TSV 128.

[0021] For example, in Fig. 1, the structured backside metallization 118 comprises a first section 118_1, which contacts the silicon layer 100 on the backside 104 through a first opening 130_1 in the backside insulation layer 116, and a second section 118_2, which contacts the electrically conductive region 124 of the insulation structure 110 or the TSV 128 through a second opening 130_2 in the backside insulation layer 116. Also in Fig. 1, the patterned front side metallization 114 may contact the electrically conductive region 124 of the isolation structure 110 or the TSV 128 through an opening 132 in the front side isolation layer 112.

[0022] Fig. 2 illustrates a cross-sectional view of a portion of the semiconductor device during a mask backside implantation process according to one embodiment. In Fig. 2, a dopant species 200 is implanted planarly into the backside 104 of the silicon layer 100 after the silicon layer 110 has been formed to have a thickness T_Si in a range of 10 µm to 200 µm, but before forming both the backside insulation layer 116 and the patterned backside metallization 118.

[0023] After an annealing process that activates the implanted dopant species 200, the silicon layer 100 includes a doped contact region 202 adjacent to any portion of the patterned backside metallization 118 that contacts the silicon layer 100 at the backside 104. The lower portion of the electrically conductive material 124 in the isolation structure 110 may also be doped if the electrically conductive material 124 is exposed at the bottom of the trench defining the isolation structure 110.

[0024] Each doped contact region 202 has a higher doping concentration than material of the silicon layer 100 adjacent to the doped contact region 202. For a p+ -doped contact region 202, the dopant species may be boron, aluminum, indium, etc. For an n+ -doped contact region 202, the dopant species may be phosphorus, arsenic, antimony, etc.

[0025] Fig. 3 illustrates a cross-sectional view of a portion of the semiconductor device during a mask backside implantation process according to one embodiment. In Fig. 3, a resist layer 300 is formed on the backside 104 of the silicon layer 100, and a dopant species 302 is implanted into the backside 104 of the silicon layer 100 through openings 304 in the resist layer 300 after the silicon layer 100 has been formed to have a thickness T_Si in a range of 10 µm to 200 µm, but before forming both the backside insulation layer 116 and the patterned backside metallization 118.

[0026] After an annealing process that activates the implanted dopant species 302, the silicon layer 100 includes a doped contact region 306 adjacent to any portion of the patterned backside metallization 118 that contacts the silicon layer 100 at the backside 104. The lower portion of the electrically conductive material 124 in the isolation structure 110 may also be doped if the electrically conductive material 124 is exposed at the bottom of the trench defining the isolation structure 110.

[0027] Each doped contact region 306 has a higher doping concentration than material of the silicon layer 100 adjacent to the doped contact region 306. For a p+ -doped contact region 306, the dopant species may be boron, aluminum, indium, etc. For an n+ -doped contact region 306, the dopant species may be phosphorus, arsenic, antimony, etc.

[0028] Contact regions of both doping types (n and p) can be formed at various locations in the silicon layer 100. For example, a patterned n-type contact can be formed, followed by a patterned p-type implantation, followed by a subsequent cleaning step and then metal deposition to form the patterned backside metallization 118.

[0029] Fig. 4A to Fig. 4C illustrate cross-sectional views of a portion of the semiconductor device during a portion of the manufacturing process according to one embodiment. In Fig. 4A, a resist layer 400 is formed on the backside insulation layer 116 after the silicon layer 100 has been formed to have a thickness T_Si in a range of 10 µm to 200 µm, but before forming the patterned backside metallization 118. In Fig. 4B, openings 402 are formed in the resist layer 400 and the backside insulation layer 116 to expose regions of the silicon layer 100 at the backside 104. Doped regions such as highly doped contact regions can be formed by implanting a dopant species (in Fig. 4A to Fig. 4C not shown, but see Fig. 2 and Fig. 3) in the exposed part of the backside 104 of the silicon layer 100 through the openings 402 in the resist layer 400 and the backside insulation layer 116. In Fig. 4C, the resist layer 400 is removed from the backside insulation layer 116.

[0030] Fig. 5A and Fig. 5B illustrate cross-sectional views of a portion of the semiconductor device during a portion of the manufacturing process according to one embodiment. In Fig. 5A, openings 500 are formed in the backside insulation layer 116 to expose regions of the silicon layer 100 at the backside 104. Doped regions 502, such as highly doped contact regions, can be formed by implanting a dopant species 504 into the exposed portion of the backside 104 of the silicon layer 100 through the openings 500 in the backside insulation layer 116. The type of dopant species 500 depends on whether n-type or p-type regions 502 are formed. Fig. 5B, a resist layer 506 is formed on the backside insulation layer 116 after the first backside implantation 504. One or more openings 508 are then formed in the resist layer 506 and the backside insulation layer 116 to expose at least another portion of the silicon layer 100 at the backside 104. A doped region 510, such as a highly doped contact region, is formed by implanting a different dopant species 512 into each exposed portion of the backside 104 of the silicon layer 100 through each opening 508 in the resist layer 506 and the backside insulation layer 116. Each in Fig. 5B may have the opposite conductivity type and / or a different dopant concentration than that shown in Fig. Doped regions 502 shown in Figure 5A.

[0031] Fig. 6A to Fig. 6C illustrate cross-sectional views of a portion of the semiconductor device during formation of the patterned backside metallization 118 according to one embodiment. In Fig. 6A, openings 600 are etched in the backside insulation layer 116, exposing the backside 104 of the silicon layer 100, and a metal or metal alloy 602 is deposited on the backside insulation layer 116 and in the openings 600 formed therein. In one embodiment, a copper damascene process is used to deposit the metal or metal alloy 602. In Fig. 6B, a resist layer 604 is formed on the metal or metal alloy 602, and the metal or metal alloy 602 is patterned through openings 606 in the resist layer 604, e.g., by etching. Fig. Figure 6C shows the semiconductor device after the resist layer 604 has been removed. The patterning process defines the patterned backside metallization 118 with a plurality of separate sections 608, 610, 612.

[0032] In another embodiment, the patterned backside metallization 118 is formed by two separate metal deposition processes. The first metal deposition process includes etching and filling each opening 600 in the backside insulation layer 116 to form at least one via 122 that contacts the backside 104 of the silicon layer 100. The second metal deposition process includes depositing and etching a metal or metal alloy on the backside insulation layer 116 and that contacts each via 122 to form the Fig. 6C to form separate sections 608, 610, 612.

[0033] Fig. 7 illustrates a cross-sectional view of a portion of the semiconductor device according to one embodiment. In Fig. 7, an additional backside insulation layer 700 is formed on the patterned backside metallization 118 and laterally insulates the portions 118_1, 118_2 of the patterned backside metallization 118 from each other. Any suitable type of dielectric material (e.g., SiO2, SiN4, etc.) may be used as the additional backside insulation layer 700. The additional backside insulation layer 700 may provide electrical isolation at the device backside, e.g., to a lead frame or another type of substrate (in Fig. 7 not shown).

[0034] Fig. 8 illustrates a cross-sectional view of a portion of the semiconductor device according to one embodiment. In Fig. 8, a substrate 800 and / or a plurality of contacts 802 are arranged on the additional backside insulation layer 700 and electrically connected to the patterned backside metallization 118. The substrate 800 may be a lead frame, a DBC (Direct Bonded Copper) substrate, an AMB (Active Metal Brazed) substrate, an IMS (Insulated Metal Substrate) substrate, a metal block, a molding compound, a die attach film, a Si carrier, an adhesive, a printed circuit board, an interposer, another die (chip), etc. The contacts 802 may be electrically conductive vias, solder bumps, Cu pillars, etc. The additional backside insulation layer 700 may be opened to enable selective contacting between the patterned backside metallization 118 and the substrate 800, e.g., the via contacts 802.

[0035] Fig. 9 illustrates a cross-sectional view of a portion of the semiconductor device according to one embodiment. In Fig. 9, an additional structured metallization 900, such as a structured Cu layer, is formed on the additional backside insulation layer 700. Providing more than one structured metallization 118, 900 on the backside 104 of the silicon layer 100 enables more complex routing on the backside 104. The structured metallizations 114, 118, 900 and insulation layers 112, 116, 700 on both sides 102, 104 of the silicon layer 100 enable the stacking of chips (dies) with two or more chips on top of each other and the exchange of information or power vertically to each other and to a substrate 900 such as a lead frame, as in Fig. 8, and / or for bonding contacts 802, as also shown in Fig. 8 shown.

[0036] Fig. 10A illustrates a plan view and Fig. Figure 10B illustrates a corresponding cross-sectional view along the line shown in Fig. 10A, labeled AA', of a portion of the semiconductor device according to an embodiment. In Fig. 10A and Fig. 10B is a vertical component that is Fig. 10B using a transistor symbol, is formed in the first device region 106 of the silicon layer 100. The patterned front-side metallization 114 provides a first power terminal connection to the vertical device at the front side 102 of the silicon layer 100 through at least one opening 132 in the front-side insulation layer 112. The patterned front-side metallization 114 and the front-side insulation layer 112 are shown in Fig. 10A and Fig. 10B not shown to highlight other features.

[0037] The patterned backside metallization 118 provides a second power terminal connection to the vertical device at the backside 104 of the silicon layer 100 through at least one opening 1000 in the backside insulation layer 116. The second power terminal potential can be input at the device frontside, with a portion of the patterned frontside metallization 114 at the second power terminal potential contacting the electrically conductive region 124 of the isolation structure 110 or the TSV 128, which in turn electrically routes the second power terminal potential vertically to the corresponding portion 118_1 of the patterned backside metallization 118. In this way, a vertical device, such as a power transistor or a power diode (e.g., 1A or higher), can be realized without having to externally contact the device backside.

[0038] In the case of an IGBT (Insulated Gate Bipolar Transistor) as the vertical device, the first power terminal connection provided by the patterned front-side metallization 114 may be the emitter "E" connection, and the second power terminal connection provided by the patterned back-side metallization 118 may be the collector "C" connection. In the case of a vertical power MOSFET (Metal Oxide Semiconductor Field-Effect Transistor) or vertical JFET (Junction Field-Effect Transistor) as the vertical device, the first power terminal connection provided by the patterned front-side metallization 114 may be the source "S" connection, and the second power terminal connection provided by the patterned back-side metallization 118 may be the drain "D" connection.In the case of a power diode as the vertical device, the first power terminal connection provided by the patterned front side metallization 114 is the anode or cathode connection, and the second power terminal connection provided by the patterned back side metallization 118 is the other of the anode or cathode connection.

[0039] Fig. 10B generally shows a source (or emitter) region 1002 and a body region 1004 formed in the first device region 106 at the front side 102 of the silicon layer 100, and a drain (or collector) region 1006 formed in the first device region 106 at the back side 102 of the silicon layer 100. In the case of a vertical power diode, the body region 1004 would correspond to the anode region, and the drain / collector region 1006 would correspond to the cathode region, omitting the source region 1002. Still other types of vertical and / or lateral devices may be formed in the first device region 106.

[0040] In one embodiment, the vertical device formed in the first device region 106 of the silicon layer 100 is a vertical power transistor device, such as an IGBT, power MOSFET, JFET, etc., and a lateral gate driver 1008 is formed in the second device region 108 on the front side 102 of the silicon layer 100. The lateral gate driver 1008 is in Fig. 10B by various doped regions 1010, 1012 and gate trenches 1014. The patterned front-side metallization 114 electrically connects the lateral gate driver 1008 formed in the second device region 108 to a gate terminal "G" of the vertical power transistor device formed in the first device region 106.

[0041] In another embodiment, the vertical device formed in the first device region 106 of the silicon layer 100 is a light-emitting diode (LED) device, and the lateral driver 1008 formed in the second device region 108 at the front side 102 of the silicon layer 100 is configured to drive the LED. The patterned front side metallization 114 electrically connects the lateral driver 1008 to the LED device. For an LED, the silicon layer 100 may include 2 to 6 or more semiconductor sublayers with epitaxial superstructures, and single-sided routing may be provided with transparent electrodes, such as conductive oxides or transparent metal films.

[0042] More generally, the Fig. 10A and Fig. The configuration illustrated in Figure 10B includes cointegration of vertical devices, such as FETs or IGBTs, with full routing at the front side 102. Such cointegration enables formation of various circuit types, such as a monolithic half-bridge, a 3-phase or LED driver with vertical power devices, etc.

[0043] Fig. 11A illustrates a plan view and Fig. Figure 11B illustrates a corresponding cross-sectional view along the line shown in Fig. 11A, labeled BB', of a portion of the semiconductor device according to an embodiment. In Fig. 11A and Fig. 11B, the patterned backside metallization 118 applies a bias voltage to the first device region 106 at the backside 104 of the silicon layer 100. For example, the patterned frontside metallization 114 may couple the bias voltage to the patterned backside metallization 118 through the electrically conductive region 124 of the isolation structure 100 or through a TSV 128.

[0044] In one embodiment, a first device 1100 is formed in the first device region 106 of the silicon layer 100, a second device 1102 is formed in the second device region 108 of the silicon layer 100, and the patterned front-side metallization 114 electrically connects the first device 1100 and the second device 1102 to form a cascode device. The first and second devices 1100, 1102 are Fig. 11B by respective doped regions 1104, 1106, 1108, 1110 and gate trenches 1112, 1114. The patterned front side metallization 114 and the front side insulation layer 112 are shown in Fig. 11A and Fig. 11B not shown to highlight other features.

[0045] The first device 1100 and the second device 1102 may have the same breakdown voltage rating. In this example, the first device 1100 and the second device 1102 individually block half the voltage across the cascode device in a cascode device blocking state. For example, the second device region 108 may include a high-voltage device 1102 (e.g., 20 V or higher) with a maximum voltage rating of 500 V and 0 V applied as a backside voltage. Including the same type of device 1100 in the first device region 106 and biasing the reference and back sides to 500 V allows stacking of both devices 1100, 1102 with a switching capability of 1000 V, with the second device 1102 in the second device region 108 operating between 0 V and 500 V and the first device 1100 in the first device region 106 operating between 500 V and 1000 V.

[0046] Other types of lateral device configurations can be implemented using the laterally isolated device regions 106, 108. For example, two or more lateral devices, such as lateral power or high-voltage devices, such as LDMOS devices, can be formed in isolated regions 106, 108 within the silicon layer 100 and connected in series by the patterned front-side metallization 114, with the backside region of one device electrically connected to the high potential of the previous device by the patterned backside metallization 118. Such a configuration allows the devices to have the same back bias, and the devices can be logically stacked as much as the isolation structure 110 allows.

[0047] Fig. 12A illustrates a plan view and Fig. Figure 12B illustrates a corresponding cross-sectional view along the line shown in Fig. 12A, labeled CC', of a portion of the semiconductor device according to an embodiment. In Fig. 12A and Fig. 12B, the structured backside metallization 118 includes a portion 118_2 that is capacitively coupled to the second device region 108 on the backside 104 of the silicon layer 100. Separately or in combination, the structured backside metallization 118 may include a further portion 118_1 that is capacitively coupled to the first device region 106 on the backside 104 of the silicon layer 100. The capacitive coupling is in Fig. 12B is schematically indicated by a capacitor 1200.

[0048] In Fig. 12B, the electrically conductive region 124 of the isolation structure 110 or the TSV 128 routes a potential of the patterned backside metallization portion 118_2, which is capacitively coupled to the second device region 108 at the backside 104 of the silicon layer 100, vertically electrically to the patterned frontside metallization 114. The capacitive coupling from the frontside 102 to the backside 104 of the silicon layer 100 enables the transmission of information across the backside 104 and enables capacitive or leakage sensing for in-situ detection of a dielectric failure of the backside isolation layer 116.

[0049] Fig. 13 illustrates a partial top view of the silicon layer 100 according to another embodiment. In Fig. 13, the isolation structure 110 includes two or more trenches 1300 extending through the silicon layer 100 from the front side 102 to the back side 104 (z-direction in Fig. 13) and laterally insulate the first device region 106 and the second device region 108 from each other. An electrically conductive material 124 is located in the trenches 1300, and a dielectric material 126 separates the electrically conductive material 124 from the silicon material of the silicon layer 100. A silicon mesa 1302 is arranged between adjacent ones of the trenches 1300. The electrically conductive material 124 in the trenches 1300 may provide vertical electrical routing between the patterned front-side metallization 114 and the patterned back-side metallization 118, e.g., as previously described herein.

[0050] In Fig. 13, a first silicon mesa 1300_2 is arranged between adjacent ones of the trenches 1300 in a first lateral direction (x-direction in Fig. 13) is arranged (bounded by these) and a second silicon mesa 1302_2 is arranged between adjacent ones of the trenches 1300 in a second lateral direction (y-direction in Fig. 13) that is transverse to the first lateral direction. The first and second silicon mesas 1302_1, 1302_2 intersect each other.

[0051] In a region 1304 where the first and second silicon mesas 1302_1, 1302_2 intersect, a silicon plug 1306, laterally surrounded by the dielectric trench material 126, interrupts the silicon mesa 1300 where two or more trenches 1300 intersect. The silicon plug 1306 may instead interrupt the electrically conductive material 124 where two or more trenches 1300 intersect. In yet another embodiment, a first silicon plug 1306, surrounded by the dielectric trench material 126, may interrupt the silicon mesa 1300, and a second silicon plug 1306, surrounded by the dielectric trench material 126, may interrupt the electrically conductive material 124 where two or more trenches 1300 intersect. In each of these cases, deep isolated mesa crossings 1304 allow different voltage domains to be placed side by side without sacrificing die area (chip area).

[0052] In one embodiment, the first device regions 106 of the silicon layer 100, which are in Fig. 13, a first voltage domain and the second device regions 108 of the silicon layer 100, which are shown in Fig. 13, support a second stress domain that is distinct from the first stress domain. In the corner region 1304, where one or more of the laterally isolated regions 106 of the first stress domain are adjacent to one or more of the laterally isolated regions 108 of the second stress domain, the silicon plug 1306 separates the first and second silicon mesas 1302_1, 1302_2 from each other.

[0053] The silicon plug 1306 may be defined by masking during the trench etching process, and a local CD reduction of the mask (not shown) used to etch the trenches 1300 into the silicon layer 100 may be used in regions 1304 where the first and second silicon mesas 1302_1, 1302_2 intersect each other, such that the dielectric trench material 126 is thicker in the reduced CD regions 1304 compared to the regions of the trenches 1300 that include the electrically conductive material 124.

[0054] In a lateral direction (x or y direction in Fig.13), the average thickness of the dielectric trench material 126 around the silicon plug 1306 may be greater than the average thickness of the dielectric trench material 126 between the silicon material of the respective mesa 1302_1, 1302_2 and the electrically conductive material 124 in the adjacent trench 1300. According to this embodiment, the silicon plug 1306 is positioned within a mesa intersection 1304 to provide a CD reduction and thus a thicker dielectric material 126 at the mesa intersection 1304.

[0055] Although the present disclosure is not so limited, the following numbered examples illustrate one or more aspects of the disclosure.

[0056] Example 1. A semiconductor device comprising: a silicon layer having a thickness in a range of 2 µm to 200 µm between a front side and a back side of the silicon layer; a first device region and a second device region laterally insulated from each other in the silicon layer by an isolation structure extending from the front side to the back side of the silicon layer; a first isolation layer on the front side of the silicon layer; a first patterned metallization on the first isolation layer; a second isolation layer on the back side of the silicon layer; and a second patterned metallization on the second isolation layer, wherein the first patterned metallization provides lateral electrical routing along the front side of the silicon layer, wherein the second patterned metallization provides lateral electrical routing along the back side of the silicon layer.

[0057] Example 2. The semiconductor device of Example 1, wherein the second patterned metallization contacts the silicon layer on the backside through a plurality of openings in the second insulation layer.

[0058] Example 3. The semiconductor device of Example 2, wherein the silicon layer comprises a doped contact region adjacent to each portion of the second patterned metallization that contacts the silicon layer at the backside, and wherein each doped contact region has a higher doping concentration than material of the silicon layer adjacent to the doped contact region.

[0059] Example 4. The semiconductor device according to any one of examples 1 to 3, wherein the second patterned metallization comprises a first portion contacting the silicon layer at the rear side through a first opening in the second insulation layer, and a second portion contacting an electrically conductive region of the insulation structure or a silicon via extending through the silicon layer through a second opening in the second insulation layer.

[0060] Example 5. The semiconductor device according to example 4, wherein the first patterned metallization contacts the electrically conductive region of the insulation structure or the silicon via through an opening in the first insulation layer.

[0061] Example 6. The semiconductor device of any one of examples 1 to 5, wherein a vertical device is formed in the first device region, wherein the first patterned metallization provides a first power terminal connection to the vertical device at the front side of the silicon layer through at least one opening in the first insulation layer, and wherein the second patterned metallization provides a second power terminal connection to the vertical device at the back side of the silicon layer through at least one opening in the second insulation layer.

[0062] Example 7. The semiconductor device of example 6, wherein the vertical device is a vertical power transistor device, wherein a lateral gate driver is formed in the second device region, and wherein the first patterned metallization electrically connects the lateral gate driver to a gate terminal of the vertical power transistor device.

[0063] Example 8. The semiconductor device of example 6, wherein the vertical device is a light-emitting diode (LED) device, wherein a lateral driver is formed in the second device region, and wherein the first patterned metallization electrically connects the lateral driver to the LED device.

[0064] Example 9. The semiconductor device of any one of examples 1 to 8, wherein the second patterned metallization applies a bias voltage to the first device region at the backside of the silicon layer.

[0065] Example 10. The semiconductor device of example 9, wherein a first device is formed in the first device region and a second device is formed in the second device region, and wherein the first patterned metallization electrically connects the first device and the second device to each other to form a cascode device.

[0066] Example 11. The semiconductor device of example 10, wherein the first device and the second device have an equal breakdown voltage rating, and wherein in a blocking state of the cascode device, the first device and the second device individually block half the voltage across the cascode device.

[0067] Example 12. The semiconductor device of any one of examples 9 to 11, wherein the first patterned metallization couples the bias voltage to the second patterned metallization through an electrically conductive region of the isolation structure or through a silicon via extending through the silicon layer.

[0068] Example 13. The semiconductor device of any one of examples 1 to 12, wherein the second patterned metallization comprises a portion capacitively coupled to the first device region or the second device region at the backside of the silicon layer.

[0069] Example 14. The semiconductor device of any one of examples 1 to 13, wherein the isolation structure provides vertical electrical routing between the first patterned metallization and the second patterned metallization.

[0070] Example 15. The semiconductor device of example 14, wherein the isolation structure comprises an electrically conductive material laterally separated from the silicon layer by a dielectric material and / or a pn junction, and wherein the electrically conductive material provides the vertical electrical routing between the first patterned metallization and the second patterned metallization.

[0071] Example 16. The semiconductor device of any one of examples 1 to 14, further comprising a silicon via extending through the silicon layer and providing vertical electrical routing between the first patterned metallization and the second patterned metallization.

[0072] Example 17. The semiconductor device of any one of examples 1 to 16, wherein the isolation structure comprises: a plurality of trenches extending through the silicon layer from the front side to the back side and laterally isolating the first device region and the second device region from each other; an electrically conductive material in the trenches; a dielectric material separating the electrically conductive material from the silicon material of the silicon layer; and a silicon mesa between adjacent ones of the trenches, wherein the electrically conductive material in the trenches provides the vertical electrical routing between the first patterned metallization and the second patterned metallization.

[0073] Example 18. The semiconductor device of Example 17, wherein the isolation structure further comprises a silicon plug laterally surrounded by the dielectric material and interrupting the silicon mesa where two or more trenches intersect each other.

[0074] Example 19. The semiconductor device of any one of examples 1 to 18, further comprising: a third insulation layer on the second patterned metallization, wherein the third insulation layer laterally insulates portions of the second patterned metallization from each other.

[0075] Example 20. The semiconductor device of Example 19, further comprising: a substrate or a plurality of contacts on the third insulation layer and electrically connected to the second patterned metallization.

[0076] Example 21. The semiconductor device of Example 19, further comprising: a third patterned metallization on the third insulation layer.

[0077] Example 22. A method for manufacturing a semiconductor device, the method comprising: forming a silicon layer having a thickness in a range of 2 µm to 200 µm between a front side and a back side of the silicon layer; forming a first device region and a second device region that are laterally insulated from each other in the silicon layer by an isolation structure extending from the front side to the back side of the silicon layer; forming a first isolation layer on the front side of the silicon layer; forming a first patterned metallization on the first isolation layer; forming a second isolation layer on the back side of the silicon layer;and forming a second patterned metallization on the second insulation layer, wherein the first patterned metallization provides lateral electrical routing along the front side of the silicon layer, wherein the second patterned metallization provides lateral electrical routing along the back side of the silicon layer;

[0078] Example 23. The method of Example 22, further comprising: after the silicon layer is formed to have a thickness in the range of 10 µm to 200 µm, but before forming both the second insulation layer and the second patterned metallization, areally implanting a dopant species into the backside of the silicon layer.

[0079] Example 24. The method of Example 23, further comprising: after the silicon layer has been formed to have a thickness in the range of 10 µm to 200 µm, but before forming both the second insulating layer and the second patterned metallization, forming a resist layer on the backside of the silicon layer and implanting a dopant species into the backside of the silicon layer through openings in the resist layer.

[0080] Example 25. The method of any one of Examples 22 to 24, further comprising: after the silicon layer has been formed to have a thickness in the range of 10 µm to 200 µm, but before forming the second patterned metallization, forming a resist layer on the second insulating layer and implanting a dopant species into the backside of the silicon layer through openings in the resist layer and the second insulating layer.

[0081] Example 26. The method of any one of examples 22 to 25, wherein forming the second patterned metallization comprises: etching a plurality of openings in the second insulating layer and exposing the backside of the silicon layer; depositing a metal or metal alloy on the second insulating layer and in the plurality of openings; forming a resist layer on the metal or metal alloy; and patterning the metal or metal alloy through openings in the resist layer.

[0082] Example 27. The method of any one of examples 22 to 25, wherein forming the second patterned metallization comprises: etching and filling an opening in the second insulating layer to form a via contacting the backside of the silicon layer; and depositing and etching a metal or metal alloy on the second insulating layer and contacting the via.

[0083] Example 28. The method of any one of examples 22 to 27, further comprising: forming a third insulation layer on the second patterned metallization, wherein the third insulation layer laterally insulates portions of the second patterned metallization from each other.

[0084] Example 29. The method of any one of examples 22 to 28, wherein the isolation structure provides vertical electrical routing between the first patterned metallization and the second patterned metallization.

[0085] Example 30. The method of any one of examples 22 to 29, further comprising: forming a silicon via extending through the silicon layer and providing vertical electrical routing between the first patterned metallization and the second patterned metallization.

[0086] Terms such as "first," "second," and the like are used to describe various elements, regions, sections, etc., and are also not intended to be limiting. Like terms refer to like elements throughout the specification.

[0087] As used herein, the terms "having," "containing," "including," "comprising," and the like are open-ended terms that indicate the presence of specified elements or features but do not preclude additional elements or features. The articles "a," "an," and "the" are intended to include both the plural and singular unless the context clearly indicates otherwise.

[0088] The term "and / or" should be interpreted to include all possible conjunctive and disjunctive combinations, unless expressly stated otherwise. For example, the term "A and / or B" should be interpreted to mean only A, only B, or both A and B. The term "at least one of" should be interpreted in the same way as "and / or" unless expressly stated otherwise. For example, the term "at least one of A and B" should be interpreted to mean only A, only B, or both A and B.

[0089] It is understood that the features of the various embodiments described herein may be combined with one another unless expressly stated otherwise.

[0090] Although specific embodiments have been illustrated and described herein, those skilled in the art will recognize that a variety of alternative and / or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and their equivalents.

Claims

[1] Semiconductor device comprising: a silicon layer having a thickness in a range of 2 µm to 200 µm between a front side and a back side of the silicon layer; a first device region and a second device region laterally insulated from each other in the silicon layer by an isolation structure extending from the front side to the back side of the silicon layer; a first insulating layer on the front side of the silicon layer; a first structured metallization on the first insulation layer; a second insulation layer on the back of the silicon layer; and a second structured metallization on the second insulation layer, wherein the first patterned metallization provides lateral electrical routing along the front side of the silicon layer, wherein the second patterned metallization provides lateral electrical routing along the backside of the silicon layer. [2] The semiconductor device of claim 1, wherein the second patterned metallization contacts the silicon layer at the backside through a plurality of openings in the second insulation layer. [3] The semiconductor device of claim 2, wherein the silicon layer comprises a doped contact region adjacent to each portion of the second patterned metallization that contacts the silicon layer at the backside, and wherein each doped contact region has a higher doping concentration than material of the silicon layer adjacent to the doped contact region. [4] Semiconductor component according to one of claims 1 to 3, wherein the second structured metallization comprises a first portion contacting the silicon layer on the back side through a first opening in the second insulation layer, and a second portion contacting an electrically conductive region of the insulation structure or a silicon via extending through the silicon layer through a second opening in the second insulation layer. [5] Semiconductor component according to claim 4, wherein the first structured metallization contacts the electrically conductive region of the insulation structure or the silicon via through an opening in the first insulation layer. [6] A semiconductor device according to any one of claims 1 to 5, wherein a vertical device is formed in the first device region, wherein the first patterned metallization provides a first power terminal connection to the vertical device at the front side of the silicon layer through at least one opening in the first insulation layer, and wherein the second patterned metallization provides a second power terminal connection to the vertical device at the back side of the silicon layer through at least one opening in the second insulation layer. [7] The semiconductor device of claim 6, wherein the vertical device is a vertical power transistor device, wherein a lateral gate driver is formed in the second device region, and wherein the first patterned metallization electrically connects the lateral gate driver to a gate terminal of the vertical power transistor device. [8] The semiconductor device of claim 6, wherein the vertical device is a light-emitting diode (LED) device, wherein a lateral driver is formed in the second device region, and wherein the first patterned metallization electrically connects the lateral driver to the LED device. [9] A semiconductor device according to any one of claims 1 to 8, wherein the second patterned metallization applies a bias voltage to the first device region at the backside of the silicon layer. [10] The semiconductor device of claim 9, wherein a first device is formed in the first device region and a second device is formed in the second device region, and wherein the first patterned metallization electrically connects the first device and the second device to each other to form a cascode device. [11] A semiconductor device according to claim 10, wherein the first device and the second device have an equal breakdown voltage rating, and wherein in a blocking state of the cascode device, the first device and the second device individually block half the voltage across the cascode device. [12] A semiconductor device according to any one of claims 9 to 11, wherein the first patterned metallization couples the bias voltage to the second patterned metallization through an electrically conductive region of the isolation structure or through a silicon via extending through the silicon layer. [13] A semiconductor device according to any one of claims 1 to 12, wherein the second structured metallization comprises a portion capacitively coupled to the first device region or the second device region at the backside of the silicon layer. [14] The semiconductor device of any one of claims 1 to 13, wherein the isolation structure provides vertical electrical routing between the first patterned metallization and the second patterned metallization. [15] The semiconductor device of claim 14, wherein the isolation structure comprises an electrically conductive material laterally separated from the silicon layer by a dielectric material and / or a pn junction, and wherein the electrically conductive material provides the vertical electrical routing between the first patterned metallization and the second patterned metallization. [16] The semiconductor device of any one of claims 1 to 15, further comprising a silicon via extending through the silicon layer and providing vertical electrical routing between the first patterned metallization and the second patterned metallization. [17] A semiconductor device according to any one of claims 1 to 16, wherein the isolation structure comprises: a plurality of trenches extending through the silicon layer from the front side to the back side and laterally isolating the first device region and the second device region from each other; an electrically conductive material in the trenches; a dielectric material separating the electrically conductive material from the silicon material of the silicon layer; and a silicon mesa between adjacent trenches, wherein the electrically conductive material in the trenches provides the vertical electrical routing between the first structured metallization and the second structured metallization. [18] The semiconductor device of claim 17, wherein the isolation structure further comprises a silicon plug laterally surrounded by the dielectric material and interrupting the silicon mesa where two or more trenches intersect each other. [19] Semiconductor device according to one of claims 1 to 18, further comprising: a third insulation layer on the second structured metallization, wherein the third insulation layer laterally insulates portions of the second structured metallization from one another. [20] A semiconductor device according to claim 19, further comprising: a substrate or a plurality of contacts on the third insulation layer and electrically connected to the second patterned metallization. [21] A semiconductor device according to claim 19, further comprising: a third structured metallization on the third insulation layer. [22] A method of manufacturing a semiconductor device, the method comprising: Forming a silicon layer having a thickness in a range of 2 µm to 200 µm between a front side and a back side of the silicon layer; Forming a first device region and a second device region that are laterally insulated from each other in the silicon layer by an isolation structure extending from the front side to the back side of the silicon layer; Forming a first insulating layer on the front side of the silicon layer; Forming a first patterned metallization on the first insulation layer; Forming a second insulating layer on the back side of the silicon layer; and Forming a second structured metallization on the second insulation layer, wherein the first patterned metallization provides lateral electrical routing along the front side of the silicon layer, wherein the second patterned metallization provides lateral electrical routing along the backside of the silicon layer. [23] The method of claim 22, further comprising: after the silicon layer has been formed to have a thickness in the range of 10 µm to 200 µm, but before forming both the second insulation layer and the second patterned metallization, areally implanting a dopant species into the backside of the silicon layer. [24] The method of claim 23, further comprising: after the silicon layer has been formed to have a thickness in the range of 10 µm to 200 µm, but before forming both the second insulation layer and the second patterned metallization, forming a resist layer on the backside of the silicon layer and implanting a dopant species into the backside of the silicon layer through openings in the resist layer. [25] A method according to any one of claims 22 to 24, further comprising: after the silicon layer has been formed to have a thickness in the range of 10 µm to 200 µm, but before forming the second patterned metallization, forming a resist layer on the second insulating layer and implanting a dopant species into the backside of the silicon layer through openings in the resist layer and the second insulating layer. [26] The method of any one of claims 22 to 25, wherein forming the second patterned metallization comprises: Etching a plurality of openings in the second insulating layer and exposing the backside of the silicon layer; Depositing a metal or metal alloy on the second insulating layer and in the plurality of openings; Forming a resist layer on the metal or metal alloy; and Structuring the metal or metal alloy through openings in the resist layer. [27] The method of any one of claims 22 to 25, wherein forming the second patterned metallization comprises: Etching and filling an opening in the second insulation layer to form a via contacting the backside of the silicon layer; and Depositing and etching a metal or metal alloy on the second insulation layer and which contacts the via. [28] A method according to any one of claims 22 to 27, further comprising: Forming a third insulation layer on the second structured metallization, wherein the third insulation layer laterally insulates portions of the second structured metallization from one another. [29] The method of any one of claims 22 to 28, wherein the isolation structure provides vertical electrical routing between the first patterned metallization and the second patterned metallization. [30] A method according to any one of claims 22 to 29, further comprising: Forming a silicon via extending through the silicon layer and providing vertical electrical routing between the first patterned metallization and the second patterned metallization.

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