Method for repairing faulty memory locations in a memory

Abstract

Method for repairing faulty memory locations in a memory (3) while a program is executed from the memory by a computer (2), wherein the program controls a technical device, characterized in that, during the execution of the program, addresses of faulty memory locations in the memory (3) and correct values ​​of the faulty memory locations are recognized, that the program provides time periods for repairing the faulty memory locations, that the time periods are selected so that the control of the technical device is not hindered, and that for the repair, the faulty memory locations are written with the correct values.

Description

State of the art

[0001] The invention relates to a method for repairing defective memory locations according to the preamble of the independent claim. This method is carried out while a computer simultaneously executes a program for controlling a technical device from the memory. Methods for detecting defective memory locations or memory locations that exhibit a deterioration in the quality of the stored data are already known from US 2015 / 0255164 A1. Advantages of the invention

[0002] In contrast, the method according to the invention has the advantage that the repair of the defective memory locations takes place while a program for controlling a technical device is being executed from memory by the computer. It is therefore not necessary to provide a separate operating mode in which the memory locations are checked and repaired. The method according to the invention can thus appear to occur simultaneously for a user of the computer and does not require an interruption of the normal operation of the computer. This can improve the operational reliability of the computer during the control of a technical device.

[0003] Further advantages and improvements arise from the features of the dependent patent claims. By specifying fixed times for the repair durations, the correct functioning of the memory can be reliably planned. Prioritizing the repair durations allows for greater flexibility in using the computer for controlling the technical device and for repairing the memory. This enables more flexible use of the computer's available time. Faulty memory locations can be detected using error-detecting codes, and the correct values ​​can be determined using error-correcting codes. However, this requires a correspondingly larger number of bits to protect the memory locations. Alternatively, methods that utilize the physical properties of the memory locations can be employed.However, this requires appropriate hardware for evaluating the physical properties of the memory locations. Checking the memory locations is particularly straightforward if they are already being read during the execution of the program that controls the technical device. To ensure that all areas of the memory are checked, additional time intervals can be allocated specifically for identifying faulty memory locations. This ensures that all areas of the memory are reliably checked. Drawings

[0004] Exemplary embodiments of the invention are illustrated in the drawing and explained in more detail in the following description. It shows the Fig. 1 a computer and a memory for the method according to the invention, Fig. 2 a first procedure for temporal allocation, and Fig. 3 a second method of temporal allocation.. Description

[0005] In the Fig. Figure 1 schematically depicts a control unit 1 with a computer 2 and a memory 3. The control unit 1 has a multitude of output lines and input lines 4 through which the control unit 1 controls an external technical device or reads sensor signals from the external technical device. Such a technical device could, for example, be a motor vehicle whose functions are controlled by the control unit 1.

[0006] Control unit 1 performs a multitude of functions seemingly simultaneously. To achieve this, computer 2 processes programs stored in memory 3. At any given time, the computer can only execute one instruction from the programs stored in memory 3. To nevertheless process a large number of tasks seemingly simultaneously, the programs are divided into individual subprograms, and switching between different subprograms is so rapid that simultaneous processing appears to occur.

[0007] This form of processing individual program parts is commonly referred to as multitasking. Each of these subprograms performs a different function, seemingly simultaneously. This means that the controlled technical device must tolerate short periods or durations during which no new responses are received from the control unit 1. The control of a motor vehicle's engine can serve as an example of such periods. Such an engine typically has a speed of 6000 rpm (revolutions per minute), i.e., 100 rpm / sec. Therefore, in a four-cylinder engine, 200 combustion processes must be controlled per second, meaning, on average, one combustion process every 2.5 msec. Between these points in time, when a combustion process is being calculated, other functions, such as monitoring and diagnostics of the controlled technical device or the control unit, can take place.This approach of performing various different functions by processing and switching between functions at different times is typically referred to as multitasking.

[0008] The one in the Fig. The memory 3 shown in Figure 1 is typically implemented using transistors that have a gate on which electrical charges can be stored. The switching behavior of the transistors forming the memory locations is influenced by the stored electrical charges when a voltage is applied to a select line or address line. However, errors can occur with this type of bit value storage if the stored charge changes. The reliability of the storage depends on the quality of individual insulation layers, which allow a certain loss of charge over time, resulting in degraded bit value recognition when a memory cell is read.To ensure the reliable operation of control unit 1 over a long period, it is therefore necessary to regularly check memory 3 and, if necessary, initiate a repair if a memory cell error is detected. The repair consists of rewriting the memory location by applying the correct charge to the gate. For such a repair, it is first necessary to detect faulty memory cells. One way to detect faulty memory cells is to use error-detection codes. A particularly simple error-detection code, for example, involves assigning a parity bit to a specific number of bit values. With such a simple code, a single-bit error can be detected, for instance. However, there are other common coding methods that allow not only the detection of bit errors but also their correction.By using such error-detecting and error-correcting encoding methods of the data in memory 3, it is thus possible to recognize which bit values ​​in memory 3 are faulty and what the correct value for the bit of a particular memory location is.

[0009] Another method for detecting faulty memory locations involves checking a physical value, dependent on the stored electrical charge, when reading the memory cell. Typically, a read voltage is applied to the memory cell, and the cell's response to this voltage is observed. The first read voltage value corresponds to a bit value of 0, and the next read voltage value corresponds to a bit value of 1. Based on the read voltage or its temporal evolution, regions can be identified where the bit value is still unambiguous and therefore reliable, but where degradation of the memory, i.e., a reduced amount of charge on the gate, is detected.Thus, two different states of the memory location can be distinguished: one classified as reliable and good, and the other as reliable but problematic. This "reliable and problematic" state can be restored to a "reliable and good" state by rewriting the memory location. These methods for detecting a still-correct but slightly degraded memory location are called "margin read" methods and allow for the detection of slow degradation of memory cells. Such "margin read" methods are described, for example, in patent application US 20150255164 A1.

[0010] The detection of faulty memory cells can be achieved by the computer using various methods during program execution. A particularly simple method involves the computer core 2 continuously checking the data read from memory 3 during the execution of a standard program for controlling the technical device. This check is performed using both an error-detecting and an error-correcting code. If, for example, a faulty value for a single bit in a memory location is detected, the error-correcting code corrects this so that only the corrected data, i.e., error-free data, is used by the computer core 2 for executing the control program. Furthermore, the address of the faulty value and the correct value for that faulty memory location are stored at this point.The correct value can then be written to the memory cell either immediately or at a later time, once sufficient time is available for memory repair. Using error-correcting code that can correct a higher number of bit errors allows for the detection and correction of correspondingly more bit errors.

[0011] Alternatively, processing core 2 can continuously check memory 3 for individual bit errors, either through error detection code or the margin read procedure described above. In addition to the planned repair time, further time is allocated for detecting faulty memory locations. This additional time can also be used as an alternative to the repair time, since memory repair only occurs if a faulty memory location has been detected. These two methods for detecting faulty memory locations can also be used together. For program components that are regularly executed by the computer, any faulty memory locations are detected and repaired through this regular execution.For program sections that are rarely used, additional time intervals can be allocated to regularly check and, if necessary, repair the memory locations for these program sections. Methods for multitasking are described below to enable such continuous checking without affecting the simultaneous control of the technical device.

[0012] An important contribution to the implementation of the procedure for repairing faulty memory locations lies in the fact that the detection of faulty memory locations and the actual repair are separated in time. The actual repair consists of programming a predefined value into a memory cell, whereby the predefined value has previously been determined to be the correct value. However, the identification of faulty memory cells and the storage of the correct value in the memory cell can be separated in time; that is, the identification and the correction do not have to occur in a single process step. This results in each individual step being very short, thus preventing significant delays in the execution of the normal control of the technical device's function. In particular, the repair steps, i.e.,Writing a memory cell with a predetermined value can be very short in time and therefore does not lead to any significant delays in the execution of the program for controlling the technical device.

[0013] In principle, two different types of multitasking are possible, and in particular multitasking involving the control of a technical system and the repair of memory.

[0014] A first method for multitasking is based on the Fig. 2 explained. In the Fig. Figure 2 plots a time axis to the right, showing the corresponding activity of the processing core 2 with subprograms. A fixed distribution of durations or time periods for processing individual subprograms is assumed. The time axis shows a period of approximately 1 ms between times 1.000 and 1.001 seconds. At each full millisecond, a memory cell is repaired, with a duration of 25 µs allocated for this repair. This means that a memory cell is repaired within the time period 21, from 1.000 to 1.000025 seconds. Memory cell repairs are performed only for this very short duration, which, due to the brevity of the time, does not lead to any significant delays in the execution of the normal program for controlling the technical device.The time interval 22, between 1.000025 and 1.001 seconds, is entirely available for executing the normal program for controlling the technical device. Within this short interval of 25 µs, for example, a memory cell previously identified as faulty can be written with the correct value. Alternatively, within this time interval, a single memory cell can be identified as faulty, and the address of this faulty memory cell and the correct value of the memory cell can be stored. Since only a very short time is allocated for memory repair, it will take a very long time overall until a complete check and repair of memory 3 has been carried out.However, this is not critical if the rate of errors occurring is so low that no multiple errors that cannot be corrected with the error-correcting code used occur during the time required for a complete check, or if the correct charge level of a single memory cell can no longer be determined with the "margin read" method used.

[0015] Another method for multitasking is based on… Fig.Section 3 explains this. It is assumed that the memory contains three different program parts, each assigned a different priority. These individual program parts compete for the processing time of the processor core, with higher-priority program parts prevailing over lower-priority program parts. Program parts for controlling the technical device are assigned a high priority, while a program part for repairing faulty memory cells is assigned only a low priority. At time 1000, a program for calculating the necessary control signals for controlling the technical device is started, as this program part has the highest priority at time 1000.This program section for calculating the necessary control signals for controlling the technical device has a high priority and is therefore processed first by the processing core 2 compared to other program sections with a lower priority. The processing of this program section for controlling the technical device 31 lasts until time 1.0005 seconds, so that the processing core does not perform any tasks for controlling the technical device between time 1.0005 and 1.001 seconds. This time window 32 between 1.0005 and 1.001 seconds can then be used for other tasks with a lower priority; in particular, a procedure for repairing faulty memory cells can be carried out during this time.For the overall function of the control unit, the only important question is how quickly it can switch from processing a low-priority task (repairing memory cells) to a high-priority task (controlling the technical device). If this switchover occurs very quickly, the control of the technical device is not hindered. Even with such a procedure, the identification of faulty memory locations and their repair must be distinguished. Regarding the identification of faulty memory locations, the actual process of identifying the faulty memory locations does not need to be completed. It only needs to be ensured that the correct memory locations are considered during the next identification.

[0016] When repairing memory locations, i.e., writing the correct bit value to individual memory locations, it is advantageous if the actual storage process is not interrupted, so as not to leave a memory location with an incomprehensible or unclear value of the stored bit or load. Since this process can be completed very quickly, however, it does not cause a long delay for a program controlling the technical device with high priority.Even if the time period is insufficient to completely program the memory location, this is acceptable for the system, since, for example, further programming can be carried out in the next period of time for the repair of the memory locations, and in the meantime, the technical function can be maintained despite the faulty memory location thanks to the error-correcting code, as the correction by the error-correcting code provides the computing unit with correct (corrected) content. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents cited by the applicant was automatically generated and is included solely for the reader's convenience. The list is not part of the German patent or utility model application. The DPMA accepts no liability for any errors or omissions. Cited patent literature

[0000] US 2015 / 0255164 A1 [0001, 0009]

Claims

[1] Method for repairing faulty memory locations of a memory (3) while a program from the memory (3) is executed by a computer (2), wherein the program controls a technical device, characterized by that during the execution of the program, addresses of faulty memory locations in the memory (3) and correct values ​​of the faulty memory locations are recognized that the program provides time periods for repairing the faulty memory locations, that the time periods are selected such that the control of the technical device is not hindered, and that the faulty memory locations are written with the correct values ​​for the repair. [2] Method according to claim 1, characterized by that the computer (2) provides a period of time for the repair at fixed times, and that the program for controlling the technical device is processed before and after the fixed periods of time. [3] Method according to claim 1, characterized by that different program parts in the program are assigned different priorities, that a program part with a high priority interrupts the processing of a program part with a lower priority by the computer, and that a program part with a time period for repairing the faulty memory locations has a lower priority compared to a program part for controlling the technical device. [4] Method according to claim 1, characterized by that the memory locations contain information encoded with an error-detecting and error-correcting code, that an erroneous memory location and the correct value are detected by evaluating the code. [5] Method according to claim 1, characterized bythat the memory locations are read out using a method which specifies a physical property of the information stored in the memory location, the physical property being classified as reliable and good or reliable and problematic, and that the memory locations whose information was classified as reliable and problematic are changed to the state of reliable and good by re-storing the information in the memory location. [6] Method according to claim 4 or 5, characterized by that when the computer executes the program from memory, faulty memory locations are detected. [7] Method according to claim 4 or 5, characterized by that the program provides additional time periods in which faulty memory locations are detected.

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