HALF-BRIDGE MODULE WITH REVERSE-CONNECTED DIODES

Abstract

A half-bridge module (10) comprises a substrate (18) formed from an insulating layer (20) and a conductive layer (22), the conductive layer (22) being structured into a DC+ region (DC+), an AC region (AC), and a DC- region (DC-); a first semiconductor switch chip (12a) bonded to the DC+ region (DC+) and electrically connected to the AC region (AC) by wire bonds (28); a first diode chip (14a) bonded to the AC region (AC) with an anode side (D+) and electrically connected to the DC+ region (DC+) with the cathode side (D-) by wire bonds (30); a second semiconductor switch chip (12b) bonded to the AC region (AC) and electrically connected to the DC- region (DC-) by wire bonds (32);and a second diode chip (14b) having an anode side (D+) bonded to the DC region (DC-) and having a cathode side (D-) electrically connected to the AC region (AC) by wire bonds (34);

Description

[0001] The invention relates to a half-bridge module.

[0002] In automotive applications with electric drives, such as electric cars and electric trucks, half-bridge modules are used to assemble inverters that generate the alternating current required to drive an electric motor from a direct current that can be provided by an electric battery. Currently, such half-bridge modules contain Si semiconductors. However, due to their higher operating voltages and the potentially higher switching frequencies, which can lead to lower losses and more efficient application of half-bridge modules, the use of wide-bandgap semiconductors is also being considered. Such power semiconductor modules based on wide-bandgap semiconductors can benefit from new module designs to reduce electromagnetic radiation and electromagnetic losses and to improve local cooling capabilities.

[0003] Therefore, it is an object of the present invention to provide a power semiconductor module that mitigates the above-mentioned problems. This object is achieved by the subject matter of the independent claims. Advantageous embodiments are recited in the dependent claims.

[0004] A first aspect of the invention relates to a half-bridge module. In general, a semiconductor module is a device for mechanically and electrically interconnecting semiconductor chips. The half-bridge module comprises semiconductor chips interconnected to form a half-bridge. The half-bridge module can be a power half-bridge module. Here and below, the term "power" refers to devices and elements configured to process voltages of more than 100 V and / or more than 10 A.

[0005] According to one embodiment, the half-bridge module comprises: a substrate formed from an insulating layer and a conductive layer, wherein the conductive layer is structured into a DC+ region, an AC region, and a DC- region; a first semiconductor switch chip having a positive terminal bonded to the DC+ region and a negative terminal electrically connected to the AC region by wire bonds; a first diode chip having an anode side bonded to the AC region and a cathode side electrically connected to the DC+ region by wire bonds; a second semiconductor switch chip having a positive terminal bonded to the AC region and a negative terminal electrically connected to the DC- region by wire bonds; a second diode chip having an anode side bonded to the DC- region and a cathode side electrically connected to the AC region by wire bonds.

[0006] The substrate can be a DBC (Direct Bonded Copper) substrate, i.e., one or two copper layers on a ceramic layer. The substrate can be an IMS (Insulated Metal Substrate) substrate with an electrically insulating layer made of a polymer filled with ceramic particles. The conductive layer can be made of metal, such as copper or aluminum. The electrically insulating layer can be made of plastic and / or ceramic.

[0007] The semiconductor switch chips and the diode chips are connected to form a half-bridge, i.e. two semiconductor switch chips connected in series and a freewheeling diode chip connected antiparallel to each semiconductor switch chip.

[0008] The semiconductor switch chips and the diode chips are connected to the conductive layer on one side. Here and in the following, bonding can refer to a process for electrically and mechanically connecting two metallic elements, such as soldering, welding, and sintering. On the other, opposite side, the semiconductor switch chips and the diode chips are connected with wire bonds to form the electrical connections. A wire bond can be a metal wire or metal strip.

[0009] Each semiconductor switch chip may include a positive terminal on a positive terminal side and a negative terminal on a negative terminal side opposite the positive terminal side. Each semiconductor switch chip is configured to switch a current from the positive terminal to the negative terminal. To this end, the semiconductor switch chip may include a control terminal for controlling the resistance of the path between the positive and negative terminals.

[0010] Such semiconductor switch chips (as well as diode chips) may comprise a plastic package enclosing a die made of a semiconductor material that provides the chip's functionality. The semiconductor switch chips may provide and / or be transistors or thyristors. The positive terminal, the negative terminal, and the control terminal may be provided as electrodes on the chip's package.

[0011] Each diode chip includes an anode on the anode side and a cathode on the cathode side opposite the anode side, designed to block current from the cathode to the anode. In the case of a diode chip, the anode may be labeled with a positive side, and the cathode may be labeled with a negative side.

[0012] The first semiconductor switch chip and the first diode chip are arranged on the substrate in the same conduction direction and electrically connected to each other in antiparallel. The same applies to the second semiconductor switch chip and the second diode chip. The diode chips are mounted with their anode side to the substrate, which may have a heat sink on its opposite side, so that the anode side of the diode chips is better cooled than the cathode side. Typically, the heat-generating layer in a diode chip is located more on the anode side than on the cathode side.

[0013] This arrangement has the advantage that the anode side of the diode chip can be cooled better than the cathode side, since a heat sink is typically attached to the side of the substrate opposite the chips. In particular, for a gallium oxide diode and other wide-bandgap materials, thermal conduction is up to a factor of 1 / 10 worse than for silicon, and most of the heating within the diode occurs near the anode layer and / or anode side. The distance of the heating layer in the diode chip from the anode side can be approximately 2µ to 10µ, while the distance from the cathode side can be approximately 70µ to 500µ. Cooling the anode side results in more effective heat transfer.

[0014] According to one embodiment, the DC+ region, the AC region, and the DC- region are rectangular regions arranged in an extension direction of the half-bridge module. As already mentioned, the conductive layer is structured into the DC+ region, the AC region, and the DC- region. The term "structured" may mean that the DC+ region, the AC region, and the DC- region are not electrically connected to each other by parts of the conductive layer. They are electrically connected solely by additional elements, such as wire bonds, etc. It should be understood that, in this context, conductive means electrically conduct and insulating means electrically insulate.

[0015] According to one embodiment, the DC+ region, the first semiconductor switch chip, the first diode chip, the second semiconductor switch chip and the second diode chip are arranged in this order along the extension direction in which the DC+ region, the AC region and the DC- region are also arranged one behind the other.

[0016] According to one embodiment, each of the first diode chip and the second diode chip comprises a gallium oxide diode. In general, each diode chip may be based on a wide-bandgap semiconductor, and / or the corresponding die may be made of a wide-bandgap material. In particular, the diode chip may comprise a gallium oxide diode. A gallium oxide diode (e.g., a β-Ga2O3 diode) has low losses and is better suited for processing high frequencies than a silicon diode. The diode may be a Schottky diode.

[0017] According to one embodiment, both the first semiconductor switch chip and the second semiconductor switch chip provide a bipolar transistor, in particular a bipolar n-channel transistor, for example, an IGBT. In this case, the positive terminal is the collector, the negative terminal is the emitter, and the control terminal is the base.

[0018] According to one embodiment, both the first semiconductor switch chip and the second semiconductor switch chip provide a field-effect transistor, for example, a MOSFET. In this case, the positive terminal is the drain, the negative terminal is the source, and the control terminal is the gate.

[0019] According to one embodiment, both the first semiconductor switch chip and the second semiconductor switch chip provide a thyristor. In this case, the positive terminal is the anode, the negative terminal is the cathode, and the control terminal is the gate.

[0020] The semiconductor switch chips can be based on a wide-bandgap semiconductor, and / or the corresponding die can be made of a wide-bandgap material. For example, the semiconductor switch chip is based on GaN (gallium nitride) or SiC (silicon carbide). Such a semiconductor switch chip enables higher switching frequencies and / or higher operating voltages. However, it is also possible for the semiconductor switch chip to be based solely on silicon.

[0021] According to one embodiment, the half-bridge module comprises a heat sink connected to the substrate opposite the semiconductor switch chips and the diode chips. The heat sink may be bonded or otherwise attached to the substrate opposite the conductive layer to which the semiconductor switch chips and the diode chips are connected. The heat sink may, for example, be an air-cooled heat sink or a liquid-cooled heat sink.

[0022] According to one embodiment, the half-bridge module is a multi-half-bridge module, i.e., it comprises at least two half-bridges and / or sub-modules configured as described above. The semiconductor switch chips and / or diode chips of the multi-half-bridge module can be configured as described above.

[0023] According to one embodiment, the multi-half-bridge module comprises: a substrate formed from an insulating layer and a conductive layer, wherein the conductive layer is structured into a plurality of DC+ regions, an AC region, and a plurality of DC- regions; a plurality of first semiconductor switch chips, each first semiconductor switch chip being bonded to a DC+ region and connected to the AC region by wire bonds; a plurality of first diode chips, each first diode chip having an anode side bonded to the AC region and having a cathode side electrically connected to a DC+ region by wire bonds; a plurality of second semiconductor switch chips, each second semiconductor switch chip being bonded to the AC region and connected to a DC- region by wire bonds;a plurality of second diode chips, each second diode chip having an anode side bonded to a DC region and having a cathode side electrically connected to the AC region by wire bonds;

[0024] If the multi-half-bridge module is divided into parts, it may comprise a half-bridge module as described above. However, the multi-half-bridge module includes more than one DC+ region and more than one DC- region. More than one semiconductor switch chip may be bonded to each of the DC+ regions and the AC region. More than one diode chip may be bonded to the DC- region.

[0025] According to one embodiment, a DC+ region, the AC region, and a DC- region are arranged in this order along a first extension direction of the multi-half-bridge module. In the first extension direction, a part of the multi-half-bridge module can be configured as described above.

[0026] According to one embodiment, the AC region extends in a second extension direction of the multi-half-bridge module. The AC region may be wider than both the DC+ regions and the DC- regions. The DC+ regions and DC- regions may be arranged along rows adjacent to the AC region in the second extension direction. A first row of DC+ regions and DC- regions may be located along one side of the AC region. A second row of DC+ regions and DC- regions may be located along a second side of the AC region.

[0027] According to one embodiment, DC+ regions and DC- regions are arranged along rows and alternate within the rows. In both the first and second rows, the DC+ regions and DC- regions alternate, i.e., a DC+ region is followed by a DC- region and vice versa. The first row and the second row may be mirror-symmetrical, but with a DC+ region replaced by a DC- region and vice versa.

[0028] According to one embodiment, only a first semiconductor switch chip is bonded to a DC+ region. One semiconductor switch chip may be present per DC+ region.

[0029] According to one embodiment, only a second diode chip is bonded to a DC region. One diode chip may be present per DC region.

[0030] According to one embodiment, at least two first semiconductor switch chips are bonded to a DC+ region. More than one semiconductor switch chip may be present per DC+ region.

[0031] According to one embodiment, at least two second diode chips are bonded to a DC region. More than one diode chip may be present per DC region.

[0032] These and other aspects of the invention will become apparent and explained with reference to the embodiments described below.

[0033] Hereinafter, embodiments of the present invention will be described in more detail with reference to the attached drawings. Fig. 1 shows a circuit diagram of a half-bridge module according to an embodiment of the invention. Fig. 2 shows a schematic cross-sectional view of a half-bridge module according to an embodiment of the invention. Fig. 3 shows a schematic plan view of a half-bridge module according to an embodiment of the invention. Fig. 4 shows a schematic top view of a multi-half-bridge module according to an embodiment of the invention. Fig. 5 shows a schematic top view of a multi-half-bridge module according to an embodiment of the invention.

[0034] The reference symbols used in the drawings and their meanings are summarized in the following list of reference symbols. Identical parts in the figures are generally provided with the same reference symbols.

[0035] Fig. Figure 1 shows a circuit diagram of a half-bridge module 10 comprising two semiconductor switch chips 12a, 12b electrically connected in series. A freewheeling diode chip 14a, 14b is connected in antiparallel to each semiconductor switch chip 12a, 12b. Each semiconductor switch chip 12a, 12b comprises a positive terminal T+, a negative terminal T-, and a control terminal 16. Each diode chip 14a, 14b comprises an anode D+ and a cathode D-.

[0036] The positive terminal T+ of the first semiconductor switch chip 12a and the cathode D- of the first diode chip 14a are interconnected and connected to a DC+ terminal of the half-bridge module 10. The negative terminal T- of the second semiconductor switch chip 12b and the anode D+ of the second diode chip 14b are interconnected and connected to a DC- terminal of the half-bridge module 10.

[0037] The negative terminal T- of the first semiconductor switch chip 12a, the anode D+ of the first diode chip 14a, the positive terminal T+ of the second semiconductor switch chip 12b and the cathode D- of the second diode chip 14b are connected to each other and are connected to an AC terminal of the half-bridge module 10.

[0038] The diode chips 14a, 14b may provide a gallium oxide diode, in particular made of β-Ga2O3, and / or they may be a Schottky diode.

[0039] The semiconductor switch chips 12a, 12b may provide a bipolar transistor, such as an IGBT, a field-effect transistor, such as a MOSFET, or a thyristor. The semiconductor switch chips 12a, 12b may be made of a wide-bandgap material.

[0040] Fig. 2 shows a schematic cross-sectional view of a half-bridge module 10 in which the semiconductor switch chips 12a, 12b and the diode chips 14a, 14b are bonded to a substrate 18. Fig. 3 shows a top view of the half-bridge module 10.

[0041] The substrate 18 is formed from an insulating layer 20 disposed between two conductive layers 22, 24. The substrate 18 can be a printed circuit board, an IMS (Insulated Metal Substrate) substrate, or a DBC (Direct Bonded Copper) substrate. The conductive layer 24 is optional. It is also possible for the substrate 18 to comprise more than three layers.

[0042] The semiconductor switch chips 12a, 12b and the diode chips 14a, 14b are bonded to the conductive layer 22. The conductive layer 22 is patterned and divided into a DC+ region connected to the DC+ terminal, an AC region connected to the AC terminal, and a DC- region connected to the DC- terminal. The semiconductor switch chip 12a is connected to the DC+ region, the diode chip 14a and the semiconductor switch chip 12b are connected to the AC region, and the diode chip 14b is connected to the DC- region.

[0043] A heat sink 26 is attached to the substrate 18, and in particular to the conductive layer 24. The heat sink 26 can be bonded or otherwise attached to the backside of the substrate 18 opposite the semiconductor switch chips 12a, 12b and the diode chips 14a, 14b. The heat sink 26 can be any cooling element and / or can be based on air and water cooling. Active and passive cooling are also possible.

[0044] There are further electrical connections to connect the chips 12a, 12b, 14a, 14b to a half bridge, as shown in Fig. 1. The first semiconductor switch chip 12a is electrically connected to the AC region by its negative terminal T- via wire bonds 28. The first diode chip 14a is electrically connected to the DC+ region by its cathode side D- via wire bonds 30. The second semiconductor switch chip 12b is electrically connected to the DC- region by its negative terminal T- via wire bonds 32. The second diode chip 14b is electrically connected to the AC region by its cathode side D- via wire bonds 34.

[0045] In this way, the diode chips 14a, 14b are arranged geometrically parallel and / or in the same conduction direction as the semiconductor switch chips 12a, 12b with respect to the positive terminals T+ and the negative terminals T-. This is advantageous with regard to cooling. Electrically, the diode chips 14a, 14b are connected antiparallel to the respective semiconductor switch chips 12a, 12b.

[0046] In particular, when each of the diode chips 14a, 14b provides a gallium oxide diode and / or a diode made of other wide bandgap materials, thermal conduction is poorer than in silicon. Furthermore, most of the heating in the diode chips 14a, 14b occurs near the anode layer and / or anode D+. The distance of the layer in the diode chip 14a, 14b where most of the heat is generated from the anode D+ may be approximately 2µ to 10µ, while the distance of this layer from the cathode D- may be approximately 70µ to 500µ. Thus, cooling the side of the diode chip 14a, 14b with the anode D+ facing the heat sink 26 results in more effective heat transfer.

[0047] As in Fig. As can be seen in Figure 4, the DC+ region, the AC region, and the DC- region are rectangular regions arranged side by side and / or one behind the other in the extension direction of the half-bridge module 10. The first semiconductor switch chip 12a, the first diode chip 14a, the second semiconductor switch chip 12b, and the second diode chip 14b are arranged in this order along this extension direction.

[0048] Fig. 4 shows a multi-half-bridge module 40, which is formed from several parts designed like the half-bridge module 10. In Fig. 4, these parts are defined by the rows of chips 12a, 14a, 12b, 14b running from top to bottom or from bottom to top; this direction is considered as the first extension direction of the multi-half-bridge module 40.

[0049] In general, the multi-half-bridge module 40 comprises: a substrate 18 formed from an insulating layer 20 and a conductive layer 22, wherein the conductive layer 22 is structured into a plurality of DC+ regions, an AC region, and a plurality of DC- regions; a plurality of first semiconductor switch chips 12a, each first semiconductor switch chip 12a being bonded to a DC+ region and electrically connected to the AC region by wire bonds 28; a plurality of first diode chips 14a, each first diode chip 14a having an anode side D+ bonded to the AC region and a cathode side D- electrically connected to a DC+ region by wire bonds 30; a plurality of second semiconductor switch chips 12a, each second semiconductor switch chip 12a being bonded to the AC region and electrically connected to a DC- region by wire bonds 32;a plurality of second diode chips 14b, each second diode chip 14b having an anode side D+ bonded to a DC- region and having a cathode side D- electrically connected to the AC region by wire bonds;

[0050] Fig. 4 also shows that the conductive layer 22 is additionally structured into control regions to which the control terminals 16 of the semiconductor switch chips 12a, 12b are connected via wire bonds 44.

[0051] The multi-half-bridge module 40 includes an AC region and a plurality of DC+ regions, as well as a plurality of DC- regions. For each part extending in the first extension direction, a DC+ region, the AC region, and a DC- region are arranged in that order along the first extension direction. The AC region extends in a second extension direction that is orthogonal to the first extension direction. The DC+ regions and DC- regions are arranged along rows 46, 48 in the second extension direction adjacent to the AC region.

[0052] In Fig. 4, there is a DC+ region and a DC- region on each side of the AC region. Two semiconductor switch chips 12a, 12b are bonded to both the DC+ region and the DC- region. In general, it is possible for at least two first semiconductor switch chips 12a to be bonded to a DC+ region and / or for at least two second diode chips 14b to be bonded to a DC- region.

[0053] Placing the same number of DC+ and DC- regions on either side of the AC regions results in the same number of clockwise and counterclockwise current loops. This can reduce the EMC caused by Module 40 because the electromagnetic fields generated by the current loops cancel each other out.

[0054] Fig. 5 shows a module with several half-bridges 40, which, like the one in Fig. 4 is formed from several parts which are designed like the half-bridge module 10. In Fig.5, there are two DC+ regions and two DC- regions on each side of the AC region. The DC+ and DC- regions also alternate within rows 46, 48. Only a first semiconductor switch chip 12a is bonded to a DC+ region. And only a second diode chip 14b is bonded to a DC- region. Such a design results in smaller current loops and lower stray inductance.

[0055] While the invention has been particularly illustrated and described in the drawings and foregoing description, such illustration and description are to be considered as illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments. Those skilled in the art, in practicing the claimed invention, can recognize and make other variations of the disclosed embodiments upon a careful examination of the drawings, the disclosure, and the appended claims. In the claims, the term "comprising" does not exclude other elements or steps, and the indefinite article "a" does not exclude plurals. A single processor or controller or other unit may perform the functions of multiple elements recited in the claims.The mere fact that certain measures are recited in different dependent claims does not mean that a combination of those measures cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope of protection. List of reference symbols 10 half-bridge module 12a first semiconductor switch chip 12b second semiconductor switch chip 14a first diode chip 14b second diode chip T+ positive connection T- negative connection 16 Control connection D+ anode D-cathode DC+ DC+ range DC-DC range AC AC range 18 Main substrate 20 insulating layer 22 first conductive layer 24 second conductive layer 26 heat sink 28 wire bond 30 wire bonds 32 wire bond 34 wire bond 40 multi-half-bridge module 42 Tax area 44 Wire Bond 46 first row 48 second row

Claims

[1] Half-bridge module (10), comprising: a substrate (18) formed from an insulating layer (20) and a conductive layer (22), the conductive layer (22) being structured into a DC+ region (DC+), an AC region (AC), and a DC- region (DC-); a first semiconductor switch chip (12a) bonded to the DC+ region (DC+) and electrically connected to the AC region (AC) by wire bonds (28); a first diode chip (14a) having an anode side (D+) bonded to the AC region (AC) and having a cathode side (D-) electrically connected to the DC+ region (DC+) by wire bonds (30); a second semiconductor switch chip (12b) bonded to the AC region (AC) and electrically connected to the DC region (DC-) by wire bonds (32); a second diode chip (14b) having an anode side (D+) bonded to the DC- region (DC-) and having a cathode side (D-) electrically connected to the AC region (AC) by wire bonds (34). [2] Half-bridge module (10) according to claim 1, wherein the DC+ region (DC+), the AC region (AC) and the DC- region (DC-) are rectangular regions arranged in the extension direction of the half-bridge module (10); wherein the first semiconductor switch chip (12a), the first diode chip (14a), the second semiconductor switch chip (12b) and the second diode chip (14b) are arranged in this order along the extension direction. [3] Half-bridge module (10) according to claim 1 or 2, wherein both the first diode chip (14a) and the second diode chip (14b) comprise a gallium oxide diode. [4] Half-bridge module (10) according to one of the preceding claims, wherein both the first semiconductor switch chip (12a) and the second semiconductor switch chip (12b) provide a bipolar transistor; or wherein both the first semiconductor switch chip (12a) and the second semiconductor switch chip (12b) provide a field effect transistor; or wherein both the first semiconductor switch chip (12a) and the second semiconductor switch chip (12b) provide a thyristor. [5] Multi-half-bridge module (40), comprising: a substrate (18) formed from an insulating layer (20) and a conductive layer (22), the conductive layer (22) being structured into a plurality of DC+ regions (DC+), an AC region (AC), and a plurality of DC- regions (DC-); a plurality of first semiconductor switch chips (12a), each first semiconductor switch chip (12a) being bonded to a DC+ region (DC+) and electrically connected to the AC region (AC) by wire bonds (28); a plurality of first diode chips (14a), each first diode chip (14a) having an anode side (D+) bonded to the AC region (AC) and electrically connected to the cathode side (D-) by wire bonds (30) to a DC+ region (DC+); a plurality of second semiconductor switch chips (12b), each second semiconductor switch chip (12b) being bonded to the AC region (AC) and electrically connected to a DC region (DC-) by wire bonds (32); a plurality of second diode chips (14b), each second diode chip (14b) having an anode side (D+) bonded to a DC- region (DC-) and having a cathode side (D-) electrically connected to the AC region (AC) by wire bonds. [6] The multi-half-bridge module (40) according to claim 5, wherein a DC+ region (DC+), the AC region (AC), and a DC- region (DC) are arranged in this order along a first extension direction of the multi-half-bridge module (40). [7] Multi-half-bridge module (40) according to claim 5 or 6, wherein the AC region (AC) extends in a second extension direction of the multi-half-bridge module (40); wherein the DC+ regions (DC+) and DC- regions (DC-) are arranged along rows (46, 48) in the second extension direction adjacent to the AC region (AC). [8] Multi-half-bridge module (40) according to one of claims 5 to 7, wherein DC+ regions (DC+) and DC- regions (DC-) are arranged along rows (46, 48) and alternate within the rows (46, 48). [9] Multi-half-bridge module (40) according to one of claims 5 to 8, wherein only a first semiconductor switch chip (12a) is bonded to a DC+ region (DC+); and / or wherein only a second diode chip (14b) is bonded to a DC--region (DC-). [10] Multi-half-bridge module (40) according to one of claims 5 to 9, wherein at least two first semiconductor switch chips (12a) are bonded to a DC+ region (DC+); and / or wherein at least two second diode chips (14b) are bonded to a DC--region (DC-).

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