ELECTRONIC SYSTEM WITH AN INTEGRATED MASTER CIRCUIT AND AN INTEGRATED SLAVE CIRCUIT

Abstract

The present disclosure relates to an electronic system (200) comprising a master IC (110), a slave IC (120), and a serial communication interface (230) having a bidirectional data line and a clock line, wherein the communication interface (230) is configured to transmit data between the master IC (110) and the slave IC (120). The master IC (110) is configured to send a data request command (140; 144) to the slave IC (120) via the data line. The slave IC (120) is configured to begin providing requested data (160) in response to the data request command (140; 144). The master IC (110) is designed to send a data read command (150; 152) for reading the requested data (160) to the slave IC (120) via the data line after the data request command (140; 144).The slave IC (120) is configured to deactivate the clock line upon receipt of the data read command (150; 152) until the slave IC (120) can provide the requested data (160). The master IC (110) is configured to measure a time duration for which the clock line is deactivated. The master IC (110) is configured to set a waiting time between a next data request command (140; 144) and a next data read command (150; 152) according to the measured time duration.

Description

Technical area

[0001] The present disclosure relates to electronic systems comprising a master integrated circuit (master IC) and a slave IC. A serial communication interface with a bidirectional data line and a clock line is configured to transmit data between the master IC and the slave IC. The serial communication interface may be I 2 C (Inter-Integrated Circuit). background

[0002] I 2 C is a serial data bus that has become a widely accepted industry standard. It can be used internally for communication between different circuits, such as within a television or between a controller and peripheral ICs.

[0003] I 2C is designed as a master-slave bus. A data transfer can be initiated by a master (controller); a slave (target) addressed via an address responds. Multiple controllers are possible (multi-controller operation). If a controller module also functions as a target in multi-controller operation, another controller can communicate directly with it by addressing it as a target.

[0004] A property of I 2 C is that a microcontroller can control an entire network of integrated circuits with just two I / O pins and simple software. Buses of this type were developed because a significant portion of the cost of an integrated circuit and a printed circuit board used depends on the size of the package and the number of pins. A large IC package has more pins, takes up more space on the circuit board, and has more connections that can fail. All of this increases production and testing costs.

[0005] Although slower than newer bus systems, I 2 C because of the low overhead, it may be advantageous for peripheral devices that do not need to be fast. I 2 C can be used for the transmission of control and configuration data. Examples include volume controls, low-sampling analog-to-digital or digital-to-analog converters, real-time clocks, small non-volatile memories, or bidirectional switches and multiplexers. Electronic sensors can also use an analog-to-digital converter with I 2 C interface integrated.

[0006] When using I 2 C, conflicting requirements may arise. For example, there may be a need for immediate data readout (e.g., measurement data) when it is available on the sensor side. There may be a need for lower system power consumption. There may be a need for low-cost I 2C-slave ICs without additional interrupt pins. Furthermore, there may be a need for increased I 2 C bandwidth.

[0007] The datasheet from Cypress Semiconductor [I2C master / multi-master / slave. 3.1. San Jose, 2012 (001-75486 Rev. *A). 48 pp. - Company publication. URL: https: / / www.infineon.com / dgdl / Infineon-Component_I2C_V3.1-Software%20Module%20Datasheets-v03_05-EN.pdf?fileId=8ac78c8c7dOd8da4017d0e9565401fd9 [accessed on August 22, 2024]] for the "I 2 C Master / Multi-Master / Slave Software Module” describes an I 2 C component, the I 2 C-Slave, Master and Multi-Master configurations supported.

[0008] US10572439B1 describes systems, methods, and devices. A device provides a clock signal, transmits an address on a second line of the serial bus followed by a read / write bit to initiate a read transaction, and delays a pulse of the clock signal after the read / write bit is transmitted. The pulse may be delayed for a first duration to account for latency of a first slave device participating in the read operation. The device may receive an acknowledgment from the first slave device during the transmission of the pulse and, upon receipt of the acknowledgment, receive a first byte of data from the first slave device. The device may hold the clock signal for a second duration after receiving the first byte of data from the first slave device and, upon acknowledgment, receive a second byte of data from the first slave device. Summary

[0009] One or more of the above-mentioned needs are addressed by devices and methods according to the independent patent claims. Advantageous further developments are addressed by the dependent claims.

[0010] According to a first aspect, an electronic system is proposed. The electronic system comprises a master integrated circuit (master IC) and a slave IC. The electronic system further comprises a serial communication interface with a bidirectional data line and a clock line. The communication interface is designed to transmit data between the master IC and the slave IC. The master IC is designed to send a data request command to the slave IC via the data line. The slave IC is designed to begin providing requested data in response to the data request command. After the data request command, the master IC is designed to send a data read command to the slave IC via the data line to read out the requested data.The slave IC is configured to deactivate the clock line upon receipt of the data read command until the slave IC can provide the requested data. The master IC is configured to measure the deactivation time of the clock line. The master IC is configured to set a waiting time between a next data request command and a next data read command according to the measured time.

[0011] According to some embodiments, the master IC is configured to send the data read command to the slave IC after a specified minimum data provision time has elapsed since the data request command. If the requested data is not yet fully available after the specified minimum data provision time, the slave IC is configured to deactivate the clock line until the slave IC can provide the requested data. The master IC is configured to measure the duration of the deactivation of the clock line and to adjust the waiting time between the next data request command and the next data read command according to the minimum data provision time and the measured duration.

[0012] According to some embodiments, the master IC is configured to maintain the wait time for a plurality of next data request commands and next data read commands, and thereafter to determine an updated wait time according to one of the described embodiments.

[0013] According to some embodiments, the master IC is configured to use the set waiting time for a data request command and the subsequent data read command and then to successively reduce the waiting time between the data request command and the data read command until a renewed deactivation of the clock line is detected by the slave IC in order to be able to provide the requested data on the data line.

[0014] According to some embodiments, the master IC is configured to measure the time duration of the renewed deactivation of the clock line and to set a newly updated waiting time between the next data provide command and the subsequent data read command according to the measured time duration.

[0015] According to some embodiments, the master IC comprises a microcontroller.

[0016] According to some embodiments, the slave IC comprises a sensor IC, such as a magnetic field sensor IC. The magnetic field sensor IC may comprise a 3D Hall sensor IC.

[0017] According to some embodiments, the serial communication interface comprises an I 2 C communication interface.

[0018] According to a second aspect, a communication method is proposed for an electronic system comprising a master IC and a slave IC. The electronic system further comprises a serial communication interface with a bidirectional data line and a clock line for transmitting data between the master IC and the slave IC. The communication method comprises sending a data request command from the master IC to the slave IC via the data line. The communication method comprises the slave IC beginning to provide requested data in response to the data request command. The communication method comprises sending a data read command from the master IC to the slave IC via the data line to read out the requested data after the data request command.The communication method comprises the slave IC deactivating the clock line upon receipt of the data read command until the slave IC can provide the requested data. The communication method comprises the master IC measuring the deactivation time of the clock line. The communication method comprises the master IC setting a wait time between a next data request command and a next data read command according to the measured time.

[0019] According to a further aspect, an integrated circuit (IC) is proposed. The IC comprises a serial communication interface with a bidirectional data line and a clock line. The communication interface is configured to transmit data between the IC and another IC via the data line. The IC further comprises a processor configured to send a data request command to the further IC via the data line, after a waiting time following the data request command, send a data read command to the further IC via the data line, measure a time duration of deactivation of the clock line by the further IC after the data read command, and update the waiting time between a next data request command and a subsequent data read command according to the measured time duration.

[0020] According to some embodiments, the processor is configured to send the data read command to the further IC after a specified minimum data provision time has elapsed since the data request command.

[0021] According to some embodiments, the processor is configured to maintain the updated wait time for a plurality of next data request commands and data read commands, and thereafter determine a newly updated wait time.

[0022] According to some embodiments, the processor is configured to use the updated wait time for the next data request command and the next data read command and thereafter to successively reduce the wait time between the data request command and the data read command until a renewed deactivation of the clock line is detected by the further IC.

[0023] According to some embodiments, the IC is designed as a microcontroller.

[0024] According to some embodiments, the data provision command includes a command to measure sensor data to a sensor IC. Short character description

[0025] Some examples of devices and / or methods are explained in more detail below with reference to the accompanying figures. They show: Fig. 1A an example of an electronic system with a master IC and a slave IC; Fig. 1B shows an example of a data request command and a data read command; Fig. 2A shows another example of an electronic system with a master IC and a slave IC; Fig. 2B shows another example of a data request instruction and a data read instruction with clock stretching; Fig. 3 shows another example of a data request command and a data read command with a long wait time; Fig. 4 an embodiment of a communication between master IC and slave IC; Fig. 5 shows another embodiment of communication between master IC and slave IC; Fig. 6 shows another embodiment of communication between master IC and slave IC; Fig. 7 shows another embodiment of communication between master IC and slave IC; and Fig. 8 shows a communication method between a master IC and a slave IC according to an embodiment. Description

[0026] Some examples will now be described in more detail with reference to the accompanying figures. However, other possible examples are not limited to the features of these detailed embodiments. These may include modifications of the features, as well as equivalents and alternatives to the features. Furthermore, the terminology used herein to describe particular examples is not intended to be limiting of other possible examples.

[0027] Throughout the description of the figures, identical or similar reference numerals refer to identical or similar elements or features, each of which may be implemented identically or in a modified form while providing the same or a similar function. Furthermore, in the figures, the thicknesses of lines, layers, and / or regions may be exaggerated for clarity.

[0028] When two elements A and B are combined using "or," this should be understood to disclose all possible combinations, i.e., only A, only B, and both A and B, unless explicitly defined otherwise in the individual case. Alternative wording for the same combinations may be "at least one of A and B" or "A and / or B." This applies equivalently to combinations of more than two elements.

[0029] If a singular form is used, such as "a," "an," and "the," and the use of only a single element is neither explicitly nor implicitly defined as mandatory, further examples may also use multiple elements to implement the same function. If a function is described below as being implemented using multiple elements, further examples may implement the same function using a single element or a single processing entity.It is further understood that the terms "comprises", "comprising", "has" and / or "having" when used herein describe the presence of the specified features, integers, steps, operations, processes, elements, components and / or a group thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, processes, elements, components and / or a group thereof.

[0030] The Fig. Figure 1A shows an electronic system 100 with a master IC 110 and a slave IC 120. The master IC 110 is embodied as a microcontroller (µC), while the slave IC 120 is embodied as a sensor IC in the example shown. Other implementations of the slave IC 120, such as a display module, real-time clock (RTC), etc., are also possible.

[0031] Master IC 110 and slave IC 120 are connected to each other via a serial communication interface 130. The serial communication interface 130 can be an I 2 C-Bus communication interface. The I 2 C-Bus communication interface 130 includes a bidirectional data line (SDA) and a clock line (SCL) between the master IC 110 and the slave IC 120. In the example shown, an interrupt line (INTN) is also present between the master IC 110 and the slave IC 120.

[0032] The master IC or microcontroller 110 is an electronic component that acts as a host or master device in an I 2 C-Bus system operates. The microcontroller 110 controls and coordinates the communication between different I 2 C-capable components, which are referred to as slaves. The tasks of the microcontroller 110 in the I 2 C systems can include, for example: - Initiating communication: The microcontroller 110 starts the communication by selecting the desired slave device, e.g. slave IC 120, on the I 2 C-Bus and communication begins. - Sending commands and data: The microcontroller 110 sends commands or data to the selected slaves, e.g. slave IC 120, to perform certain actions or retrieve information. - Receiving data: The microcontroller 110 can receive data from the slaves, e.g. slave IC 120, to collect information or monitor the status of the slaves. - Handling errors and conflicts: The microcontroller 110 may be able to handle collisions or conflicts on the I 2 C-Bus and take appropriate action to ensure that communication can continue. - Stop communication: At the end of the communication, the microcontroller 110 can stop the transmission and the I 2 Release C-Bus for other devices.

[0033] The microcontroller 110 can thus play a central role in the control and coordination of I 2 C communication in the electronic system 100 and enable the connection and interaction of various components, such as sensors, displays, memory chips and other peripherals.

[0034] The microcontroller 110 can communicate in the I 2 C protocol by creating a so-called “start condition” (S) 141 on the I 2 C-Bus. This is in Fig. 1B. The "start condition" (S) 141 may be part of a command 140, the first step to establish a connection to one or more I 2C slave devices, e.g., slave IC 120. Start condition 141 can signal the start of a new transmission. Microcontroller 110 can start communication as follows: - Send a start condition (Start Condition) 141: The microcontroller 110 can, for example, pull the data line (SDA) from HIGH to LOW, while the clock line (SCL) remains HIGH. This creates a start condition that is accepted by all I 2 C devices, e.g. Slave IC 120, is detected on the bus. - Address Transfer 142: After generating the start condition, the microcontroller 110 can, for example, send a 7-bit address of the slave device, e.g., slave IC 120, with which it wishes to communicate. The eighth bit of the address byte can indicate whether the microcontroller 110 wishes to send data to the slave device 120 (0) or receive data 160 from the slave device 120 (1). In the latter case, and if the data is not present, the command 140 can be understood, for example, as a data request command to the slave device 120. - Waiting for acknowledgement (ACK / NACK): After sending address 142, the microcontroller 110 can expect an acknowledgement (ACK) from the slave IC 120. An ACK can be a brief LOW level on the data line (SDA), signaling that the slave IC 120 is reachable. If the slave IC 120 is not reachable, it sends a NACK (Not Acknowledge) instead of the ACK, and the microcontroller 110 can take appropriate action, such as terminating communication. - Resume communication: After the ACK is received, the microcontroller 110 can either send data 143 to the slave device 120 or receive data from the slave device 120, depending on the purpose of the communication. - Terminating communication: At the end of communication, the microcontroller 110 can send a stop condition 144, for example, by pulling the data line (SDA) from low to high while the clock line remains high. This signals the end of the transmission.

[0035] The exact sequence of these steps may vary depending on the communication requirements. Microcontroller 110 may be responsible for controlling these steps and ensuring that communication proceeds correctly and reliably.

[0036] In the Fig. In the example shown in Figure 1B, the stop condition 144 of the data request command 140 triggers a measurement by the sensor IC 120. Thus, the stop condition (possibly together with the eighth bit of the address byte) can also be understood as a data request command to the sensor IC 120. In response to the data request command 140, the sensor IC 120 can begin measuring the required data 160. This can include the acquisition of information such as temperature, pressure, humidity, light intensity, or other physical parameters. For example, the sensor IC 120 can be designed as a 3D magnetic field sensor and measure x, y, and z coordinates. If necessary, the sensor IC 120 can also have a temperature sensor and provide a temperature measurement value.

[0037] In the Fig. 1A and Fig. In the example shown in Figure 1B, an interrupt line (INTN) is provided between master IC 110 and slave IC 120, which can be pulled from HIGH to LOW (or vice versa) by the sensor IC 120, for example, as soon as the measured data 160 is available in the sensor IC 120. After signaling the interrupt from the sensor IC 120, the sensor IC 120 can transmit the measured data upon request from the microcontroller 110. The data 160 can be transmitted via the I 2 C-Bus back to the microcontroller 110.

[0038] The microcontroller 110 can read the data 160 from the sensor IC 120 as follows: - After the interrupt, the microcontroller 110 can again send a start condition 151 as part of a command 150. For this purpose, the microcontroller 110 can, for example, pull the data line (SDA) from HIGH to LOW, while the clock line (SCL) remains HIGH. This creates a start condition that can be used by all I 2C devices, e.g. Slave IC 120, is detected on the bus. - Address Transfer 152: After generating the start condition, the microcontroller 110 can send the 7-bit address of the slave device, e.g., slave IC 120, from which it wants to read data. The eighth bit of the address byte indicates whether the microcontroller wants to receive data from the slave device (1). In the latter case, and if data 160 is present, the command 150 can be understood, for example, as a data read command to the slave device 120. - Waiting for acknowledgement (ACK / NACK): After sending address 152, the microcontroller 110 awaits an acknowledgement (ACK) from the slave IC 120. An ACK is a brief LOW level on the data line (SDA), which signals that the slave IC 120 is reachable. If the slave IC 120 is not reachable, it sends a NACK instead of the ACK, and the microcontroller 110 can take appropriate action, such as terminating communication. - Resume communication: After the ACK is received, the microcontroller 110 can receive the data 160 from the slave device 120. - Termination of communication: At the end of communication, the microcontroller 110 sends a stop condition 154, for example, by pulling the data line (SDA) from LOW to HIGH, while the clock line remains HIGH, for example. This signals the end of the transmission.

[0039] The stop condition 154, like the stop condition 144, can initiate or trigger the measurement of new sensor data 160, so that the stop conditions 144, 154 can each be understood as a data request command and the eighth bit of the address byte 142, 152 as a data read command.

[0040] In the case of the Fig. 1A and Fig. In the example described in Figure 1B, the interrupt allows the data 160 to be read by the slave device 120 in a time-optimized manner as soon as it is available. This results in a comparatively high communication bandwidth and low power consumption. However, the disadvantage is the additional hardware overhead for the interrupt line (INTN) between the master IC 110 and the slave IC 120.

[0041] A possible implementation of data exchange via the I 2 C-Bus 130 between Master IC 110 and Slave IC 120 without the interrupt line (INTN) is in the Fig. 2A and Fig. 2B. The Fig. Figure 2A shows an electronic system 200 with a master IC 110 and a slave IC 120. In contrast to the example of Fig. 1A and Fig. 1B there is no interrupt line between master IC 110 and slave IC 120.

[0042] Just as in the example of Fig. 1A and Fig. 1B, the master IC 110 is configured to send a data request command 140 or 144 to the slave IC 120 via the data line (SDA). The slave IC 120 is configured to begin providing (measuring) the requested data 160 in response to the data request command 140 or its stop condition 144. Immediately or directly after the data request command 140 or its stop condition 144, the slave IC 120 begins providing or measuring the requested data 160. In this example, the master IC 110 is configured to send the data read command 150 or 152 to the sensor IC 120 for reading out the requested data while the data 160 is still being measured (i.e., before it is available). The slave IC 120 is configured to deactivate the clock line (SCL) after receiving the eighth bit of the address byte (data read command) 152 until the slave IC 120 can provide the requested data 160.This concept is known as "clock stretching." In the first 2 C communication protocol, this is a technique in which the slave device 120 can temporarily "stretch" the clock line (SCL) to slow down or stop transmission when it is not ready to pass data 160.

[0043] “Clock stretching” can work as follows: Normal clock cycle: In I 2 C protocol, there is the master IC 110, which controls the clock (SCL) and the data (SDA), as well as one or more slave ICs 120 that respond to requests from the master IC 110. The clock cycle is normally controlled by the master IC 110, and communication occurs synchronously with this clock.

[0044] Clock cycle with clock stretching: If the slave IC 120 is not ready to send (or receive) data 160, it can temporarily "stretch" the clock cycle, for example, by pulling the clock line (SCL) low. This signals the master IC 110 that the slave IC 120 needs more time to prepare or process the data 160. The master IC 110 detects the "clock stretching" signal from the slave IC 120 and waits until the clock line (SCL) returns high. During "clock stretching," the master IC 110 remains inactive, giving the slave IC 120 the time it needs to complete its tasks. Once the slave IC 120 is ready, it sets the clock line (SCL) back high, and communication can resume. The master IC 110 resumes the clock cycle, and data transmission can proceed as usual.

[0045] “Clock Stretching” is a function in the I 2C protocol, as it allows the slave devices 120 to slow down or stop communication when they are unable to process data in real time. This is particularly useful in applications where the slave devices 120 may not be able to operate as quickly as the master 110, or when there are unforeseen delays. Through "clock stretching," the I 2 C communication should be more reliable and robust against delays.

[0046] In the case of the Fig. 2A and Fig. 2B, the data 160 can also be read by the slave device 120 as soon as it is available. This results in a comparatively high communication bandwidth. However, the disadvantage is high power consumption, since power is lost during clock stretching by the clock line (SCL) being pulled low in the Fig. 2A, from the VDD supply to ground. Furthermore, parallel communication between Master 110 and other slaves is not possible.

[0047] Fig. Figure 3 shows another communication option between master 110 and slave 120, which requires neither the interrupt line (INTN) nor clock stretching.

[0048] As in previous examples, the master IC 110 is configured here to send a data request command 140, 144 to the slave IC 220 via the data line (SDA). The slave IC 220 is configured to immediately begin providing (measuring) the requested data 160 in response to the data request command 140, 144. In this example, however, the master IC 110 is configured to send the data read command 150, 152 for reading the requested data to the sensor IC 220 after a longer, predefined waiting time T. The waiting time T between the data request command 140 and the data read command 150 can be selected to be long enough to outlast the data provision time (measurement time) and also to take into account possible oscillator variations on the clock line (SCL). This can lead to long waiting times and thus to a comparatively low communication bandwidth.

[0049] In view of the disadvantages of the examples described above, the present disclosure proposes an electronic system 200 having a master IC 110 and at least one slave IC 120. The electronic system 200 further comprises a serial communication interface 230 having a bidirectional data line (SDA) and a clock line (SCL). The communication interface 230 is configured to transmit data between the master IC 110 and the slave IC 120. The master IC 110 is configured to send a data request command 140, 144 to the slave IC 120 via the data line (SDA). The slave IC 120 is configured to begin providing (e.g., measuring) requested data 160 in response to the data request command 140, 144. The master IC 110 is designed to send a data read command 150, 152 to the slave IC 120 via the data line (SDA) after the data request command 140, 144 to read out the requested data 160.After receiving the data read command 150, 152, the slave IC 120 is configured to deactivate the clock line (SCL) by means of clock stretching until the slave IC 120 can provide the requested data 160. According to proposed embodiments, the master IC 110 is configured to measure a time duration of the deactivation of the clock line or a time duration of the clock stretching. According to proposed embodiments, the master IC 110 is configured to set a waiting time between at least one next data request command 154 and a next data read command according to the measured time duration. This is shown in FIG. Fig. 4 shown.

[0050] The proposed approach therefore corresponds to a combination of the approaches developed based on the Fig. 2B and Fig. 3 were described.

[0051] The master IC 110 is configured to send the data request command 144 to the slave IC 120 via the data line (SDA). The slave IC 120 is configured to begin providing (measuring) the requested data 160 in response to the data request command 144. Immediately after the data request command 144, the slave IC 120 begins providing or measuring the data 160. The master IC 110 is configured to send the data read command 152 to the sensor IC 120 for reading the requested data during the measurement or immediately after the data request command 144. The time between the data request command 144 and the data read command 152 is therefore less than an expected measurement duration. The slave IC 120 is designed to deactivate the clock line (SCL) after receiving the data read command 152 (clock stretching) until the slave IC 120 can provide the requested data 160 (after the measurement period).The master IC 110 is configured to measure the duration of the clock stretching and to adjust the wait time between the next or subsequent data request command 144, 154 and the next data read command 142, 152 based on the measured duration of the clock stretching. Between subsequent data request commands 144, 154 and subsequent data read commands 142, 152, no clock stretching is then initially necessary due to the set appropriate wait time.

[0052] The Fig. 4, the step marked (1) concerns a data readout with clock stretching and immediate readout start after the data request command 144. In (2), the microcontroller 110 measures the clock stretching time and, based on this, calculates the optimized readout start time (waiting time) after subsequent data request commands 144, 154 according to (3). This can also lead to immediate readout of the data 160 when they are available. Furthermore, a lower power consumption of the system 200 than with Fig. 2B possible. There are favorable I 2 C-Slaves 120 without interrupt pin. In addition, an increased I 2 C bandwidth possible.

[0053] In the Fig. In the embodiment shown in Figure 5, the master IC 110 is configured to execute the data read command 150, 152 after expiration of a minimum data provision time T specified in a data sheet. minsince the data request command 144 to the slave IC 120. The slave IC 120 is configured to, if the requested data 160 is not received after the specified minimum data delivery time T min are not yet fully available, to deactivate the clock line (SCL) (clock stretching) until the slave IC 120 can provide the requested data 160. The master IC 110 is configured to measure the time duration T of the deactivation of the clock line (clock stretching time) and to set the waiting time between the next data request command 144, 154 and the next data read command 142, 152 based on the minimum data provision time and the measured clock stretching time. Essentially, the waiting time between the next data request command 144, 154 and the next data read command 142, 152 can correspond to a sum of the minimum data provision time and the measured clock stretching time.

[0054] In the Fig. In the embodiment shown in Figure 5, the reading of the data 160 begins with clock stretching according to the minimum measurement time T specified in the data sheet (of the sensor IC 120). min The microcontroller 110 measures the clock stretch time. Based on this, the microcontroller 110 calculates the optimized readout start time. This optimized readout start time can then be used, for example, for all subsequent measurements and communications.

[0055] In the Fig. 6, the master IC 110 is designed according to Fig. 4 or Fig. 5 determined waiting time between data request command and data read command for a plurality of next data request commands and next data read commands, and thereafter again an updated waiting time according to Fig. 4 or Fig. 5 to be determined.

[0056] The embodiments according to Fig. 4 or Fig. 5 can therefore be used with the embodiment according to Fig. 6 can be combined. (1) The reading of the data 160 with clock stretching begins immediately or after the minimum measurement time specified in the data sheet. (2) The microcontroller 110 measures the clock stretching time. (3) The microcontroller 110 calculates the optimized readout start time. (4) Use of this optimized readout start time without clock stretching for a predetermined number of x measurements. (5) Then return to (1) to update the clock stretching time and repeat steps (2) to (5).

[0057] In the Fig. 7, the master IC 110 is designed according to one of the embodiments of the Fig. 4 to 6 for a data request command 144 and the subsequent data read command 150, 152, and then successively reduce the waiting time between further data request commands 144 and data read commands 150, 152 until a renewed clock stretching is detected by the slave IC 120 in order to be able to provide the requested data 160 on the data line (SDA). The master IC 110 is configured to measure the renewed clock stretching and to set a newly updated waiting time between the next data request command 144 and the subsequent data read command 150, 152 based on the measured renewed clock stretching.

[0058] The embodiments according to Fig. 4 to Fig. 6 can therefore be used with the embodiment according to Fig. 7 can be combined (1) The readout of the data with clock stretching begins immediately or after the minimum measurement time specified in the data sheet. (2) The microcontroller 110 measures the clock stretching time. (3) The microcontroller 110 calculates the optimized readout start time and uses this optimized readout start time for a measurement. (4) The microcontroller 110 slightly reduces the readout start time for each subsequent measurement compared to the previous readout start time (waiting time) until a clock stretching gap is detectable. Return to (2).

[0059] The Fig. 8 shows a summary flowchart of a communication method 800 between the master IC 110 and the slave IC 120.

[0060] At 802, the master IC 110 sends a data request command 140; 144 to the slave IC 120 via the data line (SDA). At 804, the slave IC 120, in response to the data request command 140; 144, begins providing requested data 160. At 806, after the data request command 140; 144, the master IC 110 sends a data read command 150; 152 to the slave IC 120 via the data line to read out the requested data 160. In step 808, after receiving the data read command 150; 152, the slave IC 120 deactivates the clock line (SCL) until the slave IC 120 can provide the requested data 160. In step 810, the master IC 110 measures a time duration of the deactivation of the clock line. In step 812, the master IC 110 sets a wait time between a next data request command 140; 144 and a next data read command 150; 152 based on the measured time period.

[0061] The aspects and features described in connection with a particular one of the previous examples may also be combined with one or more of the further examples to replace an identical or similar feature of that further example or to additionally introduce the feature into the further example.

[0062] Examples may further include or relate to a (computer) program having program code for executing one or more of the above methods when the program is executed on a computer, processor, or other programmable hardware component. Steps, operations, or processes of various of the methods described above may also be executed by programmed computers, processors, or other programmable hardware components. Examples may also include program storage devices, e.g.

[0063] Digital data storage media that are machine-, processor-, or computer-readable and encode or contain machine-executable, processor-executable, or computer-executable programs and instructions. The program storage devices may include or be, for example, digital memories, magnetic storage media such as magnetic disks and magnetic tapes, hard disk drives, or optically readable digital data storage media.Further examples may also cover computers, processors, control units, field-programmable logic arrays ((F)PLAs = (Field) Programmable Logic Arrays), field-programmable gate arrays ((F)PGA = (Field) Programmable Gate Arrays), graphics processor units (GPU = Graphics Processor Unit), application-specific integrated circuits (ASIC = application-specific integrated circuit), integrated circuits (IC = Integrated Circuit) or system-on-a-chip (SoC = System-on-a-Chip) programmed to perform the steps of the methods described above.

[0064] It is further understood that the disclosure of multiple steps, processes, operations, or functions disclosed in the specification or claims should not be construed as necessarily being in the described order, unless explicitly stated in the individual case or absolutely necessary for technical reasons. Therefore, the foregoing description does not limit the performance of multiple steps or functions to any particular order. Furthermore, in further examples, a single step, function, process, or operation may include and / or be broken down into multiple sub-steps, functions, processes, or operations.

[0065] If some aspects in the preceding sections were described in connection with a device or system, these aspects are also to be understood as a description of the corresponding method. For example, a block, a device, or a functional aspect of the device or system can correspond to a feature, such as a method step, of the corresponding method. Accordingly, aspects described in connection with a method are also to be understood as a description of a corresponding block, a corresponding element, a property, or a functional feature of a corresponding device or system.

[0066] The following claims are hereby incorporated into the Detailed Description, each claim being capable of standing on its own as a separate example. It should also be noted that although a dependent claim in the claims refers to a particular combination with one or more other claims, other examples may include a combination of the dependent claim with the subject matter of any other dependent or independent claim. Such combinations are hereby explicitly contemplated unless it is specifically stated that a particular combination is not intended. Furthermore, features of a claim for any other independent claim are also intended to be included, even if that claim is not directly defined as being dependent on that other independent claim.

Claims

[1] An electronic system (200) comprising a master integrated circuit, master IC (110); a slave IC (120); a serial communication interface (230) with a bidirectional data line and a clock line, wherein the communication interface (230) is designed to transmit data between the master IC (110) and the slave IC (120), wherein the master IC (110) is configured to send a data request command (140; 144) to the slave IC (120) via the data line, wherein the slave IC (120) is configured to begin providing requested data (160) in response to the data request command (140; 144), wherein the master IC (110) is configured to send a data read command (150; 152) for reading the requested data (160) to the slave IC (120) via the data line after the data request command (140; 144), wherein the slave IC (120) is designed, after receiving the data read command (150; 152), to deactivate the clock line until the slave IC (120) can provide the requested data (160), wherein the master IC (110) is designed to measure a time duration of the deactivation of the clock line, and wherein the master IC (110) is configured to set a waiting time between a next data request command (140; 144) and a next data read command (150; 152) according to the measured time period, and wherein the master IC is designed to use the set waiting time for a data request command and the subsequent data read command and then to successively reduce the waiting time between the data request command and the data read command until a renewed deactivation of the clock line is detected by the slave IC in order to be able to provide the requested data on the data line. [2] The electronic system (200) according to claim 1, wherein the master IC is configured to send the data read command to the slave IC after a specified minimum data provision time has elapsed since the data request command, wherein the slave IC is configured to deactivate the clock line if the requested data is not yet fully available after the specified minimum data provision time until the slave IC can provide the requested data, wherein the master IC is designed to measure the duration of deactivation of the clock line, and wherein the master IC is configured to set the waiting time between the next data request command and the next data read command according to the minimum data provision time and the measured time duration. [3] The electronic system (200) according to any one of the preceding claims, wherein the master IC is configured to maintain the wait time for a plurality of next data request commands and next data read commands, and thereafter to determine an updated wait time according to any one of the preceding claims. [4] The electronic system (200) of claim 3, wherein the master IC is configured to measure the time duration of the renewed deactivation of the clock line and to set a newly updated waiting time between the next data provide command and the subsequent data read command according to the measured time duration. [5] The electronic system (200) according to any one of the preceding claims, wherein the master IC comprises a microcontroller. [6] The electronic system (200) according to any one of the preceding claims, wherein the slave IC comprises a sensor IC. [7] The electronic system (200) according to any one of the preceding claims, wherein the slave IC comprises a magnetic field sensor IC. [8] The electronic system (200) according to any one of the preceding claims, wherein the slave IC comprises a 3D Hall sensor IC. [9] The electronic system (200) according to any one of the preceding claims, wherein the serial communication interface comprises an I 2 C communication interface. [10] An integrated circuit, IC (110), comprising a serial communication interface (230) having a bidirectional data line and a clock line, wherein the communication interface (230) is configured to transmit data between the IC (110) and another IC (120) via the data line; and a processor configured to to send a data request command (140; 144) to the further IC (120) via the data line, after a waiting time after the data request command (140; 144), to send a data read command (150; 152) to the further IC via the data line, to measure a time duration of deactivation of the clock line by the further IC (120) after the data read command (150; 152), and to update the waiting time between a next data request command (140; 144) and a subsequent data read command (150; 152) according to the measured time duration, wherein the IC (110) is designed to use the set waiting time for a data request command and the subsequent data read command and then to successively reduce the waiting time between the data request command and the data read command until a renewed deactivation of the clock line is detected by the further IC (120) in order to be able to provide the requested data on the data line. [11] The IC (110) according to claim 10, wherein the processor is configured to send the data read command (150; 152) to the further IC (120) after a specified minimum data provision time has elapsed since the data request command (140; 144). [12] The IC (110) of claim 10 or 11, wherein the processor is configured to maintain the updated wait time for a plurality of next data request commands (140; 144) and data read commands (150; 152), and thereafter determine a newly updated wait time. [13] The IC (110) according to any one of claims 10 to 12, wherein the processor is configured to use the updated wait time for the next data request command (140; 144) and the next data read command (150; 152) and thereafter to successively reduce the wait time between the data request command (140; 144) and the data read command (150; 152) until a renewed deactivation of the clock line by the further IC (120) is detected. [14] The IC (110) according to any one of claims 10 to 13, wherein the IC (110) is designed as a microcontroller. [15] The IC (110) of any one of claims 10 to 14, wherein the data request command (140; 144) comprises a command (144) for measuring sensor data to a sensor IC (120).

Images