DIGITAL CONTROL DEVICE

Abstract

A digital control device for a switching converter configured to receive an input voltage at an input voltage node and to generate an output voltage at an output voltage node, wherein the switching converter comprises one or more power switches and an energy storage element, wherein the digital control device comprises a pulse-width modulation control circuit configured to receive the output voltage and generate a PWM control signal to control the switching operation of the one or more power switches, and a switching circuit configured to couple the pulse-width modulation control circuit to the input voltage node during a first phase and to couple the pulse-width modulation control circuit to a supply voltage node during a second phase, wherein the supply voltage node is connected to a supply voltage.

Description

[0001] The present disclosure relates to a digital control device. In particular, the present disclosure relates to a digital control device for a switching converter. BACKGROUND

[0002] Fig. Figure 1(a) is a schematic representation of a digital step-down converter 100 with analog-to-digital converters (ADCs) 102, 104, 106 and a control device 108. The step-down converter 100 includes switches 110, 112, an inductor 114 and a capacitor 116. During operation, the switching converter receives an input voltage VIN and generates an output voltage VOUT.

[0003] While the power stage and passive components (inductor 114 and capacitor 116) remain the same as in an analog buck converter, the ADC 102 converts the output voltage VOUT into a digital value. Optionally, the inductor current IL of inductor 114 and the input voltage VIN can also be converted from analog to digital, depending on the digital control method.

[0004] We distinguish between: • The switching frequency (FSW) of the buck converter 100, for example 2 MHz. FSW is equal to 1 / TSW, where TSW is the switching period of the buck converter 100. FSW is the frequency of the power stage. • The processing frequency of the digital control device 108 (FS), for example, approximately 100 MHz. FS is equal to 1 / TS, where TS is the processing time of the control device 108. FS can optionally also be the sampling frequency of the ADC 102.

[0005] The control device 108 can operate in different modes depending on load conditions. The load is a component that consumes electrical power, as provided by the buck converter 100 when coupled to the load. The load can draw a load current from the buck converter 100, with a "high load" referring to a higher load current draw than during a "low load" or a "light load".

[0006] Under high load, the digital control device uses pulse width modulation (PWM), and under low load, pulse frequency modulation (PFM) is used.

[0007] Digital control loops under high loads operate in PWM mode to meet the following requirements: • Higher accuracy and lower waviness or ripple, as required for VOUT, compared to PFM. • PWM uses a constant frequency. • Transition load response: PWM can react faster than PFM.

[0008] Under light load, the digital step-down converter 100 operates in PFM mode, where the requirements are less stringent. However, the control device 108 is permitted to consume less power.

[0009] Fig. Figure 1(b) is a schematic representation of the digital step-down converter 100 and the control device 108 for providing PWM and PFM control. The step-down converter 100 includes a switching circuit 109. The control device 108 includes a PWM control circuit 118 and a PFM control circuit 120. The operation of the circuit components is synchronized using a clock signal FS. The system includes a finite-state machine (FSM) 121 for managing the control of the system and a decoupling capacitor 123. The FSM 121 is always switched on. The PWM control circuit 118 and the PFM control circuit 120 receive a supply voltage VDIG from a low-dropout regulator (LDO) 121, which provides power to the respective control circuits.

[0010] The PWM control circuit 118 comprises an ADC 122, a DIGLOOP circuit 124, and a DIGPWM circuit 126. The PWM control circuit 118 is used for high-performance PWM control and is deactivated under low load.

[0011] The PFM control circuit 120 comprises an analog comparator 128 and a DIGPFM circuit 130. The analog comparator 128 detects the output voltage level VOUT during PFM operation, and the DIGPFM circuit 130 controls the switching operation of the buck converter 100 to "fill up" the input voltage VOUT whenever it drops. It should be noted that the DIGPFM circuit 130 can use the clock signal FS, another slower clock, or no clock at all to reduce its power consumption.

[0012] The PWM control circuit 118 increases power consumption and reduces efficiency. For example, if the load current IOUT is in the range of 100 µA to 1 mA, the typical consumption of the PWM control circuit while the clock signal FS switches is 10 mA for a total of 100,000 transistor gates. Therefore, the control device 108 consumes 100 times more power than the load at the output voltage VOUT. SUMMARY

[0013] It is desirable to reduce power consumption and improve the efficiency of a control device for a switching converter that uses a pulse width modulation control scheme.

[0014] According to a first aspect of the disclosure, a digital control device is provided for a switching converter configured to receive an input voltage at an input voltage node and to generate an output voltage at an output voltage node, the switching converter comprising one or more power switches and an energy storage element, the digital control device comprising a pulse-width modulation (PWM) control circuit configured to receive the output voltage and generate a PWM control signal to control the switching operation of the one or more power switches, and a switching circuit configured to couple the PWM control circuit to the input voltage node during a first phase and to couple the PWM control circuit to a supply voltage node during a second phase.where the supply voltage node is connected to a supply voltage.

[0015] Optionally, the switching converter can be a buck converter, a boost converter, or a buck-boost converter.

[0016] Optionally, the energy storage element can be an inductor.

[0017] Optionally, the one or more circuit breakers may include a first circuit breaker and a second circuit breaker.

[0018] Optionally, the pulse width modulation control circuit includes an analog-to-digital converter that is coupled to the output voltage node and configured to digitize the output voltage to provide a digital representation of the output voltage.

[0019] Optionally, the pulse width modulation control circuit includes a digital control loop.

[0020] Optionally, the pulse width modulation control circuit includes a digital PWM circuit.

[0021] Optionally, the first phase precedes the second phase.

[0022] Optionally, the first phase is a charging phase and the second phase is a holding phase.

[0023] Optionally, during the first phase the supply voltage node is decoupled from the pulse width modulation control circuit, and during the second phase the input voltage node is decoupled from the pulse width modulation control circuit.

[0024] Optionally, the switching circuit includes one or more first phase switches for coupling the pulse width modulation control circuit with the input voltage node during the first phase and one or more second phase switches for coupling the pulse width modulation control circuit with the supply voltage node during the second phase.

[0025] Optionally, the first phase precedes the second phase.

[0026] Optionally, the first phase is a charging phase and the second phase is a holding phase.

[0027] Optionally, during the first phase, one or more second phase switches are open, so that the supply voltage node is decoupled from the pulse width modulation control circuit, and during the second phase, one or more first phase switches are open, so that the input voltage node is decoupled from the pulse width modulation control circuit.

[0028] Optionally, the pulse width modulation control circuit includes an analog-to-digital converter coupled to the output voltage node and configured to digitize the output voltage to provide a digital representation of the output voltage, wherein the one or more first phase switches include a first switch for coupling the analog-to-digital converter to the input voltage node during the first phase, and the one or more second phase switches include a second switch for coupling the analog-to-digital converter to the supply voltage node during the second phase.

[0029] Optionally, the pulse width modulation control circuit includes a digital control loop, which includes one or more first phase switches, a third switch for coupling the digital control loop to the input voltage node during the first phase, and one or more second phase switches, a fourth switch for coupling the digital control loop to the supply voltage node during the second phase.

[0030] Optionally, the pulse width modulation control circuit includes a digital PWM circuit, one or more first phase switches include a fifth switch for coupling the digital PWM circuit to the input voltage node during the first phase, and one or more second phase switches include a sixth switch for coupling the digital PWM circuit to the supply voltage node during the second phase.

[0031] Optionally, the digital control device includes a circuit component comprising one or more first phase switches, each comprising a first switch including a first transistor for coupling the circuit component to the input voltage node during the first phase, and one or more second phase switches, each comprising a second switch including a second transistor for coupling the circuit component to the supply voltage node during the second phase, a third transistor with a gate coupled to a gate of the first transistor, a fourth transistor coupled in series with the third transistor, a comparator with a first comparator input terminal coupled to the first and second transistors, a second comparator input terminal coupled to the supply voltage node, and a comparator output terminal for outputting a load signal.an OR gate comprising a first OR gate input coupled to a turn-off signal, a second OR gate input coupled to the comparator output for receiving the charge signal, an OR gate output coupled to a gate of the second transistor, an AND gate comprising a first AND gate input coupled to the comparator output for receiving the charge signal, a second AND gate input coupled to a turn-on signal, and an AND gate output coupled to a gate of the fourth transistor.

[0032] Optionally, the circuit component consists of an analog-to-digital converter coupled to the output voltage node and configured to digitize the output voltage to provide a digital representation of the output voltage, a digital control loop, and a digital PWM circuit.

[0033] Optionally, the pulse width modulation control circuit is configured to control the switching operation of one or more switches during a first operating mode.

[0034] Optionally, the digital control device includes an additional control circuit configured to control the switching operation of one or more switches during a second operating mode.

[0035] Optionally, the additional control circuit includes a pulse frequency modulation control circuit.

[0036] Optionally, the first operating mode is a high-load operating mode and the second operating mode is a low-load operating mode.

[0037] Optionally, the digital control device includes a voltage regulator or a power rail to provide the supply voltage at the supply voltage node.

[0038] Optionally, the voltage regulator includes a low-dropout regulator or a buck converter.

[0039] Optionally, the voltage regulator includes a low-dropout regulator configured to receive the input voltage and provide the supply voltage at the supply voltage node.

[0040] According to a second aspect of the disclosure, a method for controlling a switching converter is provided, which is configured to receive an input voltage at an input voltage node and to generate an output voltage at an output voltage node, wherein the switching converter comprises one or more power switches and an energy storage element, wherein the method comprises receiving the output voltage at a pulse width modulation control circuit, generating a PWM control signal to control the switching operation of the one or more power switches using the pulse width modulation control circuit, coupling the pulse width modulation control circuit to the input voltage node during a first phase, and coupling the pulse width modulation control circuit to a supply voltage node during a second phase, wherein the supply voltage node is connected to a supply voltage.

[0041] It is obvious that the procedure of the second aspect can include the features set out in the first aspect and can incorporate other features described here. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] The revelation is described in more detail below by way of example and with reference to the accompanying drawings, in which: Fig. 1(a) a schematic representation of a digital step-down converter, Fig. 1(b) a schematic representation of the digital step-down converter of Fig. 1(a) and a control device for providing PWM and PFM control; Fig. 2 a schematic representation of the system of Fig. 1(b) is configured to use a known power gating method; Fig. 3 a schematic representation of a digital control device for a switching converter according to a first embodiment of the present disclosure; Fig. 4(a) a schematic representation of a digital control device according to a second embodiment of the present disclosure, Fig. 4(b) a schematic representation of the digital control device of Fig. 4(a) with a specific embodiment of switching circuits according to a third embodiment of the present disclosure; Fig. 5(a) a schematic representation of a digital control device and a switching converter according to a fourth embodiment of the present disclosure, Fig. 5(b) is a schematic representation of a digital control device and a switching converter according to a fifth embodiment of the present disclosure; Fig. 6(a) a schematic representation of part of a digital control device, how in a specific embodiment one of the digital control devices can be implemented, Fig. 6(b) is a diagram showing exemplary waveforms that vary over time for a practical implementation of the digital control device of Fig. 6(a); Fig. 7(a) is a schematic representation of a digital control device according to a sixth embodiment of the present disclosure, Fig. 7(b) is a diagram that shows simulation results of the in Fig. 7(a) shows the system depicted; and Fig. Figure 8 is a schematic representation of a specific embodiment of a PWM control circuit. DETAILED DESCRIPTION

[0043] It is desirable to reduce the power consumption of the DIGLOOP 124 and DIGPWM 126 blocks. The ADC 122 can be switched off when not in use, thus reducing its power consumption to zero.

[0044] One immediate method is to control the clock signal FS, where the total budget of the supply current IDD can be as follows: Block IDD (während FS nicht schaltet) ACOMP 10µA DIGLOOP + DIGPWM 20µA DIGPFM + FSM 5µA

[0045] The residual consumption of 20µA for DIGLOOP+DIGPWM is due to digital leakage currents (also known as subthreshold current).

[0046] If the load current IOUT is 100µA (i.e., output power POUT = 100µW at output voltage VOUT = 1V), the input power PIN is: PIN=VIN×(Total_IDD+(IOUT×VOUT) / VIN) where Total_IDD is the total supply current IDD and the other symbols have the meaning described above. PIN=3.6V×(35μA+(100μA×1V) / 3.6V)=226μW

[0047] The POUT / PIN efficiency is 44%, and this leakage current of 20µA has contributed to a loss of 72µW. Without this leakage current, the efficiency would be 66%.

[0048] Fig. 2 is a schematic representation of the system of Fig. 1(b), which is configured to use the known power-gating method. The control device 108 further comprises switches 200, 202, 204.

[0049] The PWM control circuit 118 can be disconnected from VDIG, thus suppressing the leakage current. A daisy chain of switches 200, 202, 204 is created to generate the power-controlled supplies VDIG1, ​​VDIG2, VDIG3, in order to control the inrush current drawn from VDIG. VDIG1, ​​VDIG2, VDIG3 designate voltage busbars.

[0050] However, applying this method in the context of the down converter 100 leads to the following disadvantages: • The wake-up time of the daisy chain (turning on VDIG1, ​​VDIG2, VDIG3) is typically 100ns: it cannot be used for a buck converter 100 which needs to wake up its PWM control circuit 118 within 20ns in the event of a sudden load transition at the output voltage VOUT. • There is a residual kickback on VDIG due to the daisy chain 200, 202, 204. If the buck converter 100 is instantiated in a power management integrated circuit (PMIC) with multiple buck converters 100, the wake-up of the supply voltage VDIG may be further slowed. • When designing the PMIC layout of the upper cell, the following must be considered: the metal traces supplying VDIG1, ​​VDIG2, and VDIG3 must be oversized to support the large inrush current required to charge these nodes compared to their normal consumption. For example, if the total equivalent capacitance at VDIG1 is 100pF (due to all digital gates) and a wake-up time of 20ns at 1V supply is preferred, the inrush current is: I_in-rush = 100pF × (1V / 20ns) = 5mA, while the normal consumption of this block might be, for example, 2.5mA: the power connection to VDIG1 must be twice as large just to be able to charge it in 20ns.

[0051] Fig. Figure 3 is a schematic representation of a digital control device 300 for a switching converter 302 according to a first embodiment of the present disclosure. The switching converter 302 receives an input voltage VIN at an input voltage node NVIN and generates an output voltage VOUT at an output voltage node NOUT. The switching converter 302 comprises one or more power switches 304 and an energy storage element 306.

[0052] The switching converter 302 can, for example, be a buck converter, a boost converter, or a buck-boost converter. The energy storage element 306 can be an inductor. The switching converter 302 can include a first power switch and a second power switch (as is the case for the buck converter of Fig. 1(a)).

[0053] The digital control device 300 further comprises a pulse-width modulation (PWM) control circuit 310, which is configured to receive the output voltage VOUT and generate a PWM control signal 312, which is used to control the switching operation of the circuit breakers 304. It should be noted that for illustrative purposes only a single circuit breaker is shown. Specific embodiments may include one or more circuit breakers, according to the understanding of those skilled in the art.

[0054] The PWM control circuit 310 can include a gate driver, so that the PWM control signal 312 in a high state is used to activate the high-side switches and the PWM control signal 312 in a low state is used to activate the low-side switches.

[0055] The PWM control signal 312 can be generated as follows. The digitized output voltage is compared with a reference voltage (target or "desired" voltage setting: synthesized or configurable output voltage setting) and based on the result, the PWM signal 312 is generated and used to control the switches, which are turned on or off to regulate VOUT to the desired value.

[0056] The digital control device 300 further comprises a switching circuit 314. During operation, the switching circuit 314 couples the PWM circuit 310 to the input voltage node NVIN during a first operating phase. During operation, the switching circuit 314 couples the PWM control circuit 310 to a supply voltage node Nsupply during a second operating phase. The supply voltage node is connected to a supply voltage VDIG.

[0057] In a specific embodiment, the digital control device 300 can include a low-dropout regulator LDO 308 configured to receive the input voltage VIN and provide the supply voltage VDIG at the supply voltage node Nsupply.

[0058] The following description and embodiments describe the LDO 308 for providing the VDIG supply voltage. It is evident that other embodiments may use alternative methods and / or components for providing the VDIG supply voltage. For example, the VDIG supply voltage may be provided by a different type of voltage regulator, such as a buck converter; or it may be provided via a power rail.

[0059] Therefore, during the first phase, the PWM control circuit 310 is powered by the input voltage VIN; and during the second phase, the PWM control circuit 310 is powered by the supply voltage VDIG.

[0060] The first phase can precede the second phase. For example, the first phase can be a start-up phase in which the digital control device 300 initially activates the PWM control mode. When a specific condition is met, the digital control device 300 can then switch to a second phase, which relates to normal operation during PWM control mode when the PWM control circuit 310 is powered via the power supply VDIG. The first phase can be a charging phase, and the second phase can be a holding phase.

[0061] During the first phase, the supply voltage node Nsupply can be decoupled from the PWM control circuit 310. During the second phase, the input voltage node NVIN can be decoupled from the PWM control circuit 310.

[0062] The switching circuit 314 can include one or more first phase switches, which include a first switch 316 for coupling the PWM control circuit 310 with the input voltage node NVIN during the first phase, and one or more second phase switches, which include a second switch 318 for coupling the PWM control circuit 310 with the supply voltage node Nsupply during the second phase.

[0063] During the first phase, the second switch 318 can be open, thus decoupling the supply voltage node Nsupply from the PWM control circuit 310. During the second phase, the first switch 316 can be open, thus decoupling the input voltage node NVINV from the PWM control circuit 310.

[0064] By first supplying power via the input voltage VIN instead of the supply voltage VDIG, the inrush current is drawn from the input voltage supply VIN (typically 3.6V), which can contribute to kickback effects and may result in a larger voltage drop (e.g., from 3.6V to the 1.0V rail). This suppresses the current draw from the supply voltage VDIG and resolves the disadvantages described in relation to control device 108, as described in relation to Fig. 2 described.

[0065] Fig. Figure 4(a) is a schematic representation of a digital control device 400 according to a second embodiment of the present disclosure. The digital control device 400 is a specific implementation of the digital control device 300.

[0066] In the present embodiment, the PWM control circuit 310 comprises an analog-to-digital converter (ADC) 402 which is coupled to the output voltage node NOUT and configured to digitize the output voltage VOUT.

[0067] The PWM control circuit 310 can further include a digital control loop 404.

[0068] The PWM control circuit 310 can further include a digital PWM circuit 406.

[0069] Fig. 4(b) is a schematic representation of the digital control device 400 of Fig. 4(a) with a specific embodiment of the switching circuit 314 according to a third embodiment of the present disclosure.

[0070] The first phase switches include the first switch 316, a third switch 408 and a fifth switch 410 for coupling the ADC 402, the digital control loop 404 or the digital PWM circuit 406 with the input voltage node NVIN during the first phase.

[0071] The second phase switches include the second switch 318, a fourth switch 412 and a sixth switch 414 for coupling the ADC 402, the digital control loop 404 or the digital PWM circuit 406 with the supply voltage node Nsupply during the second phase.

[0072] Fig. Figure 5(a) is a schematic representation of a digital control device 500 and the switching converter 302 according to a fourth embodiment of the present disclosure. The digital control device 500 may include all the features described herein with respect to other embodiments, according to the understanding of those skilled in the art.

[0073] In the present embodiment, the PWM control circuit 310 is configured to control the switching operation of one or more circuit breakers 304 during a first operating mode. The first operating mode can be used, for example, in the case of "high load" requirements where the load current exceeds a threshold value.

[0074] The digital control device 500 can include an additional circuit 502 configured to control the switching operation of one or more circuit breakers 304 during a second operating mode. The second operating mode can be used, for example, for "light load" requirements where the load current is below a threshold. The additional circuit can, for example, include a PFM control circuit.

[0075] Fig. Figure 5(b) is a schematic representation of a digital control device 504 and the switching converter according to a fifth embodiment of the present disclosure. In the present example, the digital control device 504 shares features with the system as shown in Figure 5(b). Fig. 2 described.

[0076] Examples of the digital control device as described here offer the following advantages: • It suppresses the bounce / kickback on VDIG, which was due to excessive inrush current (as in the system of Fig. 2 would occur). • It enables shorter turn-on times, typically 20ns instead of 100ns, thus making the entire system compatible with downward PFM to PWM transition times. • It relieves the top-cell routing, which can again be limited to the normal supply current consumption IDD, instead of also having to deal with inrush current.

[0077] Fig. Figure 6(a) is a schematic representation of part of a digital control device 600, as it can be implemented in a specific embodiment of one of the digital control devices described herein, according to the understanding of those skilled in the art.

[0078] The present embodiment shows an example of how switches 316 and 318 can be actuated based on the operating phase during PWM operating mode. Although shown for switches 316 and 318, which are used for the power supply of the ADC 402, it is evident that the system of Fig. 6(b) can alternatively or additionally be used to control the power supply of the digital control loop 404 and / or the digital PWM circuit 406, according to the understanding of those skilled in the art.

[0079] Switches 316 and 318 each comprise a transistor. Digital control device 600 comprises a transistor 602, whose gate is coupled to a gate of transistor 316. Digital control device 600 further comprises a transistor 604, which is coupled in series with transistor 602.

[0080] The digital control device 600 further comprises a comparator 606 with a first input coupled to transistors 316 and 318, and a second input coupled to the supply voltage node Nsupply. During operation, the comparator 606 outputs a charging signal (labeled "Charging").

[0081] The digital control device 600 further comprises an OR gate 608 with a first input terminal for receiving a turn-off signal and a second input terminal for receiving the charge signal. The OR gate 608 has an output terminal that is coupled to a gate of transistor 318.

[0082] The digital control device 600 further comprises an AND gate 610 with a first input for receiving the charging signal and a second input for receiving a power-on signal. An output terminal of the AND gate 610 is coupled to a gate of the transistor 604.

[0083] The digital control device 600 further comprises a resistor 611 and a capacitor 613.

[0084] Fig. Figure 6(b) is a diagram showing exemplary waveforms that change over time for a practical implementation of the 600 digital control device. Fig. 6(a). Shown are: a curve 612 of the turn-on signal; a curve 614 of the AND gate output signal; a curve 615 of the charging signal; and a curve 617 of the voltage on the voltage rail VDIG1 supplied to the ADC 402 during operation.

[0085] As previously discussed, three instances of the digital control device 600 can be used to control the power supply of the ADC 402, the digital control loop 404, and the digital PWM circuit 406, with a separate instance being used for each of the three components. Such an embodiment would allow all rails VDIG1, ​​VDIG2, and VDIG3 to "wake up" simultaneously.

[0086] Each rail VDIG1, ​​VDIG2, VDIG3 is individually charged via the associated switch (316, 408, 410), with a large inrush current provided directly from the input voltage VIN, leaving the supply voltage VDIG unloaded.

[0087] As soon as these rails VDIG1, ​​VDIG2, VDIG3 reach a voltage close to VDIG, switches 316, 408, 410 can be switched off and switches 318, 412, 414 can be switched on to connect VDIG1, ​​VDIG2 and VDIG3 to VDIG respectively. Normal operation then resumes.

[0088] The lines connecting switches 316, 408, 410 to VDIG1, ​​VDIG2, VDIG3 are the only ones that need to support the inrush current, while switches 318, 412, 414 can be lower voltage switches designed only for the current during normal operation.

[0089] With reference to Fig. 6(b) VDIG1 is disconnected from a power source before time t1, and the turn-on signal is zero. Transistor 604 is in an off state and therefore does not allow any current flow, thus disabling the current mirror formed by transistor 316 and transistor 602. Furthermore, the turn-off signal is one, so transistor 602 is off. VDIG1 is in a high-impedance state and can optionally be pulled down. In this case, VDIG1 becomes less than VDIG, and the charge signal is one.

[0090] It is obvious that the comparator 606 can be a static comparator, so that it only consumes power when it switches; otherwise, it consumes no power.

[0091] When the FSM 121 sets the turn-on signal to one at time t1 and the turn-off signal to zero, the output of the AND gate 610 goes to one and switches on the high-voltage current mirror formed by transistor 316 and transistor 602. This mirror charges VDIG1 from the input voltage VIN.

[0092] In one specific example, the FSM 121 requires information about when to activate the step-down converter. This could be indicated, for example, by a central point in the system or an external host. The FSM 121 itself follows a predefined (or configurable) sequence of transitions for starting and shutting down.

[0093] In summary: the FSM 121 monitors the load and switches to PWM at high loads (turn-on enabled and turn-off disabled) and to PFM at low loads (turn-on disabled and turn-off enabled).

[0094] When VDIG1 exceeds VDIG, comparator 606 sets the charging signal to zero at time t2. This resets the output of AND gate 610 to zero and prevents the high-voltage current mirror VDIG1 from charging, causing transistor 318 to turn on, connecting and holding VDIG1 with the supply voltage VDIG.

[0095] In summary, the VDIG1 rail now has two switches for power gating: • Switch 316 (charging switch): it has high-voltage characteristics for charging VDIG1 from VIN • The switch 318 (holding switch): it is a low-voltage switch for holding VDIG1 on VDIG.

[0096] Fig. 7(a) is a schematic representation of a digital control device 700 according to a sixth embodiment of the present disclosure.

[0097] The present embodiment shows a possible implementation using a common-gate amplifier. This embodiment does not use a current mirror, so the charging current is defined by the upper resistor and can vary with the voltage vdd.

[0098] Fig. 7(b) is a diagram showing simulation results of the Fig. 7(a) shows the system and uses parameters suitable for practical implementation.

[0099] A curve 702 is a switch-on signal; a curve 704 shows a start-in-progress signal; a curve 706 shows a first start-end signal; a curve 708 shows a second start-end signal; a curve 710 shows VDIG (as in Fig. 5(b) shown); and a curve 712 shows VDIG1 (as in Fig. 5(b) shown). It should be noted that *_n indicates that the curves startlnProgress_n and startFinished_n are ‘inverted’ with respect to the behavior their names suggest (these signals are effectively active low).

[0100] Fig. Figure 8 is a schematic representation of a specific embodiment of the PWM control circuit 310, one or more features of which may be implemented in the embodiments of the present disclosure, according to the understanding of those skilled in the art.

[0101] The operation of the circuit of Fig. 8 is as follows: The output voltage VOUT is digitized by the ADC 402 to provide a digitized output voltage signal DOUT. This digitized output voltage signal DOUT is compared to a digital reference voltage DREF, which corresponds to the target voltage for the output voltage VOUT. Both values, DOUT and DREF, can be, for example, 8-bit bus values, where the digital code [0; 255] corresponds to the analog range [0.50V; 1.50V]. • A digital fault voltage signal DVERR is equal to DREF-DOUT, which is fed into a digital proportional-integral-derivative (PID) control circuit 800 to convert this digitized fault voltage DVERR into a digital setpoint current DITARGET, which is a digital number that specifies the target for setting the analog inductor current IL. If the output voltage VOUT decreases, then the digitized output voltage signal DOUT also decreases, the digital fault voltage signal DVERR increases, and the digital setpoint current DITARGET increases: the digital PID controller 800 requests more inductor current IL to restore the output voltage VOUT. • The digital setpoint current DITARGET can be encoded on multiple bits, e.g., 16 bits, as well as the following signals. The inductor setpoint current DITARGET enters an "inner loop" consisting of (a digital current generation circuit 802; a PIDI circuit 804; a PWM circuit 806; and the power stage 100). This inner loop adjusts the duty cycle MAG / DEMAG so that the analog inductor current IL matches its digital counterpart, the inductor setpoint current DITARGET, on average. • The digital power generation circuit 802 can be the ADC 104, as shown in Fig. 1(a) shown, or can be a “synthesizer” so that it can digitally reproduce the behavior of the inductor current IL depending on the input voltage VIN, the output voltage VOUT, the duty cycle and possibly other parameters. • The inner loop operates as follows: if the digital target current DITARGET is higher than the digital inductor current DIL, the digital current error DIERR increases. The digital current error DIERR passes through an integrator (PID 804) to produce a filtered and amplified version, with the filtered digital current error DIERRF increasing and entering a digital-to-duty converter (the PWM circuit 806) to increase the duty cycle. This results in an increase in the inductor current IL.

[0102] The digital control circuit 404 further includes addition / subtraction circuits 808, 810 and the digital PWM circuit 406 includes the logic and gate driver circuit 812.

[0103] Once the inner loop has reached a stable state, the average digital set current is equal to the average digital inductor current, which can be described as follows: <ditarget> = <dil>

[0104] A variable enclosed in “<>” is used to denote an average of the variables. For example, <x>the average of the variables x.

[0105] In summary, embodiments of this disclosure employ power gating, which is introduced into time-critical control loops of DC-DC converters to enable the use of a technology with lower supply power, lower latency, and higher leakage voltage. This is desirable due to the time-critical nature of VOUT regulation by the control loop, and the extensive processing and calculations that must be completed within two clock cycles (i.e., 40 ns for a 50 MHz clock) to achieve the required timing. Furthermore, embodiments of this disclosure can employ dual-switch charge / hold power gating to meet the requirements of a buck converter (leakage current and 20 ns transition time) and the requirements of the PMIC top cell (routing and kickback / inrush to VDIG).

[0106] Embodiments of the present disclosure can reduce the power consumption and improve the efficiency of a control device for a switching converter that uses a pulse-width modulation control scheme, compared to known systems. Furthermore, embodiments of the present disclosure can satisfy turn-on timing criteria that are not met by known systems.

[0107] Various improvements and modifications can be made to the above without altering the scope of the disclosure.< / x> < / dil> < / ditarget>

Claims

[1] A digital control device for a switching converter configured to receive an input voltage at an input voltage node and generate an output voltage at an output voltage node, the switching converter comprising one or more power switches and an energy storage element, the digital control device comprising: a pulse width modulation control circuit configured to receive the output voltage and generate a PWM control signal to control the switching operation of the one or more power switches; and a switching circuit configured to: i) coupling the pulse width modulation control circuit to the input voltage node during a first phase; and ii) coupling the pulse width modulation control circuit to a supply voltage node during a second phase, wherein the supply voltage node is at a supply voltage. [2] The digital control device according to claim 1, wherein the switching converter is a buck converter, a boost converter or a buck-boost converter. [3] The digital control device according to claim 1 or 2, wherein the energy storage element is an inductor. [4] The digital control device of any preceding claim, wherein the pulse width modulation control circuit comprises an analog-to-digital converter coupled to the output voltage node and configured to digitize the output voltage to provide a digital representation of the output voltage. [5] The digital control device according to claim 4, wherein the pulse width modulation control circuit comprises a digital control loop. [6] The digital control device according to claim 5, wherein the pulse width modulation control circuit comprises a digital PWM circuit. [7] The digital control device according to any preceding claim, wherein the switching circuit comprises one or more first phase switches for coupling the pulse width modulation control circuit to the input voltage node during the first phase and one or more second phase switches for coupling the pulse width modulation control circuit to the supply voltage node during the second phase. [8] The digital control device of claim 7, wherein during the first phase, the one or more second phase switches are open such that the supply voltage node is decoupled from the pulse width modulation control circuit, and during the second phase, the one or more first phase switches are open such that the input voltage node is decoupled from the pulse width modulation control circuit. [9] The digital control device according to any preceding claim, wherein the pulse width modulation control circuit is configured to control the switching operation of the one or more switches during a first mode of operation. [10] The digital control device of claim 9, comprising an additional control circuit configured to control the switching operation of the one or more switches during a second mode of operation. [11] The digital control device according to claim 10, wherein the additional control circuit comprises a pulse frequency modulation control circuit. [12] A method for controlling a switching converter configured to receive an input voltage at an input voltage node and generate an output voltage at an output voltage node, the switching converter comprising one or more power switches and an energy storage element, the method comprising: Receiving the output voltage at a pulse width modulation control circuit; Generating a PWM control signal to control the switching operation of the one or more power switches using the pulse width modulation control circuit; coupling the pulse width modulation control circuit to the input voltage node during a first phase; and Coupling the pulse width modulation control circuit to a supply voltage node during a second phase, wherein the supply voltage node is at a supply voltage.