INTEGRATED CIRCUIT PACKAGE AND METHOD FOR MAKING THE SAME

Abstract

A process comprises forming first conductive elements on and extending through a first composite layer; forming a first polymer layer on the first composite layer; forming a first metallization structure extending through the first polymer layer; forming a second polymer layer over the first polymer layer, wherein the second polymer layer is thinner than the first polymer layer; forming a second metallization structure on and extending through the second polymer layer, wherein the second metallization structure is thinner than the first metallization structure; forming a second composite layer on the first composite layer; and forming second conductive elements extending through the second composite layer.

Description

PRIORITY CLAIM AND CROSS-REFERENCE

[0001] This application claims priority to U.S. Provisional Application No. 63 / 581,039, filed September 7, 2023, which is incorporated by reference into the present application. BACKGROUND

[0002] The semiconductor industry has experienced rapid growth due to ongoing improvements in the integration density of a wide variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). This improvement in integration density is largely due to the iterative reduction of the minimum size of the elements, allowing more components to be integrated in a given area. As the demand for ever smaller electronic devices has increased, a need for smaller and more creative packaging techniques for semiconductor dies has arisen. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of the present disclosure are best understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration. The Fig. 1, Fig. 2, Fig. 3 and Fig. 4 illustrate cross-sectional views of intermediate steps during a process for forming an integrated circuit package according to some embodiments. The Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9 and Fig. 10 illustrate cross-sectional views of intermediate steps during a process for forming a redistribution structure of an integrated circuit package according to some embodiments. The Fig. 11, Fig. 12, Fig. 13, Fig. 14 and Fig. 15 illustrate cross-sectional views of intermediate steps during a process for forming a redistribution structure of an integrated circuit package according to some embodiments. The Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. 20, Fig. 21, Fig. 22, Fig. 23, Fig. 24, Fig. 25 and Fig. 26 illustrate cross-sectional views of intermediate steps during a process for forming an integrated circuit package according to some embodiments. Fig. 27 illustrates a cross-sectional view of a singulation process for forming an integrated circuit package according to some embodiments. Fig. 28 illustrates a cross-sectional view of an integrated circuit package according to some embodiments. Fig. 29 illustrates a cross-sectional view of an integrated circuit package according to some embodiments. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments or examples for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, forming a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are formed in direct contact, and also embodiments in which additional elements may be formed between the first and second elements such that the first and second elements may not be in direct contact. Furthermore, the present disclosure may repeat reference numbers and / or characters in the various examples.This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations described.

[0005] Furthermore, for ease of discussion, spatially relative terms such as "beneath," "under," "lower," "over," "upper," and the like may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass various orientations of the device during use or operation of the device, in addition to the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0006] The embodiments are described with respect to embodiments in a specific context, i.e., integrated circuit packages and methods of forming them. In various embodiments illustrated herein, a package includes a routing structure formed from a plurality of redistribution structures, which may be formed, for example, from polymer layers. The routing structure is formed over a composite interconnect structure formed from a plurality of composite layers, which may be formed, for example, from prepreg layers. Each redistribution structure of the routing structure has different thicknesses and conductive elements of different sizes. The redistribution structures are formed using photolithography techniques, which can improve yield and package manufacturing throughput.The use of multiple composite layers can improve the structural stability and thermal performance of a package.

[0007] The Fig. 1 to 28 illustrate cross-sectional views of intermediate steps in the formation of an integrated circuit package 100 (see Fig. 28) according to some embodiments. In Fig. 1, a carrier substrate 102 is provided or formed. In some embodiments, the carrier substrate 102 comprises a semiconductor material (e.g., silicon or the like), a dielectric material (e.g., glass, ceramic, quartz, plastic, or the like), a combination thereof, or the like. The carrier substrate 102 may be a wafer, so that multiple package components may be formed on the carrier substrate 102 simultaneously. Fig. 1 to 18 illustrate intermediate steps in the formation of a single package component in a structural region 101A of the carrier substrate 102, which is surrounded by an edge region 101B. In some embodiments, the edge regions 101B may be formed as follows for Fig. 18. It should be understood that multiple package components may be formed in the structure region 101A and subsequently processed to form multiple integrated circuit packages 100. The multiple integrated circuit packages 100 may be singulated to form individual integrated circuit packages 100, as described in more detail below.

[0008] Furthermore, Fig. 1, according to some embodiments, a seed layer 104 is formed over the support substrate 102. The seed layer 104 may include a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed from different materials. In a particular embodiment, the seed layer 104 includes a titanium layer and a copper layer over the titanium layer. The seed layer 104 may be formed, for example, by physical vapor deposition (PVD), sputtering, or the like. Other materials or deposition techniques are possible.

[0009] In Fig. 2, according to some embodiments, a first composite layer 106 is formed over the seed layer 104. The first composite layer 106 is an insulating layer formed from one or more layers of composite material. In some embodiments, the first composite layer 106 may be formed from a prepreg composite fiber material ("prepreg" material) or the like, although other materials are also possible. For example, the first composite layer 106 may be formed from a prepreg material comprising resin-prepregnated glass fibers, such as an epoxy-impregnated fiberglass woven laminate, a polyimide-impregnated fiberglass woven laminate, or the like. The first composite layer 106 may comprise a fiberglass woven fabric having any suitable weight, thickness, weave, density, resin content, coefficient of thermal expansion (CTE), or the like.In some cases, the materials of the first composite layer 106 may be selected such that the first composite layer 106 has a CTE similar to the CTE of other elements of the package, such as integrated circuit dies, a support ring, other composite layers, or the like. The first composite layer 106 may comprise a single prepreg material or a stack of prepreg materials. In some embodiments, the first composite layer 106 may be formed on the seed layer 104 using a suitable process, such as a lamination process or the like. In some embodiments, the first composite layer 106 may have a thickness TP1 ranging from approximately 100 μm to approximately 300 μm, although other thicknesses are possible.In some cases, forming an insulating layer from a composite material such as prepreg can enable the formation of packages with improved structural strength and a reduced overall thickness.

[0010] In Fig. 3, according to some embodiments, openings 107 are formed in the first composite layer 106. The openings 107 may extend through the first composite layer 106 to expose portions of the seed layer 104. The openings 107 may be formed using a mechanical drilling process, a laser drilling process, a photolithography masking and etching process, or another suitable process. In some embodiments, each opening 107 may have a width in the range of approximately 100 μm to approximately 300 μm, although other widths are also possible.

[0011] In Fig. 4, according to some embodiments, a conductive material is deposited to form a metallization structure 108. The metallization structure 108 includes conductive portions that extend through the first composite layer 106 and physically and electrically contact the underlying seed layer 104. As shown in Fig. 4, the metallization structure 108 may also include conductive element portions extending along the top surface of the first composite layer 106, such as conductive lines, conductive pads, or the like. In some embodiments, the conductive element portions of the metallization structure 108 on the top surface of the first composite layer 106 may have a thickness in the range of approximately 20 μm to approximately 40 μm, although other thicknesses are also possible. In some cases, the metallization structure 108 and the first composite layer 106 may be considered together as an "interconnect layer."

[0012] The metallization structure 108 may include a conductive material, such as copper, tungsten, aluminum, silver, gold, ruthenium, cobalt, a combination thereof, or the like. The conductive material may be deposited using a suitable technique, such as plating (e.g., electrochemical or electroless plating), chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, or another technique. Other materials or deposition techniques are possible. In some embodiments, the metallization structure 108 may include an optional barrier layer, liner layer, or the like (not shown) covered by the conductive material.

[0013] In some embodiments, the metallization structure 108 may be formed by depositing a cap layer of the conductive material that fills the openings 107 and covers the top surface of the first composite layer 106, and then patterning the cap layer. The conductive material may be patterned using suitable photolithography masking and etching techniques. For example, a photoresist (not shown) may be formed and patterned on the conductive material. The photoresist may be formed by spin-coating or the like and may be exposed to light for patterning. The patterned photoresist may cover portions of the conductive material corresponding to the metallization structure 108, while exposing other portions of the conductive material.An etching process may then be performed to remove the exposed portions of the conductive material, with the metallization structure 108 being formed by the remaining portions of the conductive material. The etching process may include a wet etching process and / or a dry etching process. The photoresist may then be removed using a suitable process, such as an ashing or stripping process.

[0014] In some embodiments, the metallization structure 108 may be formed by first forming a patterned photoresist on the first composite layer 106. For example, a photoresist (not shown) may be formed by spin coating or the like and exposed to light for patterning. The patterned photoresist may expose portions of the first composite layer 106 corresponding to the metallization structure 108, such as exposing the openings 107. The conductive material may then be deposited using a suitable technique. The photoresist and overlying portions of the conductive material may be removed using a suitable technique, with the remaining portions of the conductive material forming the metallization structure 108.

[0015] In some embodiments, the metallization structure 108 may be formed by first forming a seed layer (not shown) over the first composite layer 106 and in the openings 107. A photoresist is then formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization structure 108. Patterning forms openings through the photoresist to expose the seed layer. A conductive material is then formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electrochemical plating, electroless plating, or the like. The photoresist and portions of the seed layer on which the conductive material is not formed are removed.Once the photoresist is removed, exposed portions of the seed layer are removed, for example, using a suitable etching process, such as a wet etching process and / or a dry etching process. The remaining conductive material and the underlying portions of the seed layer form the metallization structure 108. These are examples; other formation techniques are possible.

[0016] The Fig. 5 to 10 illustrate the formation of a first redistribution structure 114 (see Fig. 10) according to some embodiments. The first redistribution structure 114 includes a plurality of metallization structures 112A-D formed in a plurality of dielectric layers 110A-D. The metallization structures 112A-D may include conductive lines, conductive vias, conductive pads, or other conductive elements, and in some cases may be considered redistribution layers or interconnects. The first redistribution structure 114 described herein is an example and may include a different number, arrangement, or configuration of dielectric layers or metallization structures in other embodiments. For example, if fewer dielectric layers and metallization structures are to be formed, some of the steps and processes described below may be omitted.If more dielectric layers and metallization structures are to be formed, some of the steps and procedures described below can be repeated.

[0017] In Fig. 5, according to some embodiments, a dielectric layer 110A is deposited over the first composite layer 106 and the metallization structure 108. In some embodiments, the dielectric layer 110A is formed from a polymer, which may be a photosensitive material such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), or the like, which may be patterned using a lithography mask. In other embodiments, the dielectric layer 110A is formed from a nitride such as silicon nitride; an oxide such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like; or the like. The dielectric layer 110A may be formed by any acceptable deposition process, such as spin coating, chemical vapor deposition (CVD), lamination, the like, or a combination thereof.In some embodiments, the dielectric layer 110A may be formed over the first composite layer 106 with a thickness T1 ranging from about 10 μm to about 60 μm, although other thicknesses are possible.

[0018] In Fig. 6, the dielectric layer 110A is patterned to form openings 111 that expose portions of the metallization structure 108. The dielectric layer 110A may be patterned using an acceptable photolithography process. In embodiments where the dielectric layer 110A is a photosensitive material, the dielectric layer 110A may be exposed to light, for example, using a lithography mask. The dielectric layer 110A may then be developed after exposure to form the openings 111. In other embodiments, a photoresist may be formed and patterned over the dielectric layer 110A, and then the dielectric layer 110A may be etched using the patterned photoresist as an etch mask. In some embodiments, the openings 111 may have a width in the range of approximately 10 μm to approximately 60 μm, although other widths are also possible.

[0019] In Fig. 7, a metallization structure 112A is formed on the dielectric layer 110A. The metallization structure 112A includes conductive lines extending along the top surface of the dielectric layer 110A and conductive vias extending through the openings 111 in the dielectric layer 110A to physically and electrically contact the metallization structure 108. As an example of forming the metallization structure 112A, a seed layer is first formed over the dielectric layer 110A and within the openings 111. In some embodiments, the seed layer is similar to the seed layer 104 or other seed layers described herein. For example, the seed layer may include a metal layer, which may be a single layer or a composite layer comprising multiple sublayers formed from different materials.In some embodiments, the seed layer includes a titanium layer and a copper layer over the titanium layer. The seed layer may be formed, for example, using PVD or the like. Subsequently, a photoresist (not shown) is formed and patterned on the seed layer. The photoresist may be formed by spin coating or the like and may be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 112A. Patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electrochemical plating, electroless plating, or the like.The conductive material may comprise a metal, such as copper, titanium, tungsten, aluminum, or the like. Then, the photoresist and portions of the seed layer on which the conductive material is not formed are removed. The photoresist may be removed, for example, by a suitable ashing or stripping process. Once the photoresist is removed, the exposed portions of the seed layer are removed, for example, using a suitable wet or dry etching process. The remaining portions of the seed layer and the conductive material form the metallization structure 112A. In some embodiments, the conductive line portions of the metallization structure 112A have a thickness above the top surface of the dielectric layer 110A that ranges from approximately 5 μm to approximately 30 μm, although other thicknesses are possible.

[0020] In some embodiments, a further metallization structure 112B may be formed over the metallization structure 112A. In Fig. 8, for example, a dielectric layer 110B may be deposited over the dielectric layer 110A and the metallization structure 112A. The dielectric layer 110B may be a similar material to the dielectric layer 110A and may be formed using similar techniques. In some embodiments, the dielectric layer 110B may also be formed with a similar thickness (e.g., thickness T1) as the dielectric layer 110A. However, in other embodiments, the dielectric layer 110B may be formed from a different material than the dielectric layer 110A and / or have a different thickness than the dielectric layer 110A.

[0021] In Fig. 9, the metallization structure 112B may be formed over the dielectric layer 110B using similar techniques as described for the metallization structure 112A. For example, openings may be patterned into the dielectric layer 110B, exposing portions of the metallization structure 112A. A seed layer may be formed over the dielectric layer 110B and into the openings, and a patterned photoresist may then be formed over the seed layer. A conductive material may be deposited on the exposed portions of the seed layer. The conductive material may be similar to those previously described for the metallization structure 112A.The photoresist and underlying seed layer may then be removed using suitable processes, with the remaining portions of the seed layer and conductive material forming the metallization structure 112B. Thus, the metallization structure 112B includes conductive lines extending along the top surface of the dielectric layer 110B and conductive vias extending through the dielectric layer 110B to physically and electrically contact the metallization structure 112A. The conductive line portions of the metallization structure 112B may have a similar thickness to the metallization structure 112A, although in some embodiments, the metallization structures 112A and 112B may have different thicknesses.

[0022] Additional metallization structures may be formed according to some embodiments using similar techniques as described in the Fig. 5 to 9, to form the first redistribution structure 114. Fig. 10 illustrates the first redistribution structure 114 with four dielectric layers 110A-D and four metallization structures 112A-D, but the first redistribution structure 114 may include any suitable number of dielectric layers and metallization structures. The dielectric layers of the first redistribution structure 114 may have a similar thickness to the thickness T1 described for the dielectric layer 110A, or the dielectric layers may have different thicknesses. The metallization structures of the first redistribution structure 114 may have a similar thickness to the thickness described for the metallization structure 112A, or the metallization structures may have different thicknesses.

[0023] If more dielectric layers and metallization structures are to be formed, the steps and processes described above can be repeated. The metallization structures can include one or more conductive elements. The conductive elements can be formed during the formation of the metallization structure by forming the seed layer and the conductive material of the metallization structure over a surface of the underlying dielectric layer and in openings of the underlying dielectric layer, thereby interconnecting and electrically coupling various conductive lines.

[0024] The Fig. 11 to 16 illustrate, according to some embodiments, the formation of a second redistribution structure 120 (see Fig. 16) over the first redistribution structure 114. The second redistribution structure 120 includes a plurality of metallization structures 118A-C formed in a plurality of dielectric layers 116A-C. The metallization structures 118A-C may include conductive lines, conductive vias, conductive pads, or other conductive elements, and in some cases may be considered redistribution layers or interconnects. The second redistribution structure 120 described herein is an example and may include a different number, arrangement, or configuration of dielectric layers or metallization structures in other embodiments. For example, if fewer dielectric layers and metallization structures are to be formed, some of the steps and processes described below may be omitted.If more dielectric layers and metallization structures are to be formed, some of the steps and procedures described below can be repeated.

[0025] The dielectric layers 116A-C of the second redistribution structure 120 may be formed from similar materials as described for the dielectric layers 110A-D of the first redistribution structure 114. In some embodiments, the dielectric layers 116A-C are formed, for example, from a polymer, which may be a photosensitive material such as PBO, polyimide, BCB, or the like, which may be patterned using a lithography mask. In other embodiments, the dielectric layers 116A-C may be formed from different materials than the dielectric layers 110A-C of the first redistribution structure 114. The dielectric layers 116A-C may be formed by any acceptable deposition process, such as spin coating, chemical vapor deposition (CVD), lamination, the like, or a combination thereof.In some embodiments, each dielectric layer 116A-C may be formed with a thickness T2 ranging from approximately 5 μm to approximately 10 μm, although other thicknesses are also possible. The dielectric layers 116A-C may have similar or different thicknesses. In some embodiments, each dielectric layer of the second redistribution structure 120 has a thickness (e.g., thickness T2) that is less than a thickness (e.g., thickness T1) of each dielectric layer of the first redistribution structure 114.

[0026] In Fig. 11, according to some embodiments, a dielectric layer 116A is deposited over the first redistribution structure 114. The dielectric layer 116A in Fig. 11 is deposited, for example, over the dielectric layer 110D and the metallization structure 112D, which are the topmost dielectric layer and the topmost metallization layer of the first redistribution structure 114. As previously described, the dielectric layer 116A may have a thickness T2 that is smaller than that of the underlying dielectric layer 110D.

[0027] In Fig. 12, the dielectric layer 116A is patterned to form openings 117 that expose portions of the metallization structure 112D. The dielectric layer 116A may be patterned using an acceptable photolithography process. In embodiments where the dielectric layer 116A is a photosensitive material, the dielectric layer 116A may be exposed to light, for example, using a lithography mask. The dielectric layer 116A may then be developed after exposure to form the openings 117. In other embodiments, a photoresist may be formed and patterned over the dielectric layer 116A, and then the dielectric layer 116A may be etched using the patterned photoresist as an etch mask. In some embodiments, the openings 117 may have a width in the range of approximately 5 μm to approximately 10 μm, although other widths are also possible.In some embodiments, the openings 117 have a smaller width and / or a smaller spacing than the openings 111 (see . Fig. 6).

[0028] In Fig. 13, a metallization structure 118A is formed on the dielectric layer 116A. The metallization structure 118A includes conductive lines extending along the top surface of the dielectric layer 116A and conductive vias extending through the openings 117 in the dielectric layer 116A to physically and electrically contact the metallization structure 112D. The metallization structure 118A may be formed using techniques similar to those previously described for forming the metallization structure 112A. For example, a seed layer may first be formed over the dielectric layer 116A and within the openings 117. In some embodiments, the seed layer is similar to the seed layer 104 or other seed layers described herein.For example, the seed layer may include a metal layer formed using PVD or the like. A photoresist (not shown) is then formed and patterned on the seed layer, wherein the pattern of the photoresist corresponds to the metallization pattern 118A. The patterning forms openings through the photoresist to expose the seed layer. A conductive material is formed in the openings of the photoresist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electrochemical plating or electroless plating, or the like. The conductive material may include a metal, such as copper, titanium, tungsten, aluminum, or the like.Subsequently, the photoresist and portions of the seed layer on which the conductive material is not formed are removed, for example, using an ashing process. Once the photoresist is removed, the exposed portions of the seed layer are removed, for example, using a suitable wet or dry etching process. The remaining portions of the seed layer and conductive material form the metallization structure 118A.

[0029] In some embodiments, the conductive line portions of the metallization structure 118A have a thickness above the dielectric layer 116A that ranges from approximately 1 μm to approximately 10 μm, although other thicknesses are possible. The other metallization structures 118B-C of the second redistribution structure 120 may have conductive line thicknesses that are similar to or different from the conductive line thickness of the metallization structure 118A. In some embodiments, each metallization structure of the second redistribution structure 120 has a thickness that is less than a thickness of each metallization structure of the first redistribution structure 114. In some embodiments, each metallization structure of the second redistribution structure 120 has a pitch that is less than a pitch from each metallization structure of the first redistribution structure 114.

[0030] If more dielectric layers and metallization structures are to be formed, the steps and processes described above can be repeated. As shown in the Fig. 14 to 15, additional metallization structures 118B-C may be formed using similar techniques as for metallization structure 118A. For example, in Fig. 14, a dielectric layer 116B is formed over the dielectric layer 116A and the metallization structure 118A. A metallization structure 118B is formed, including conductive line portions on the dielectric layer 116B and conductive via portions extending through the dielectric layer 116B to physically and electrically contact the metallization structure 118A. For example, the metallization structure 118B may be formed by forming the seed layer and the conductive material of the metallization structure 118B over a surface of the underlying dielectric layer 116B and in openings of the underlying dielectric layer 116B, thereby interconnecting and electrically coupling various conductive lines.In some embodiments, the thickness and materials of the dielectric layer 116B and the metallization structure 118B may be similar to those described for the dielectric layer 116A and the metallization structure 118A.

[0031] In Fig. 15, a dielectric layer 116C is formed over the dielectric layer 116B and the metallization structure 118B. A metallization structure 118C is formed, which includes conductive via portions extending through the dielectric layer 116C to physically and electrically contact the metallization structure 118B. In some embodiments, the metallization structure 118C is also formed with conductive line portions on the dielectric layer 116C. The metallization structure 118C may be formed by forming the seed layer and the conductive material of the metallization structure 118C in openings of the underlying dielectric layer 116B, thereby interconnecting and electrically coupling various conductive lines.In some embodiments, the thickness and materials of the dielectric layer 116C and the metallization structure 118C may be similar to those described for the dielectric layer 116A and the metallization structure 118A.

[0032] As described above, in some embodiments, the dielectric layers of the first redistribution structure 114 are thicker than the dielectric layers of the second redistribution structure 120. Furthermore, the metallization structure of the first redistribution structure 114 includes conductive elements (e.g., conductive lines and conductive vias) that are larger (e.g., thicker or wider) than the conductive elements of the metallization structure of the second redistribution structure 120. In some embodiments, a total thickness T3 of the first redistribution structure 114 may be greater than a total thickness T4 of the second redistribution structure 120. In other embodiments, the first redistribution structure 114 may have a total thickness T3 that is less than or approximately equal to the total thickness T4 of the second redistribution structure 120.In some embodiments, a total thickness T3 of the first redistribution structure 114 ranges from approximately 100 μm to approximately 350 μm, and a total thickness T4 of the second redistribution structure 120 ranges from approximately 15 μm to approximately 70 μm, although other thicknesses are possible. Forming a "thin" second redistribution structure 120 over and electrically coupled to a "thick" first redistribution structure 114, as described herein, may enable efficient fan-out routing within a package. In some cases, the first redistribution structure 114 and the second redistribution structure 120 may collectively be considered a "redistribution substrate" or "routing structure" formed on the first composite layer 106.

[0033] Forming the redistribution structures 114 / 120 on the first composite layer 106 as described herein may enable improved yield, improved process throughput, and / or a thinner package. For example, forming the redistribution structures 114 / 120 using photolithography techniques for patterning dielectric layers formed from polymers may result in better yield and faster processing than using other techniques, such as using laser drilling on layers of Ajinomoto build-up film (ABF), organic core, or the like. Furthermore, in some cases, the redistribution structures 114 / 120 may be formed using polymer layers with fewer and / or thinner layers than redistribution structures formed from ABF layers or other composite materials. In this way, the overall thickness of a package may be reduced.By forming the redistribution structures 114 / 120 on the first composite layer 106, a package may further have improved structural stability, improved thermal properties, and improved operation.

[0034] In Fig. 16, according to some embodiments, conductive connectors 122 are formed over the second redistribution structure 120. The conductive connectors 122 may be physically and electrically in contact with the topmost metallization structure of the second redistribution structure 120, such as the metallization structure 118C of the Fig. 16. The conductive interconnects 122 may include ball grid array (BGA) interconnects, solder balls, metal pillars, conductive pads, controlled collapse chip connection (C4) bumps, micro bumps, bumps formed with the electroless nickel-palladium immersion gold (ENEPIG) technique, underbump metallizations (UBMs), or the like. The conductive interconnects 122 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In some embodiments, the conductive interconnects 122 are formed by initially forming a layer of solder by evaporation, electroplating, printing, solder transfer, ball placement, or the like. Once a solder layer has been formed on the structure, reflow may be performed to shape the material into the desired bump shapes.In another embodiment, the conductive connectors 122 include metal pillars (e.g., copper pillars) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal pillars may be solder-free and have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed on top of the metal pillars. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or a combination thereof, and may be formed by a plating process.

[0035] In Fig. 17, one or more integrated circuit dies 126 are attached to the second redistribution structure 120, according to some embodiments. The integrated circuit dies 126 may include a logic die (e.g., a central processing unit (CPU), a graphics processing unit (GPU), system-on-a-chip (SoC), application processor (AP), microcontroller, application-specific integrated circuit (ASIC), etc.), a memory die (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, hybrid memory cube (HMC) module, high bandwidth memory (HBM) module, etc.), a power management die (e.g., power management integrated circuit (PMIC) die), a radio frequency (RF) die, a sensor die, a micro-electro-mechanical system (MEMS) die, a signal processing die (e.g., digital signal processing (DSP) die), a front-end die (e.g., analog front-end (AFE) die), and the like, or combinations thereof.Multiple integrated circuit dies 126 may include similar die types and / or different chip types. The integrated circuit dies 126 may have different sizes (e.g., different heights and / or surface areas) or the same size (e.g., the same heights and / or surface areas).

[0036] In some embodiments, the integrated circuit dies 126 are attached to the second redistribution structure 120 using solder regions that may be formed on the conductive connectors 122 and / or on conductive connectors of the integrated circuit dies 126. The integrated circuit dies 126 may be placed on the second redistribution structure 120 using, for example, a placement tool. After placing the integrated circuit dies 126 on the second redistribution structure 120, the solder regions are in physical contact with the corresponding conductive connectors 122 of the second redistribution structure 120 and corresponding conductive connectors of the integrated circuit dies 126.After placing the integrated circuit dies 126 on the second redistribution structure 120, a reflow process is performed on the solder regions to melt the solder regions and join them together into the solder interconnects 124. The solder interconnects 124 electrically and mechanically couple the integrated circuit dies 126 to the second redistribution structure 120. In some embodiments, an optional underfill (not shown) may be formed between the integrated circuits 126 and the second redistribution structure 120. As shown in FIG. Fig. As shown in Figure 17, in some embodiments, the integrated circuit dies 126 may be attached directly to the second redistribution structure 120 without an interposer or the like. Thus, the redistribution structures 114 / 120 may, in some cases, take the place of an interposer. In other embodiments, an interposer is disposed between the integrated circuit dies 126 and the second redistribution structure 120.

[0037] As in Fig. 17, according to some embodiments, a support ring 128 is attached to the second redistribution structure 120. The support ring 128 may be attached, for example, to mechanically support the package and reduce deflection. In some embodiments, the support ring 128 may enclose the integrated circuit dies 126. The support ring 128 may be formed from a rigid material, such as a metal, a semiconductor, a ceramic, or another material. In some embodiments, the support ring 128 may be attached to the topmost dielectric layer (e.g., the dielectric layer 116C) of the second redistribution structure 120 using an adhesive film or the like (not shown). In some embodiments, the support ring 128 may have a thickness TR ranging from approximately 500 μm to approximately 700 μm, although other thicknesses are possible.The thickness TR of the support ring 128 may be greater than, approximately equal to, or less than the thickness of an integrated circuit die 126.

[0038] In Fig. 18, according to some embodiments, an encapsulation material 130 is formed over the structure, and the edge regions 101B are optionally trimmed. The encapsulation material 130 may be formed over and around the integrated circuit dies 126 and the support ring 128, and in some cases, under the integrated circuit dies 126. In this way, the encapsulation material 130, once formed, encloses the integrated circuit dies 126 and the support ring 128. The encapsulation material 130 may be a molding compound, epoxy, or the like. The encapsulation material 130 may be applied by compression molding, transfer molding, or the like and formed over the carrier substrate 102 such that the integrated circuit dies 126 and the support ring 128 are buried or covered. The encapsulation material 130 may be applied in liquid or semi-liquid form and subsequently cured.

[0039] In some embodiments, a planarization process may be performed after forming the encapsulation material 130. The planarization process may include a chemical mechanical polishing (CMP) process, a grinding process, or the like. The planarization process may remove the encapsulation material 130 over the integrated circuit die 126 and the support ring 128. In some embodiments, the planarization process may expose the support ring 128 and / or one or more of the integrated circuit dies 126. In other embodiments, the support ring 128 and / or one or more of the integrated circuit dies 126 may remain covered by the encapsulation material 130, as shown in Fig. 18. After performing the planarization process, the top surfaces of the encapsulation material 130, the support ring 128, and / or one or more of the integrated circuit dies 126 may be level.

[0040] According to Fig. 18, the edge regions 101B may optionally be trimmed in some embodiments. The trimming process may partially or completely remove material within the edge regions 101B. The trimming process may include a mechanical sawing process, a laser sawing process, an etching process, or the like, or a combination thereof. In some embodiments, after performing the trimming process, the sidewall surfaces of the encapsulation material 130, the first redistribution structure 114, the second redistribution structure 120, and / or the first composite layer 106 may be coplanar or congruent.

[0041] In Fig. 19 the package component of Fig. 18, according to some embodiments, the package component is debonded from the carrier substrate 102, flipped over, and bonded to another carrier substrate 132. The carrier substrate 132 may, in some cases, be similar to the carrier substrate 102. The package component may be attached to the carrier substrate 132 using an adhesive, a release liner, or the like (not shown).

[0042] In Fig. 20, according to some embodiments, a metal layer 105 is formed on the seed layer 104. The metal layer 105 may be formed, for example, using a coating process (e.g., electrochemical plating, electroless plating, or the like) to deposit metal material(s) on the seed layer 104. The deposited metal material(s) and the seed layer 104 together form the metal layer 105, which physically contacts the first composite layer 106 and conductive portions of the metallization structure 108. The metal layer 105 may comprise one or more metals such as copper, titanium, tungsten, aluminum, or the like. In some embodiments, the metal layer 105 has a thickness in the range of approximately 20 μm to approximately 40 μm, although other thicknesses are possible. In some embodiments, the thickness of the metal layer 105 is greater than the thickness of the conductive line portions (e.g.,the metallization layers) of the first redistribution structure 114 and / or the second redistribution structure 120.

[0043] In Fig. 21, according to some embodiments, the metal layer 105 is patterned to form conductive elements 134 on the composite layer 106. The conductive elements 134 may, for example, comprise conductive lines, conductive pads, or the like. The conductive elements 134 may physically and electrically contact the conductive portions of the metallization structure 108. In some embodiments, the conductive elements 134 are thicker than the conductive line portions of the first redistribution structure 114 and / or the second redistribution structure 120. Forming relatively thicker conductive elements 134 in this manner may enable efficient fan-out routing within a package. In some cases, the conductive elements 134 may be considered a metallization structure.

[0044] In Fig. 22, according to some embodiments, a second composite layer 136 is formed over the conductive elements 134 and the first composite layer 106. The second composite layer 136 may be formed from one or more layers of composite material(s), which may be similar to those previously described for the first composite layer 106. For example, the second composite layer 136 may be formed from prepreg or the like. In some embodiments, the second composite layer 136 may be a different material than the first composite layer 106, such as a prepreg with different properties. Other materials or combinations of materials are possible. In some cases, forming an insulating layer from a composite material such as prepreg may enable the formation of packages with improved structural strength and a reduced overall thickness.In some embodiments, the material of the second composite layer 136 may be selected to have a similar CTE to other elements in the package, such as the integrated circuit dies 126, the first composite layer 106, the support ring 128, or the like. In some cases, the materials of the first composite layer 106 and the second composite layer 136 may be selected to have a combined CTE that appropriately matches the CTE of the support ring 128. In this way, a package may have improved thermal performance. In some cases, the first composite layer 106 and the second composite layer 136 may be collectively considered a "composite layer stack" or a "composite interconnect structure."

[0045] In some embodiments, the second composite layer 136 may have a thickness TP2 ranging from approximately 100 μm to approximately 300 μm, although other thicknesses are possible. The second composite layer 136 may have a thickness TP2 that is greater than, approximately equal to, or less than the thickness TP1 of the first composite layer 106. In some embodiments, the first composite layer 106 and the second composite layer 136 may have a combined thickness TP ranging from approximately 500 μm to approximately 700 μm. In some embodiments, the total thickness TP of the composite layers 106 / 136 may be greater than the thickness T4 of the second redistribution structure 120. In some embodiments, the total thickness TP of the composite layers 106 / 136 may be approximately equal to the thickness TR of the support ring 128. In this way, the structural and thermal performance of the package may be improved.Other thicknesses TP1, TP2 or TP or relative thicknesses thereof are possible.

[0046] In Fig. 23, according to some embodiments, openings 135 are formed in the second composite layer 136. The openings 135 may extend through the second composite layer 136 to expose portions of the conductive elements 134. The openings 135 may be formed using a similar technique as described for the openings 107 (see Fig. 3). The openings 135 may be formed, for example, using a mechanical drilling process, a laser drilling process, a photolithography masking and etching process, or another suitable process. In some embodiments, each opening 135 may have a width in the range of approximately 100 μm to approximately 300 μm, although other widths are also possible.

[0047] In Fig. 24, according to some embodiments, a conductive material is deposited to form a metallization structure 138. The metallization structure 138 includes conductive portions that extend through the second composite layer 136 and physically and electrically contact the underlying conductive elements 134. As shown in Fig. 24, the metallization structure 138 may also include conductive element portions extending along the top surface of the second composite layer 136, such as conductive lines, conductive pads, or the like. In some embodiments, the conductive element portions of the metallization structure 138 on the top surface of the first composite layer 106 may have a thickness in the range of approximately 100 μm to approximately 300 μm, although other thicknesses are also possible. In some cases, the conductive elements 134, the metallization structure 138, and the second composite layer 136 may collectively be considered an "interconnect layer."

[0048] The metallization structure 138 may be formed using similar techniques as described for the metallization structure 108. For example, a seed layer may be formed over the second composite layer 136 and in the openings 135, and a patterned photoresist may then be formed over the seed layer. A conductive material may be deposited on the exposed portions of the seed layer. The conductive material may be similar to those previously described for the metallization structure 108. The photoresist and the underlying seed layer may then be removed using suitable processes, with the remaining portions of the seed layer and conductive material forming the metallization structure 108. Other formation techniques are possible.

[0049] In Fig. 25, according to some embodiments, a solder resist layer 140 is formed over the second composite layer 136 and the metallization structure 138. The solder resist layer 140 may comprise a suitable insulating material, such as a dielectric material, a polymer material, or the like, and may be formed using any suitable deposition technique. In some embodiments, the solder resist layer 140 is patterned to form one or more openings in the solder resist layer 140 that expose portions of the metallization structure 138. The patterning process may include suitable photolithography and etching techniques. The etching techniques may include a dry etching process or a wet etching process and may be anisotropic.

[0050] In Fig. 26, according to some embodiments, conductive connectors 142 are formed. The conductive connectors 142 extend through the openings in the solder resist layer 140 to physically and electrically contact the exposed portions of the metallization structure 138. The conductive connectors 142 may be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, bumps formed with the electroless nickel-electroless palladium immersion gold (ENEPIG) technique, or the like. In some cases, the conductive connectors 142 may be formed using similar materials and methods as those described above with reference to Fig. 17 described conductive connector 122.

[0051] In Fig. 27, according to some embodiments, a dicing process is performed to separate the structure into individual integrated circuit packages 100. The dicing process may include mechanical sawing, laser sawing, etching, dicing, a combination thereof, or the like. In some cases, the techniques described herein enable the formation of integrated circuit packages 100 using only one dicing process. In other words, all sidewall layers of the integrated circuits 100 are sawed through in the same process, thus avoiding the need to perform multiple sawing processes when manufacturing the integrated circuit packages 100. In this way, a package may be formed using fewer processing steps, which may reduce costs and increase throughput.

[0052] Fig. 28 illustrates a singulated integrated circuit package 100 according to some embodiments. Due to the singulation process described above, the integrated circuit package 100 has planar sidewalls. As shown in Fig. 28, for example, sidewall surfaces of the encapsulation material 130, the first composite layer 106, the second composite layer 136, the first redistribution structure 114, the second redistribution structure 120, and / or the solder resist layer 140 may be coplanar (e.g., congruent).

[0053] In other embodiments, the composite interconnect structure of an integrated circuit package 100 may include a different number of composite layers and associated metallization structures. Fig. For example, Figure 29 illustrates an integrated circuit package 100 similar to the integrated circuit package 100 of claim 28, except that a third composite layer 146 is formed on the second composite layer 136. Furthermore, a metallization structure 148 is formed on the third composite layer 146. The metallization structure 148 may include conductive portions extending through the third composite layer 146 and physically and electrically contacting the underlying metallization layer 138. As shown in Fig.29, the metallization structure 148 may also include conductive element portions extending along the top surface of the third composite layer 146, such as conductive lines, conductive pads, or the like. The third composite layer 146 may be formed using materials and techniques similar to those previously described for the first composite layer 106 and / or the second composite layer 136. The composite layers 106 / 136 / 146 may be formed from similar or different materials. The metallization structure 148 may be formed using materials and techniques similar to those previously described for the metallization structure 108 and / or the metallization structure 138. In some cases, the metallization structure 148 and the third composite layer 146 may collectively be considered an "interconnect layer."The process steps described for the composite layers 136 / 146 and the metallization structures 138 / 148 can be repeated to form any number of composite layers and metallization structures in an integrated circuit package 100. The conductive interconnects 142 can be formed on the metallization layer 148. In some cases, forming additional composite layers and metallization structures can provide improved structural stability, improved thermal performance, and additional electrical routing.

[0054] Other elements and processes may also be included. For example, test structures may be included to assist in verification testing of the 3D packaging or 3DIC devices. The test structures may, for example, include test pads formed in a redistribution layer or on a substrate, enabling testing of the 3D packaging or 3DIC, the use of probes and / or probe cards, and the like. Verification testing may be performed on intermediate structures as well as on the final structure. Furthermore, the structures and methods disclosed herein may be used in conjunction with test methodologies that include intermediate verification of known good dies to increase yield and reduce costs.

[0055] Embodiments may achieve advantages. Forming routing over a composite layer using polymer layers instead of, for example, ABF layers can improve yield, increase throughput, increase routing density, and reduce package thickness. Using photolithography techniques instead of laser drilling, for example, can avoid drilling particles, which reduces yield, and multiple openings can be formed simultaneously instead of sequentially, which can increase process throughput. Additionally, using polymer layers instead of ABF layers or the like can reduce the total number of layers used for routing, which can reduce thickness, processing time, and cost.Forming a second redistribution structure with thinner dielectric layers and smaller line widths over a first redistribution structure with thicker dielectric layers and larger line widths can enable efficient fan-out routing for a package. The techniques described herein also enable a single dicing or singulation process, which can reduce processing time and cost and improve throughput. Furthermore, forming multiple composite layers can improve package strength and enable better CTE matching, which can improve package thermal performance.

[0056] According to one embodiment of the present disclosure, a method comprises forming first conductive elements on and extending through a first composite layer; forming a first polymer layer on the first composite layer; forming a first metallization structure extending through the first polymer layer; forming a second polymer layer over the first polymer layer, wherein the second polymer layer is thinner than the first polymer layer; forming a second metallization structure on and extending through the second polymer layer, wherein the second metallization structure is thinner than the first metallization structure; forming a second composite layer on the first composite layer; and forming second conductive elements extending through the second composite layer.In one embodiment, forming the first metallization structure comprises patterning the first polymer layer using a lithography mask to expose a first conductive element, and depositing a conductive material on the first polymer layer and on the exposed first conductive element. In one embodiment, the method comprises bonding integrated circuit dies to the second metallization structure. In one embodiment, the first composite layer comprises a layer of prepreg material. In one embodiment, the first polymer layer physically contacts the first composite layer. In one embodiment, the method comprises forming third conductive elements on the first composite layer and on the first conductive elements prior to forming the second composite layer.In one embodiment, a thickness of the third conductive elements is greater than the thickness of the first metallization structure. In one embodiment, the first polymer layer and the second polymer layer are different polymers.

[0057] According to one embodiment of the present disclosure, a method comprises forming a first interconnect layer on a first carrier substrate, wherein the first interconnect layer comprises a first composite material; forming a first redistribution structure on the first interconnect layer, wherein forming the first redistribution structure comprises depositing a first dielectric layer; patterning the first dielectric layer using a lithography mask; and depositing a first conductive material on the first dielectric layer; forming a second redistribution structure on the first redistribution structure,wherein forming the second redistribution structure comprises depositing a second dielectric layer; patterning the second dielectric layer using a lithography mask; and depositing a second conductive material on the second dielectric layer; and attaching an integrated circuit die to the second redistribution structure. In one embodiment, the first conductive material is deposited to a first thickness and the second conductive material is deposited to a second thickness that is less than the first thickness. In one embodiment, the first dielectric layer comprises at least one of polybenzoxazole (PBO), polyimide, or benzocyclobutene (BCB). In one embodiment, the method comprises attaching a support ring to the second redistribution structure. In one embodiment, the method comprises forming a second interconnect layer on the first interconnect layer,wherein the second interconnect layer comprises a second composite material, wherein the second interconnect layer is electrically connected to the first interconnect layer. In one embodiment, the method comprises performing a sawing process, wherein, after performing the sawing process, sidewall surfaces of the first interconnect layer, the first redistribution structure, and the second redistribution structure are coplanar. In one embodiment, the method comprises depositing a seed layer on the first carrier substrate prior to forming the first interconnect layer.

[0058] According to one embodiment of the present disclosure, a package comprises a first composite layer; a second composite layer on the first composite layer; conductive elements within the first composite layer and the second composite layer; a first redistribution structure on the second composite layer, the first redistribution structure comprising first polymer layers and first conductive lines; a second redistribution structure on the first redistribution structure, the second redistribution structure comprising second polymer layers and second conductive lines, the second polymer lines being thinner than the first polymer lines, the second conductive lines being thinner than the first conductive lines; and a semiconductor device attached to the second redistribution structure.In one embodiment, the package includes an encapsulation material over the semiconductor device, wherein the encapsulation material and the second redistribution structure have coplanar sidewalls. In one embodiment, the first composite layer, the second composite layer, the first redistribution structure, and the second redistribution structure have coplanar sidewalls. In one embodiment, the thickness of the first redistribution structure is greater than the thickness of the second redistribution structure. In one embodiment, a combined thickness of the first composite layer and the second composite layer is greater than a thickness of the second redistribution structure.

[0059] The foregoing describes features of several embodiments so that those skilled in the art can better understand aspects of the present disclosure. It should be apparent to those skilled in the art that they can readily use the present disclosure as a basis to design or modify other processes and structures to carry out the same purposes and / or achieve the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 581,039

[0001]

Claims

[1] Method comprising: Forming a plurality of first conductive elements on and extending through a first composite layer; Forming a first polymer layer on the first composite layer; Forming a first metallization structure extending through the first polymer layer; Forming a second polymer layer over the first polymer layer, wherein the second polymer layer is thinner than the first polymer layer; Forming a second metallization structure on and extending through the second polymer layer, the second metallization structure being thinner than the first metallization structure; Forming a second composite layer on the first composite layer; and Forming a plurality of second conductive elements extending through the second composite layer. [2] The method of claim 1, wherein forming the first metallization structure comprises: Patterning the first polymer layer using a lithography mask to expose a first conductive element; and Depositing a conductive material on the first polymer layer and on the exposed first conductive element. [3] The method of claim 1 or 2 further comprising connecting a plurality of integrated circuit dies to the second metallization structure. [4] A method according to any one of the preceding claims, wherein the first composite layer comprises a layer of prepreg material. [5] A method according to any preceding claim, wherein the first polymer layer physically contacts the first composite layer. [6] The method of any preceding claim 1, further comprising, prior to forming the second composite layer, forming a plurality of third conductive elements on the first composite layer and on the plurality of first conductive elements. [7] The method of claim 6, wherein a thickness of the plurality of third conductive elements is greater than a thickness of the first metallization structure. [8] A method according to any one of the preceding claims, wherein the first polymer layer and the second polymer layer comprise different polymers. [9] Method comprising: Forming a first interconnect layer on a first carrier substrate, the first interconnect layer comprising a first composite material; Forming a first redistribution structure on the first interconnect layer, wherein forming the first redistribution structure comprises: depositing a first dielectric layer; Structuring the first dielectric layer using a lithography mask; and depositing a first conductive material on the first dielectric layer; Forming a second redistribution structure on the first redistribution structure, wherein forming the second redistribution structure comprises: depositing a second dielectric layer; Structuring the second dielectric layer using a lithography mask; and depositing a second conductive material on the second dielectric layer; and Attaching an integrated circuit die to the second redistribution structure. [10] The method of claim 9, wherein the first conductive material is deposited to a first thickness and the second conductive material is deposited to a second thickness that is less than the first thickness. [11] The method of claim 9 or 10, wherein the first dielectric layer comprises at least one of polybenzoxazole (PBO), polyimide, or benzocyclobutene (BCB). [12] The method of any one of claims 9 to 11, further comprising attaching a support ring to the second redistribution structure. [13] The method of any one of claims 9 to 12, further comprising forming a second interconnect layer on the first interconnect layer, the second interconnect layer comprising a second composite material, the second interconnect layer being electrically connected to the first interconnect layer. [14] The method of any one of claims 9 to 13, further comprising performing a sawing process, wherein after performing the sawing process, the sidewall surfaces of the first interconnect layer, the first redistribution structure and the second redistribution structure are coplanar. [15] The method of any one of claims 9 to 14, further comprising, prior to forming the first interconnect layer, depositing a seed layer on the first carrier substrate. [16] Package comprising: a first composite layer; a second composite layer on the first composite layer; a plurality of conductive elements within the first composite layer and the second composite layer; a first redistribution structure on the second composite layer, the first redistribution structure comprising a plurality of first polymer layers and a plurality of first conductive lines; a second redistribution structure on the first redistribution structure, the second redistribution structure comprising a plurality of second polymer layers and a plurality of second conductive lines, the second polymer lines being thinner than the first polymer lines, the second conductive lines being thinner than the first conductive lines; and a semiconductor device attached to the second redistribution structure. [17] The package of claim 16, further comprising an encapsulation material over the semiconductor device, wherein the encapsulation material and the second redistribution structure have coplanar sidewalls. [18] The package of claim 16 or 17, wherein the first composite layer, the second composite layer, the first redistribution structure and the second redistribution structure have coplanar sidewalls. [19] Package according to one of claims 16 to 18, wherein a thickness of the first redistribution structure is greater than a thickness of the second redistribution structure. [20] The package of any one of claims 16 to 19, wherein the combined thickness of the first composite layer and the second composite layer is greater than a thickness of the second redistribution structure.

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