Etching stop layers

Abstract

Contact structures and methods for their fabrication are provided. A method according to the present disclosure comprises the following steps: receiving a workpiece with a conductive structural element embedded in a first dielectric layer; treating the workpiece with a nitrogen-containing plasma; after treatment, depositing a first etch stop layer (ESL) over the workpiece; depositing a second ESL over the first ESL; depositing a second dielectric layer over the second ESL; forming an opening through the second dielectric layer, the second ESL, and the first ESL to expose the conductive structural element; and creating a contact via in the opening. The first ESL comprises aluminum nitride or silicon carbonitride, and the second ESL comprises aluminum oxide or silicon oxide carbide.

Description

PRIORITY CLAIM

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 585,440, filed September 26, 2023, which is incorporated by reference into the present application. BACKGROUND

[0002] The electronics industry has experienced an ever-increasing demand for smaller and faster electronic devices that are simultaneously capable of supporting a greater number of increasingly complex and demanding functions. Therefore, there is a continuing trend in the semiconductor industry to produce low-cost integrated circuits (ICs) with high performance and low power consumption. To date, these goals have been achieved largely by reducing the dimensions of semiconductor ICs (e.g., the smallest feature width), thereby improving production performance and reducing associated costs. However, this downsizing has also made the semiconductor manufacturing process more complex. Therefore, the realization of further advances in semiconductor ICs and devices requires similar advances in semiconductor manufacturing processes and technologies.

[0003] As semiconductor device dimensions continue to shrink, back-end-of-line (BEOL) interconnect structures are subject to tighter power, performance, and area (PPA) process windows and more stringent requirements. Etch stop layers in BEOLs play an important role in reducing leakage, improving adhesion, improving resistance-capacitance matching, and reducing resistance-capacitance delay. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present disclosure are best understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration. Fig. 1 is a flow diagram of a method 100 for fabricating a contact structure according to one or more aspects of the present disclosure. The Fig. 2-16 are fragmentary sectional views of a workpiece at various stages of manufacture according to the process in Fig. 1 according to one or more aspects of the present disclosure. Fig. 17 is a flow diagram of a method 400 for fabricating a contact structure according to one or more aspects of the present disclosure. The Fig. 18-25 are fragmentary sectional views of a workpiece at various stages of manufacture according to the process in Fig. 17 according to one or more aspects of the present disclosure. Fig. 26 shows a fragmentary cross-sectional view of a fin-type field effect transistor (FinFET) 500 and associated contact structures in accordance with one or more aspects of the present disclosure. Fig. 27 shows a fragmentary cross-sectional view of a gate-all-around (GAA) transistor 600 and associated contact structures in accordance with one or more aspects of the present disclosure. DETAILED DESCRIPTION

[0005] The following description provides many different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and may also include embodiments in which additional elements may be fabricated between the first and second elements such that the first and second elements are not in direct contact. Furthermore, in the present disclosure, reference numbers and / or letters may be repeated in the various examples.This repetition is for simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to conveniently describe the relationship of one element or structure to one or more other elements or structures illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative descriptors used herein may be interpreted accordingly.

[0007] Furthermore, when a number or range of numbers is described with the terms "about," "approximately," and the like, the term is intended to include numbers that are within a reasonable range, taking into account variations inherent in manufacturing, that would be known to one of ordinary skill in the art. For example, based on known manufacturing tolerances associated with the manufacture of a feature having a characteristic associated with the number, the number or range of numbers may have a reasonable range that includes the stated number, such as within ±10% of the stated number. For example, a material layer having a thickness of "about 5 nm" may include a dimensional range of 4.25 nm to 5.75 nm if one of ordinary skill in the art would know that the manufacturing tolerances associated with depositing the material layer are ±15%.One or more source / drain regions may individually or collectively represent a source or a drain, depending on the context.

[0008] As device dimensions continue to shrink, the industry is working hard to keep pace with Moore's Law. As front-end-of-line (FEOL) devices become smaller, back-end-of-line (BEOL) interconnect structures play a larger role in keeping pace with PPA requirements. For example, BEOL interconnect structures can incorporate low-k dielectric layers to minimize parasitic capacitance. To achieve etch endpoint detection, etch stop layers (ESLs) that are more etch-resistant than the low-k dielectric layers can be deposited to provide different etch rates.Existing etch stop layers may not have sufficiently large process windows when applied to device structures that include thick, small-pitch metal structures, radio frequency (RF) devices, and high-performance computing (HPC) systems.

[0009] The present disclosure provides several etch stop layer (ESL) structures to meet various device performance requirements. When used over a conductive copper feature in a dielectric layer, the conductive copper feature and the dielectric layer are first subjected to a plasma treatment. A metal nitride layer or a nitrogen-doped silicon carbide layer may be deposited as a lower ESL over the conductive copper feature. A metal oxide layer or an oxygen-doped silicon carbide layer may be deposited as an upper ESL over the lower ESL. In some embodiments where the lower ESL comprises metal nitride and the upper ESL comprises metal oxide, a middle ESL may be deposited to improve adhesion between the lower and upper ESLs.When used over a conductive tungsten feature in a dielectric layer, a metal oxide layer can be deposited as a lower ESL over the conductive tungsten feature and the dielectric layer to improve adhesion. A metal nitride layer or another metal oxide layer can be deposited as an upper ESL over the lower ESL.

[0010] The various aspects of the present disclosure will now be described in more detail with reference to the figures. In this regard, the Fig. 1 and Fig. 17 Flow diagrams illustrating a method 100 and a method 400 for producing a contact structure on a workpiece 200. The methods 100 and 400 are merely examples and are not intended to limit the present disclosure to what is expressly set forth in the method 100 or the method 400. Additional steps may be provided before, during, and after the method 100 or the method 400, and some of the described steps may be replaced, omitted, or shifted for further embodiments of the method 100 or the method 400. For simplicity, not all steps are described in detail here. The method 100 is described below in connection with the Fig. 2-16, which are fragmentary sectional views of a workpiece 200 at various stages of manufacture according to embodiments of the method 100. The method 400 is described below in connection with the Fig. 18-25, which are fragmentary cross-sectional views of the workpiece 200 at various stages of fabrication according to embodiments of the method 400. Since the workpiece 200 is fabricated into a semiconductor structure 200 after completion of the fabrication process, the workpiece 200 may be referred to as a semiconductor structure 200, as the context warrants. Furthermore, throughout the present application and across the various embodiments, similar features having similar structures and compositions are referred to with similar reference numerals unless otherwise indicated. As used in this disclosure, one or more source / drain regions may individually or collectively refer to a source or a drain, depending on the context.

[0011] In the Fig. 1 and Fig. 2, the method 100 includes a block 102 in which a workpiece 200 having a first contact structure element 204 disposed in a first dielectric layer 202 is received. The first contact structure element 204 comprises copper (Cu) and may also comprise cobalt (Co) or nickel (Ni). The first contact structure element 204 may be a metal line, a contact via, or a source / drain contact. The first dielectric layer 202 may be an interlayer dielectric (ILD) layer or an intermetal dielectric (IMD) layer. In some embodiments, the first dielectric layer 202 may comprise silicon oxide or a low-k dielectric material having a k-value (dielectric constant) less than that of silicon oxide; the k-value of silicon oxide is approximately 3.9.In some embodiments, the low-k dielectric material comprises a porous organosilicate thin film (e.g., SiOCH), tetraethylorthosilicate oxide (TEOS oxide), undoped silicate glass, borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, porous carbon-doped silicon dioxide, silicon oxide carbonitride (SiOCN), spin-coated silicon-based polymeric dielectrics, or combinations thereof. Although not explicitly shown in the figures, the first contact structure element 204 may be spaced from the first dielectric layer 202 by a barrier layer. The barrier layer can be titanium nitride (TiN), cobalt nitride (CoN), manganese nitride (MnN), nickel nitride (NiN), tungsten nitride (WN), or tantalum nitride (TaN). As shown in . Fig. 2, the top surfaces of the first contact structure element 204 and the first dielectric layer 202 may be coplanar as a result of a planarization process.

[0012] In the Fig. 1 and Fig. 2, the method 100 includes a block 104 in which a plasma treatment 300 is performed on a top surface of the workpiece 200. To passivate the top surface of the first contact structure element 204 and to improve the adhesion between the first contact structure element 204 and the lower ESL 208, the top surface of the workpiece 200 is subjected to a plasma treatment 300. The plasma treatment 300 includes the use of a plasma of ammonia (NH3) and nitrogen (N2) and may create a nitrogen-rich top surface 206 on the workpiece 200. Prior to the plasma treatment 300, a top surface of the first contact structure element 204 may be oxidized to include copper oxide as a result of the planarization process or the treatment with oxygen, and a top surface of the first dielectric layer 202 may include dangling bonds, an oxygen bond, and alkyl groups.Experimental results show that the plasma treatment 300 can reduce the surface copper oxide to copper, remove the dangling bonds, or replace the alkyl group with nitrogen atoms. Furthermore, the plasma treatment 300 in block 104 can create low-orbital metal-nitrogen bonds, such as nitrogen-copper bonds. The surface reduction and nitriding caused by the plasma treatment promotes adhesion and reduces electromigration of copper. In some implementations, a ratio of a nitrogen (N2) flow rate to ammonia (NH3) flow rate in the plasma treatment 300 can be between about 45 and about 15.

[0013] In the Fig. 1 and Fig. 3, the method 100 includes a block 106 in which a lower etch stop layer (ESL) 208 is deposited over the workpiece 200. In some embodiments, the lower ESL 208 may comprise a metal nitride, such as aluminum nitride (AlN). When the lower ESL 208 comprises aluminum nitride (AlN), the lower ESL 208 may be deposited using atomic layer deposition (ALD), which includes multiple thermal ALD cycles at a temperature between about 300°C and about 400°C. The deposition of the lower ESL 208 may include the use of an aluminum-containing precursor, such as trimethylaluminum (Al(CH3)3), and a nitrogen-containing precursor, such as ammonia (NH3). In some alternative embodiments, the lower ESL 208 may be deposited using chemical vapor deposition (CVD) or plasma-enhanced chemical vapor deposition (PECVD) (PECVD).In embodiments where the lower ESL 208 comprises aluminum nitride (AlN), the lower ESL 208 may have a thickness between about 20 Å and about 40 Å. Because the lower ESL 208 is deposited on the nitrogen-rich top surface 206, a bottom surface of the lower ESL 208 has a greater nitrogen content than a top surface of the lower ESL 208.

[0014] In the Fig. 1 and Fig. 4, the method 100 includes an optional block 108 in which a middle ESL 210 is deposited over the workpiece 200. The operations in block 108 are optional. When the operations are performed, the middle ESL 210 is deposited directly on the lower ESL 208 to serve as an adhesion promotion layer between the lower ESL 208 and an upper ESL 212 (described below). In some embodiments, the middle ESL 210 comprises oxygen-doped silicon carbide (SiC:O or O-SiC). The middle ESL 210 may be deposited using CVD or PECVD using tetramethylsilane (Si(CH3)4), silane (SiH4), trimethylsilane (Si(CH3)3H), carbon dioxide (CO2), xenon (Xe), oxygen (O2), and the like. It should be noted that the medium ESL 210, when manufactured, is deliberately and intentionally deposited with an oxygen atomic percentage between about 20% and about 30%.The middle ESL 210 can not only improve the adhesion between the lower ESL 208 and the upper ESL 212, but also suppress etch bump formation in the first metal contact feature 204. When implemented, the middle ESL 210 can have a thickness between about 50 Å and about 100 Å. This thickness range is not insignificant. If the thickness of the middle ESL 210 is less than 50 Å, it cannot effectively suppress etch bump formation. If the thickness of the middle ESL 210 is greater than 100 Å, the increased thickness can excessively increase the parasitic capacitance. In some embodiments, the operations in block 108 are omitted, and the upper ESL 212 is deposited directly on the lower ESL 208.

[0015] In the Fig. 1 and Fig. 5, the method 100 includes an optional block 110 in which an upper ESL 212 is deposited over the workpiece 200. The operations in block 110 are also optional. When the operations are performed, the upper ESL 212 is deposited directly on the middle ESL 210 (if the operations in block 108 are performed) or on the lower ESL 208 (if the operations in block 108 are not performed). The upper ESL 212 comprises a metal oxide. In some embodiments, the upper ESL 212 may comprise alumina (AlO), hafnium silicate (HfSiO4), or hafnium alumina (HfAlO). In one embodiment, the upper ESL 212 comprises alumina. The upper ESL 212 may be deposited using CVD, ALD, PECVD, or plasma-enhanced ALD (PEALD). The upper ESL 212 and the lower ESL 208 may have the same thickness to facilitate etch endpoint detection.In some cases, the upper ESL 212 may have a thickness between about 20 Å and about 40 Å. For ease of reference, the lower ESL 208, the middle ESL 210, and the upper ESL 212 may be collectively referred to as a first ESL stack 2002. Although not explicitly shown in the figures, an oxygen-doped silicon carbide (SiC:O or O-SiC) may be deposited over the upper ESL 212 to improve adhesion with a later-formed low-k dielectric layer, such as the second dielectric layer 230.

[0016] In the Fig. 1 and Fig. 6, the method 100 includes a block 112 in which a second dielectric layer 230 is deposited over the workpiece 200. In some embodiments, a composition of the second dielectric layer 230 may be similar to the composition of the first dielectric layer 202. In some implementations, the second dielectric layer 230 may be deposited over the upper ESL 212 using spin coating, CVD, or flowable chemical vapor deposition (FCVD). To improve the quality and density of the second dielectric layer 230 to withstand later patterning operations, in some cases, an annealing process may be performed to improve the quality of the second dielectric layer 230.After deposition of the second dielectric layer 230, a planarization process, such as a chemical mechanical polishing (CMP) process, may be performed on the second dielectric layer 230 to provide a planar top surface.

[0017] In the Fig. 1 and Fig. 7, the method 100 includes a block 114 in which a first conductive feature 240 is formed through the second dielectric layer 230, the upper ESL 212, the middle ESL 210, and the lower ESL 208. The operations in block 114 may include forming a dual damascene opening through the second dielectric layer 230, the upper ESL 212, the middle ESL 210 (if formed), and the lower ESL 208 to expose the first contact feature 204, and forming the first conductive feature 240 in the dual damascene opening. In an exemplary process, a first patterned mask is first formed by photolithographic processes, and a dry etch process is performed to form a via opening through the second dielectric layer 230 and the first ESL stack 2002.A second patterned mask is then formed, and another dry etch process is performed to create a trench opening that overlaps the via opening. The dry etches in block 114 may implement an oxygen-containing gas, hydrogen, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, CH3F, C4H8, C4F6, and / or C2F6), a carbon-containing gas (e.g., CO, CH4, and / or C3H8), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBR3), an iodine-containing gas, other suitable gases and / or plasmas, and / or combinations thereof. In some implementations, the fluorine in the dry etch process may form compounds or polymers with the upper ESL 212, the lower ESL 208, and the first contact structure element 204. These compounds or polymers may be redeposited in the dual damascene opening.To remove these compounds and polymers, a wet cleaning process can be performed. In some cases, the wet cleaning process may involve ammonium hydroxide (NH4OH) and a copper corrosion inhibitor. The copper inhibitor may, for example, include 5-methyl-1H-benzotriazole (MBTA) and 1H-benzotriazole (BTA).

[0018] After forming the dual damascene opening, block 114 includes depositing a barrier layer 242 in the dual damascene opening. In some embodiments, the barrier layer 242 may comprise a metal nitride, such as titanium nitride, cobalt nitride, manganese nitride, nickel nitride, tungsten nitride, or tantalum nitride. In one embodiment, the barrier layer 242 comprises titanium nitride. The barrier layer 242 may be deposited using chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), or plasma-enhanced ALD (PEALD). After depositing the barrier layer 242, a metal fill layer 244 may be deposited over the barrier layer 242. The metal fill layer 244 may comprise copper (Cu), cobalt (Co), nickel (Ni), ruthenium (Ru), or tungsten (W). In one embodiment, the metal fill layer 244 comprises copper (Cu).The metal fill layer 244 can be deposited by physical vapor deposition (PVD), electroplating, or electroless plating. For example, the metal fill layer 244 can be deposited by electroplating. In this example process, a seed layer can be deposited over the workpiece 200 using PVD or CVD. The seed layer can include titanium, copper, or both. Then, copper is deposited over the seed layer by electroplating. After deposition of the barrier layer 242 and the metal fill layer 244, the workpiece 200 is planarized to expose the second dielectric layer 230 and to form the first conductive feature 240. The planarization can include chemical mechanical polishing (CMP). As shown in FIG. Fig. 7, the workpiece 200 is planarized until a planar top surface of the workpiece 200 includes top surfaces of the second dielectric layer 230, the barrier layer 242, and the metal fill layer 244.

[0019] As shown by the dashed lines, a via portion of the first conductive feature 240 may have a varying sidewall profile. Since the lower ESL 208 and the upper ESL 212 are etched more slowly and their etching creates compounds and polymers that may be redeposited over the dual damascene opening, the sidewalls extending through the first ESL stack 2002 are substantially straight along the z-direction. The same cannot be said for the second dielectric layer 230. First, the second dielectric layer 230 is etched much faster than the lower ESL 208 and the upper ESL 212. During the dry etch of the second dielectric layer 230, the byproducts are easily removed and are not redeposited. Consequently, the sidewalls extending through the second dielectric layer 230 may taper downwards. As shown in Fig. 7, the sidewall profiles in the via section change from the second dielectric layer 230 to the first contact structure element 204 from a downward taper to a smaller downward taper along the z-direction.

[0020] The method 100 may be applied to fabricate alternative ESL stacks over the first contact structure element 204. First, reference is made to the Fig. 8-10. In some embodiments, the operations in block 108 are omitted, and the middle ESL 210 is not deposited on the lower ESL 208. Referring to Fig. 8, the upper ESL 212 is deposited directly on the lower ESL 208 in block 110. The lower ESL 208 and the upper ESL 212 in Fig. 8 may be collectively referred to as a second ESL stack 2004. The method 100 then continues with block 112, in which the second dielectric layer 230 is formed over the second ESL stack 2004 (shown in Fig. 9). In block 114, the first conductive structure element 240 is formed through the second dielectric layer 230 and the second ESL stack 2004 to contact the first contact structure element 204. Because the lower ESL 208 is deposited on the nitrogen-rich top surface 206, a bottom surface of the lower ESL 208 has a greater nitrogen content than a top surface of the lower ESL 208.

[0021] Now we turn to the Fig. 11-13. In some embodiments, the operations in block 110 are omitted and the middle ESL 210 is deposited on the lower ESL 208. After deposition of the middle ESL 210 on the lower ESL 208 in block 108, the method 100 in Fig. 11, block 110 is skipped and the method 100 continues with block 112. The lower ESL 208 and the middle ESL 210 in Fig. 12 or Fig. 13 may be collectively referred to as a third ESL stack 2006. In block 112, the second dielectric layer 230 is deposited directly on the third ESL stack 2006 (shown in Fig. 12). In block 114, the first conductive structure element 240 is formed through the second dielectric layer 230 and the third ESL stack 2006 to contact the first contact structure element 204. Because the lower ESL 208 is deposited on the nitrogen-rich top surface 206, a bottom surface of the lower ESL 208 has a greater nitrogen content than a top surface of the lower ESL 208.

[0022] Now we turn to the Fig. 14-16. In some embodiments, in block 106, a carbide ESL 214 is deposited in place of the lower ESL 208. In some embodiments, the carbide ESL 214 comprises nitrogen-doped silicon carbide (SiC:N or N-SiC). The carbide ESL 214 may be deposited using CVD or PECVD using tetramethylsilane (Si(CH3)4), silane (SiH4), trimethylsilane (Si(CH3)3H), ammonia (NH3), xenon (Xe), nitrogen (N2), and the like. It should be noted that the carbide ESL 214, when fabricated, is deliberately and intentionally deposited with a nitrogen atomic percentage between about 20% and about 30%. In some cases, a thickness of the carbide ESL 214 may be between about 50 Å and about 100 Å. Since the carbide ESL 214 is deposited on the nitrogen-rich top surface 206, a bottom surface of the carbide ESL 214 has a greater nitrogen content than a top surface of the carbide ESL 214.In block 108, a middle ESL 210 is deposited directly on the carbide ESL 214. The operations in block 110 are omitted, and the upper ESL 212 is not deposited. The carbide ESL 214 and the middle ESL 210 in . Fig. 12 may be collectively referred to as a fourth ESL stack 2008. In these embodiments, the middle ESL 210 does not serve to improve adhesion between the lower ESL 208 and the upper ESL 212. Instead, the middle ESL 210 serves to provide etch selectivity. For these reasons, the middle ESL 210, when deposited over the carbide ESL 214, may have a thickness similar to the thickness of the carbide ESL 214. The method 100 then proceeds to block 112, in which the second dielectric layer 230 is formed over the fourth ESL stack 2008 (shown in Fig. 14). In block 114, a second conductive feature 250 is formed through the second dielectric layer 230 and the fourth ESL stack 2008 to contact the first contact feature 204. Like the first conductive feature 240, the second conductive feature includes the barrier layer 242 and the metal fill layer 244. However, the second conductive feature 250 may have a different sidewall profile than the first conductive feature 240. Because the carbide ESL 214 and the middle ESL 210 are etched faster than the bottom ESL 208 or the top ESL 212 and no interconnects or polymers are created during their etching, the sidewall profile of the via portion of the second conductive feature 250 tapers substantially uniformly downward.

[0023] In contrast to the method 100, which is more suitable for the copper-containing first contact structure element 204, the method 400 is in Fig. 17 is more suitable for contact structure elements made of refractory metals. The method 400 is described with reference to Fig. 18-25, which include fragmentary sectional views of the workpiece 200 at various stages of the process 400.

[0024] In the Fig. 17 and Fig. 18, the method 400 includes a block 402 in which a workpiece 200 having a second contact structure element 205 disposed in a first dielectric layer 202 is received. The second contact structure element 205 is made of a refractory metal, such as tungsten (W) and ruthenium (Ru). In one embodiment, the second contact structure element 205 comprises tungsten (W). The second contact structure element 205 may be a metal line, a contact via, or a source / drain contact. The first dielectric layer 202 has been described above, and for brevity, its detailed description will not be repeated here. Although not explicitly shown in the figures, the second contact structure element 205 may be spaced from the first dielectric layer 202 by a barrier layer.The barrier layer may comprise titanium nitride (TiN), cobalt nitride (CoN), manganese nitride (MnN), nickel nitride (NiN), tungsten nitride (WN), or tantalum nitride (TaN). Since the second contact structure element 205 is subject to less electromigration, the barrier layer may be omitted. As shown in . Fig. 18, top surfaces of the second contact structure element 205 and the first dielectric layer 202 may be coplanar as a result of a planarization process.

[0025] In the Fig. 17 and Fig. 19, the method 400 includes a block 404 in which a first ESL 218 is deposited over the workpiece 200. The first ESL 218 comprises a metal oxide. In one embodiment, the first ESL 218 may comprise alumina (AlO), hafnium silicate (HfSiO4), or hafnium alumina (HfAlO). In one embodiment, the first ESL 218 comprises alumina. The first ESL 218 may be deposited using CVD, ALD, PECVD, or plasma-enhanced ALD (PEALD) using trimethylaluminum (TMA, Al(CH3)3), aluminum trichloride, nitric oxide (N2O), or oxygen (O2). In some embodiments, the oxygen content in the first ESL 218 may be varied across its depth by varying a flow rate of the oxygen-containing precursor, such as nitric oxide (N2O) and oxygen (O2).For example, to improve adhesion to a silicon oxide-containing dielectric layer, such as the first dielectric layer 202 or the second dielectric layer 230, the oxygen content of the contacting surface of the first ESL 218 may be increased. In some cases, the first ESL 218 may have a thickness between about 5 Å and about 20 Å.

[0026] In the Fig. 17 and Fig. 20, the method 400 includes an optional block 406 in which a second ESL 220 is deposited over the workpiece 200. The operations in block 406 are optional and may be omitted entirely. The second ESL 220 may comprise a metal nitride. In some embodiments, the second ESL 220 comprises aluminum nitride (AlN). When the second ESL 220 comprises aluminum nitride (AlN), the second ESL 220 may be deposited using atomic layer deposition (ALD), which includes multiple thermal ALD cycles at a temperature between about 300°C and about 400°C. In the deposition of the second ESL 220, an aluminum-containing precursor, such as trimethylaluminum (TMA, Al(CH3)3), and a nitrogen-containing precursor, such as ammonia (NH3), may be used.In some alternative embodiments, the second ESL 220 may be deposited using chemical vapor deposition (CVD) or plasma-enhanced CVD (PECVD). The second ESL 220 and the first ESL 218 may have the same thickness to facilitate etch endpoint detection. In some embodiments, the second ESL 220 may have a thickness between about 5 Å and about 20 Å. As shown in FIG. Fig. 20, the second ESL 220 is deposited directly on the first ESL 218. The first ESL 218 and the second ESL 220 may be collectively referred to as a fifth ESL stack 2010.

[0027] In the Fig. 17 and Fig. 21, the method 400 includes a block 408 in which a second dielectric layer 230 is deposited over the workpiece 200. In some embodiments, the composition of the second dielectric layer 230 may be similar to the composition of the first dielectric layer 202. In some implementations, the second dielectric layer 230 may be deposited over the second ESL 220 using spin coating, CVD, or flowable chemical vapor deposition (FCVD). To improve the quality and density of the second dielectric layer 230 to withstand later patterning operations, in some cases, an annealing process may be performed to improve the quality of the second dielectric layer 230.After deposition of the second dielectric layer 230, a planarization process, such as a chemical mechanical polishing (CMP) process, may be performed on the second dielectric layer 230 to provide a planar top surface.

[0028] In the Fig. 17 and Fig. 22, the method 400 includes a block 410 in which a first conductive feature 240 is formed through the second dielectric layer 230, the second ESL 220, and the first ESL 218. The operations in block 410 may include forming a dual damascene opening through the second dielectric layer 230, the second ESL 220, and the first ESL 218 to expose the second contact feature 205, and forming the first conductive feature 240 in the dual damascene opening. In an exemplary process, a first patterned mask is first formed by photolithographic processes, and a dry etch process is performed to form a via opening through the second dielectric layer 230 and the fourth ESL stack 2008.A second patterned mask is then formed, and another dry etch process is performed to create a trench opening that overlaps the via opening. The dry etches in block 410 may implement an oxygen-containing gas, hydrogen, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, CH3F, C4H8, C4F6, and / or C2F6), a carbon-containing gas (e.g., CO, CH4, and / or C3H8), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBR3), an iodine-containing gas, other suitable gases and / or plasmas, and / or combinations thereof. In some implementations, the fluorine may form compounds or polymers with the second ESL 220, the first ESL 218, and the second contact structure element 205 in the dry etch process. These compounds or polymers may be redeposited in the dual damascene opening.To remove these compounds and polymers, a wet cleaning process may be performed. In some cases, the wet cleaning process may include ammonium hydroxide (NH4OH) and a tungsten corrosion inhibitor. The tungsten inhibitor may include, for example, benzethonium chloride. After forming the dual damascene opening, block 410 includes depositing a barrier layer 242 in the dual damascene opening, followed by depositing the metal fill layer 244. The composition and deposition of the barrier layer 242 and the metal fill layer 244 have been described above and will not be repeated here.

[0029] As indicated by the dashed lines in Fig. As shown in Figure 22, a via portion of the first conductive feature 240 has a varying sidewall profile. Since the first ESL 218 and the second ESL 220 are etched more slowly and their etching creates compounds and polymers that can be redeposited over the dual damascene opening, the sidewalls extending through the fourth ESL stack 2008 are substantially straight along the z-direction. The same cannot be said for the second dielectric layer 230. First, the second dielectric layer 230 is etched much faster than the first ESL 218 and the second ESL 220. During the dry etch of the second dielectric layer 230, the byproducts are easily removed and are not redeposited. Consequently, the sidewalls extending through the second dielectric layer 230 may taper downwards. As shown in Fig. 22, the sidewall profiles in the via section change from the second dielectric layer 230 to the second contact structure element 205 from a downward taper to a smaller downward taper along the z-direction.

[0030] The method 400 may be applied to fabricate alternative ESL stacks over the second contact structure element 205. First, reference is made to the Fig. 23-25. In some embodiments, in block 404, a gradient ESL 2180 is deposited instead of the first ESL 218. Although also made of a metal oxide, the gradient ESL 2180 has an oxygen concentration gradient. As shown in Fig. 20, the gradient ESL 2180 includes a bottom surface 222 adjacent to the first dielectric layer 202 and the second contact structure element 205, and a top surface 224 facing away from the first dielectric layer 202 and the second contact structure element 205. In the illustrated embodiments, the flow rate of the oxygen-containing precursor is controlled such that an oxygen content at the top surface 224 is greater than an oxygen content at the bottom surface 222. In some embodiments, the gradient ESL 2180 may have a thickness between about 10 Å and about 20 Å. An oxygen content (atomic percentage %) at the bottom 222 of the gradient ESL 2180 may be between about 40% and about 60%, and an oxygen content at the top 224 of the gradient ESL 2180 may be between about 60% and about 75%.This higher oxygen content at the top surface 224 serves to improve adhesion with the second dielectric layer 230. The operations in block 406 are omitted, and the second ESL 220 is not deposited on the gradient ESL 2180. The method 400 then proceeds to block 408, where the second dielectric layer 230 is formed over the first ESL 218 (shown in FIG. Fig. 24). In block 410, the first conductive structure element 240 is formed through the second dielectric layer 230 and the gradient ESL 2180 to contact the second contact structure element 205. As indicated by the dashed lines in Fig. 25, a via portion of the first conductive structure element 240 has a varying sidewall profile.

[0031] The first ESL stack 2002, the second ESL stack 2004, the third ESL stack 2006, the fourth ESL stack 2008, the fifth ESL stack 2010, and the gradient ESL 2180 are suitable for implementation at various locations within a BEOL interconnect structure. Since the fifth ESL stack 2010 and the gradient ESL 2180 contact the contact structure element with an oxygen-containing metal oxide layer, they are better suited for fabrication over contact structure elements made of refractory metals rather than copper (Cu).Since the first ESL stack 2002, the second ESL stack 2004, the third ESL stack 2006, and the fourth ESL stack 2008 contact the underlying contact features with an oxygen-free layer, such as the bottom ESL 208 or the carbide ESL 214, and their manufacturing processes include plasma treatment, they are comparatively better suited to being fabricated over contact features made of copper (Cu). Furthermore, cost-effectiveness in reducing parasitic capacitance also plays an important role in the selection of the ESL. A BEOL interconnect structure may include about 5 to about 20 metallization layers. Each of the metallization layers includes metal features (i.e., vias and metal lines) spaced apart by IMD layers and ESLs. Depending on their distances from the FEOL structures, metallization layers have different thicknesses.In metallization layers closer to the FEOL structures, such as the first 4 to 7 metallization layers that have line pitches greater than 90 nm, the total thickness is thinner, and the ESLs make up a larger percentage of the total thickness. In metallization layers farther from the FEOL structures, such as the last 6 to 15 metallization layers that have line pitches greater than 90 nm, the total thickness increases significantly, and the ESL thicknesses can become negligible. In general, the parasitic capacitance due to an ESL is proportional to a product of a dielectric constant of the ESL and a thickness of the ESL. Metal nitride, such as aluminum nitride, has a dielectric constant between about 13 and about 15. Compared to other ESL materials that have a dielectric constant less than 7 or so, metal nitride seems like an unlikely choice.However, it has been observed that metal nitride, when used as an ESL, requires a much smaller thickness. In some embodiments, a metal nitride ESL thickness may be between about one-fifth (1 / 5) and about one-tenth (1 / 10) of a silicon nitride ESL or a silicon carbide ESL thickness. Due to the smaller thickness, the metal nitride ESL (e.g., the bottom ESL 208) may introduce a smaller capacitance. Since capacitance due to the ESL plays a more significant role in lower metallization layers, the implementation of the first ESL stack 2002 and the second ESL stack 2004 is better suited for the first 4-7 metallization layers.Since the capacitance due to ESL plays a negligible role in higher metallization layers and the deposition of the metal nitride layer is associated with higher costs and a slower process time, the implementation of the third ESL stack in 2006 is better suited for the last 6 to 15 metallization layers.

[0032] Fig. Figure 26 shows the implementation of ESLs in a fin-type field effect transistor (FinFET) 500. The FinFET 500 includes a fin structure 504 extending from a substrate 502. The fin structure 504 extends lengthwise along the x-direction between a source feature 506S and a drain feature 506D. The portion of the fin structure 504 between the source feature 506S and the drain feature 506D defines a channel region. A gate structure 508 encloses the channel region of the fin structure 504. The gate structure 508 extends lengthwise along the y-direction and is defined between two gate spacers 510 along the x-direction. A contact etch stop layer (CESL) 512 is disposed over the source structure element 506S and the drain structure element 506D.An interlayer dielectric (ILD) layer 514 is disposed over the CESL 512. An ESL 516 is disposed over the gate structure 508, the gate spacers 510, and the ILD layer 514. An IMD layer 518 is disposed over the ESL 516. A source contact 522S extends through the IMD layer 518, the ESL 516, the ILD layer 514, and the CESL 512 to connect to the source structure 506S. A gate contact via 520 extends through the IMD layer 518 and the ESL 516 to connect to the gate structure 508. A drain contact 522D extends through the IMD layer 518, the ESL 516, the ILD layer 514, and the CESL 512 to connect to the drain structure 506D. An ESL 530 is disposed over the IMD layer 518, the source contact 522S, the gate contact via 520, and the drain contact 522D.An IMD layer 532 is disposed over the ESL 530. A first contact via 540, a second contact via 542, and a third contact via 544 extend through the IMD layer 532 and the ESL 530 to connect to the gate contact via 520, the source contact 522S, and the drain contact 522D, respectively. An ESL 550 is disposed over the IMD layer 532, the first contact via 540, the second contact via 542, and the third contact via 544. An IMD layer 552 is disposed over the ESL 550. A fourth contact via 560, a fifth contact via 562, and a sixth contact via 564 extend through the IMD layer 552 and the ESL 550 to connect to the first contact via 540, the second contact via 542, and the third contact via 544, respectively.

[0033] In some embodiments, the substrate 502 and the fin structure 504 may comprise silicon (Si). The source feature 506S and the drain feature 506D may be n-type features or p-type features. If they are n-type features, they comprise silicon (Si) and an n-type dopant, such as phosphorus (P) or arsenic (As). If they are p-type features, they comprise silicon germanium (SiGe) and a p-type dopant, such as boron (B). The gate structure 508 includes an interface layer to form an interface with the fin structure 504, a gate dielectric layer over the interface layer, and a gate electrode over the gate dielectric layer. The interface layer may comprise silicon oxide. The gate dielectric layer may comprise a high-k dielectric material, such as hafnium oxide. The gate electrode may comprise titanium nitride, titanium aluminum, titanium aluminum nitride, titanium, tantalum, or tungsten.The gate spacers 510 may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon oxide carbonitride, or silicon oxide carbide. The CESL 512 may comprise silicon nitride or silicon oxynitride. The ILD layer 514, the IMD layer 518, the IMD layer 532, and the IMD layer 552 may comprise a porous organosilicate thin film (e.g., SiOCH), tetraethylorthosilicate oxide (TEOS oxide), undoped silicate glass, borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, porous carbon-doped silicon dioxide, silicon oxide carbonitride (SiOCN), spin-coated silicon-based polymeric dielectrics, or combinations thereof. The source contact 522S and the drain contact 522D may comprise cobalt (Co), nickel (Ni), or titanium nitride (TiN).The gate contact via 520 may comprise cobalt (Co), nickel (Ni), tungsten (W), or ruthenium (Ru). The first contact via 540, the second contact via 542, and the third contact via 544 comprise tungsten (W). The fourth contact via 560, the fifth contact via 562, and the sixth contact via 564 comprise copper (Cu).

[0034] In some embodiments, the ESL 516 and the ESL 530 may be implemented with the first ESL stack 2002, the second ESL stack 2004, or the third ESL stack 2006 because the underlying contact structure element is not made of refractory metal. Furthermore, the first ESL stack 2002, the second ESL stack 2004, or the third ESL stack 2006 provide better etch control because compounds or polymer are created during the etching process to prevent over-etching.In some embodiments, the ESL 550 may be implemented with the fifth ESL stack 2010 or the gradient ESL 2180 because the metal oxide in the fifth ESL stack 2010 or the gradient ESL 2180 adheres well to the first contact via 540, the second contact via 542, and the third contact via 544, which are made of tungsten (W), and is subject to less electromigration when contacted with metal oxide. As described above, the fourth ESL stack 2008 may be better suited for use in metallization layers over the FinFET 500 and having metal line pitches greater than 90 nm.

[0035] Fig.Figure 27 shows an implementation of ESLs on a gate-all-around transistor (GAA transistor) 600. The GAA transistor 600 includes a vertical stack of channel elements 6080 disposed above a substrate 602. The channel elements 6080 may also be referred to as nanostructures. Depending on their cross-sectional shape, they may be referred to as nanosheets or nanowires. The channel elements 6080 extend between a source feature 606S and a drain feature 606D along the x-direction. A gate structure 610 encloses each of the vertical stack of channel elements 6080. The gate structure 610 is laterally spaced from the source feature 606S or the drain feature 606D by a plurality of inner spacer features 612. Above the channel elements 6080, the gate structure 610 is arranged between two upper gate spacers 614.A contact etch stop layer (CESL) 618 is disposed over the source feature 606S and the drain feature 606D. An interlayer dielectric (ILD) layer 620 is disposed over the CESL 618. An ESL 622 is disposed over the gate structure 610, the top gate spacers 614, and the ILD layer 620. An IMD layer 624 is disposed over the ESL 622. A source contact 632S extends through the IMD layer 624, the ESL 622, the ILD layer 620, and the CESL 618 to connect to the source feature 606S. A gate contact via 630 extends through the IMD layer 624 and the ESL 622 to connect to the gate structure 610. A drain contact 632D extends through the IMD layer 624, the ESL 622, the ILD layer 620, and the CESL 618 to connect to the drain structure 606D.An ESL 636 is disposed over the IMD layer 624, the source contact 632S, the gate contact via 630, and the drain contact 632D. An IMD layer 638 is disposed over the ESL 636. A seventh contact via 640, an eighth contact via 642, and a ninth contact via 644 extend through the IMD layer 638 and the ESL 636 to connect to the gate contact via 630, the source contact 632S, and the drain contact 632D, respectively. An ESL 650 is disposed over the IMD layer 638, the seventh contact via 640, the eighth contact via 642, and the ninth contact via 644. An IMD layer 652 is disposed over the ESL 650.A tenth contact via 660, an eleventh contact via 662, and a twelfth contact via 664 extend through the IMD layer 652 and the ESL 650 to connect to the seventh contact via 640, the eighth contact via 642, and the ninth contact via 644, respectively.

[0036] In some embodiments, the substrate 602 and the channel elements 6080 may comprise silicon (Si). The source structure element 606S and the drain structure element 606D may be n-type or p-type structures. If they are n-type structures, they comprise silicon (Si) and an n-type dopant, such as phosphorus (P) or arsenic (As). If they are p-type structures, they comprise silicon germanium (SiGe) and a p-type dopant, such as boron (B). The gate structure 610 includes an interface layer to form an interface with the channel elements 6080, a gate dielectric layer over the interface layer, and a gate electrode over the gate dielectric layer. The interface layer may comprise silicon oxide. The gate dielectric layer may comprise a high-k dielectric material, such as hafnium oxide. The gate electrode may comprise titanium nitride, titanium aluminum, titanium aluminum nitride, titanium, tantalum, or tungsten.The upper gate spacer 614 and the inner gate spacer features 612 may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, or silicon oxycarbide. The CESL 618 may comprise silicon nitride or silicon oxynitride. The ILD layer 620, the IMD layer 624, the IMD layer 638, and the IMD layer 652 may comprise a porous organosilicate thin film (e.g., SiOCH), tetraethylorthosilicate oxide (TEOS oxide), undoped silicate glass, borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), fluorine-doped silicon dioxide, carbon-doped silicon dioxide, porous silicon dioxide, porous carbon-doped silicon dioxide, silicon oxide carbonitride (SiOCN), spin-deposited silicon-based polymeric dielectrics, or combinations thereof. The source contact 632S and the drain contact 632D may comprise cobalt (Co), nickel (Ni), or titanium nitride (TiN).The gate contact via 630 may comprise cobalt (Co), nickel (Ni), tungsten (W), or ruthenium (Ru). The seventh contact via 640, the eighth contact via 642, and the ninth contact via 644 comprise tungsten (W). The tenth contact via 660, the eleventh contact via 662, and the twelfth contact via 664 comprise copper (Cu).

[0037] In some embodiments, the ESL 622 and the ESL 636 may be implemented with the first ESL stack 2002, the second ESL stack 2004, or the third ESL stack 2006 because the underlying contact structure element is not made of refractory metal. Furthermore, the first ESL stack 2002, the second ESL stack 2004, or the third ESL stack 2006 may provide better etch control because compounds or polymer are created during the etching process to prevent over-etching.In some embodiments, the ESL 650 may be implemented with the fifth ESL stack 2010 or the gradient ESL 2180 because the metal oxide in the fifth ESL stack 2010 or the gradient ESL 2180 adheres well to the seventh contact via 640, the eighth contact via 642, and the ninth contact via 644, which are made of tungsten (W), and is subject to less electromigration when contacted with metal oxide. As described above, the fourth ESL stack 2008 may be better suited for use in metallization layers over the GAA transistor 600 and having metal line pitches greater than 90 nm.

[0038] Therefore, one of the embodiments of the present disclosure provides a method. The method comprises the steps of: receiving a workpiece having a conductive feature embedded in a first dielectric layer; treating the workpiece with a nitrogen-containing plasma; after the treatment, depositing a first etch stop layer (ESL) over the workpiece; depositing a second ESL over the first ESL; depositing a second dielectric layer over the second ESL; forming an opening through the second dielectric layer, the second ESL, and the first ESL to expose the conductive feature; and forming a contact via in the opening. The first ESL comprises aluminum nitride or silicon carbonitride, and the second ESL comprises aluminum oxide or silicon oxide carbide.

[0039] In some embodiments, the conductive feature comprises copper (Cu). In some embodiments, the nitrogen-containing plasma comprises ammonia plasma and nitrogen plasma. In some implementations, the method further comprises, prior to depositing the second ESL, depositing a middle ESL over the first ESL. In some cases, a composition of the middle ESL is different from either a composition of the first ESL or a composition of the second ESL. In some embodiments, the middle ESL comprises oxygen-doped silicon carbide. In some embodiments, depositing the middle ESL comprises using tetramethylsilane, silane, trimethylsilane, carbon dioxide, xenon, oxygen, or a combination thereof.In some embodiments, the first ESL has a bottom surface closer to the conductive structure and a top surface remote from the conductive structure; and a nitrogen content at the bottom surface is greater than a nitrogen content at the top surface.

[0040] In another of the embodiments, a contact structure is provided. The contact structure comprises: a conductive feature embedded in a first dielectric layer; a first etch stop layer (ESL) over the conductive feature and the first dielectric layer; a second ESL over the first ESL; a second dielectric layer over the second ESL; and a contact via extending through the second dielectric layer, the second ESL, and the first ESL to connect to the conductive feature. The first ESL comprises aluminum nitride or silicon carbonitride; and the second ESL comprises aluminum oxide or silicon oxide carbide.

[0041] In some embodiments, the conductive feature comprises copper. In some embodiments, the contact structure further comprises a middle ESL disposed between the first ESL and the second ESL. In some implementations, the middle ESL comprises silicon oxide carbide. In some embodiments, the top surfaces of the conductive feature and the first dielectric layer are coplanar. In some cases, the first ESL has a bottom surface closer to the conductive feature and a top surface remote from the conductive feature; and a nitrogen content at the bottom surface is greater than a nitrogen content at the top surface.

[0042] In yet another of the embodiments, a method is provided. The method comprises the steps of: receiving a workpiece having a conductive feature embedded in a first dielectric layer; depositing a first etch stop layer (ESL) over the workpiece such that the first etch stop layer is in direct contact with top surfaces of the conductive feature and the first dielectric layer; depositing a second ESL over the first ESL; depositing a second dielectric layer over the second ESL; forming an opening through the second dielectric layer, the second ESL, and the first ESL to expose the conductive feature; and forming a contact via in the opening. The first ESL comprises metal oxide.

[0043] In some embodiments, the conductive structural element comprises tungsten (W). In some embodiments, the first ESL comprises aluminum oxide. In some implementations, the second ESL comprises metal nitride or metal oxide. In some cases, when the second ESL comprises metal oxide, an oxygen content in the second ESL is greater than an oxygen content in the first ESL. In some embodiments, the second ESL comprises aluminum nitride.

[0044] Features of various embodiments have been described above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use the present disclosure as a basis for designing or modifying other methods and structures for achieving the same objectives and / or obtaining the same benefits as the embodiments presented herein. Those skilled in the art will also appreciate that such equivalent interpretations do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 585,440

[0001]

Claims

[1] Procedure with the following steps: Receiving a workpiece having a conductive structural element embedded in a first dielectric layer; Treating the workpiece with a nitrogen-containing plasma; after treatment, depositing a first etch stop layer over the workpiece; depositing a second etch stop layer over the first etch stop layer; depositing a second dielectric layer over the second etch stop layer; Forming an opening through the second dielectric layer, the second etch stop layer, and the first etch stop layer to expose the conductive structure element; and Creating a contact via in the opening, wherein the first etch stop layer comprises aluminum nitride or silicon carbonitride, wherein the second etch stop layer comprises aluminum oxide or silicon oxide carbide. [2] The method of claim 1, wherein the conductive structural element comprises copper (Cu). [3] The method of claim 1 or 2, wherein the nitrogen-containing plasma comprises ammonia plasma and nitrogen plasma. [4] A method according to any one of the preceding claims, further comprising: before depositing the second etch stop layer, depositing a middle etch stop layer over the first etch stop layer. [5] The method of claim 4, wherein a composition of the middle etch stop layer is different from either a composition of the first etch stop layer or a composition of the second etch stop layer. [6] The method of claim 4 or 5, wherein the middle etch stop layer comprises oxygen-doped silicon carbide. [7] The method of claim 4, 5 or 6, wherein depositing the middle etch stop layer comprises using tetramethylsilane, silane, trimethylsilane, carbon dioxide, xenon, oxygen, or a combination thereof. [8] Method according to one of the preceding claims, wherein the first etch stop layer has a bottom side that is closer to the conductive structure element and a top side that is remote from the conductive structure element where a nitrogen content at the bottom is greater than a nitrogen content at the top. [9] Contact structure with: a conductive structural element embedded in a first dielectric layer; a first etch stop layer over the conductive structure element and the first dielectric layer; a second etch stop layer over the first etch stop layer; a second dielectric layer over the second etch stop layer; and a contact via extending through the second dielectric layer, the second ESL and the first etch stop layer to connect to the conductive structure element, wherein the first etch stop layer comprises aluminum nitride or silicon carbonitride, wherein the second etch stop layer comprises aluminum oxide or silicon oxide carbide. [10] Contact structure according to claim 9, wherein the conductive structural element comprises copper. [11] Contact structure according to claim 9 or 10, further comprising: a middle etch stop layer disposed between the first etch stop layer and the second etch stop layer. [12] The contact structure of claim 11, wherein the middle etch stop layer comprises silicon oxide carbide. [13] Contact structure according to one of claims 9 to 12, wherein top surfaces of the conductive structural element and the first dielectric layer are coplanar. [14] Contact structure according to one of claims 9 to 13, wherein the first etch stop layer has a bottom side that is closer to the conductive structure element and a top side that is remote from the conductive structure element, where a nitrogen content at the bottom is greater than a nitrogen content at the top. [15] Procedure with the following steps: Receiving a workpiece having a conductive structural element embedded in a first dielectric layer; Depositing a first etch stop layer over the workpiece such that the first etch stop layer is in direct contact with top surfaces of the conductive structure element and the first dielectric layer; depositing a second etch stop layer over the first etch stop layer; depositing a second dielectric layer over the second etch stop layer; Forming an opening through the second dielectric layer, the second etch stop layer, and the first etch stop layer to expose the conductive structure element; and Creating a contact via in the opening, wherein the first etch stop layer comprises metal oxide. [16] The method of claim 15, wherein the conductive structural element comprises tungsten (W). [17] The method of claim 15 or 16, wherein the first etch stop layer comprises aluminum oxide. [18] A method according to any one of claims 15 to 17, wherein the second etch stop layer comprises metal nitride or metal oxide. [19] The method of claim 18, wherein when the second etch stop layer comprises metal oxide, an oxygen content in the second etch stop layer is greater than an oxygen content in the first etch stop layer. [20] The method of any one of claims 15 to 19, wherein the second etch stop layer comprises aluminum nitride.

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