ARRANGEMENT OF BOND PADS TO REDUCE INFLUENCE ON PASSIVE STRUCTURAL ELEMENTS

Abstract

A method comprises forming a functional circuit on a semiconductor substrate of a device die, wherein the functional circuit is located in a functional circuit region of the device die; forming a passive component over the semiconductor substrate, wherein the passive component is located in a passive component region of the device die; forming the first of several bond pads in the functional circuit region and on a surface of the device die, wherein the first of several bond pads have a first structure density; and forming the second of several bond pads in the passive component region and on the surface of the device die. The second of several bond pads has a second structure density that is lower than the first structure density.

Description

PRIORITY CLAIM AND CROSS-REFERENCE

[0001] This application claims priority to U.S. Provisional Patent Application No. 63 / 584,561, filed September 22, 2023, and entitled "SEMICONDUCTOR DIE WITH OPTIMIZED ARRANGEMENT OF BOND METALS," which is incorporated by reference into the present application. BACKGROUND

[0002] Semiconductor chips can include active components and passive components, such as transistors, capacitors, inductors, or the like. In a semiconductor chip, the transistors are formed on the surface of a semiconductor substrate of the semiconductor chip. The passive components can be formed above the semiconductor chip. Bond pads can be formed above the passive components and active components and can be used for bonding to another package component, such as a semiconductor chip, an interposer, a package substrate, or the like. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of the present disclosure are best understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration. Fig. 1 illustrates a cross-sectional view of a device die having a passive device and overlying bond pads, in accordance with some embodiments. Fig. 2 illustrates a top view of a device die including a passive device and overlying bond pads, in accordance with some embodiments. Fig. 3 illustrates a top view of a passive device region, a junction region, and a functional circuit region in accordance with some embodiments. Fig. 4 illustrates a top view of a passive device region in accordance with some embodiments. Fig. 5 illustrates a top view of the transition region with graded structure densities in accordance with some embodiments. Fig. 6 illustrates a cross-sectional view of a portion of a device die including a passive device, a transition region, a functional circuit region, and the overlying bond pads, in accordance with some embodiments. Fig. 7 illustrates several distribution structures of bond pads in passive device regions in accordance with some embodiments. Fig. 8 and Fig. 9 illustrate the possible top view shapes of bond pads in passive device regions in accordance with some embodiments. Fig. 10 illustrates several distribution structures of cluster bond pads in passive device regions in accordance with some embodiments. Fig. 11 illustrates several distribution structures of bond pads in transition zones in accordance with some embodiments. Fig. 12 and Fig. 13 illustrate cross-sectional view shapes of redistribution conduits in accordance with some embodiments. Fig. 14 illustrates a cross-sectional view of two bonded device dies in accordance with some embodiments. Fig. 15-26 illustrate cross-sectional views of intermediate stages in the formation of a cap structure of a device die in accordance with some embodiments. Fig. 27-35 illustrate cross-sectional views of some structures incorporating the embodiments, in accordance with some embodiments. Fig. 36 illustrates a process flow for forming a cover structure in accordance with some embodiments. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments, or examples, for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first structural element over or on top of a second structural element in the following description may include embodiments in which the first and second structural elements are formed in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements such that the first and second structural elements may not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition is for the purpose of simplification and clarity and does not in itself imply any relationship between the different embodiments and / or configurations discussed.

[0005] Furthermore, spatially relative terms such as "underlying," "beneath," "under," "overlying," "upper," and the like may be used herein for ease of description to describe the relationship of one element or structural element to another element(s) or structural element(s) as illustrated in the figures. The spatially relative terms are intended to encompass various orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented differently (rotated 90 degrees or at other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0006] A device die comprising passive components and an optimized arrangement of bond pads, and the method for forming the same, are provided. In accordance with some embodiments, a passive component, such as an inductor, is formed in a passive component region. Functional circuits comprising active components are formed in a functional circuit region. A transition region is formed to separate the passive component region from the functional circuit region. Bond pads are formed in the passive component region and transition region (in addition to the functional circuit region) to reduce pattern loading effects. To minimize the adverse effect of the bond pads in the passive component region on the performance of the passive component and the circuits, the pattern density in the passive component region is lower than that in the functional circuit region.The structure density in the transition zone may be further higher than that in the passive device zone and lower than that in the functional circuit zone in order to mitigate the structure density difference between the passive device zone and the functional circuit zone.

[0007] Embodiments discussed herein are intended to provide examples of making or using the subject matter of this disclosure, and one of ordinary skill in the art will readily understand modifications that may be made while maintaining the contemplated scope of various embodiments. Across the various views and illustrative embodiments, similar reference numerals are used to identify similar elements. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0008] Fig. 1 illustrates a cross-sectional view of wafer 20. In accordance with some embodiments, wafer 20 is, or may include, a device wafer including active devices and passive devices, depicted as IC devices 26. Wafer 20 may include a plurality of chips (device dies) 20' therein, one of the device dies 20' being illustrated.

[0009] In accordance with some embodiments, wafer 20 includes semiconductor substrate 24 and the features formed on a top surface of semiconductor substrate 24. Semiconductor substrate 24 may be formed of or include crystalline silicon, crystalline germanium, silicon germanium, carbon-doped silicon, or a III-V compound semiconductor such as GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or the like. Shallow trench isolation (STI) regions (not shown) may be formed in semiconductor substrate 24 to isolate the active regions in semiconductor substrate 24.

[0010] In accordance with some embodiments, wafer 20 includes IC devices 26 formed on the top surface of semiconductor substrate 24. IC devices 26 may include complementary metal-oxide semiconductor (CMOS) transistors, resistors, capacitors, diodes, and the like, in accordance with some embodiments. The details of IC devices 26 are not illustrated herein.

[0011] Interconnect structure 32 is formed over IC devices 26 and includes ILD 28 and contact plugs 30. Inter-layer dielectric (ILD) 28 fills the spaces between the gate stacks of transistors (not shown) in IC devices 26. In accordance with some embodiments, ILD 28 is formed from silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), fluorine-doped silicate glass (FSG), or the like. ILD 28 may be formed using spin-on coating.In accordance with alternative embodiments, ILD 28 may also be formed using a deposition process such as flowable chemical vapor deposition (FCVD), plasma enhanced chemical vapor deposition (PECVD), low pressure chemical vapor deposition (LPCVD), or the like.

[0012] Contact plugs 30 are formed in ILD 28 and are used to electrically connect IC components 26 to overlying metal lines and vias. In accordance with some embodiments, contact plugs 30 are formed from or include a conductive material selected from tungsten, aluminum, copper, titanium, tantalum, titanium nitride, tantalum nitride, alloys thereof, and / or multilayers thereof. Formation of contact plugs 30 may include forming contact openings in ILD 28, filling the contact openings with conductive material(s), and performing a planarization process (such as a chemical mechanical polish (CMP) process or a mechanical grinding process) to level the top surfaces of contact plugs 30 with the top surface of ILD 28.

[0013] Interconnect structure 32 further includes metal lines 34 and vias 36 formed within dielectric layers 38 (also referred to as inter-metal dielectrics (IMDs)) and etch stop layers 37. The metal lines on a same level are collectively referred to herein as a metal layer. In accordance with some embodiments, interconnect structure 32 includes multiple metal layers including metal lines 34 interconnected by vias 36. Metal lines 34 and vias 36 may be formed from copper or copper alloys and may also be formed from other metals, such as tungsten, nickel, or the like.

[0014] In accordance with some embodiments, dielectric layers 38 are formed from low-k dielectric materials. The dielectric constants (k values) of the low-k dielectric materials may be, for example, lower than about 3.5 or 3.0. Dielectric layers 38 may include a carbonaceous low-k dielectric material, hydrogen silsesquioxane (HSQ), methyl silsesquioxane (MSQ), or the like. Etch stop layers 37 are formed underlying the respective dielectric layers 38 and may be formed from or include aluminum nitride, aluminum oxide, silicon oxycarbide, silicon nitride, silicon carbide, silicon oxynitride, or the like, or multiple layers thereof.

[0015] The formation of metal lines 34 and vias 36 in dielectric layers 38 may include single damascene processes and / or dual damascene processes. In a single damascene process for forming a metal line or via, a trench or via opening is first formed in one of the dielectric layers 38, followed by filling the trench or via opening with a conductive material. A planarization process, such as a CMP process, is then performed to remove the excess portions of the conductive material that are higher than the top surface of the dielectric layer, leaving a metal line or via in the corresponding trench or via opening.In a double damascene process, both a trench and a via opening are formed in a dielectric layer, with the via opening underlying and connected to the trench. Conductive materials are then filled into the trench and the via opening to form a metal line and a via, respectively. The conductive materials may include a diffusion barrier layer and a copper-containing metallic material over the diffusion barrier layer. The diffusion barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like.

[0016] Metal lines 34 include conductive capping (metal) features (referred to as 34T), such as metal lines, metal pads, or vias, in a capping dielectric layer (referred to as dielectric layer 38T), which is the top layer of dielectric layers 38. In accordance with some embodiments, dielectric layer 38T is formed from a low-k dielectric material similar to the material of lower dielectric layers 38. The metal features 34T in the capping dielectric layer 38T may also be formed from copper or a copper alloy and may include a double damascene structure or a single damascene structure.

[0017] Passivation layer 42 (sometimes referred to as Passivation-1 or Pass-1) is formed over interconnect structure 32. In accordance with some embodiments, passivation layer 42 is formed from a non-low-k dielectric material having a dielectric constant equal to or greater than the dielectric constant of silicon oxide. Passivation layer 42 may be formed from or include an inorganic dielectric material, which may include a material selected from, but not limited to, undoped silicate glass (USG), silicon nitride (SiN), silicon oxide (SiO2), silicon oxynitride (SiON), silicon oxycarbide (SiOC), or the like, combinations thereof, and / or multilayers thereof. In accordance with some embodiments, the top surfaces of dielectric cap layer 38T and metal lines / pads 34T are planar with each other. Accordingly, passivation layer 42 may be a planar layer.

[0018] In accordance with some embodiments, vias 44 are formed in passivation layer 42 to electrically connect to the underlying cap metal features 34T. Redistribution lines (RDLs) 46, which may include metal lines and metal pads, are further formed over vias 44. In accordance with some embodiments, RDLs 46 include aluminum, aluminum-copper, or the like. Passivation layer 48 (sometimes referred to as passivation-2 or pass-2) is also formed and may extend on the sidewalls and cap surfaces of RDLs 46. Passivation layer 48 may be formed of, or include, silicon oxide, silicon nitride, or the like, or multiple layers thereof.

[0019] In accordance with some embodiments, dielectric layer 50 is formed. Dielectric layer 50 may be planarized and is referred to as a planarization layer. In accordance with some embodiments, dielectric layer 50 may be formed by dispensing a polymer in a flowable form and then curing polymer layer 50. Dielectric layer 50 may also be formed by deposition. Dielectric layer 50 is patterned to expose RDLs 46. Dielectric layer 50, when formed from polymer, may be formed from or include polyimide, polybenzoxazole (PBO), or the like. Alternatively, dielectric layer 50 may be formed from or include an inorganic dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0020] Dielectric layer 56 is formed over dielectric layer 50. Bond pads 54 and bond vias 52 are formed in dielectric layer 56 to electrically connect to the underlying RDLs 46. The detailed structures, materials, and formation processes of bond vias 52, bond pads 54, and dielectric layer 56 are discussed with reference to the processes described in Fig. 15 to 26 are shown.

[0021] In accordance with some embodiments, device die 20' includes functional circuitry region 58F having functional circuitry 26 therein. Functional circuitry 26 may include active devices, such as transistors, therein. Bond pads 54F, which are portions of bond pads 54, are formed on the surface of device die 20' and in functional circuitry region 58F. At least some of bond pads 54F are electrically connected to IC devices 26. There may or may not be dummy bond pads (also referred to as 54F) in functional circuitry region 58F. The dummy bond pads have no electrical functions and may be electrically floating (when device die 20' is powered on). In accordance with some embodiments, all bond pads 54F overlap functional circuitry 26 in functional circuitry region 58F.

[0022] Component die 20' further includes passive component region 58P having passive component 62 therein. Bond pads 54P, which are part of bond pads 54, are formed on the surface of component die 20' and passive component region 58P. Passive component 62 may or may not include an inductor, a capacitor, or the like. Fig. 1, passive component 62 is schematically illustrated. In accordance with some embodiments, passive component 62 includes multiple portions of RDLs 46, vias 44, and underlying metal lines 34T interconnected to form coils (spirals) when passive component 62 includes an inductor. In accordance with other embodiments, passive component 62 may be formed in RDLs 46 and may not include portions of the underlying cap metal layer. In accordance with still other embodiments, the entire passive component 62 may be formed in lower metal layers including and possibly underlying the cap metal layer.

[0023] In accordance with some embodiments, there are IC components 26, metal lines 34, and / or vias 36 formed beneath passive component 62 in passive component region 58P, where IC components 26 may be electrically connected to overlying bond pads 54P. In accordance with some embodiments, all bond pads 54P overlap the functional circuits 26 in passive component region 58P. In accordance with alternative embodiments, no IC components 26, metal lines 34, and / or vias 36 are formed beneath passive component 62. Accordingly, IC components 26, metal lines 34, and / or vias 36 are illustrated in dashed lines in passive component region 58P to indicate that these features may or may not be formed.

[0024] In accordance with some embodiments, depending on the number of passive components 62, the number of terminals of the passive component(s) 62, the number of bond pads 54F, and the connection scheme of passive components 62 to the IC components 26, there may or may not be dummy bond pads (also referred to as 54P) in passive component region 58P. In accordance with some embodiments, all bond pads 54P are connected to the passive component(s) 62 and / or the underlying IC components 26. In accordance with alternative embodiments, all bond pads 54P are dummy bond pads. In accordance with still alternative embodiments, some bond pads 54P are connected to the passive component(s) 62 and / or the underlying IC components 26, while other bond pads 54P are dummy bond pads.

[0025] Transition zone 58T is located between functional circuit zone 58F and passive component zone 58P. In accordance with some embodiments, transition zone 58T includes bond pads 54T (which are also parts of bond pads 54T). Bond pads 54T may be dummy bond pads. In accordance with some embodiments, some or all of bond pads 54T do not include underlying vias 52. In accordance with some embodiments, no IC components 26, metal lines 34, and / or vias 36 are formed in transition zone 58T and beneath bond pads 54T.

[0026] In accordance with alternative embodiments, some IC components 26, metal lines 34, and / or vias 36 may also be formed in transition zone 58T and beneath bond pads 54T. In accordance with still alternative embodiments, there may be some dummy metal lines 34 and / or vias 36 (not shown) in transition zone 58T and beneath bond pads 54T, wherein the dummy metal lines 34 and / or vias 36 are used to reduce the structural charge effect during the formation of metal lines 34 and / or vias 36. These dummy metal lines 34 and / or vias 36 may be electrically floating and may be electrically connected to or electrically disconnected from bond pads 54T.

[0027] Fig. 2 illustrates a top view of a portion of device die 20' in accordance with some embodiments. Passive device region 58P may be enclosed by transition zone 58T. Transition zone 58T separates passive device region 58T from functional circuit region 58F, which may further enclose transition zone 58T. Fig. 1 shown cross-sectional view may be different from the cross section 1-1 in Fig. 2 can be obtained.

[0028] In each of the zones 58F, 58T, and 58P, the respective bond pads 54 have a structure density calculated as the ratio of the total area of ​​bond pads 54 in the respective zone to the total chip area of ​​the zone. Accordingly, the bond pads 54F in functional circuit zone 58F have a structure density PD. 54F the bond pads 54T in transition zone 58T have structure density PD 54T and the bond pads 54P in passive component zone 58P have structure density PD 54PFurthermore, since the pattern density of bond pads 54 exhibits a greater variation when calculated for smaller chip areas, the pattern density of bond pads 54 is defined to be calculated in a minimum chip area, where both length and width are equal to or greater than 50 µm. In accordance with some embodiments, the pattern density of PD 54P based on the total area of ​​the passive component zone 58P and the structure density of PD 54T can be calculated based on the total area of ​​the transition zone 58T. The structural density of PD 14F can be calculated based on an annular chip area with a width W3 greater than 1.5 µm or the total area of ​​the functional circuit region 58F.

[0029] The bond pads 54P directly above passive component 62 ( Fig. 1) can adversely affect the performance of the passive component 62 and the circuit connected to the passive component 62. To reduce the adverse influence, the structure density PD 54P of passive component zone 58P small and is smaller than structure density PD 54F of functional circuit zone 58F. The structure density PD 54P so that it is smaller than structural density PD 54F However, it degrades the structural charge effect, for example in the planarization process (with respect to Fig. 26) to form bond pads 54.

[0030] To solve this problem, the structural density PD 54T in transition zone 58P designed to be smaller than structural density PD 54F and greater than the structural density PD 54PThis may mitigate the structural charge effect and may reduce the likelihood of non-bonding problems. In accordance with some embodiments, the structural density PD 54P in the passive component zone 58P in the range between approximately 0 percent (if there is no bond pad in the passive component zone 58P) and approximately 6 percent. The structure density PD 54T in the transition zone 58T can range between about 0.5 percent and about 2 percent. The structural density PD 54F in the functional circuit zone 58F can range between about 5 percent and about 25 percent. The ratio PD 54P / PD 54T can range between about 0 and about 0.3 and the ratio PD 54T / PD 54F can range between about 0.3 and about 1. The ratio PD 54P / PD 54F may be less than about 0.3 and may range from about 0 to about 0.3.

[0031] In accordance with some embodiments, the length L1 and width W1 of passive component region 58P may range between about 3 µm and about 3,000 µm. The width W2 of an annular transition region 58T may range between about 2 µm and about 40 µm. The width W3 of an annular functional circuit region 58F may range between about 3 µm and about 3,000 µm.

[0032] Fig. 3 illustrates an exemplary top view of passive device region 58P, transition region 58T, and functional circuit region 58F and the corresponding bond pads 54P, 54T, and 54F in accordance with some embodiments. An exemplary inductor 62 is also illustrated. As shown in Fig. 3, the pitch S1 of bond pads 54P may be equal to or greater than the pitch S2 of bond pads 54T and / or the pitch S2 of bond pads 54T may be equal to or greater than the pitch S3 of bond pads 54F. The diameter D1 of bond pads 54P may also be equal to or less than the diameter D2 of bond pads 54T and / or the diameter D2 of bond pads 54T may be equal to or less than the diameter D3 of bond pads 54F. Accordingly, the difference in feature densities may be achieved by different spacings (spacings, pitches) and / or different lateral dimensions (diameters or lengths and widths) of the bond pads 54P, 54T, and 54F. In accordance with some embodiments, diameters D1, D2, and D2 may range from about 0.5 μm to about 20 μm.

[0033] In accordance with some embodiments, the bond pads 54T in transition zone 58T may include multiple columns of bond pads, for example, greater than about 5 or 10 columns of bond pads. Accordingly, as shown in Fig. 2 and Fig. 3, the bond pads 54T may be aligned with multiple rings, with the outer rings enclosing the respective inner rings. Aligning the bond pads 54T with a single ring may be referred to as a bond pad ring. Bond pads 85P in functional circuit zone 58P may also have multiple (e.g., more than 5 or 10) bond pad rings.

[0034] Fig. 4 illustrates an exemplary top view of passive component region 58P in accordance with some embodiments. Passive component region 58P may, in accordance with these embodiments, include a larger number of bond pads 54P than the embodiments in Fig. 3. In addition, some bond pads 54P may overlap the passive component 62 and / or the underlying IC 26 (if present), while in the embodiments in Fig. 3 the bond pads 54P may form a rectangular structure enclosing passive component 62, wherein the bond pads 54P are located at locations close to, but not overlapping, passive component 62 and / or the underlying IC components 26.

[0035] In accordance with some embodiments, all of the bond pads 54P overlap passive component 62 and / or the underlying IC components 26. In accordance with alternative embodiments, bond pads 54P may include the bond pads that may overlap passive component 62 and / or the underlying IC components 26, and may or may not include a ring of bond pads that do not overlap and enclose the passive component 62 and / or the underlying IC components 26 in plan view.

[0036] In accordance with some embodiments, the bond pads 54T in transition zone 54T are uniformly distributed with a uniform pitch and therefore a uniform feature density. In accordance with alternative embodiments, the bond pads 54T in transition zone 54T have a graded (increasing or decreasing) pitch and therefore a graded (increasing or decreasing) feature density. For example, Fig. 3 dashed lines mark multiple subzones 58T1, 58T2, and 58T3 (or more) of transition zone 58T. The dashed lines indicate that the structural density of bond pads 54T may be uniform or graded (increasing or decreasing). In accordance with some embodiments, the number of subzones may range from 2 to 20.

[0037] In accordance with some embodiments, the bond pads 54T in each of the subzones (such as 58T1, 58T2, and 58T3) have a uniform feature density and pitch. However, the feature densities and pitches of adjacent subzones are different from each other. To minimize the feature loading effect, the bond pads 54T in the subzones closer to the passive device zone 58P have lower feature densities (and larger pitches and / or smaller lateral dimensions) than the bond pads 54T in the respective subzones closer to the functional circuit zone 54F. In other words, in the transition zone 58T, in the direction pointing from the passive device zone 54P to the functional circuit zone 54F, the feature densities may increase gradually, which means that the diameters (lateral dimensions) of bond pads 54P may increase gradually and / or the pitches may decrease gradually. For example, Fig. 5 three subzones 58T1, 58T2 and 58T3 with distances S1A, S1B and S1C respectively, where distance S1B is smaller than distance S1A and distance S1C is smaller than distance S1B.

[0038] In accordance with some exemplary embodiments where there are three subzones, the feature densities in subzones 58T1, 58T2, and 58T3 may be about 1%~3%, about 8%~15%, and about 18%~22%, respectively. In accordance with alternative embodiments where there are five subzones, the feature densities in subzones 58T1, 58T2, 58T3, 58T4 (not shown), and 58T5 (not shown) may be about 1%~3%, about 5%~8%, about 9%~13%, about 14%~16%, and about 18%~22%, respectively. Fig. Figure 6 illustrates the cover structural elements in three device zones 58P, 58T, and 58F, in accordance with some embodiments. Some structural elements, such as the details of dielectric layers, are not illustrated. RDLs 46 forming the passive device 62 in passive device zone 58P and the metal pads in functional circuit zone 58F may have rounded top surfaces resulting from the plating of copper, in accordance with some embodiments. Fig. 7 illustrates some possible arrangements of bond pads 54P in passive device region 58P in accordance with some embodiments. For example, bond pads 54P may be on, or form the nodes of, a square array, a rectangular array, a diamond-shaped array, a pentagonal array, a hexagonal array, or the like, or any other regular or irregular structure. The top view shapes of bond pads 54 (54P, 54T, and / or 54F) may have any shape, including, but not limited to, circles ( Fig. 3), squares ( Fig. 8), rectangles ( Fig. 9), ovals, hexagons, octagons or the like. Fig. 10 illustrates some possible arrangements of the bond pads 54P in the passive component region 58P in accordance with some embodiments. The bond pads 54P may be arranged as multiple clusters, and the clusters may be further arranged as regular or irregular structures. The structures of the multiple clusters may be the same or different. As shown in Fig. 10, the clusters of bond pads 54P may be on, or form, the nodes of a square array, a rectangular array, a hexagonal array, a diamond-shaped array, or the like, or any other regular or irregular structure.

[0039] Fig. 11 illustrates some possible arrangements of bond pads 54T in junction device region 58T in accordance with some embodiments. For example, bond pads 54T may be on or form the nodes of a square array, a rectangular array, a diamond-shaped array, a pentagonal array, a hexagonal array, or the like, or any other regular or irregular structure.

[0040] Fig. 12 and Fig. 13 illustrate the cross-sectional shapes of RDLs 46 that form the passive component 62 in passive component zone 58P and the metal pads in the functional circuit zone 58F. In Fig. 12, RDLs have 46 planar upper surfaces. This can be achieved by plating aluminum or aluminum-copper. In Fig. 13, RDLs 46 have planar top surfaces. This can be achieved by plating copper in accordance with some embodiments.

[0041] Fig. 14 illustrates the bonding of two device dies 20' (comprising 20'-1 and 20'-2) to each other in accordance with some embodiments. Device die 20'-1 has bond pads corresponding to the bond pads of device die 20'-2. For example, after bonding, passive device region 58P, transition region 58T, and functional circuit region 58F of device die 20'-1 overlap passive device region 58P, transition region 58T, and functional circuit region 58F of device die 20'-2, respectively. Furthermore, the positions and sizes of bond pads 54P, 43T, and 54F of device die 20'-1 may be the same as those of bond pads 54P, 43T, and 54F of device die 20'-2. In accordance with some embodiments, passive component 62 in device die 20'-1 is connected to passive component 62 in device 20'-2 in parallel or in series.

[0042] Fig. 15 to 26 illustrate some exemplary processes for forming the upper structure, the passive component 62 ( Fig. 1), in accordance with some embodiments. The corresponding processes are also schematically depicted in the process flow 200 as shown in Fig. 36. The lower structures in Fig. 1 are not illustrated, while the lower structures lying beneath the illustrated section are still present. Some of the Fig. 15-26 shown structural elements were related to Fig. 1. The discussion of the processes in Fig. 15-26 can be discussed in relation to Fig. 1. It is appreciated that these processes are examples and that other applicable processes, structures, and materials can be used.

[0043] In relation to Fig. 15, cap metal structure element 34T is formed in dielectric cap layer 38T. Passivation layer 42 is then deposited over cap metal structure element 34T. The respective process is illustrated as process 202 in the process flow 200 as shown in Fig. 36. The passivation layer may contain silicon oxide or other materials, as described in relation to Fig. 1 is discussed. Fig. 16 illustrates the formation of opening 43 in passivation layer 42 by an etching process, wherein cap metal feature 34T is exposed. The respective process is illustrated as process 204 in the process flow 200 as shown in Fig. 36 is shown.

[0044] Next, as in Fig. 17, metal seed layer (which is also a barrier) 45A is deposited, which may include a titanium layer and a copper layer over the titanium layer. The respective process is illustrated as process 206 in the process flow 200 as shown in Fig. 36. A patterned photoresist 47 is then formed. The respective process is illustrated as process 208 in the process flow 200 as shown in Fig. 36. Regarding Fig. 18, a plating process is performed to deposit a metallic material 45B such as copper. The respective process is illustrated as process 210 in the process flow 200 as shown in Fig. 36. The resulting upper surface of the metallic material 45B may be rounded, as shown in Fig. 13. Alternatively, the metallic material 45B may include aluminum, which may have the planar upper surface as shown in Fig. 12 is shown.

[0045] In a subsequent process, photoresist 47 is removed to expose the underlying portions of metal seed layer 45A. The exposed metal seed layer 45A is then removed by etching. The respective process is illustrated as process 212 in the process flow 200 as shown in Fig. 36. The remaining portions of the metal seed layer 45A and the metallic material 45B together form via 44 and RDL 46, which are shown in Fig. 19 and also in Fig. 1. RDL 46 can be used to form passivation device 62 and the RDLs and metal pads in functional circuit region 58F.

[0046] Next, as in Fig. 20, passivation layer 38 is deposited, for example, using a material containing silicon nitride, silicon oxide, or the like. The respective process is illustrated as process 214 in process flow 200 as shown in Fig. 36. Passivation layer 48 may be formed as a conformal layer, for example, by a conformal deposition process such as ALD, CVD, or the like.

[0047] In relation to Fig. 21, dielectric layer 50A, also referred to as a planarization layer, is deposited. Dielectric layer 50A may be a polymer layer formed from polyimide, PBO, or the like. The respective process is illustrated as process 216 in the process flow 200 as shown in Fig. 36 is shown. In Fig. 22, several dielectric layers are deposited. The respective process is illustrated as process 218 in the process flow 200 as shown in Fig. 36. The plurality of dielectric layers may include dielectric layers 50B, 50C, 56A, and 56B. In accordance with some embodiments, dielectric layers 50B, 50C, 56A, and 56B, respectively, may include silicon nitride, silicon oxide, silicon nitride, or silicon oxide, while other materials may be used. Dielectric layers 50A, 50B, and 50C are collectively referred to as dielectric layer 50. Dielectric layers 56A and 56B are collectively referred to as dielectric layer 56, which, in accordance with some embodiments, is also referred to as a bond film.

[0048] In relation to Fig. 23, a patterned photoresist 57 is formed. Dielectric layers 56B and 56A are etched using the patterned photoresist 57 as an etch mask, so that trench 59 is formed. The respective process is illustrated as process 220 in the process flow 200 as shown in Fig. 36. The etching of dielectric layer 56B may be performed using dielectric layer 56A as an etch stop layer, which is then etched through. The patterned photoresist 57 is then removed.

[0049] Fig. 24 and Fig. 25 illustrate the formation of via opening 63 in accordance with some embodiments. With respect to Fig. 24, a patterned photoresist 61 is formed. Dielectric layers 50C, 50B, and 50A and passivation layer 48 are etched using patterned photoresist 61 as an etch mask, so that via opening 63 is formed. The respective process is illustrated as process 222 in process flow 200 as shown in Fig. 36. The resulting structure is shown in Fig. 25. The patterned photoresist 61 is then removed.

[0050] In a subsequent process, as in Fig. 26, via 52 and bond pad 54 are formed. The bond pad 54 represents the bond pads 54P, 54T and 54F as shown in Fig. 1. The respective process is illustrated as process 224 in the process flow 200 as shown in Fig. 36. The formation process may include depositing barrier 53A and metallic material 53B, followed by a planarization process to remove the excess portions of the deposition barrier 53A and metallic material 53B.

[0051] Fig. Figures 27 to 35 illustrate some packages in which the 20' component die can be used. Fig. Figure 27 illustrates a structure in which two system-on-chip (SOC) packages are bonded to an underlying SoC package by chip-to-wafer bonding. One or more of the three packages may comprise the component die 20' as shown in Fig. 1 shown, in any combination.

[0052] Fig. Figure 28 illustrates two chips, Chip1 and Chip2, bonded by wafer-to-wafer bonding. Therefore, after sawing, the edges of the chips Chip1 and Chip2 are vertically aligned. One or both of the chips Chip1 and Chip2 can adopt the structure from the device die 20' in any combination.

[0053] Fig. Figure 29 illustrates a high-bandwidth memory (HBM) and another package bonded to an interposer. The package includes SoC package SoC-1 bonded to two SoC packages SoC-2 and SoC-3. The interposer is further bonded to a package substrate. One, several, or all of SoC packages SoC-1, SoC-2, and SoC-3 can adopt the structure of component die 20 in any combination.

[0054] Fig. 30 illustrates a package having a deck package bonded to a bottom package. The deck package may have dynamic random-access memory (DRAM) dies bonded to a package substrate. The bottom package may be an integrated fanout (InFO) package having another package therein, the other package having SoC packages SoC-1, SoC-2, and SoC-3. One or more or all of the SoC packages SoC-1, SoC-2, and SoC-3 may adopt the structure of device die 20' in any combination.

[0055] Fig. Figure 31 illustrates a package comprising two chips, ChipA and ChipB, bonded to a package substrate. One or both of ChipA and ChipB can adopt the structure of component die 20' in any combination.

[0056] Fig. Figure 32 illustrates a package comprising an SoC package and two HBMs bonded to an InFO package, which further rests on a package substrate. The InFO package may include passive component dies and bridge dies. The SoC package may adopt the structure of component die 20'.

[0057] Fig. Figure 33 illustrates a package including a DRAM package bonded to an InFO package. The InFO package may include a logic component die. The logic component die may adopt the structure of component die 20'.

[0058] Fig. 34 illustrates a package including an InFO package having a top package bonded to a bottom package. The bottom package including the InFO structure includes an SoC package, which may include the structure of device die 20'.

[0059] Fig. Figure 35 illustrates a package that includes an InFO package that includes a deck package bonded to a floor package. This structure is similar to that shown in Fig. 29, except that in the Fig. 35, there is a single SoC package (instead of three SoC packages) that may have the structure of device die 20'.

[0060] The embodiments of the present disclosure include several advantageous structural elements. By reducing the structural density of the bond pads in the passive component region, the adverse impact of the bond pads on the circuit is reduced. However, the difference in structural densities can result in a structural charge effect. By having the bond pads in the transition zone with a structural density between the structural densities of the bond pads in the passive component region and the functional circuit region, the structural charge effect can be reduced.

[0061] In accordance with some embodiments, a method comprises forming a functional circuit on a semiconductor substrate of a device die, wherein the functional circuit is in a functional circuit region of the device die; forming a passive device over the semiconductor substrate, wherein the passive device is in a passive device region of the device die; forming a first plurality of bond pads in the functional circuit region and at a surface of the device die, wherein the first plurality of bond pads have a first feature density; and forming a second plurality of bond pads in the passive device region and at the surface of the device die, wherein the second plurality of bond pads have a second feature density that is lower than the first feature density.

[0062] In one embodiment, the method further comprises forming a third plurality of bond pads in a transition zone and at the surface of the device die, wherein the transition zone is between the passive device zone and the functional circuit zone, and wherein the third plurality of bond pads have a third feature density that is lower than the first feature density. In one embodiment, the third plurality of bond pads are greater than the second feature density. In one embodiment, the third plurality of bond pads are dummy pads. In one embodiment, the transition zone has a ring shape enclosing the passive device zone. In one embodiment, the third feature density is graded (increasing or decreasing), wherein feature densities in portions of the transition zone closer to the passive device zone are lower than densities in portions of the transition zone closer to the functional circuit zone.

[0063] In one embodiment, forming the passive component comprises forming an inductor, and wherein forming the inductor comprises forming and interconnecting a plurality of redistribution lines. In one embodiment, the method further comprises bonding the component die to a package component, wherein the first plurality of bond pads and the second plurality of bond pads are physically bonded to additional bond pads of the package component.In one embodiment, forming the first plurality of bond pads and forming the second plurality of bond pads comprises forming a dielectric layer; etching the dielectric layer to form a plurality of openings; filling a conductive material into the plurality of openings; and performing a planarization process to flatten upper surfaces of the dielectric layer and the conductive material, wherein remaining portions of the conductive material comprise the first plurality of bond pads, and forming the second plurality of bond pads.

[0064] In accordance with some embodiments, a structure comprises a device die having a functional circuit region; a first plurality of bond pads in the functional circuit region, the functional circuit region having a first pattern density of bond pads; a functional circuit in the functional circuit region and underlying the first plurality of bond pads; a passive device region; a passive device in the passive device region; a second plurality of bond pads in the passive device region and above the passive device, the passive device region having a second pattern density of bond pads, the second pattern density being lower than the first pattern density; a transition zone between the functional circuit region and the passive device region;and a third plurality of bond pads in the transition zone, wherein the transition zone has a third structural density of bond pads, the third structural density being lower than the first structural density and greater than the second structural density;

[0065] In one embodiment, the second plurality of bond pads comprise electrically floating bond pads. In one embodiment, the third plurality of bond pads are electrically floating. In one embodiment, the transition zone comprises a plurality of subzones, and wherein first ones of the plurality of subzones closer to the passive component zone have lower structure densities than respective second ones of the plurality of subzones closer to the functional circuit zone.

[0066] In one embodiment, the transition zone is free of active components therein. In one embodiment, the passive component comprises an inductor. In one embodiment, the structure further comprises a package component bonded to the device die, wherein the first plurality of bond pads, the second plurality of bond pads, and the third plurality of bond pads are in physical contact with and connected to the package component.

[0067] In accordance with some embodiments, a structure comprises a semiconductor substrate; a plurality of metal layers over the semiconductor substrate; an inductor over the plurality of metal layers; a first plurality of bond pads, wherein a first die area occupied by the first plurality of bond pads overlaps the inductor, and the first plurality of bond pads have a first pitch; a second plurality of bond pads in a second die area surrounding the first plurality of bond pads, the second plurality of bond pads having a second pitch that is smaller than the first pitch; and a third plurality of bond pads in a third die area surrounding the second plurality of bond pads, the third plurality of bond pads having a third pitch that is smaller than the second pitch.

[0068] In one embodiment, the first plurality of bond pads have a first feature density, and wherein the second plurality of bond pads have a second feature density greater than the first feature density, and the third plurality of bond pads have a third feature density greater than the second feature density. In one embodiment, the first plurality of bond pads have a first lateral dimension, and wherein the second plurality of bond pads have a second lateral dimension greater than the first lateral dimension, and the third plurality of bond pads have a third lateral dimension greater than the second lateral dimension.

[0069] The foregoing outlines features of some embodiments so that those skilled in the art will better understand aspects of the present disclosure. Those skilled in the art should appreciate that they can already use the present disclosure as a basis for designing or modifying other processes and structures for implementing the same purposes and / or achieving the same benefits of the embodiments presented herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] US 63 / 584,561

[0001]

Claims

[1] Method comprising: Forming a functional circuit on a semiconductor substrate of a device die, wherein the functional circuit is a functional circuit region of the device die; Forming a passive device over the semiconductor substrate, wherein the passive device is in a passive device region of the device die; Forming a first plurality of bond pads in the functional circuit region and on a surface of the device die, wherein the first plurality of bond pads have a first structural density; and Forming a second plurality of bond pads in the passive device region and at the surface of the device die, wherein the second plurality of bond pads have a second structure density that is lower than the first structure density. [2] The method of claim 1, further comprising: Forming a third plurality of bond pads in a transition zone and at the surface of the device die, wherein the transition zone is located between the passive device zone and the functional circuit zone, and wherein the third plurality of bond pads have a third structure density that is lower than the first structure density. [3] The method of claim 2, wherein the third plurality of bond pads are more than the second structure density. [4] The method according to claim 2 or 3, wherein the third plurality of bonding pads are dummy pads. [5] A method according to any one of claims 2 to 4, wherein the transition zone has a ring shape enclosing the passive component zone. [6] The method of any one of claims 2 to 5, wherein the third structure density is increasing or decreasing, wherein structure densities in portions of the transition zone closer to the passive device zone are lower than densities in portions of the transition zone closer to the functional circuit zone. [7] The method of any one of claims 1 to 6, wherein forming the passive component comprises forming an inductor, and wherein forming the inductor comprises forming a plurality of redistribution lines and connecting the plurality of redistribution lines together. [8] Method according to one of claims 1 to 7, further comprising: Bonding the device die to a package component, wherein the first plurality of bond pads and the second plurality of bond pads are physically bonded to additional bond pads of the package component. [9] The method of any one of claims 1 to 8, wherein forming the first plurality of bond pads and forming the second plurality of bond pads comprise: forming a dielectric layer; Etching the dielectric layer to form a plurality of openings; Filling a conductive material into the plurality of openings; and Performing a planarization process to flatten upper surfaces of the dielectric layer and the conductive material, wherein remaining portions of the conductive material comprise the first plurality of bond pads, and forming the second plurality of bond pads. [10] The method of any one of claims 1 to 9, wherein a ratio of the second structural density to the first structural density is less than about 0.

3. [11] Structure comprising a device die comprising: a functional circuit zone; a first plurality of bond pads in the functional circuit zone, the functional circuit zone having a first structural density of bond pads; a functional circuit in the functional circuit zone and underlying the first plurality of bond pads; a passive component zone; a passive component in the passive component zone; a second plurality of bond pads in the passive component zone and above the passive component, the passive component zone having a second pattern density of bond pads, the second pattern density being lower than the first pattern density; a transition zone between the functional circuit zone and the passive component zone; and third plurality of bond pads in the transition zone, wherein the transition zone has a third structural density of bond pads and the third structural density is lower than the first structural density and greater than the second structural density. [12] The structure of claim 11, wherein the second plurality of bond pads comprise electrically floating bond pads. [13] The structure of claim 11 or 12, wherein the third plurality of bond pads are electrically floating. [14] The structure of any one of claims 11 to 13, wherein the transition zone comprises a plurality of subzones, and wherein first ones of the plurality of subzones closer to the passive device zone have lower structure densities than respective second ones of the plurality of subzones closer to the functional circuit zone. [15] A structure according to any one of claims 11 to 14, wherein the transition zone is free of active devices therein. [16] A structure according to any one of claims 11 to 15, wherein the passive component comprises an inductor. [17] The structure of any one of claims 11 to 16, further comprising a package component bonded to the device die, wherein the first plurality of bond pads, the second plurality of bond pads, and the third plurality of bond pads are physically in contact with and connected to the package component. [18] Structure: a semiconductor substrate; multiple metal layers over the semiconductor substrate; an inductor over the plurality of metal layers; a first plurality of bond pads, wherein a first chip area occupied by the first plurality of bond pads overlaps the inductor and the first plurality of bond pads have a first spacing; a second plurality of bond pads in a second chip area surrounding the first plurality of bond pads, the second plurality of bond pads having a second spacing that is smaller than the first spacing; and third plurality of bond pads in a third chip area surrounding the second plurality of bond pads, the third plurality of bond pads having a third spacing that is smaller than the second spacing. [19] The structure of claim 18, wherein the first plurality of bond pads have a first feature density, and wherein the second plurality of bond pads have a second feature density greater than the first feature density, and the third plurality of bond pads have a third feature density greater than the second feature density. [20] The structure of claim 18 or 19, wherein the first plurality of bond pads have a first lateral dimension, and wherein the second plurality of bond pads have a second lateral dimension that is greater than the first lateral dimension, and the third plurality of bond pads have a third lateral dimension that is greater than the second lateral dimension.

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