Semiconductor device structure and method for manufacturing the same

Abstract

Procedure with the following steps: Producing a fin structure (112) from a substrate (101); Depositing a first semiconductor material (154) on a first semiconductor layer (106) of the fin structure (112); Depositing a second semiconductor material (156) on the first semiconductor material (150); depositing an interlayer dielectric layer over the second semiconductor material (156); forming an opening (180) in the interlayer dielectric layer to expose the second semiconductor material (156); Performing a first implantation process to create an amorphous region (186, 187) in the second semiconductor material (156) and to implant a first species into the amorphous region (186, 187); performing a second implantation process to implant a second species into the amorphous region (186, 187), the second species comprising fluorine, nitrogen, or carbon; and Performing an annealing process to recrystallize the amorphous region (186, 187), wherein the fin structure (112) comprises the first semiconductor layer (106), a second semiconductor layer (108) located below the first semiconductor layer (106), and a third semiconductor layer located below the second semiconductor layer (108), wherein the method further comprises depositing the first semiconductor material (154) on the first semiconductor layer (106) and the third semiconductor layer (106).

Description

BACKGROUNDThe IC (Semiconductor Integrated Circuit) industry has experienced exponential growth. Technological advances in IC materials and designs have produced generations of ICs, each generation having smaller and more complex circuits than the previous generation. In the course of IC evolution, the functional density (i.e., the number of interconnected devices per chip area) has generally increased, while the feature size (i.e., the smallest component (or line) that can be created with a fabrication process) has decreased. This process of downsizing generally offers advantages in increasing production efficiency and decreasing the costs associated therewith. However, this downsizing has also increased the complexity of processing and manufacturing ICs.Therefore, there is a need to improve the processing and fabrication of ICs.US 2020 / 0020772 A1 discloses a method of forming a semiconductor device structure. The method includes forming a semiconductor structure over a semiconductor substrate. The method also includes implanting carbon into the semiconductor structure. The method further includes implanting gallium into the semiconductor structure. Moreover, the method comprises heating the semiconductor structure after implanting carbon and gallium.DE 10 2017 126 510 A1 describes a structure with an active region of a transistor. The active region includes a source / drain region and the source / drain region is at least partially defined by a first dopant having a first dopant concentration. The source / drain region further includes a second dopant having a concentration profile that has a uniform concentration from an area of the source / drain region to a depth of the source / drain region. The uniform concentration is higher than the first dopant concentration. The structure further includes a conductive feature contacting the source / drain region at the surface of the source / drain region.The invention is defined in the claims.BRIEF DESCRIPTION OF THE DRAWINGSAspects of the present invention may best be understood from the following detailed description taken in conjunction with the accompanying drawings. It should be appreciated that, in accordance with practice in the industry, various features are not drawn to scale. Indeed, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased.FIGS. 1-5 are perspective views of various stages of manufacturing a semiconductor device structure, in accordance with some embodiments.FIGS. 6-20 are side sectional views of various stages of the fabrication of the semiconductor device structure taken along line A-A in FIG. 5, in accordance with some embodiments.DETAILED DESCRIPTIONThe following description provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements will be described below to simplify the present disclosure. For example, in the description below, the formation of a first element over or on a second element may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements such that the first and second elements are not in direct contact. Moreover, in the present invention, reference numerals and / or letters may be repeated in the various examples. This repetition is for convenience and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.Moreover, spatially relative terms such as "lower", "lower", "lower(r)" / "lower", "higher", "upper(r)" / "upper" and the like may be used herein to easily describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or in another orientation) and the spatially relative descriptors used herein interpreted accordingly.Various embodiments described below generally relate to implanting one species into a source / drain region to delay diffusion of another species from the source / drain region into a channel region. The diffusion of the species from the source / drain region to the channel region may cause Ge out-diffusion from an adjacent semiconductor layer into the channel region, which may negatively affect the yield line.While embodiments of this invention are discussed in relation to nanostructure channel field-effect transistor (FET)s, such as gate-all-around FETs (GAA-FETs, for example horizontal gate-all-around FETs (HGAA-FETs) or vertical gate-all-around FETs (VGAA-FETs), implementations of some aspects of the present invention may also be used in other processes and / or in other devices, such as planar FETs, fin FETs, and other suitable devices. In cases where gate-all-around (GAA) transistor structures are employed, the GAA transistor structures may be patterned using any suitable method. For example, the structures may be patterned using one or more photolithography processes, such as dual-patterning or multi-patterning processes. Generally, double-patterning or multi-patterning processes combine photolithography and self-aligned processes that can produce patterns having pitches, for example, that are smaller than those that can otherwise be achieved with a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate, which is then patterned using a photolithography process. Spacers are produced along the structured sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers may then be used to pattern the GAA structure.FIGS. 1-20 illustrate exemplary processes for fabricating a semiconductor device structure 100 in accordance with embodiments of the present invention. It should be appreciated that further operations before, during, and after processes shown in FIGS. 1-20 may be provided, and that some of the operations described below may be replaced or omitted in further embodiments of the method. The order of operations / processes is not limiting and may be interchanged.FIGS. 1-5 are perspective views of various stages of manufacturing a semiconductor device structure 100, in accordance with some embodiments. As shown in FIG. 1, a semiconductor device structure 100 includes a stack of semiconductor layers 104 formed over a front side of a substrate 101. The substrate 101 may be a semiconductor substrate. The substrate 101 may include a crystalline semiconductor material such as, but not limited to, silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimon phosphide (GaSbP), gallium arsenic antimonide (GaAsSb), and indium phosphide (InP). In some embodiments, the substrate 101 is a silicon-on-insulator (SOI) substrate (SOI) having an insulating layer (not shown) disposed between two silicon layers for reinforcement. In one aspect, the insulating layer is an oxygen-containing layer.The substrate 101 may have different regions doped with different dopants (e.g., p- or n-type dopants). Depending on the circuit design, the dopants may be, for example, phosphorous for an n-type field effect transistor (NFET) and boron for a p-type field effect transistor (PFET).The stack of semiconductor layers 104 includes alternating semiconductor layers made of different materials to facilitate the formation of nanostructure channels in a multi-gate device, such as nanostructure channel FETs. In some embodiments, the stack of semiconductor layers 104 includes first semiconductor layers 106 and second semiconductor layers 108. In some embodiments, the stack of semiconductor layers 104 includes alternating first semiconductor layers 106 and second semiconductor layers 108. The first semiconductor layers 106 and the second semiconductor layers 108 are made of semiconductor materials having different etch selectivity and / or oxidation rates. For example, the first semiconductor layers 106 may be made of Si and the second semiconductor layers 108 may be made of SiGe. In some examples, the first semiconductor layers 106 may be made of SiGe and the second semiconductor layers 108 may be made of Si. Alternatively, in some embodiments, each of the two semiconductor layers 106, 108 may be or include other materials such as Ge, SiC, GaAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or combinations thereof.The first semiconductor layers 106 and the second semiconductor layers 108 are formed by a suitable deposition process, such as epitaxy. For example, the epitaxial growth of the layers of the stack of semiconductor layers 104 may be performed using a molecular beam epitaxy (MBE) process (MBE), a metalorganic chemical vapor deposition (MOCVD) process (MOCVD), and / or other suitable epitaxial growth processes.The first semiconductor layers 106 or portions thereof may form one or more nanostructure channels of the semiconductor device structure 100 at later fabrication stages. The term nanostructure is used in this disclosure to refer to a piece of material having nanoscale or even micron-scale dimensions and having an elongated shape regardless of the shape of the cross-section of that piece. Consequently, the term refers to both elongated material parts with a round and substantially round cross section and bar- or rod-shaped material parts with, for example, a cylindrical or substantially rectangular cross section. The one or more nanostructure channels of the semiconductor device structure 100 may be surrounded by a gate electrode. The semiconductor device structure 100 may include a nanostructure transistor. The nanostructure transistors may be referred to as nanolayer transistors, nanowire transistors, gate-all-around (GAA) transistors, multi-bridge channel (MBC) transistors, or transistors with a gate electrode enclosing the channels. The use of the first semiconductor layers 106 to define one or more channels of the semiconductor device structure 100 will be discussed further below.Each first semiconductor layer 106 may have a thickness in a range between about 5 nm and about 30 nm. Each second semiconductor layer 108 may have a thickness equal to or less than or greater than the thickness of the first semiconductor layer 106. In some embodiments, each second semiconductor layer 108 has a thickness in a range between about 2 nm and about 50 nm. Three first semiconductor layers 106 and three second semiconductor layers 108 are arranged alternately, as shown in FIG. 1. It is understood that any number of first semiconductor layers 106 and second semiconductor layers 108 may be formed in the stack of semiconductor layers 104, and the number of layers depends on the number of channels predetermined for the semiconductor device structure 100. In some embodiments, the stack of semiconductor layers 104 includes two first semiconductor layers 106. In some embodiments, the stack of semiconductor layers 104 includes three first semiconductor layers 106. In some embodiments, the stack of semiconductor layers 104 includes four first semiconductor layers 106.As shown in FIG. 2, fin structures 112 are formed from the stack of semiconductor layers 104. Each of the fin structures 112 has an upper portion including the semiconductor layers 106, 108 and a well portion 116 formed from the substrate 101. The fin structures 112 may be formed using multiple patterning operations with photolithography and etching processes by patterning a hard mask layer (not shown) formed on the stack of semiconductor layers 104. The etching process may include dry etching, wet etching, reactive ion etch (RIE) (RIE), and / or other suitable processes. The photolithography process may include the steps of forming a photoresist layer (not shown) over the hard mask layer, exposing the photoresist layer to a pattern, performing curing processes after the exposure, and developing the photoresist layer to form a masking element including the photoresist layer. In some embodiments, the patterning to form the masking element may be performed using an electron beam (e-beam) lithographic process. The etching process forms trenches 114 in unprotected regions through the hard mask layer, through the stack of semiconductor layers 104 and into the substrate 101, leaving the plurality of extending fin structures 112. The trenches 114 extend along the x-direction. The trenches 114 may be formed using a dry etch (e.g., RIE), a wet etch, and / or combinations thereof.As shown in FIG. 3, after the fin structures 112 are formed, an insulating material 118 is formed on the substrate 101. The isolation material 118 fills the trenches 114 between adjacent fin structures 112 until the fin structures 112 are embedded in the isolation material 118. Then, a planarization operation, such as a chemical mechanical polishing (CMP) process and / or an etch back process, is performed so that the top surface of the fin structures 112 is exposed. The insulating material 118 may be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine doped silicate glass (FSG), a low-k dielectric material, or another suitable dielectric material. The insulating material 118 may be performed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD) (LPCVD), plasma enhanced CVD (PECVD) (PECVD), or flowable CVD (FCVD).As shown in FIG. 4, the insulating material 118 is recessed to form isolation regions 120. Recessing the insulating material 118 exposes portions of the fin structures 112, such as the stack of semiconductor layers 104. By recessing the insulating material 118, the trenches 114 between the adjacent fin structures 112 are revealed. The isolation regions 120 may be formed by any suitable process, such as a dry etch process, a wet etch process, or a combination thereof. A top surface of the insulating material 118 may be level with or below a surface of the second semiconductor layers 108 in contact with the well part 116 made of the substrate 101. In some embodiments, isolation regions 120 are shallow trench isolation (STI) regions (STI).As shown in FIG. 5, one or more sacrificial gate structures 130 (only one is shown) are formed over the semiconductor device structure 100. The sacrificial gate structures 130 are formed over a portion of the fin structures 112. Each sacrificial gate structure 130 may include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a mask layer 136. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136 are formed by sequentially depositing unpatterned layers of the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136, and then patterning these layers into the sacrificial gate structures 130. While only one sacrificial gate structure 130 is shown, in some embodiments, two or more sacrificial gate structures 130 may be arranged along the x-direction.The sacrificial gate dielectric layer 132 may include one or more layers of dielectric material, such as a silicon oxide-based material. The sacrificial gate electrode layer 134 may include silicon, such as polycrystalline silicon or amorphous silicon. The mask layer 136 may include more than one layer such as an oxide layer and a nitride layer. The portions of the fin structures 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 serve as channel regions for the semiconductor device structure 100.FIGS. 6-20 are side sectional views of various stages of the fabrication of the semiconductor device structure 100 taken along line A-A of FIG. 5, in accordance with some embodiments. As shown in FIG. 6, a first gate spacer 138 is deposited on the exposed surfaces of the semiconductor device structure 100. For example, the first gate spacer 138 is deposited on the fin structures 112, the isolation regions 120, and the sacrificial gate structure 130. The first gate spacer 138 may be made of a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiCON, and / or combinations thereof. The first gate spacer 138 may be formed using any suitable process. In some embodiments, the first gate spacer 138 is a conformal layer formed using a conformal process, such as an atomic layer deposition (ALD) process (ALD).As shown in FIG. 7, a second gate spacer 139 is deposited on the first gate spacer 138. The second gate spacer 139 may include any suitable dielectric material, such as SiO x, SiON, SiN, SiCON, or SiCO. The second gate spacer 139 may have a thickness in a range from about 0.5 nm to about 5 nm. The second gate spacer 139 may be formed by any suitable process. In some embodiments, the second gate spacer 139 is deposited using CVD, PECVD, or electron cyclotron resonance (ECR-CVD) (ECR-CVD).As shown in FIG. 8, horizontal portions of the first gate spacer 138 and the second gate spacer 139 are removed. In some embodiments, the horizontal portions of the first gate spacer 138 and the second gate spacer 139 are removed with an anisotropic etching process. The anisotropic etching process may be a selective etching process that leaves the mask layer 136, the stack of semiconductor layers 104, and the isolation regions 120 substantially unaffected.As shown in FIG. 9, the portions of the fin structures 112 not covered by the sacrificial gate structure 130, and the first gate spacer 138 and the second gate spacer 139 are saved to a height equal to or above or below the height of the tops of the isolation regions 120. The recessing of the portions of the fin structures 112 may be performed with an etching process. The etching process may be a dry etch such as RIE, NBE, or the like, or a wet etch such as using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH 4 OH), or another suitable etchant. The well portions 116 are exposed on opposite sides of the sacrificial gate structure 130, as shown in FIG. 9.As shown in FIG. 10, edge portions of each second semiconductor layer 108 of the stack of semiconductor layers 104 are horizontally removed along the x-direction. By removing the edge portions of the second semiconductor layers 108, voids are formed. In some embodiments, the edge portions of the second semiconductor layers 108 are removed with a selective wet etching process. In cases where the second semiconductor layers 108 are made of SiGe and the first semiconductor layers 106 are made of silicon, the second semiconductor layer 108 may be selectively etched with a wet etchant such as ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solutions, among others.After removing the edge portions of each second semiconductor layer 108, a dielectric layer is deposited in the cavities to form dielectric spacers 144. The dielectric spacers 144 may be made of a low-k dielectric material such as SiON, SiCN, SiOC, SiOCN, or SiN. The dielectric spacers 144 may be formed by first forming a conformal dielectric layer with a conformal deposition process such as ALD and then performing an anisotropic etch process to remove portions of the conformal dielectric layer except for the dielectric spacers 144. The dielectric spacers 144 are protected by the first semiconductor layers 106 during the anisotropic etching process. The remaining second semiconductor layers 108 are capped between the dielectric spacers 144 along the x-direction.As shown in FIG. 11, a first semiconductor material 150 is formed on the exposed well portions 116. In some embodiments, the first semiconductor material 150 includes undoped silicon or undoped SiGe. The first semiconductor material 150 may be first formed on semiconductor surfaces, such as on the exposed well portions 116 and on the first semiconductor layers 106, with an epitaxy process. Subsequently, an etching process is performed to remove the portions of the first semiconductor material 150 formed on the first semiconductor layers 106. The first semiconductor material 150 formed on the exposed well portions 116 may form a concave top as a result of the etching process. In some embodiments, the first semiconductor material 150 has a thickness along the z-direction in a range from about 5 nm to about 50 nm.Then, as shown in FIG. 12, a dielectric layer 152 is formed on the first semiconductor material 150. The dielectric layer 152 may be formed by first forming a dielectric layer on the exposed surfaces of the semiconductor device structure 100 and then performing one or more etch processes to remove portions of the dielectric layer except for the dielectric layer 152. A mask layer (not shown), such as a bottom anti-reflective coating (BARC) layer (BARC), may be used to assist in removing portions of the dielectric layer. The dielectric layer 152 may include any suitable dielectric material. In some embodiments, the dielectric layer 152 includes SiN. The dielectric layer 152 may be formed by any suitable process. In some embodiments, the dielectric layer 152 is formed by CVD. Then, a second semiconductor material 154 is formed from the first semiconductor layers 106. The second semiconductor material 154 may be made of one or more layers of Si, SiP, SiC, SiAs, SiSb, and SiCP for n-channel FETs or Si, SiGe, Ge for p-channel FETs. For p-channel FETs, p-dopants, such as boron (B), may be incorporated into the second semiconductor material 154. For n-channel FETs, n-dopants such as phosphorus (P) or arsenic (As) may be incorporated into the second semiconductor material 154. In some embodiments, the doping concentration of the second semiconductor material 154 may be in a range from about 1×10 19 cm -3 to about 2×10 21 cm -3. The second semiconductor material 154 may be formed by an epitaxial growth method using CVD, ALD, or MBE. As shown in FIG. 12, in some embodiments, the second semiconductor material 154 is selectively formed on semiconductor materials such as the first semiconductor layers 106, and is not formed on dielectric materials such as the dielectric layer 152 and the dielectric spacers 144. In some embodiments, the second semiconductor material 154 has facets that may correspond to crystalline planes of the material used for the first semiconductor layers 106.Then, as shown in FIG. 12, a third semiconductor material 156 is formed from the second semiconductor material 154. The third semiconductor material 156 may be formed by an epitaxial growth method using CVD, ALD, or MBE. The third semiconductor material 156 may be made of one or more layers of Si, SiP, SiC, and SiCP for n-FETs or Si, SiGe, Ge for p-FETs. For p-FETs, p-dopants, such as boron (B), may be incorporated into the second semiconductor material 154. For n-FETs, n-dopants, such as phosphorus (P) or arsenic (As), may be incorporated into the third semiconductor material 156. In some embodiments, the second semiconductor material 154 and the third semiconductor material 156 may include the same semiconductor materials but with different doping concentrations. The doping concentration of the third semiconductor material 156 may be substantially greater than the doping concentration of the second semiconductor material 154. In some embodiments, the doping concentration of the third semiconductor material 156 may be in a range from about 5×10 19 cm -3 to about 4×10 21 cm -3. The third semiconductor material 156 may be epitaxially grown from the second semiconductor material 154. The quality of the third semiconductor material 156 can be improved by the facets made of the second semiconductor material 154. In some embodiments, the dielectric layer 152 is not present and the third semiconductor material 156 is grown from the first semiconductor material 150 and the second semiconductor material 154.In some embodiments, a capping layer (not shown) may be formed on the third semiconductor material 156. The capping layer may include a semiconductor material. In some embodiments, the capping layer comprises the same material as the third semiconductor material. The capping layer may be epitaxially grown from the third semiconductor material 156.In some embodiments, the second semiconductor material 154 and the third semiconductor material 156 may be doped in situ during growth. If the doping concentrations of the second semiconductor material 154 and the third semiconductor material 156 are greater than the respective ranges mentioned above, this may negatively affect the quality of the second semiconductor material 154 and the third semiconductor material 156. Consequently, later processes may be performed to increase the doping concentration and / or the activation of dopants and thus decrease the electrical contact resistance.The second semiconductor material 154 and the third semiconductor material 156 together may be the source / drain (S / D) region. In this disclosure, a source region and a drain region are used interchangeably and their structures are substantially the same. Additionally, depending on the context, the one or more source / drain regions may individually or collectively refer to a source or a drain. In some embodiments, p-S / D regions and n-S / D regions may be separately formed using one or more mask layers. In some embodiments, the second semiconductor material 154 and the third semiconductor material 156 are crystalline semiconductor materials.Then, as shown in FIG. 12, a contact etch stop layer (CESL) (CESL) 162 is conformally formed on the exposed surfaces of the semiconductor device structure 100. The CESL 162 covers the second gate spacer 139, the isolation regions 120, and the third semiconductor material 156 (or the capping layer, if present). The CESL 162 may include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbon nitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbon oxide, or the like, or a combination thereof, and may be formed by CVD, PECVD, ALD, or any suitable deposition method. In some embodiments, the CESL 162 is a single layer, as shown in FIG. 12. In some embodiments, the CESL 162 includes two or more layers. An interlayer dielectric (ILD) layer 164 is then formed on the CESL 162. The materials for the ILD layer 164 may include compounds with Si, O, C, and / or H, such as silicon oxide, SiCOH, or SiOC. Organic materials such as polymers may also be used for the ILD layer 164. The ILD layer 164 may be formed using a PECVD process or other suitable deposition process. In some embodiments, after forming the ILD layer 164, the semiconductor device structure 100 may be subjected to a thermal process to anneal the ILD layer 164.After forming the ILD layer 164, a planarization operation such as CMP is performed on the semiconductor device structure 100 until the sacrificial gate electrode layer 134 is exposed, as shown in FIG. 12.Then, as shown in FIG. 13, the sacrificial gate structure 130 and the second semiconductor layers 108 are removed. By removing the sacrificial gate structure 130 and the semiconductor layers 108, an opening is formed between the first gate spacers 138 and between the first semiconductor layers 106. The ILD layer 164 protects the second semiconductor material 156 during the removal process. The sacrificial gate structure 130 may be removed with a plasma dry etch and / or a wet etch. The sacrificial gate electrode layer 134 may be first removed by any suitable process, such as dry etching, wet etching, or a combination thereof, followed by removal of the sacrificial gate dielectric layer 132, which may also be performed by any suitable process, such as dry etching, wet etching, or a combination thereof. In some embodiments, a wet etchant such as a tetramethylammonium hydroxide (TMAH) solution may be used to selectively remove the sacrificial gate electrode layer 134 without removing the first gate spacers 138, the ILD layer 164, and the CESL 162.The second semiconductor layers 108 may be removed with a selective wet etching process. In cases where the second semiconductor layers 108 are made of SiGe and the first semiconductor layers 106 are made of Si, the chemicals used in the selective wet etching process remove the SiGe while substantially intact Si, the dielectric materials of the first gate spacers 138, and the dielectric spacers 144. In an embodiment, the second semiconductor layers 108 may be removed with a wet etchant such as, but not limited to, hydrogen fluoride (HF), nitric acid (HNO 3), hydrochloric acid (HCl), or phosphoric acid (H 3 PO 4).As shown in FIG. 14, after the nanostructure channels (i.e., the exposed portions of the first semiconductor layers 106) are formed, a gate dielectric layer 170 is formed to enclose the exposed portions of the first semiconductor layers 106, and a gate electrode layer 172 is formed on the gate dielectric layer 170. The gate dielectric layer 170 and the gate electrode layer 172 may be collectively referred to as a gate structure 174. In some embodiments, an interfacial layer (IL) (IL) (not shown) is formed between the gate dielectric layer 170 and the exposed surfaces of the first semiconductor layers 106, and one or more exit working layers (not shown) are formed between the gate dielectric layer 170 and the gate electrode layer 172. In some embodiments, the gate dielectric layer 170 includes one or more layers of a dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric material, another suitable dielectric material, and / or combinations thereof. Examples of high-k dielectric materials include HfO 2, HfSiO, HfSiON, HfTaO, HfTiO, HfNbO, zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-aluminum oxide (HfO 2- Al 2 O 3- alloy), other suitable high-k dielectric materials, and / or combinations thereof. The gate dielectric layer 170 may be formed by CVD, ALD, or any suitable deposition method. The work function layer may include polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, or other suitable materials. The gate electrode layer 172 may include one or more layers of conductive material, such as platinum (Pt), palladium (Pd), tantalum (Ta), ytterbium (Yb), aluminum (Al), silver (Ag), titanium (Ti), ruthenium (Ru), molybdenum (Mo), chromium (Cr), tungsten (W), copper (Cu), or a similar material, and / or combinations thereof. The gate electrode layer 172 may be formed by CVD, ALD, electroplating, or other suitable deposition method. Gate electrode layer 172 may also be deposited over the top surface of ILD layer 164. The gate dielectric layer 170 and the gate electrode layer 172 formed over the ILD layer 164 are then removed with, for example, CMP until the top surface of the ILD layer 164 is exposed.It is understood that the semiconductor device structure 100 may be subjected to further processes such as a metal gate cut (CMG) process (CMG) and / or a continuous poly on diffusion edge (CPODE) process. With the CMG process, the gate electrode layer 172 is separated into a plurality of segments that can be individually controlled. The CPODE process establishes isolation between devices.As shown in FIG. 15, an etch stop layer 166 and a second ILD layer 168 are formed over the ILD layer 164 and the gate electrode layer 172. The etch stop layer 166 may include the same material as the CESL 162 and may be formed with the same process as the CESL 162. The second ILD layer 168 may include the same material as the ILD layer 164 and may be formed using the same process as the ILD layer 164.Then, as shown in FIG. 16, openings 180 are formed in the second ILD layer 168, the etch stop layer 166, the ILD layer 164, and the CESL 162 to expose the third semiconductor material 156. In some embodiments, portions of the ILD layer 164 and the CESL 162 that are over the third semiconductor material 156 may be removed. In some embodiments, the capping layer (not shown) and a portion of the third semiconductor material 156 may also be removed. The openings 180 may be formed with an etching process, such as a dry etching process, a wet etching process, or a combination thereof. A patterned mask (not shown) may be formed over the second ILD layer 168, and the pattern of the patterned mask is transferred to the second ILD layer 168, the etch stop layer 166, the ILD layer 164, and the CESL 162.As shown in FIG. 16, the semiconductor device structure 100 includes an IL 167 formed on the first semiconductor layers 106 and a work function layer 169 formed between the gate dielectric layer 170 and the gate electrode layer 172. Moreover, the semiconductor device structure 100 includes a dielectric liner 196 and a dielectric material 198. The dielectric liner 196 and the dielectric material 198 may be an isolation structure formed using a CPODE process. In some embodiments, the dielectric material 198 comprises the same material as the etch stop layer 166.As shown in FIG. 17, a liner 184 is formed on the vertical surfaces of the second ILD layer 168, the etch stop layer 166, and the first gate spacers 138. The liner 184 may comprise any suitable material. In some embodiments, the liner 184 is a nitride layer, such as a silicon nitride layer. In some embodiments, the liner 84 includes the same material as the etch stop layer 166. The liner 184 may be formed by first forming a dielectric layer on the exposed surfaces of the semiconductor device structure 100 and then performing an anisotropic etching process to remove portions of the dielectric layer formed on horizontal surfaces of the semiconductor device structure 100. For example, portions of the dielectric layer formed on the second ILD layer 168 and the third semiconductor material 156 are removed with an anisotropic etching process. The liner 184 protects the second ILD layer 168 during later processes.In some embodiments, to reduce the electrical contact resistance, one or more processes may be performed to increase the doping concentration and / or the activation of dopants in the third semiconductor material 156 and / or the second semiconductor material 154. In some embodiments, an amorphization process and an annealing process are performed. In some embodiments, portions of the second semiconductor material 154 and the third semiconductor material 156, which are crystalline semiconductor materials, are amorphized with the amorphization process. For example, a first species may be injected into the second semiconductor material 154 and the third semiconductor material 156 to form an amorphous region 186 as shown in FIG. 18. In some embodiments, the amorphous region 186 extends to a height between the uppermost first semiconductor layer 106 and the adjacent first semiconductor layer 106 below the uppermost first semiconductor layer 106.In some embodiments, the amorphization process is an ion implantation process that incorporates the first species into the second semiconductor material 154 and the third semiconductor material 156, such that at least a top portion of the third semiconductor material 156 and portions of the second semiconductor material 154 that are in contact with the uppermost first semiconductor layers 106 are converted to an amorphous structure (i.e., the amorphous region 186). The first species of the ion implantation process may be a Group IV element such as C, Si, Ge; a Group III element such as B, Al, Ga, In; a Group V element such as P, As, Sb; or a Group VIII element such as He, Ar, Xe. The implantation process may have an implantation energy in a range from about 0.3 keV to about 60 keV, a dosage of greater than about 1×10 13 cm -2 and a processing temperature in a range from about -150 degrees Celsius to about 500 degrees Celsius. In some embodiments, the projected range Rp of the first species is about 4 nm to about 5 nm, and the depth of the amorphous region 186 is about 5 nm to about 10 nm. In some embodiments, a bottom surface of the amorphous region 186 is at a height between the uppermost first semiconductor layer 106 and the first semiconductor layer 106 that is below the uppermost first semiconductor layer 106. In some embodiments, the first species in the amorphous region 186 has a concentration gradient. As shown in FIG. 18, the amorphous region 186 includes a first sub-region 186 awith a first species concentration of about 5×10 20 cm -3, a second sub-region 186 bwith a first species concentration of about 1×10 20 cm -3 and a third sub-region 186 cwith a first species concentration of about 1×10 19 cm -3.In some embodiments, the S / D region is an n-S / D region, and the second semiconductor material 154 and the third semiconductor material 156 comprise SiP. The first species of the ion implantation process comprises phosphorus (P). With the higher concentration of P, the contact resistance of the S / D region can be reduced. However, during the subsequent anneal process, the first species may diffuse into the adjacent first semiconductor layer 106. In some embodiments, the first species may diffuse into the interface between the first semiconductor layer 106 and the dielectric spacer 144 and into the interface between the first semiconductor layer 106 and the first gate spacer 138. In some embodiments, the first species comprises phosphorus (P), and the phosphorus diffusion is based on phosphorus hole (PV) pairs (PV: phosphorus-vacance). The first species in the aforementioned interfaces may cause the germanium (Ge) in the second semiconductor layer 108 to diffuse into the first semiconductor layer 106, and thereby yield deteriorates.To retard diffusion of the first species, a second species is incorporated into the amorphous region 186. In some embodiments, the second species is incorporated with a second ion implantation process. The second species comprises fluorine (F), carbon (C) or nitrogen (N). In some embodiments, the second species comprises F. Vacancies are grown in the amorphous region 186 as F 3 V clusters and cooperate with interstitial F i, as shown in the equation F 3 V+I ←→ 3 F i. Consequently, diffusion of the first species during the subsequent annealing process is reduced by elimination of void and interstitial. This may eliminate the PV pairs, resulting in delayed phosphorus diffusion during the subsequent anneal process. In some embodiments, the second ion implantation process implants the second species to a depth of about 5 nm to about 8 nm into the amorphous region 186 where a void-rich region is located.The second implantation process may include an implantation energy in a range of about 1 keV to about 2 keV, a dosage in a range of about 5×10 14 cm -2 to about 1×10 15 cm -2, a processing temperature in a range of about -60 degrees Celsius to about 450 degrees Celsius, and an implantation angle having an inclination in a range of about 0 degrees to about 15 degrees and a rotation in a range of about 0 degrees to about 360 degrees. The concentration of the second species in the amorphous region 186 is between about 5×10 20 cm -3 and about 1×10 21 cm -3. In some embodiments, the second species has an Rpthat is greater than the Rpof the first species. The Rpof the second species may be in a range from about 5 nm to about 7 nm. In some embodiments, the Rpof the second species is at least 1.3 nm deeper than the Rpof the first species. This makes the delay of diffusion of the first species more effective because the interaction region is about 5 nm to about 10 nm (FV clustering). The depth of the region having the second species may be shallower than the depth of the amorphous region 186. In some embodiments, the amorphous region 186 may prevent the later implanted second species from channeling through the interstices between the crystal lattice structure and advancing to greater depths than desired.In some embodiments, a third ion implantation process is performed to implant a third species into the amorphous region 186. The third species includes fluorine (F), carbon (C) and / or nitrogen (N) and is different from the second species. The third ion implantation process may have the same process conditions as the second implantation process. By supplying the third species, the diffusion of the first species into the first semiconductor layers 106 may be further delayed. The third ion implantation process may be optional.In some embodiments, as shown in FIG. 18, the amorphous region 186 formed by the ion implantation process is in contact with the first semiconductor layers 106. In some embodiments, as shown in FIG. 19, the amorphous region 186 formed by the ion implantation process does not extend to the second semiconductor material 154. The upper portion of the third semiconductor material 156 is amorphized to form the amorphous region 186, while the second semiconductor material 154 disposed on opposite sides of the amorphous region 186 remains crystalline. The size of the amorphous region 186 may be controlled with the implantation angle and / or the implantation energy and duration. Then, the second ion implantation process is performed to form an amorphous region 187 as shown in FIG. 19. In some embodiments, amorphous region 187 is wider and deeper than amorphous region 186 and amorphous region 186 is within amorphous region 187. In other words, the second semiconductor material 154 and the parts of the third semiconductor material 156 arranged underneath is amorphized by the second ion implantation process. The second species is implanted into both the first amorphous region 186 and the second amorphous region 187. In some embodiments, the first species in the amorphous region 186 is surrounded by the second species in the amorphous region 187. As a result, the diffusion of the first species in the amorphous region 186 into the first semiconductor layers 106 is further delayed. In some embodiments, the second ion implantation process described in FIG. 19 may have a higher implantation energy compared to the second ion implantation process described in FIG. 18 for forming the amorphous region 187. In some embodiments, the second species in the amorphous region 187 is adjacent to the first species in the amorphous region 186.In some embodiments, the third ion implantation process is performed to implant the third species into the amorphous regions 186, 187. As described above, the third implantation process may be optional.After the amorphization process and the second ion implantation process (and in some embodiments, the third ion implantation process), the anneal process is performed to recrystalize the amorphous region 186 (and in some embodiments, the amorphous region 187). In some embodiments, the annealing process may be a flash lamp annealing (FLA) process (FLA), a laser spike annealing (LSA) process (LSA), or a rapid thermal annealing (RTA) process (RTA). The annealing temperature may be in a range from about 1050 degrees Celsius to about 1200 degrees Celsius for FLA or LSA and in a range from about 900 degrees Celsius to about 1000 degrees Celsius for RTA. The dwell time of the annealing process may be in a range from about 0.1 ms to about 40 ms for FLA or LSA and in a range from about 1 s to about 20 s for RTA. The chamber pressure during the annealing process may be in a range from about 133 Pa to about 100 kPa (about 1 Torr to about 760 Torr).After the amorphous regions 186, 187 are recrystallized, the second semiconductor material 154 in contact with the uppermost first semiconductor layers 106 has the second species such as F, N, or C, and the concentration of the second species in the second semiconductor material 154 in contact with the uppermost first semiconductor layers 106 is in a range of about 5×10 20 cm -3 to about 1×10 21 cm -3. In some embodiments, the second semiconductor material 154 in contact with the uppermost first semiconductor layers 106 also includes the third species, such as F, N, or C, different from the second species. In some embodiments, the second semiconductor material 154 in contact with the first semiconductor layers 106 located below the uppermost first semiconductor layers 106 is free of the second and third species because the amorphous regions 186, 187 do not extend to the second semiconductor material 154 in contact with the first semiconductor layers 106 located below the uppermost first semiconductor layers 106. Thereby, the first species, the second species, and the third species in the amorphous regions 186, 187 are not implanted into the second semiconductor material 154 that is in contact with the first semiconductor layers 106 that are below the uppermost first semiconductor layers 106. In some embodiments, the second semiconductor material 154 in contact with the first semiconductor layers 106 located below the uppermost first semiconductor layers 106 has a concentration gradient of the second species and the third species. For example, the concentration of the second species and the third species in the second semiconductor material 154 in contact with the first semiconductor layers 106 located below the uppermost first semiconductor layers 106 decreases in a direction toward the substrate 101.As shown in FIG. 20, silicide layers 192 are formed on the S / D regions (second semiconductor material 154 and third semiconductor material 156). The silicide layer 192 may be formed by any suitable process. In some embodiments, a metal layer (not shown) is first formed on the semiconductor device structure 100. The metal layer may comprise Ti, Ni, Ru, Co, W or another suitable metal. In some embodiments, the metal layer is a multilayer structure. The multilayer structure may include a metal layer and a metal nitride or metal oxide layer. The metal layer may be deposited using any suitable process, such as ALD, CVD, or PVD. After deposition of the metal layer, an anneal process is performed to react the amorphous region 186 with the metal layer, thereby forming the silicide layers 192. The silicide layer 192 may comprise any suitable material, such as NiSi, TiSi, CoSi, RuSi, or wSi. Conductive contacts 194 are then deposited in the openings 180. The conductive contact 194 may be electrically conductive and may include a material including Ru, Mo, Co, Ni. W, Ti, Ta, Cu, Al, TiN, and / or TaN, and the conductive contact 194 may be formed by any suitable method, such as electrochemical plating (ECP) (ECP) or physical vapor deposition (PVD) (PVD).Embodiments of the present invention provide a semiconductor device structure and methods for manufacturing the same. In some embodiments, the method includes performing an amorphization process on a portion of the third semiconductor material 156 to form an amorphous region 186 and to implant a first species into the amorphous region 186. A second implantation process may be performed to implant a second species into the amorphous region 186. The presence of the second species retards diffusion of the first species by eliminating vacancies and interstitials. Some embodiments may achieve benefits. For example, by delaying diffusion of the first species, the risk of Ge outdiffusing may be reduced, which in turn improves yield performance.One embodiment is a method. The method includes the steps of: forming a fin structure from a substrate; depositing a first semiconductor material on a first semiconductor layer of the fin structure; depositing a second semiconductor material on the first semiconductor material; depositing an interlayer dielectric layer over the second semiconductor material; forming an opening in the interlayer dielectric layer to expose the second semiconductor material; performing a first implantation process to form an amorphous region in the second semiconductor material and to implant a first species into the amorphous region; and performing a second implantation process to implant a second species into the amorphous region. The second species comprises fluorine, nitrogen or carbon. The method further includes performing an annealing process to recrystalize the amorphous region.Another embodiment is a method. The method includes the steps of: forming a fin structure from a substrate; depositing a first semiconductor material over the substrate; depositing an interlayer dielectric layer over the first semiconductor material; forming an opening in the interlayer dielectric layer to expose the first semiconductor material; performing a first implantation process to form a first amorphous region in the first semiconductor material and to implant a first species into the first amorphous region; performing a second implantation process to form a second amorphous region in the first semiconductor material and to implant a second species into the first amorphous region and the second amorphous region; performing an annealing process to recrystalize the first amorphous region and the second amorphous region.Another embodiment is a semiconductor device structure. The structure includes a plurality of semiconductor layers disposed over a substrate and a source / drain region disposed adjacent to the plurality of semiconductor layers. The source / drain region includes a first semiconductor material in contact with each semiconductor layer of the plurality of semiconductor layers. A first portion of the first semiconductor material in contact with an uppermost semiconductor layer of the plurality of semiconductor layers includes a first species, and a second portion of the first semiconductor material in contact with a semiconductor layer of the plurality of semiconductor layers disposed below the uppermost semiconductor layer has a concentration gradient of the first species. The source / drain region further includes a second semiconductor material adjacent to the first semiconductor material.

Claims

A method comprising: forming a fin structure (112) from a substrate (101); depositing a first semiconductor material (154) on a first semiconductor layer (106) of the fin structure (112); depositing a second semiconductor material (156) on the first semiconductor material (150); depositing an interlayer dielectric layer over the second semiconductor material (156); forming an opening (180) in the interlayer dielectric layer to expose the second semiconductor material (156); performing a first implantation process to form an amorphous region (186, 187) in the second semiconductor material (156) and to implant a first species in the amorphous region (186, 187); Performing a second implantation process to implant a second species into the amorphous region (186, 187), the second species comprising fluorine, nitrogen, or carbon; and performing an annealing process to recrystalize the amorphous region (186, 187), the fin structure (112) comprising the first semiconductor layer (106), a second semiconductor layer (108) located below the first semiconductor layer (106), and a third semiconductor layer located below the second semiconductor layer (108), the method further comprising depositing the first semiconductor material (154) on the first semiconductor layer (106) and the third semiconductor layer (106).The method of claim 1, wherein the second semiconductor material (156) comprises SiP and the first species comprises phosphorus.The method of claim 1 or 2, wherein a concentration of the first species in the amorphous region (186, 187) is about 1×10 19 cm -3 to about 5×10 20 cm -3.The method of any preceding claim, wherein a concentration of the second species in the amorphous region (186, 187) is about 5×10 20 cm -3 to about 1×10 21 cm -3.The method of any of claims 1 to 4, wherein a bottom surface of the amorphous region (186, 187) is located at a height between the first semiconductor layer (106) and the second semiconductor layer (108).A method comprising: forming a fin structure (112) from a substrate (101); depositing a first semiconductor material (156) over the substrate (101); depositing an interlayer dielectric layer over the first semiconductor material (156); forming an opening (180) in the interlayer dielectric layer to expose the first semiconductor material (156); performing a first implantation process to form a first amorphous region (186, 187) in the first semiconductor material (156) and to implant a first species into the first amorphous region (186, 187); performing a second implantation process to form a second amorphous region (186, 187) in the first semiconductor material (156) and to implant a second species into the first amorphous region (186, 187) and the second amorphous region (186, 187); and performing an annealing process to re-crystallize the first amorphous region (186, 187) and the second amorphous region (186, 187), wherein the fin structure (112) has a plurality of semiconductor layers (106, 108), the method further comprising depositing a second semiconductor material (154) on each semiconductor layer of the plurality of semiconductor layers (106, 108), wherein the first semiconductor material (156) is deposited on the second semiconductor material (154).The method of claim 6, wherein the first species comprises phosphorus and the second species comprises fluorine, nitrogen, or carbon.The method of claim 6 or 7, wherein the second amorphous region (186, 187) is wider and deeper than the first amorphous region (186, 187).The method of any of claims 6 to 8, wherein the first amorphous region (186, 187) is located between portions of the second semiconductor material (154).The method of any of claims 6 to 9, wherein the portions of the second semiconductor material (154) are part of the second amorphous region (186, 187).A semiconductor device structure comprising: a plurality of semiconductor layers (106) disposed over a substrate (101); and a source / drain region disposed adjacent to the plurality of semiconductor layers (106), the source / drain region comprising: a first semiconductor material (150) in contact with each semiconductor layer of the plurality of semiconductor layers, a first portion of the first semiconductor material (150) in contact with an uppermost semiconductor layer of the plurality of semiconductor layers (106) comprising a first species, and a second portion of the first semiconductor material (150) in contact with a semiconductor layer of the plurality of semiconductor layers (106) disposed below the uppermost semiconductor layer having a concentration gradient of the first species; and a second semiconductor material (156) adjacent to the first semiconductor material (150).The semiconductor device structure of claim 11, wherein the first species comprises fluorine, nitrogen, or carbon.The semiconductor device structure of claim 11 or 12, wherein the second semiconductor material (156) comprises a second species.The semiconductor device structure of any one of claims 11 to 13, wherein a second species comprises phosphorus.The semiconductor device structure according to any one of claims 11 to 14, wherein the second species has a concentration gradient that decreases in a direction toward the substrate (101).The semiconductor device structure according to any one of claims 11 to 15, further comprising a third semiconductor material (150) disposed over the substrate (101), and a dielectric layer (152) disposed on the third semiconductor material (150), wherein the second semiconductor material (154) is disposed on the dielectric layer (152).

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