Devices and methods for controlling the threshold voltage drift of a selection device

Abstract

A device is provided that includes a memory cell and control circuitry coupled to the memory cell. The memory cell includes a reversible resistive switching memory element coupled in series with a select element having a threshold voltage. The control circuitry is configured to use a first pulse having a first polarity for the first access to the memory cell and a second pulse having a second polarity opposite the first polarity for the second access to and reading of the memory cell, the second pulse being adjacent to the first pulse. The first pulse is configured to reduce the rate of threshold voltage drift of the select element.

Description

BACKGROUND

[0001] Memory is used in various electronic devices such as mobile phones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, non-mobile computing devices, and data servers. Memory can be non-volatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a power source (e.g., a battery).

[0002] An example of non-volatile memory is magnetoresistive random access memory (MRAM), which uses magnetization to represent stored data, unlike some other memory technologies that store data using electronic charge. Generally, MRAM involves a large number of magnetic memory cells formed on a semiconductor substrate, with each memory cell representing one bit of data.

[0003] A data bit is written to a memory cell by changing the direction of magnetization of a magnetic element within the memory cell, and a bit is read by measuring the resistance of the memory cell (a low resistance typically represents a "0" bit, and a high resistance typically represents a "1" bit). As used herein, the magnetization direction is the direction of alignment of the magnetic moment. Some memory cells may include a selection device, such as an Ovonic threshold switch or other selection device.

[0004] Although MRAM is a promising technology, numerous design and process challenges remain. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A to 1H illustrate various embodiments of a memory system. Fig. Figure 2A illustrates one embodiment of a portion of a three-dimensional memory array. Fig. Figure 2B illustrates an embodiment of a memory cell of the three-dimensional memory array of Fig. 2A. Fig. Figure 2C illustrates an exemplary current-voltage characteristic of a threshold selection device of Fig. 2B. Fig. 3A to 3B illustrate one embodiment of a crosspoint memory array. Fig. 4 illustrates an exemplary read and write sequence for determining a bit error rate of one or more memory cells in a memory array. Fig. Figure 5A illustrates two consecutive self-referenced reads separated by one bit access time. Fig. Figure 5B is a graph showing the average bit error rate versus bit access time. Fig. Figure 5C illustrates a graph with example threshold voltage versus delay values ​​for a population of memory cells. Fig. Figure 5D shows a graph with further example values ​​of the threshold voltage versus delay for a population of memory cells. Fig. Figure 6A illustrates two consecutive self-referenced read operations separated by a bit access time interval. Fig. Figure 6B illustrates two alternative consecutive self-referenced read operations separated by a bit access time interval. Fig. Figure 7 illustrates one embodiment of a read and write sequence of this technology. Fig. Figure 8 illustrates another embodiment of a read and write sequence of this technology. Fig. Figure 9 shows a graph with further exemplary values ​​of the threshold voltage as a function of the delay for a population of memory cells. Fig. Figure 10 illustrates an embodiment of a gate control signal superimposed over a pre-read pulse. Fig. Figure 11 illustrates yet another embodiment of a read and write sequence of this technology. Fig. 12 is a flowchart of one embodiment of a method for determining a bit error rate of a plurality of memory cells. Fig. 13 is a flowchart of another embodiment of a method for determining a bit error rate of a plurality of memory cells. Fig. 14 is a flowchart of yet another embodiment of a method for determining a bit error rate of a plurality of memory cells. DETAILED DESCRIPTION

[0005] A technology for controlling threshold voltage drift in memory cells including a storage element coupled in series with a select device is described. In some embodiments, the memory cells may include a threshold select device, such as an Ovonic threshold switch, having a threshold voltage that changes over time after access to the threshold select device. In some embodiments, the memory cells may include a threshold select device, such as an Ovonic threshold switch, having a threshold voltage that increases (e.g., ramps up) over time after access to the threshold select device.In some embodiments, the memory cells may include a threshold selection device, such as an Ovonic threshold switch, having a threshold voltage that increases after accessing the threshold selection device using pulses of opposite polarities. One effect of the threshold voltage drift and / or threshold voltage rise is that the memory state of the memory elements may be disturbed during read operations, resulting in a bit error rate that increases with increasing bit access time.

[0006] In one embodiment, the threshold voltage drift is controlled using a post-set pulse after each SET pulse applied to the memory cells. In one embodiment, the post-set pulse turns the selector ON and OFF and has a polarity opposite to the polarity of the SET pulse.

[0007] In another embodiment, a pre-read pulse is used to turn the selector ON and OFF shortly before each read access. In one embodiment, the pre-read pulse has the same polarity as the polarity of the read access.

[0008] In yet another embodiment, a polarity-switching bit access pulse is used to switch the selector ON and OFF shortly before each read access. In one embodiment, the polarity-switching bit access pulse has a polarity opposite to that of the read access.

[0009] In one embodiment, the memory cells include a memory element coupled in series with a select device. In one embodiment, the memory element is a magnetic memory element. In one embodiment, the memory element is a magnetic tunnel junction memory element. In one embodiment, the select device is an Ovonic threshold switch.

[0010] In one embodiment, memory cells within a memory array may include non-volatile memory cells that include a reversible resistive switching element. A reversible resistive switching element may include a reversible resistive switching material having a resistance that can be reversibly switched between two or more states.

[0011] In one embodiment, the reversible resistive switching material may include a metal oxide, solid electrolyte, phase-change material, magnetic material, or other similar resistive switching material. Various metal oxides may be used, such as transition metal oxides. Examples of metal oxides include, but are not limited to, NiO, Nb2O5, TiO2, HfO2, Al2O3, MgO x , CrO2, VO, BN, TaO2, Ta2O3 and AIN.

[0012] In one embodiment, non-volatile memory cells within a memory array include one-time programmable memory cells. In one embodiment, non-volatile memory cells within a memory array include rewritable memory cells.

[0013] Fig. 1A illustrates one embodiment of a storage system 100 and a host 102. The storage system 100 may include a non-volatile storage system connected to the host 102 (e.g., a mobile computing device or a server) via an interface. In some cases, the storage system 100 may be embedded within the host 102. As examples, the storage system 100 may be a memory card, a solid-state drive (SSD), such as a high-density MLC SSD (e.g., 2 bits / cell or 3 bits / cell), a high-performance SLC SSD, or a hybrid HDD / SSD drive.

[0014] As shown, the memory system 100 includes a memory chip controller 104 and a memory chip 106. A memory chip 106 may include volatile memory and / or non-volatile memory. Although a single memory chip is shown, the memory system 100 may include more than one memory chip. The memory chip controller 104 may receive data and commands from the host 102 and provide memory chip data to the host 102.

[0015] The memory chip controller 104 may include one or more of control circuitry, state machines, page registers, SRAM, decoders, sense amplifiers, read / write circuits, and / or control units, or any combination thereof, for controlling the operation of the memory chip 106. The one or more circuitry, state machines, page registers, SRAM, decoders, sense amplifiers, read / write circuits, and / or control units for controlling the operation of the memory chip may be referred to as management or control circuitry. The management or control circuitry may enable one or more memory array operations, including build, erase, program, or read operations.

[0016] In some embodiments, the management or control circuitry (or a portion of the management or control circuitry) for enabling one or more memory array operations may be integrated within the memory chip 106. The memory chip controller 104 and the memory chip 106 may be disposed on a single integrated circuit or disposed on a single chip. In other embodiments, the memory chip controller 104 and the memory chip 106 may be disposed on different integrated circuits. In some cases, the memory chip controller 104 and the memory chip 106 may be integrated on a system board, a logic board, or a printed circuit board (PCB).

[0017] The memory chip 106 includes memory core control circuitry 108 and a memory core 110. The memory core control circuitry 108 may include logic for controlling the selection of memory blocks (or arrays) within the memory core 110, controlling the generation of voltage references for biasing a particular memory array into a read or write state, and generating row and column addresses.

[0018] The memory core 110 may include one or more two-dimensional arrays of memory cells and / or one or more three-dimensional arrays of memory cells. In one embodiment, the memory core may include rewritable memory cells, one-time programmable memory cells, and / or multiple programmable memory cells, or any combination thereof.

[0019] In one embodiment, the memory core control circuits 108 and the memory core 110 may be arranged on a single integrated circuit. In other embodiments, the memory core control circuits 108 (or a portion of the memory core control circuits 108) and the memory core 110 may be arranged on different integrated circuits.

[0020] A store operation may be initiated when the host 102 sends instructions to the memory chip controller 104 indicating that the host 102 wishes to read data from the memory system 100 or write data to the memory system 100. In the case of a write operation (or program operation), the host 102 may send both a write command and the data to be written to the memory chip controller 104.

[0021] The memory chip controller 104 may buffer data to be written and may generate error correction code (ECC) data corresponding to the data to be written. The ECC data, which enables detection and / or correction of data errors occurring during transmission or storage, may be written to the memory core 110 or stored in non-volatile memory within the memory chip controller 104. In one embodiment, circuitry within the memory chip controller 104 generates the ECC data and corrects data errors.

[0022] The memory chip controller 104 may control the operation of the memory chip 106. In one example, before issuing a write operation to the memory chip 106, the memory chip controller 104 may check a status register to ensure that the memory chip 106 is capable of accepting the data to be written.

[0023] In another example, before issuing a read operation to memory chip 106, memory chip controller 104 may prefetch overhead information associated with the data to be read. The overhead information may include ECC data associated with the data to be read or a redirection pointer to a new memory location within memory chip 106 into which the requested data should be read.

[0024] When the memory chip controller 104 initiates a read or write operation, the memory core control circuits 108 may generate appropriate bias voltages and / or currents for word lines and bit lines within the memory core 110, as well as generate the appropriate memory block, row, and column addresses.

[0025] Fig. 1B illustrates one embodiment of memory core control circuitry 108. In one embodiment, memory core control circuitry 108 includes address decoders 120, voltage generators for selected control lines 122, and voltage generators for unselected control lines 124. Control lines may include word lines, bit lines, or a combination of word lines and bit lines. Selected control lines may include selected word lines or selected bit lines used to place memory cells in a selected state. Unselected control lines may include unselected word lines or unselected bit lines used to place memory cells in a unselected state.

[0026] The voltage generators (or voltage regulators) for the selected control lines 122 may include one or more voltage generators for generating selected control line voltages. The voltage generators for the unselected control lines 124 may include one or more voltage generators for generating unselected control line voltages. The address decoders 120 may generate memory block addresses, as well as row addresses and column addresses for a particular memory block.

[0027] Fig. 1C through 1F illustrate one embodiment of a memory core organization including a memory core 110 having multiple memory locations, each memory location having multiple memory blocks. Although a memory core organization is disclosed in which memory locations include memory blocks and memory blocks include a group of memory cells, other organizations or groupings may be used with the technology described herein.

[0028] Fig. Figure 1C illustrates an embodiment of the memory core 110 of Fig. 1A. As illustrated, memory core 110 includes a memory location 130 and a memory location 132. In some embodiments, the number of memory locations per memory core may vary for different implementations. For example, a memory core may include only a single memory location or multiple memory locations (e.g., 16 memory locations or 256 memory locations, etc.).

[0029] Fig. Figure 1D illustrates an embodiment of the memory location 130 of Fig. 1C. As illustrated, memory location 130 includes memory blocks 140-144 and read / write circuits 150. In some embodiments, the number of memory blocks per memory location may vary for different implementations. For example, a memory location may include one or more memory blocks (e.g., 32 memory blocks per memory location).

[0030] The read / write circuits 150 include circuitry for reading and writing memory cells within the memory blocks 140-144. As illustrated, the read / write circuits 150 may be shared across multiple memory blocks within a memory location. This allows for chip area to be reduced because a single group of read / write circuits 150 may be used to support multiple memory blocks. However, in some embodiments, only a single memory block may be electrically coupled to the read / write circuits 150 at a given time to avoid signal conflicts.

[0031] In some embodiments, read / write circuits 150 may be used to write one or more pages of data to memory blocks 140-144 (or to a subset of the memory blocks). The memory cells within memory blocks 140-144 may allow direct page overwriting (i.e., data representing a page or a portion of a page may be written to memory blocks 140-144 without requiring an erase or reset operation on the memory cells prior to writing the data).

[0032] In one example, the storage system 100 may be Fig. 1A, receive a write command that includes a destination address and a set of data to be written to the destination address. The memory system 100 may perform a read-before-write (RBW) operation to read the data currently stored at the destination address before performing a write operation to write the set of data to the destination address. The memory system 100 may then determine whether a particular memory cell can remain in its current state (i.e., the memory cell is already at the correct state), needs to be set to a "0" state, or needs to be reset to a "1" state.

[0033] The memory system 100 may then write a first subset of the memory cells to the "0" state and then write a second subset of the memory cells to the "1" state. Memory cells already in the correct state may be skipped, thereby improving programming speed and reducing the cumulative voltage stress applied to unselected memory cells.

[0034] A specific memory cell can be set to the "1" state by applying a first voltage difference across the specific memory cell of a first polarity (e.g., +1.5 V). The specific memory cell can be reset to the "0" state by applying a second voltage difference across the specific memory cell of a second polarity opposite to the first polarity (e.g., -1.5 V).

[0035] In some cases, the read / write circuits 150 may be used to program a particular memory cell to be in one of three or more data / resistance states (i.e., the particular memory cell may comprise a multi-level memory cell). In one example, the read / write circuits 150 may apply a first voltage difference (e.g., 2 V) across the particular memory cell to program the particular memory cell to a first state of the three or more data / resistance states, or apply a second voltage difference (e.g., 1 V) across the particular memory cell that is less than the first voltage difference to program the particular memory cell to a second state of the three or more data / resistance states.

[0036] Applying a smaller voltage difference across the particular memory cell may cause the particular memory cell to be partially programmed or programmed at a slower rate than when a larger voltage difference is applied. In another example, the read / write circuits 150 may apply a first voltage difference across the particular memory cell for a first time period (e.g., 150 ns) to program the particular memory cell in a first of the three or more data / resistance states, or apply the first voltage difference across the particular memory cell for a second time period less than the first time period (e.g., 50 ns). One or more programming pulses followed by a memory cell verify phase may be used to program the particular memory cell to be in the correct state.

[0037] Fig. Figure 1E illustrates an embodiment of the memory block 140 of Fig. 1D. As illustrated, memory block 140 includes a memory array 160, a row decoder 162, and a column decoder 164. Memory array 160 may include a contiguous group of memory cells with contiguous word lines and bit lines. Memory array 160 may include one or more layers of memory cells and may include a two-dimensional memory array and / or a three-dimensional memory array.

[0038] The row decoder 162 decodes a row address and selects a particular word line in the memory array 160 when appropriate (e.g., when reading or writing memory cells in the memory array 160). The column decoder 164 decodes a column address and selects a particular group of bit lines in the memory array 160 to electrically connect to read / write circuits such as the read / write circuits 150 of Fig. 1D. In one embodiment, the number of wordlines is 4K per memory layer, the number of bitlines is 1K per memory layer, and the number of memory layers is 4, providing a memory array 160 containing 16M memory cells. Other numbers of wordlines per layer, bitlines per layer, and number of layers may be used.

[0039] Fig. 1F illustrates one embodiment of a memory location 170. The memory location 170 is an example of an alternative implementation for the memory location 130 of Fig. 1 D. In some embodiments, row decoders, column decoders, and read / write circuits may be split or shared between memory arrays. As illustrated, a row decoder 172 is shared between memory arrays 174 and 176 because row decoder 172 controls word lines in both memory arrays 174 and 176 (i.e., the word lines controlled by row decoder 172 are shared).

[0040] Row decoders 178 and 172 may be partitioned so that even word lines in memory array 174 are driven by row decoder 178 and odd word lines in memory array 174 are driven by row decoder 172. Column decoders 180 and 182 may be partitioned so that even bit lines in memory array 174 are driven by column decoder 182 and odd word lines in memory array 174 are driven by column decoder 180.

[0041] The selected bit lines controlled by column decoder 180 may be electrically coupled to read / write circuits 184. The selected bit lines controlled by column decoder 182 may be electrically coupled to read / write circuits 186. Dividing the read / write circuits into read / write circuits 184 and 186 when splitting the column decoders may enable a more efficient layout of the memory space.

[0042] Row decoders 188 and 172 may be partitioned so that even word lines in memory array 176 are driven by row decoder 188 and odd word lines in memory array 176 are driven by row decoder 172. Column decoders 190 and 192 may be partitioned so that even bit lines in memory array 176 are driven by column decoder 192 and odd word lines in memory array 176 are driven by column decoder 190.

[0043] The selected bit lines controlled by column decoder 190 may be electrically coupled to read / write circuits 184. The selected bit lines controlled by column decoder 192 may be electrically coupled to read / write circuits 186. Dividing the read / write circuits into read / write circuits 184 and 186 when splitting the column decoders may enable a more efficient layout of the memory space.

[0044] Fig. Figure 1G illustrates one embodiment of a schematic diagram (including word lines and bit lines) corresponding to memory location 170 in Fig. 1F. As shown, word lines WL1, WL3 and WL5 are shared between memory arrays 174 and 176 and are decoded by row decoder 172 from Fig. 1F. Word lines WL0, WL2, WL4 and WL6 are driven from the left side of the memory array 174 and are decoded by the row decoder 178 from Fig. 1F. Word lines WL14, WL16, WL18 and WL20 are driven from the right side of the memory array 176 and are decoded by the row decoder 188 from Fig. 1F controlled.

[0045] Bit lines BL0, BL2, BL4 and BL6 are driven from the bottom of the memory array 174 and by the column decoder 182 from Fig. 1F. Bit lines BL1, BL3 and BL5 are driven from the top of the memory array 174 and are controlled by the column decoder 180 from Fig. 1F. Bit lines BL7, BL9, BL11 and BL13 are driven from the bottom of the memory array 176 and are controlled by the column decoder 192 from Fig. 1F. Bit lines BL8, BL10 and BL12 are driven from the top of the memory array 176 and are controlled by the column decoder 190 from Fig. 1F controlled.

[0046] In one embodiment, memory arrays 174 and 176 may include memory layers aligned in a plane that is horizontal to the support substrate. In another embodiment, memory arrays 174 and 176 may include memory layers aligned in a plane that is vertical with respect to the support substrate (i.e., the vertical plane is substantially perpendicular to the support substrate). In this case, the bitlines of the memory array may include substantially vertical bitlines.

[0047] Fig. Figure 1H illustrates one embodiment of a schematic diagram (including word lines and bit lines) corresponding to a memory location arrangement, where word lines and bit lines are shared across memory blocks and both row decoders and column decoders are shared. Sharing word lines and / or bit lines helps reduce layout area because a single row decoder and / or column decoder can be used to support two memory arrays.

[0048] As shown, word lines WL1, WL3, and WL5 are shared between memory arrays 200 and 202. Bit lines BL1, BL3, and BL5 are shared between memory arrays 200 and 204. Word lines WL8, WL10, and WL12 are shared between memory arrays 204 and 206. Bit lines BL8, BL10, and BL12 are shared between memory arrays 202 and 206.

[0049] Row decoders are divided such that word lines WL0, WL2, WL4, and WL6 are driven from the left side of memory array 200, and word lines WL1, WL3, and WL5 are driven from the right side of memory array 200. Similarly, word lines WL7, WL9, WL11, and WL13 are driven from the left side of memory array 204, and word lines WL8, WL10, and WL12 are driven from the right side of memory array 204.

[0050] Column decoders are split such that bit lines BL0, BL2, BL4, and BL6 are driven from the bottom of memory array 200, and bit lines BL1, BL3, and BL5 are driven from the top of memory array 200. Similarly, bit lines BL7, BL9, BL11, and BL13 are driven from the bottom of memory array 202, and bit lines BL8, BL10, and BL12 are driven from the top of memory array 202. Splitting the row and / or column decoders also helps relieve layout constraints (e.g., column decoder pitch can be reduced by 2x because the split column decoders only need to drive every other bit line instead of every bit line).

[0051] Fig. 2A illustrates one embodiment of a portion of a monolithic three-dimensional memory array 210 including a first memory plane 212 and a second memory plane 214 positioned above the first memory plane 212. The memory array 210 is an example of an implementation for the memory array 160 in Fig. 1E. Word lines 216 and 218 are arranged in a first direction, and bit lines 220 are arranged in a second direction perpendicular to the first direction. As illustrated, the upper conductors of the first memory level 212 can be used as the lower conductors of the second memory level 214. In a memory array with additional layers of memory cells, there would be corresponding additional layers of bit lines and word lines.

[0052] The memory array 210 includes a plurality of memory cells 222. In embodiments, the memory cells 222 may include rewritable memory cells, one-time programmable memory cells, and multiple-time programmable memory cells. In one embodiment, each of the memory cells 222 is vertically aligned. The memory cells 222 may include non-volatile memory cells and volatile memory cells. With respect to the first memory level 212, a first portion of the memory cells 222 are located between and connected to the word lines 216 and the bit lines 220. With respect to the second memory level 214, a second portion of the memory cells 222 are located between and connected to the word lines 218 and the bit lines 220.

[0053] In one embodiment, each memory cell 222 includes a select element coupled in series with a resistive switching memory element, where each memory cell 222 represents a bit of data. In one embodiment, the resistive switching memory element may be a magnetic memory element, a ReRAM memory element, a phase-change memory element, or another type of resistive switching memory element.

[0054] In one embodiment, each memory cell 222 includes a select element coupled in series with a magnetic storage element, where each memory cell 222 represents a bit of data. Fig. 2B is a simplified schematic diagram of a memory cell 222a illustrating an example implementation of the memory cells 222 of Fig. 2A is.

[0055] In one embodiment, the memory cell 222a includes a magnetic memory element M x , in series with a selection element Sx , both coupled between a first terminal T1 and a second terminal T2. In one embodiment, the memory cell 222a is vertically aligned. In the embodiment of Fig. 2B, the magnetic storage element M x above the selection element S x In other embodiments, the selection element S x above the magnetic storage element M x arranged.

[0056] In one embodiment, the magnetic storage element is a magnetic tunnel junction, and the selection element S x is a threshold selection device. In one embodiment, the selection element S x a conductive bridge threshold selection device. In other embodiments, the selection element S xan ovonic threshold switch (e.g., binary SiTe, CTe, BTe, AlTe, etc., or ternary type AsTeSi, AsTeGe, or AsTeGeSiN, etc.), a metal-insulator junction (MIT) of a phase-change material type (e.g., VO2, NbO2, etc.), or other similar threshold selection device.

[0057] In one embodiment, the magnetic memory element M x an upper ferromagnetic layer 230, a lower ferromagnetic layer 232, and a tunnel barrier (TB) 234, which is an insulating layer between the two ferromagnetic layers. In this example, the lower ferromagnetic layer 232 is a free layer (FL), which has a magnetization direction that can be switched. The upper ferromagnetic layer 230 is the pinned (or fixed) layer (PL), which has a magnetization direction that cannot be easily changed.

[0058] In other embodiments, the magnetic memory element M x fewer, additional or different layers than those in Fig. 2B. In other embodiments, the lower ferromagnetic layer 232 is a pinned layer (PL), and the upper ferromagnetic layer 230 is the free layer (FL).

[0059] If the direction of magnetization in the free layer 232 is parallel to that of the pinned layer 230, the memory element M x has a relatively low resistance (referred to herein as the “P-state”), and when the direction of magnetization in the free layer 232 is antiparallel to that of the pinned layer 230, the memory element M x a relatively high resistance (referred to herein as the “AP state”).

[0060] In one embodiment, the data state (“0” or “1”) of the magnetic storage element M xread by changing the resistance of the magnetic storage element M x is measured. By default, both the parallel and antiparallel configurations remain stable in idle state and / or during a read operation (with sufficiently lower read current).

[0061] In one embodiment, the selection element S x an Ovonic threshold switch including a first region 236 and optionally including a second region 238 disposed over the first region 236. In one embodiment, the first region 236 is a SiTe alloy and the optional second region 238 is carbon nitride. Other materials may be used for the first region 236 and the optional second region 238. In other embodiments, the selection element S xa conductive bridge threshold selection element. In one embodiment, the first region 236 is a solid electrolyte region and the second region 238 is an ion source region.

[0062] Fig. 2C is a diagram showing example current-voltage (IV) characteristics of a threshold selection device S x Each threshold selection device S x is initially in a high-impedance state (OFF). To activate the threshold selection device S x To operate as a threshold switch, an initial formation process may be required so that the threshold selection device S x operates in a current range where switching may occur.

[0063] For example, a formation process may involve applying one or more voltage pulses, each having a magnitude greater than or equal to a formation voltage V FORMis to the threshold selection device S x After the formation process, the threshold selection device S x can be switched ON and OFF and can be used as either a unipolar or a bipolar threshold selection device. Accordingly, the threshold selection device S x be referred to as a bipolar threshold selection device.

[0064] In the Example IV characteristics of Fig. 2C for positive applied voltages, the threshold selection device remains in a high resistance state (HRS) (e.g., OFF) until the voltage across the device reaches a first threshold voltage, V TP , satisfies or exceeds (ie, it is more positive than) where the threshold selection device S x to a low-resistance state (LRS) (e.g., ON). The threshold selection device S xremains ON until the voltage across the device reaches or falls below a first holding voltage, V HP , where the threshold selector 224 is turned OFF.

[0065] For negative applied voltages, the threshold selection device S x in an HRS (e.g., OFF) until the voltage across the device reaches a second threshold voltage, V TN , meets or exceeds (ie, is more negative than) this, where the threshold selector 304 switches to an LRS (e.g., ON). The threshold selector S x remains ON until the voltage across the device reaches a second holding voltage, V HN , increases or exceeds (ie is less negative than) this threshold, where the threshold selection device S x is switched OFF.

[0066] With further reference to Fig. 2B uses, in one embodiment, the magnetic memory element Mx a spin-transfer torque switching (STT switching). To change a bit value of the magnetic storage element M x To "set" (i.e., to select the direction of magnetization of the free layer), an electric write current is applied from the first terminal T1 to the second terminal T2. The electrons in the write current become spin-polarized as they pass through the pinned layer 230 because the pinned layer 230 is a ferromagnetic metal.

[0067] A substantial majority of the conduction electrons in a ferromagnet exhibit a spin orientation parallel to the magnetization direction, resulting in a net spin polarization current. (Electron spin refers to angular momentum directly proportional to, but antiparallel to, the electron's magnetic moment, but this directional distinction will be dropped in the future for ease of discussion.)

[0068] As spin-polarized electrons tunnel through TB ​​234, conservation of angular momentum may impart a torque to both the free layer 232 and the pinned layer 230, but this torque is (intentionally) insufficient to affect the magnetization direction of the pinned layer 230. In contrast, if the initial magnetization direction of the free layer 232 was antiparallel to the pinned layer 230, this torque is (intentionally) sufficient to switch the magnetization direction of the free layer 232 to become parallel to that of the pinned layer 230. The parallel magnetizations then remain stable before and after such a turning-off of the write current.

[0069] In contrast, if the magnetizations of the free layer 232 and the pinned layer 230 are initially parallel, the magnetization direction of the free layer 232 can be SST-switched to become antiparallel to that of the pinned layer 230 by applying a write current in the opposite direction to the above case. Thus, using the same STT physics, the magnetization direction of the free layer 232 can be deterministically set to one of two stable orientations by deliberately choosing the write current direction (polarity).

[0070] In the example described above, spin transfer torque switching (STT switching) is used to change a bit value of the magnetic storage element M x"to adjust." In other embodiments, field-induced switching, spin-orbit torque switching (SOT switching), (magnetoelectric) VCMA switching, or other switching techniques may be used.

[0071] Fig. 3A through 3B are simplified schematic diagrams of an example crosspoint memory array 300 including a first memory level 300a and a second memory level 300b positioned above the first memory level 300a. The crosspoint memory array 300 is an example implementation for the memory array 160 in Fig. 1E. The crosspoint storage array 300 may include more than two storage levels.

[0072] The crosspoint memory array 300 includes word lines WL1a, WL2a, WL3a, WL1b, WL2b, and WL3b and bit lines BL1, BL2, and BL3. The first memory plane 300a includes memory cells 302 11a , 302 12a , ..., 302 33awhich are coupled to word lines WL1a, WL2a, WL3a and bit lines BL1, BL2 and BL3, and the second memory level 300b includes memory cells 302 11b , 302 12b , ..., 302 33b coupled to word lines WL1b, WL2b, WL3b and bit lines BL1, BL2, and BL3. In one embodiment, each of the memory cells 302 11a , 302 12a , ..., 302 33a vertically aligned. In one embodiment, each of the memory cells 302 11b , 302 12b , ..., 302 33b vertically aligned.

[0073] The first memory level 300a is an example of an implementation for the first memory level 212 of the monolithic three-dimensional memory array 210 of Fig. 2B, and the memory level 300b is an example of an implementation for the second memory level 214 of the monolithic three-dimensional memory array 210 of Fig. 2B. In one embodiment, each of the memory cells 302 11a , 302 12a , ..., 302 33a , 302 11b , 302 12b , ..., 302 33b an implementation of the memory cell 222a of Fig. 2B.

[0074] One of ordinary skill in the art will understand that the crosspoint memory array 300 may have more or less than six word lines, more or less than three bit lines, and more or less than eighteen memory cells 302 11a , 302 12a , ... , 302 33a , 302 11b , 302 12b , ... , 302 33b In some embodiments, the crosspoint memory array 300 may include 1000 × 1000 memory cells, although other array sizes may be used.

[0075] Each memory cell 302 11a , 302 12a , ..., 302 33a , 302 11b , 302 12b , ..., 302 33bis coupled to one of the word lines and one of the bit lines and includes a corresponding magnetic storage element M 11a , M 12a , ... , M 33a , M 11b , M 12b , ..., or M 33b one, each in series with a corresponding selection element S 11a , S 12a , ..., S 33a , S 11b , S 12b , ..., or S 33b In one embodiment, each of the magnetic memory elements M 11a , M 12a , ..., M 33a , M 11b , M 12b , ..., M 33b is an implementation of the magnetic memory element M x from Fig. 2B, and each of the selection elements S 11a , S 12a , ..., S 33a , S 11b , S 12b , ..., S 33b is an implementation of the selection element S x from Fig. 2B.

[0076] Each memory cell 302 11a , 302 12a, ..., 302 33a has a first terminal coupled to one of the bit lines BL1, BL2, BL3, and a second terminal coupled to one of the word lines WL1a, WL2a, WL3a, and each memory cell 302 11b , 302 12b , ..., 302 33b has a first terminal coupled to one of the bit lines BL1, BL2, BL3, and a second terminal coupled to one of the word lines WL1b, WL2b, WL3b. For example, the memory cell 302 13a the magnetic storage element M 13a that is connected to the selection element S 13a coupled in series, and includes a first terminal coupled to the bit line BL3 and a second terminal coupled to the word line WL1a.

[0077] Likewise, the memory cell 302 closes 22b the magnetic storage element M 22p that is connected to the selection element S 22bcoupled in series, and includes a first terminal coupled to the bit line BL2 and a second terminal coupled to the word line WL2b. Similarly, the memory cell 302 33a the magnetic storage element M 33a that is connected to the selection element S 33a coupled in series, and includes a first terminal coupled to the bit line BL3 and a second terminal coupled to the word line WL3a.

[0078] The magnetic storage elements M 11a , M 12a , ..., M 33a can be placed above or below corresponding selection elements S 11a , S 12a , ..., or S 33a be arranged, and the magnetic storage elements M 11b , M 12b , ..., M 33b can be placed above or below corresponding selection elements S 11b , S 12b , ..., or S 33b be arranged.

[0079] In one embodiment, the alignment of the memory cells 302 11a , 302 12a , ..., 302 33a the first memory level 300a is equal to the orientation of the memory cell 302 11b , 302 12b , ..., 302 33b the second storage level 300b.

[0080] In another embodiment, the orientation of the memory cells 302 11a , 302 12a , ..., 302 33a the first memory plane 300a opposite to the orientation of the memory cell 302 11b , 302 12b , ..., 302 33b the second storage level 300b.

[0081] With further reference to Fig. 1A, in one embodiment, the memory core 110 may include one or more two-dimensional arrays of memory cells and / or one or more three-dimensional arrays of memory cells. In one embodiment, the memory core 110 may include rewritable memory cells, one-time programmable memory cells, and / or multiple programmable memory cells, or any combination thereof.

[0082] A measure of the performance of one or more memory cells is the bit error rate. In one embodiment, a bit error rate for one or more memory cells is determined by writing various data values ​​to the memory cells, reading the written data values ​​from the memory cells, determining the number of times the read value did not match the written value, and then dividing the number of read errors by the total number of read operations performed.

[0083] With reference to Fig. 4, an exemplary read and write sequence 400 is illustrated for determining a bit error rate for one or more memory cells in a memory array, such as one of the memory arrays 160, 174, 176, 200, 202, 204, 206, 210, or 300 described above. In particular, the read and write sequence 400 represents a voltage across a memory cell versus time for a memory cell including a select element coupled to a magnetic memory element, such as the memory cell 222a of Fig. 2B, coupled in series. For simplicity, the voltage across the memory cell is referred to as the “word line voltage” in the following description.

[0084] As described in more detail below, the Fig. In the example shown in Figure 4, a read operation is performed using a pulse with a first (e.g., positive) polarity, a reset operation is performed using a pulse with the first polarity, and a set operation is performed using a pulse with a second (e.g., negative) polarity opposite the first polarity. Those of ordinary skill in the art will understand that, alternatively, the first polarity may be negative and the second polarity may be positive.

[0085] In one embodiment, the memory cell includes an Ovonic threshold switch selection element S x which is provided with a magnetic storage element M x coupled in series. For the sake of simplicity, the term Ovonic threshold switch S will be used in the following description. xThose of ordinary skill in the art will understand that the principles described below apply to any type of selection element that has the same characteristics as an Ovonic threshold switch.

[0086] In one embodiment, each read in the read and write sequence 400 is a self-referenced read. In an exemplary self-referenced read technique, a memory cell is first read and then written to a first memory state, a second read is performed, and then the results of the first and second reads are compared. If the two read results are the same, it is determined that the memory cell was originally in the first memory state and remains in the first memory state. However, if the two read results do not match, it is determined that the memory cell was originally in a second memory state but is now in the first memory state.

[0087] Referring to Figures 4 and 2B, the symbol “P” indicates that the magnetization direction of the memory element M x of the memory cell is parallel to that of the pinned layer 230 (and the memory element M x has a relatively low resistance), the symbol “AP” indicates that the magnetization direction of the memory element M x of the memory cell is antiparallel to that of the pinned layer 230 (and the memory element M x has a relatively high resistance).

[0088] Before time t0, the word line voltage is the initial voltage V i (e.g., 0 volts). Between time t0 and time t5, a self-referenced read operation is performed. In particular, from time t0, the word line voltage begins to exceed the initial voltage V i to rise. The word line voltage is below the first threshold voltage V TP, and the Ovonic threshold switch S x is set to OFF.

[0089] At time t1, the word line voltage corresponds to the first threshold voltage V TP , and the Ovonic threshold switch S x switches ON. The voltage at the Ovonic threshold switch S x falls to a value referred to herein as “V offset “, and the remaining word line voltage drops across the memory element M x the memory cell.

[0090] Between time t1 and time t2, a first read operation RD1 is performed. During the first read operation, a current source generates a first current, and a current mirror coupled to the current source and the memory cell increases the voltage across the memory cell to conduct the first current through the memory cell. In one embodiment, the first current is about 15 µA and has a pulse width of about 25 ns to about 50 ns, although larger or smaller current values ​​and larger or smaller pulse widths may also be used. The voltage across the memory cell corresponds to the first current multiplied by the resistance of the memory element M x . In the Fig. In the example shown in Figure 4, the magnetization direction of the memory element M x P, and the word line voltage has a value V a on.

[0091] Between times t2 and t4, a RESET pulse is applied to the memory cell to reset the memory element M x to write to a first memory state (AP). During a RESET operation, a current source generates a second current, and a current mirror coupled to the current source and the memory cell increases the voltage across the memory cell to conduct the second current through the memory cell. The second current is greater than the first current. In one embodiment, the RESET operation puts the memory element M x always into the first memory state AP and is referred to in this context as “erasing read”.

[0092] The voltage across the memory cell corresponds to the second current multiplied by the resistance of the memory element M x In particular, the memory element M x between times t2 and t3 in state P, and the word line voltage has a value V cFrom time t3, the storage element M x into the (higher-resistance) state AP, and between times t3 and t4 the word line voltage has a value V TP on.

[0093] At time t4 the RESET pulse ends, the memory element M x is in the AP state and the word line voltage drops to a voltage V b Between time t4 and time t5, a second read operation RD2 is performed. During the second read operation, a current source generates the first current, and a current mirror coupled to the current source and the memory cell increases the voltage across the memory cell to conduct the first current through the memory cell. In one embodiment, the first current is about 15 µA and has a pulse width of about 25 ns to about 50 ns, although larger or smaller current values ​​and larger or smaller pulse widths may also be used.

[0094] The voltage across the memory cell corresponds to the first current multiplied by the resistance of the memory element M x . In the Fig. In the example shown in Figure 4, the magnetization direction of the memory element M x AP, and the word line voltage has a value V b At time t5, the second read operation ends, the word line voltage returns to the initial voltage V i (e.g. 0 volts) and the Ovonic threshold switch switches OFF.

[0095] The results of the first read RD1 and the second read RD2 are compared. If the two read results match, it is determined that the memory element M x was originally in the first memory state AP, and it remains in the first memory state AP. However, if the two read results do not match, it is determined that the memory element M xwas originally in a second memory state (P), but it is now in the first memory state AP.

[0096] In the example of Fig. 4, the word line voltage during the first reading RD1 and the second reading RD2 is not the same, and therefore it is determined that the memory element M x was originally in a second memory state P. Therefore, in one embodiment, a second pulse (a SET pulse between times t6 and t7) would typically be used to reset the memory element M x to the second memory state P. In Fig. 4, a SET pulse between times t6 and t7 is shown as a dashed line to indicate that the SET pulse may or may not be used depending on the operation performed by the read sequence 400.

[0097] During a SET operation, a current source generates a third current, and a current mirror coupled to the current source and the memory cell increases the voltage across the memory cell to conduct the third current through the memory cell. The third current has a polarity opposite to that of the first current and the second current.

[0098] The third current is large enough to turn the Ovonic threshold switch ON. The voltage across the memory cell is equal to the third current multiplied by the resistance of the memory element M x , and in particular, if a SET pulse is used between times t6 and t7, the memory element M x in the AP state, and the word line voltage has a value V s In one embodiment, during a SET operation, the Ovonic threshold switch is switched ON before the memory element M x is described.

[0099] The exemplary read and write sequence 400 of Fig. 4 can be used to determine a bit error rate for the memory cell. In particular, a first self-referenced read operation can be performed between times t0 and t7, a second self-referenced read operation between times t8 and t9, a third self-referenced read operation between times t 10 and t 11 , a fourth self-referenced read operation between times t 12 and t 13 etc.

[0100] In one embodiment, no alternating SET pulses are applied, so that the memory element M x repeatedly switches between the first memory state AP (“1”) and the second memory state P (“0”). Since the RESET process resets the memory element M xAlways set to the first memory state AP, the values ​​to be read from the memory cells are known. The bit error rate is determined by comparing the read values ​​with the expected values ​​and then determining the number of errors.

[0101] A phenomenon that can be observed using the exemplary read and write sequence 400 of Fig. 4 is that the bit error rate increases as the time between successive bit access operations increases. Fig. Figure 5A illustrates two consecutive self-referenced read operations characterized by a bit access time Δ t are separated, and Fig. Figure 5B is a graph showing an example bit error rate versus bit access time. As the graph shows, the average bit error rate increases with increasing bit access time.

[0102] Without wishing to be bound to any particular theory, it is suspected that the threshold voltage drift of the Ovonic threshold switch of the memory cell is a cause of the phenomenon of the increase in the bit error rate with increasing bit access time. In particular, for some selection elements S x , such as Ovonic threshold switches, a phenomenon called threshold voltage drift occurs. That is, when an Ovonic threshold switch is turned ON by applying a voltage to the switch that exceeds the threshold voltage (e.g., the first threshold voltage V TP from Fig. 2C), the threshold voltage of the Ovonic threshold switch begins to increase over time.

[0103] Fig. For example, Figure 5C shows a diagram of exemplary values ​​of the threshold voltage V TH depending on the delay for a population of memory cells, such as memory cell 222a of Fig. 2B, where the selection element S x is an Ovonic threshold switch. In this example, the Ovonic threshold switch has an initial threshold voltage V TH of about 2.3 V. After a delay of about 1 ms, the threshold voltage V TH a value of about 2.5 V. After about 100 s, the threshold voltage V TH a value of about 2.8 V. In this example diagram, the threshold voltage of the Ovonic threshold switch increases by about 60 mV / decade. In the Fig. In the example shown in Figure 5C, the values ​​of the threshold voltage V TH linearly depending on the delay. Those of ordinary skill in the art understand that the values ​​of the threshold voltage V TH can alternatively be nonlinear depending on the delay.

[0104] A consequence of threshold voltage drift is that as the delay time increases, the voltage required to turn the Ovonic threshold switch ON also increases. As described above, when the Ovonic threshold switch turns ON (when the wordline voltage is equal to the threshold voltage V TH corresponds) the voltage a to the Ovonic threshold switch S x to a value V offset and the remaining word line voltage drops across the memory element M x the memory cell.

[0105] This remaining voltage is referred to herein as “snapback voltage” as follows: Snapback voltage = (VTH − Voffset) The value of V offset does not seem to be affected by the delay, which means that as the bit access time increases, the snapback voltage increases with the increasing threshold voltage V TH increases.

[0106] Without wishing to be bound to a particular theory, it is assumed that the increase in the snapback voltage with increasing bit access time affects the bit access time stored in the memory element M x the data value stored in the memory cell. If the snapback voltage becomes sufficiently large, the memory element M x consequently change its state (e.g., from the P state to the AP state). Without wishing to be bound by any particular theory, it is suspected that the increase in the snapback voltage with increasing bit access time is one cause of the phenomenon of the increase in the bit error rate with increasing bit access time.

[0107] Fig. Figure 5D shows a diagram of further exemplary values ​​of the threshold voltage V TH depending on the delay for a population of memory cells, such as memory cell 222a of Fig. 2B, where the selection element S xis an Ovonic threshold switch. In this example, the Ovonic threshold switch has an initial threshold voltage V TH of about 2.4 V. After a delay of about 100 ms, the threshold voltage V TH a value of about 2.5 V. After about 100 s, the threshold voltage V TH a value of about 2.7 V. In this example diagram, the threshold voltage of the Ovonic threshold switch increases by about 45 mV / decade. In the Fig. In the example shown in Figure 5D, the values ​​of the threshold voltage V TH linearly depending on the delay. Those of ordinary skill in the art understand that the values ​​of the threshold voltage V TH can alternatively be nonlinear depending on the delay.

[0108] As described above and in the example of Fig. 4, each read operation is performed using pulses with a first (e.g., positive) polarity, and each set operation is performed using a pulse with a second (e.g., negative) polarity opposite to the first polarity.

[0109] As used herein, a pulse used to turn an Ovonic threshold switch ON is referred to as an "access pulse." Thus, each read operation is performed after using an access pulse having the first (e.g., positive) polarity (a "positive access pulse"), and each set operation is performed after using an access pulse having the second (e.g., negative) polarity (a "negative access pulse").

[0110] Without wishing to be bound by any particular theory, it is hypothesized that a relationship between the polarity of successive access pulses affects the rate of threshold voltage drift with increasing bit access time.

[0111] Without wishing to be bound by any particular theory, it is conjectured that the rate of threshold voltage drift with increasing bit access time of an Ovonic threshold switch depends on whether successive access pulses have the same or opposite polarity.

[0112] Without wishing to be bound by any particular theory, it is conjectured that when successive access pulses having the same polarity are used to turn an Ovonic threshold switch ON, the rate of threshold voltage drift with increasing bit access time is less than the rate of threshold voltage drift with increasing bit access time when successive access pulses having opposite polarities are used to turn an Ovonic threshold switch ON.

[0113] Fig. 6A and Fig. 6B, for example, each represents two consecutive self-referenced read operations separated by a bit access time interval Δ t are separated.

[0114] In Fig. 6A, no SET pulse is used after the first self-referenced read. Thus, during the first self-referenced read, the Ovonic threshold switch is turned ON with a positive access pulse, and during the second self-referenced read, the Ovonic threshold switch is subsequently turned ON with another positive access pulse. Thus, the Ovonic threshold switch is turned ON with two consecutive access pulses of the same polarity.

[0115] In contrast, in Fig. 6B, a SET pulse is used after the first self-referenced read. The SET pulse has a negative polarity, which activates the Ovonic threshold switch S x switches to ON and also changes the magnetization direction of the memory element M xfrom AP to P. During the second self-referenced read, the Ovonic threshold switch is turned ON with a positive access pulse. Thus, the Ovonic threshold switch is turned ON with two consecutive access pulses of different polarity.

[0116] Empirical data has shown that the rate of threshold voltage drift with increasing bit access time varies depending on the polarity relationship of consecutive access pulses used to turn an Ovonic threshold switch ON. Without wishing to be bound by any particular theory, it is conjectured that when an Ovonic threshold switch is turned ON with two consecutive access pulses of the same polarity, the rate of threshold voltage drift with increasing bit access time is lower than when the Ovonic threshold switch is turned ON with two consecutive access pulses of different polarity.

[0117] For example, an Ovonic threshold switch that is turned ON with two consecutive access pulses of the same polarity (e.g. as in Fig. 6A), have a first rate of threshold voltage drift with increasing bit access time (e.g., 45 mv / dec, as shown in Fig. 5D).

[0118] In contrast, an Ovonic threshold switch that is switched ON with two consecutive access pulses of different polarity (e.g. as in Fig. 6B), have a second rate of threshold voltage drift with increasing bit access time (e.g., 60 mv / dec, as in Fig. 5C). In one embodiment, the first rate of threshold voltage drift is less than the second rate of threshold voltage drift.

[0119] Empirical data has also shown that the magnitude of the threshold voltage varies depending on the polarity relationship of consecutive access pulses used to turn an Ovonic threshold switch ON. Without wishing to be bound by any particular theory, it is conjectured that when an Ovonic threshold switch is turned ON with two consecutive access pulses of the same polarity, the magnitude of the threshold voltage remains essentially constant, whereas when the Ovonic threshold switch is turned ON with two consecutive access pulses of different polarity, the magnitude of the threshold voltage may increase, which in turn may increase the snapback voltage.

[0120] A technology is described for controlling the effect of threshold voltage drift of an Ovonic threshold switch selection element. In particular, a technology is described for controlling the effect of threshold voltage drift of an Ovonic threshold switch selection element on the bit error rate of memory cells incorporating such Ovonic threshold switches. Without wishing to be bound by any particular theory, it is conjectured that this technology can be used to reduce the effect of threshold voltage drift of an Ovonic threshold switch selection element on the bit error rate of memory cells incorporating such Ovonic threshold switches.

[0121] Fig. 7 illustrates one embodiment of the technology for controlling the impact of threshold voltage drift of an Ovonic threshold switch selection element. In particular, the read and write sequence 700 illustrates a voltage across a memory cell versus time for a memory cell including a selection element coupled to a magnetic memory element, such as the memory cell 222a of Fig. 2B, coupled in series. In one embodiment, the selection element is an Ovonic threshold switch.

[0122] In the embodiment of Fig. 7, a self-referenced read operation is performed and a SET pulse is used if the read results indicate that the magnetic storage element was originally in the P state prior to the RESET operation. In one embodiment, a reset pulse 702 with the same polarity (e.g., positive) as the read operations is performed after each SET pulse.

[0123] In one embodiment, a current source generates a fourth current, and a current mirror coupled to the current source and the memory cell increases the voltage across the memory cell to conduct the fourth current through the memory cell to generate the resetting pulse 702.

[0124] In one embodiment, the reset pulse 702 should be short enough not to significantly impact latency, but long enough to turn the Ovonic threshold switch ON. In one embodiment, the reset pulse 702 should not disturb the state of the magnetic storage element.

[0125] In one embodiment, the follow-up pulse 702 is generated by a fourth current ranging from about 5 µA to about 20 µA, although larger or smaller current values ​​may be used. Alternatively, the follow-up pulse 702 may have a maximum voltage of about 3 V to about 4 V, although larger or smaller maximum voltage values ​​may be used.

[0126] In one embodiment, the follow-up pulse 702 has a pulse width PW psp In one embodiment, the pulse width PW psp from about 5 ns to about 40 ns, although larger or smaller pulse widths can also be used.

[0127] In one embodiment, the follow-up pulse 702 is applied at a time T psp after each SET pulse. In one embodiment, the time T psp as short as possible. In one embodiment, the time T psp shorter than about 1 µs. In one embodiment, the time Tpsp shorter than about 100 ns. In one embodiment, the time T psp about zero seconds.

[0128] In the Fig. 7, a single post-set pulse 702 is used after each SET pulse. In other embodiments, more than one post-set pulse 702 may be used. In one embodiment, a post-set pulse is used only after a SET pulse. As shown in Fig. For example, as shown in Figure 7, the second self-referenced read is not followed by a SET pulse, which means that no follow-up pulse is used after the second self-referenced read.

[0129] Without wishing to be bound by any particular theory, it is conjectured that using post-settlement pulses, such as post-settlement pulse 702, after each SET pulse may result in a lower rate of threshold voltage drift with increasing bit access time, compared to the rate of threshold voltage drift with increasing bit access time that would occur without the post-settlement pulses. Without wishing to be bound by any particular theory, it is conjectured that using post-settlement pulses, such as post-settlement pulse 702, after each SET pulse may reduce a rate of threshold voltage drift with increasing bit access time.

[0130] Without wishing to be bound by any particular theory, it is conjectured that the use of post-set pulses, such as post-set pulse 702, after each SET pulse may result in a rate of threshold voltage drift with increasing bit access time being lower than would otherwise be the case if post-set pulses were not used.

[0131] Without wishing to be bound by any particular theory, it is conjectured that using post-set pulses, such as post-set pulse 702, after each SET pulse may reduce the threshold voltage magnitude compared to what the threshold voltage would be if post-set pulses were not used.

[0132] Without wishing to be bound by any particular theory, it is conjectured that using reset pulses, such as reset pulse 702, after each SET pulse may reduce the effect of the threshold voltage drift of an Ovonic threshold switch selection element on the bit error rate of memory cells incorporating such Ovonic threshold switches.

[0133] Using post-settlement pulses, such as post-settlement pulse 702, does not eliminate threshold voltage drift with increasing bit access time. As a result, the threshold voltage increases over time. However, by reducing the rate of threshold voltage drift with increasing bit access time, the technique can reduce the amount of threshold voltage drift that occurs.

[0134] Fig. Figure 8 illustrates another embodiment of the technology for controlling the impact of threshold voltage drift of an Ovonic threshold switch selection element. In particular, the read and write sequence 800 illustrates a voltage across a memory cell versus time for a memory cell including a selection element coupled to a magnetic memory element, such as the memory cell 222a of Fig. 2B, coupled in series. In one embodiment, the selection element is an Ovonic threshold switch.

[0135] In the embodiment of Fig. 8, a self-referenced read operation is performed, and a SET pulse may or may not be used after the read operation. In one embodiment, a pre-read pulse 802 with the same polarity (e.g., positive) as that of the read operations is performed before each self-referenced read operation.

[0136] In one embodiment, a current source generates a fifth current, and a current mirror coupled to the current source and the memory cell increases the voltage across the memory cell to conduct the fifth current through the memory cell to generate pre-read pulse 802.

[0137] In one embodiment, the prefetch pulse 802 should be short enough not to significantly impact latency, but long enough to turn the Ovonic threshold switch ON. In one embodiment, the prefetch pulse 802 should not disturb the state of the magnetic storage element.

[0138] In one embodiment, pre-read pulse 802 is generated by a fifth current ranging from about 5 µA to about 20 µA, although larger or smaller current values ​​may be used. Alternatively, pre-read pulse 802 may have a maximum voltage of about 3 V to about 4 V, although larger or smaller maximum voltage values ​​may be used.

[0139] In one embodiment, the pre-read pulse 802 has a pulse width PW prp In one embodiment, the pulse width PW prp about 5 ns to about 40 ns, although larger or smaller pulse widths can also be used.

[0140] In one embodiment, the prefetch pulse 802 is generated at a time T prp before each self-referenced read. In one embodiment, the time T prp as short as possible. In one embodiment, the time T rapshorter than about 1 µs. In one embodiment, the time T prp shorter than about 100 ns. In one embodiment, the time T prp about zero seconds.

[0141] In the Fig. 8, a single pre-read pulse 802 is used before each self-referenced read. In other embodiments, more than one pre-read pulse 802 may be used. In one embodiment, a pre-read pulse 802 is used regardless of whether the self-referenced read was preceded by a SET pulse. As shown in Fig. For example, as shown in Figure 8, the second self-referenced read is not followed by a SET pulse, but a pre-read pulse 802 is used before the second self-referenced read.

[0142] Without wishing to be bound by any particular theory, it is believed that using pre-read pulses, such as pre-read pulse 802, before each self-referenced read operation can significantly reduce or eliminate the threshold voltage drift that occurred before pre-read pulse 802.

[0143] Fig. For example, Figure 9 shows a diagram of exemplary values ​​of the threshold voltage V TH depending on the delay for a population of memory cells, such as memory cell 222a of Fig. 2B, where the selection element S x an Ovonic threshold switch. In this diagram, it is assumed that a delay of 100 seconds has elapsed immediately before the pre-read pulse 802 and that the threshold voltage V TH = 2.8 volts. When the pre-read pulse 802 turns the Ovonic threshold switch ON, the threshold voltage V THessentially reset to the value at which essentially no delay occurs (e.g. V TH = 2.3 volts).

[0144] Without wishing to be bound by any particular theory, it is conjectured that using pre-read pulses, such as pre-read pulse 802, before each self-referenced read operation may reduce the effect of the threshold voltage drift of an Ovonic threshold switch selection element on the bit error rate of memory cells incorporating such Ovonic threshold switches.

[0145] In particular, without wishing to be bound by any particular theory, it is conjectured that read-ahead pulses, such as the exemplary read-ahead pulse 802, may "absorb" the snapback voltage. Without wishing to be bound by any particular theory, it is conjectured that when the amplitude of the read-ahead pulse 802 exceeds the threshold voltage V THof the Ovonic threshold switch is reached, the switch turns ON and the snapback voltage begins to discharge.

[0146] Without wishing to be bound to a specific theory, it is assumed that a sufficiently short pulse width PW prp of the pre-read pulse 802, the Ovonic threshold switch turns OFF and the snapback voltage discharges (e.g., to GROUND). Without wishing to be bound by any particular theory in this regard, it is suspected that pre-read pulses, such as the exemplary pre-read pulse 802, "absorb" the snapback voltage and cause a disturbance of the memory element M x can prevent.

[0147] As described above, in one embodiment, a current source generates a fifth current, and a current mirror coupled to the current source and the memory cell increases the voltage across the memory cell to conduct the fifth current through the memory cell to generate pre-read pulse 802.

[0148] In one embodiment, each memory cell is coupled to a wordline, which in turn is coupled to various circuitry, such as drivers, decoders, and other circuitry, collectively referred to herein as "external circuitry." External circuitry has the disadvantage of imposing a capacitive load on the wordline.

[0149] In one embodiment, a transistor having a control gate is coupled between the word line and the external circuitry, and a gate control signal having a voltage (VG CON) and is coupled to the control gate, can be used to selectively connect and disconnect external circuitry to the word line. If VG CON for example, has a first value (LOW), the transistor turns ON and connects the external circuitry to the word line, and when VG CON has a second value (HIGH), the transistor turns OFF and essentially disconnects the external circuitry from the wordline.

[0150] In one embodiment, the gate control signal VG CON be used to further enhance the effect of the pre-read pulse 802. Fig. For example, Figure 10 shows an embodiment of a control signal VG CON , which is superimposed on a pre-read pulse 802. In the illustrated embodiment, the control signal VG CONshortly before the pre-read pulse 802 goes HIGH (essentially disconnecting the external circuitry from the word line) and goes LOW (connecting the external circuitry to the word line).

[0151] Without wishing to be bound to a particular theory, it is assumed that by using the gate control signal VG CON in this way, the capacitive load of the word line can be reduced while the pre-read pulse 802 is applied to the word line, and the time required to discharge the snapback voltage (e.g., to GROUND) can be shortened.

[0152] Those of ordinary skill in the art understand that the gate control signal VG CON can have values ​​other than LOW and HIGH. VG CONFor example, it can have values ​​that result in the transistor being neither fully ON nor fully OFF. Without wishing to be bound to a particular theory, it is assumed that such gate control signal values ​​VG CON can also reduce the capacitive load of the word line while the pre-read pulse 802 is applied to the word line, and the time required to discharge the snapback voltage (e.g., to GROUND) can be shortened.

[0153] Without wishing to be bound to a particular theory, it is also assumed that the gate control signal VG CON can also be used as described above, while the follow-up pulse (e.g. the follow-up pulse 702 of Fig. 7) is applied to the word line and can reduce the time required to discharge the snapback voltage (e.g., to GROUND).

[0154] As described above, the prefetch pulse 802 is generated at a time T prpbefore each self-referenced read. In one embodiment, the time T prp as short as possible, and ideally the time T prp zero. However, if the time T prp = 0, the Ovonic threshold switch may not fully turn OFF and the snapback voltage may not be fully discharged. As a result, a residual portion of the snapback voltage may damage the storage element M x disturb.

[0155] Fig. 11 illustrates yet another embodiment of a technology for controlling the impact of threshold voltage drift of an Ovonic threshold switch selection element. In particular, the read and write sequence 1100 illustrates a voltage across a memory cell versus time for a memory cell including a selection element coupled to a magnetic memory element, such as the memory cell 222a of Fig. 2B, coupled in series. In one embodiment, the selection element is an Ovonic threshold switch.

[0156] In the embodiment of Fig. 11, a self-referenced read operation is performed, and a SET pulse may or may not be used after the read operation. In one embodiment, a pre-read pulse 1102 with an opposite polarity (e.g., negative) to that of the read operations is performed before each self-referenced read operation.

[0157] In one embodiment, a current source generates a sixth current, and a current mirror coupled to the current source and the memory cell increases the magnitude of the voltage across the memory cell to conduct the sixth current through the memory cell to generate pre-read pulse 1102.

[0158] In one embodiment, the pre-read pulse 1102 should be short enough not to significantly impact latency, but long enough to turn the Ovonic threshold switch ON. In one embodiment, the pre-read pulse 1102 should not disturb the state of the magnetic storage element.

[0159] In one embodiment, pre-read pulse 1102 is generated by a sixth current ranging from about 5 µA to about 20 µA, although larger or smaller current values ​​may be used. Alternatively, pre-read pulse 1102 may have a maximum voltage magnitude of about 3 V to about 4 V, although larger or smaller maximum voltage values ​​may be used.

[0160] In one embodiment, the pre-read pulse 1102 has a pulse width PW prnp In one embodiment, the pulse width PW prnpfrom about 5 ns to about 15 ns, although larger or smaller pulse widths can also be used.

[0161] In one embodiment, the prefetch pulse 1102 is generated at a time T prnp before each self-referenced read. In one embodiment, the time T prnp as short as possible. In one embodiment, the time T prnp = 0.

[0162] In the Fig. 11, a single pre-read pulse 1102 is used before each self-referenced read. In other embodiments, more than one pre-read pulse 1102 may be used. In one embodiment, a pre-read pulse 1102 is used regardless of whether the self-referenced read was preceded by a SET pulse. As shown in Fig. For example, as shown in Figure 11, the second self-referenced read is not followed by a SET pulse, but a pre-read pulse 1102 is used before the second self-referenced read.

[0163] Without wishing to be bound by any particular theory, it is believed that using pre-read pulses, such as pre-read pulse 1102, before each self-referenced read operation can significantly reduce or eliminate the threshold voltage drift that occurred before pre-read pulse 1102.

[0164] Without wishing to be bound by any particular theory, it is conjectured that using pre-read pulses, such as pre-read pulse 1102, before each self-referenced read operation may reduce the effect of the threshold voltage drift of an Ovonic threshold switch selection element on the bit error rate of memory cells incorporating such Ovonic threshold switches.

[0165] In particular, without wishing to be bound by any particular theory, it is conjectured that read-ahead pulses, such as the exemplary read-ahead pulse 1102, may "absorb" the snapback voltage. Without wishing to be bound by any particular theory, it is conjectured that when the amplitude of the read-ahead pulse 1102 exceeds the threshold voltage V TH of the Ovonic threshold switch is reached, the switch turns ON and the snapback voltage begins to discharge.

[0166] Without wishing to be bound to a specific theory, it is assumed that a sufficiently short pulse width PW prnpof the pre-read pulse 1102, the Ovonic threshold switch turns OFF and the snapback voltage discharges (e.g., to ground). Without wishing to be bound to any particular theory in this regard, it is suspected that pre-read pulses, such as the exemplary pre-read pulse 1102, "absorb" the snapback voltage and cause a disturbance of the memory element M x can prevent.

[0167] Without wishing to be bound to a specific theory, it is further assumed that, in contrast to the pre-reading pulse 802 of Fig. 8 the pre-read pulse 1102 can be generated such that the pre-read pulse 1102 is directly connected to the beginning of the self-referenced reading (ie to the time T prnp= 0). In particular, without wishing to be bound by any particular theory, it is conjectured that by using a negative polarity pre-read pulse 1102 and a positive polarity access pulse for the self-referenced read, the Ovonic threshold switch must turn OFF after the pre-read pulse 1102 before it can turn ON again at the start of the self-referenced read. Therefore, without wishing to be bound by any particular theory, it is conjectured that the snapback voltage can be fully discharged even if the pre-read pulse 1102 directly adjoins the start of the self-referenced read.

[0168] With reference to Fig. 12, an embodiment of a method 1200 for determining a bit error rate of a plurality of memory cells, each having an Ovonic threshold switch coupled in series with a magnetic storage element, will now be described.

[0169] In step 1202, performing a sequence of self-referenced reads of each of the memory cells, each self-referenced read including a RESET pulse having a first polarity.

[0170] In step 1204, after every second self-referenced read operation, apply a SET pulse including a second polarity and a reset pulse having the first polarity to the memory cells. In one embodiment, the reset pulses are configured to reduce the bit error rate of the plurality of memory cells.

[0171] With reference to Fig. 13, an embodiment of a method 1300 for determining a bit error rate of a plurality of memory cells, each having an Ovonic threshold switch coupled in series with a magnetic storage element, will now be described.

[0172] In step 1302, performing a sequence of self-referenced read operations of each of the memory cells, each self-referenced read operation including a RESET pulse having a first polarity.

[0173] In step 1304, prior to each self-referenced read operation, applying a pulse having the first polarity to the memory cells to turn the Ovonic threshold switch ON without disturbing the data state of the corresponding magnetic storage element. The pre-read pulses are configured to reduce the bit error rate of the plurality of memory cells.

[0174] With reference to Fig. 14, an embodiment of a method 1400 for determining a bit error rate of a plurality of memory cells, each having an Ovonic threshold switch coupled in series with a magnetic storage element, will now be described.

[0175] In step 1402, performing a sequence of self-referenced reads of each of the memory cells, each self-referenced read comprising a RESET pulse having a first polarity.

[0176] In step 1404, prior to each self-referenced read operation, applying a pulse having a second polarity opposite to the first polarity to the memory cells to turn the Ovonic threshold switch ON without disturbing a data state of the corresponding magnetic storage element. The pre-read pulses are configured to reduce the bit error rate of the plurality of memory cells.

[0177] The technology described above has been described with respect to self-referenced reading. Those of ordinary skill in the art will understand that the described technology can also be used with other reading techniques, such as non-destructive reading techniques (sometimes referred to as "speed reading techniques").

[0178] One embodiment of the disclosed technology includes a device including a memory cell and a control circuit coupled to the memory cell. The memory cell includes a reversible resistive switching memory element coupled in series with a selection element having a threshold voltage. The control circuit is configured to use a first pulse having a first polarity for the first access to the memory cell, a second pulse having a second polarity opposite the first polarity for the second access to the memory cell, and a third pulse having the first polarity for the third access to the memory cell. The third pulse is configured to reduce a rate of threshold voltage drift of the selection element.

[0179] One embodiment of the disclosed technology includes a device including a crosspoint memory array and control circuitry coupled to the crosspoint memory array. The crosspoint memory array includes a plurality of memory cells, each memory cell including a magnetic tunnel junction memory element coupled in series with a select element. The control circuitry is configured to perform a self-referenced read operation for each of the plurality of memory cells and, for each memory cell that has changed from a first magnetization direction to a second magnetization direction as a result of the self-referenced read operation, apply a SET pulse to change the magnetization direction from the second magnetization direction to the first magnetization direction and apply a reset pulse including a polarity opposite to the polarity of the SET pulse.

[0180] One embodiment of the disclosed technology includes a method including determining a bit error rate of a plurality of memory cells, each including an Ovonic threshold switch connected in series with a magnetic storage element, by: performing a sequence of self-referenced reads of each of the memory cells, each self-referenced read including a RESET pulse having a first polarity, and applying a SET pulse including a second polarity and a reset pulse having the first polarity to the memory cells after every second self-referenced read. The reset pulses are configured to reduce the bit error rate of the plurality of memory cells.

[0181] One embodiment of the disclosed technology includes a device including a memory cell and a control circuit coupled to the memory cell. The memory cell includes a reversible resistive switching memory element coupled in series with a selection element having a threshold voltage. The control circuit is configured to use a first pulse having a first polarity for the first access to the memory cell and a second pulse having the first polarity for the second access to the memory cell and reading of the memory cell. The first pulse is configured to reduce the rate of threshold voltage drift of the selection element.

[0182] One embodiment of the disclosed technology includes a device including a crosspoint memory array and a control circuit coupled to the crosspoint memory array. The crosspoint memory array includes a plurality of memory cells, each memory cell including a magnetic tunnel junction memory element coupled in series with a select element. The control circuit is configured to perform a self-referenced read operation for each of the plurality of memory cells and, prior to each self-referenced read operation, apply a pre-read pulse to reset a threshold voltage of the corresponding select element.

[0183] One embodiment of the disclosed technology includes a method including determining a bit error rate of a plurality of memory cells, each having an Ovonic threshold switch connected in series with a magnetic storage element, by performing a sequence of self-referenced read operations of each of the memory cells, each self-referenced read operation including a RESET pulse having a first polarity, and, prior to each self-referenced read operation, applying a pulse having the first polarity to the memory cells to turn the Ovonic threshold switch ON without disturbing a data state of the corresponding magnetic storage element. The pre-read pulses are configured to reduce the bit error rate of the plurality of memory cells.

[0184] One embodiment of the disclosed technology includes a device including a memory cell and control circuitry coupled to the memory cell. The memory cell includes a reversible resistive switching memory element coupled in series with a select element having a threshold voltage. The control circuitry is configured to use a first pulse having a first polarity for the first access to the memory cell and a second pulse having a second polarity opposite the first polarity for the second access to the memory cell and reading of the memory cell, the second pulse being adjacent to the first pulse. The first pulse is configured to reduce the rate of threshold voltage drift of the select element.

[0185] One embodiment of the disclosed technology includes a device including a crosspoint memory array including a plurality of memory cells and a control circuit coupled to the crosspoint memory array. Each memory cell includes a magnetic tunnel junction memory element coupled in series with a select element. The control circuit is configured to perform a self-referenced read operation for each of the plurality of memory cells and, prior to each self-referenced read operation, apply a pre-read pulse configured to discharge a voltage difference between a threshold voltage and an offset voltage of the corresponding select element.

[0186] One embodiment of the disclosed technology includes a method that includes determining a bit error rate of a plurality of memory cells, each having an Ovonic threshold switch coupled in series with a magnetic storage element. The method includes performing a sequence of self-referenced read operations of each of the memory cells, each self-referenced read operation comprising a RESET pulse having a first polarity, and, prior to each self-referenced read operation, applying a pulse having a second polarity opposite the first polarity to the memory cells to turn the Ovonic threshold switch ON without disturbing a data state of the corresponding magnetic storage element. The pre-read pulses are configured to reduce the bit error rate of the plurality of memory cells.

[0187] For the purposes of this document, a first layer may be above or above a second layer if there are zero, one, or more intermediate layers between the first layer and the second layer.

[0188] For the purposes of this document, it should be noted that the dimensions of the various features illustrated in the figures are not necessarily drawn to scale.

[0189] For purposes of this document, reference in the specification to "one embodiment," "some embodiments," or "another embodiment" may be used to describe different embodiments and does not necessarily refer to the same embodiment.

[0190] For the purposes of this document, a connection can be a direct connection or an indirect connection (e.g., via another part). In some cases, when an element is described as being connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via intermediate elements. When an element is described as being directly connected to another element, there are no intermediate elements between the element and the other element.

[0191] For the purposes of this document, the term “based on” can be read as “at least partly based on”.

[0192] For the purposes of this document, without additional context, the use of numeric expressions such as a "first" object, a "second" object, and a "third" object may not imply ordering of objects, but may instead be used for identification purposes to identify different objects.

[0193] For the purposes of this document, the term “set” of objects may refer to a “set” of one or more of the objects.

[0194] Although the subject matter has been described in language specific to structural features and / or methodological acts, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Accordingly, the specific features and acts described above are disclosed as exemplary forms of implementing the claims.

Claims

[1] Facility comprising: a memory cell comprising a reversible resistive switching memory element coupled in series with a selection element having a threshold voltage; and a control circuit coupled to the memory cell, the control circuit being configured to: to use a first pulse having a first polarity for the first access to the memory cell; and to use a second pulse having a second polarity opposite to the first polarity for the second access to the memory cell and the reading of the memory cell, the second pulse being adjacent to the first pulse, wherein the first pulse is configured to reduce the rate of threshold voltage drift of the selection element. [2] The device according to claim 1, wherein the reversible resistance switching memory element comprises a magnetic memory element. [3] The device according to claim 1, wherein the reversible resistance switching memory element comprises a magnetic tunnel junction. [4] The device according to claim 1, wherein the selection element comprises a threshold selection device. [5] The device of claim 1, wherein the selection element comprises an Ovonic threshold switch. [6] The device of claim 1, wherein the selection element has a threshold voltage that changes at an increasing rate over time. [7] The device according to claim 1, wherein the selection element can be selectively switched ON. [8] The device according to claim 1, wherein the first pulse and the second pulse each turn the selection element ON. [9] The device of claim 1, wherein the control circuit is further configured to perform a first reading and a second reading of the reversible resistance switch memory element after the second pulse. [10] The device of claim 1, wherein the control circuit is further configured to perform a destructive reading of the reversible resistance switch memory element after the second pulse. [11] The device of claim 1, wherein the second pulse comprises a RESET pulse. [12] The device of claim 1, wherein the first pulse is configured to turn the selection element ON without disturbing a data state of the reversible resistance switch storage element. [13] The device of claim 1, wherein the first pulse is configured to reduce a bit error rate of the memory cells. [14] Facility comprising: a crosspoint memory array comprising a plurality of memory cells, each memory cell comprising a magnetic tunnel junction memory element coupled in series to a select element; a control circuit coupled to a crosspoint memory array, the control circuit being configured to: perform a self-referenced read operation from each of the plurality of memory cells; and to apply a pre-read pulse before each self-referenced read operation, which is arranged to discharge a voltage difference between a threshold voltage and an offset voltage of the corresponding selection element. [15] Apparatus according to claim 14, wherein each selection element comprises a threshold selection device. [16] The device of claim 14, wherein each selection element comprises an Ovonic threshold switch. [17] The device of claim 14, wherein each selection element has a threshold voltage that changes at an increasing rate over time. [18] The device of claim 14, wherein the prefetch pulse is configured to reduce a bit error rate of the plurality of memory cells. [19] Method comprising: Determining a bit error rate of a plurality of memory cells, each having an Ovonic threshold switch coupled in series with a magnetic storage element, by: Performing a sequence of self-referenced read operations of each of the memory cells, each self-referenced read operation comprising a RESET pulse having a first polarity; and prior to each self-referenced read operation, applying a pulse having a second polarity opposite to the first polarity to the memory cells to turn the Ovonic threshold switch ON without disturbing the data state of the corresponding magnetic storage element. wherein the pre-read pulses are configured to reduce the bit error rate of the plurality of memory cells. [20] The method of claim 19, wherein the magnetic memory elements each have a magnetic tunnel junction.

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