Method for forming a semiconductor device comprising a plasma doping process

Abstract

A method for producing a semiconductor device (100) is proposed. The method comprises forming a doped region (118) of a first conductivity type in a SiC semiconductor body (102). Forming the doped region (118) comprises introducing dopants of the first conductivity type into the SiC semiconductor body (102) by at least one ion implantation process (I2t, I2nt). Forming the doped region (118) further comprises introducing dopants of the first conductivity type into the SiC semiconductor body (102) by at least one plasma doping process (104). A penetration depth of the dopants introduced by the at least one ion implantation process (I2t, I2nt) is greater than a penetration depth of the dopants introduced by the at least one plasma doping process (104).The method further comprises forming a contact material (129) on a contact surface area of the doped region (118), wherein the contact surface area comprises the dopants introduced by at least the plasma doping process (104).

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a method of forming a semiconductor device, in particular to a method of forming a doped region of a semiconductor device, comprising introducing dopants into a SiC semiconductor body by at least one ion implantation process. BACKGROUND

[0002] A key component in semiconductor applications is a solid-state switch. For example, switches turn loads of automotive or industrial applications on and off. Solid-state switches typically include, for example, field-effect transistors (FETs) such as metal-oxide-semiconductor FETs (MOSFETs), insulated-gate bipolar transistors (IGBTs), or junction field-effect transistors (JFETs). Exemplary solid-state switches are known from US Pat. No. 6,051,482. The technology development of new generations of SiC semiconductor switches aims to improve the properties of electrical devices and reduce costs by shrinking device geometries. Although costs can be reduced by shrinking device geometries, a variety of trade-offs and challenges must be met when increasing device functionalities per unit area.For example, reducing the area-specific on-resistance, Ron x A, by shrinking device geometries can be challenging to form ohmic contacts on doped regions in trenches or small mesa regions.

[0003] There is a need to improve formation processes of SiC semiconductor devices. SUMMARY

[0004] The invention is defined in the independent patent claims. Further developments are the subject of the dependent patent claims.

[0005] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The accompanying drawings are included to provide a further understanding of the embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of semiconductor devices and methods of fabricating semiconductor devices and, together with the description, serve to explain principles of the embodiments. Further embodiments are described in the following detailed description and claims. Fig. 1 is an exemplary process illustration for manufacturing a semiconductor device. Fig. 2A and Fig. 2B are schematic cross-sectional views illustrating process features for forming a doped region comprising a plasma doping process. Fig. 3A to Fig. 3E are schematic sectional views with respect to Fig. 2A for illustrating process features for manufacturing a semiconductor device. Fig. 4A and Fig. 4B are schematic sectional views with respect to Fig. 2B for illustrating process features for manufacturing a semiconductor device. DETAILED DESCRIPTION

[0007] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific examples in which semiconductor substrates may be processed. It should be understood that other examples may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. For example, features illustrated or described for one example may be used on or in conjunction with other examples to provide yet another example. It is intended that the present disclosure encompass such modifications and variations. The examples are described using specific language that should not be construed as limiting the scope of the appended claims.The drawings are not to scale and are for illustrative purposes only. Corresponding elements are designated by the same reference numerals throughout the various drawings unless otherwise indicated.

[0008] The terms "have," "contain," "comprise," "have," and the like are open-ended, and the terms indicate the presence of the specified structures, elements, or features, but do not preclude the presence of additional elements or features. The articles "a," "an," and "the" are intended to include both the plural and the singular, unless the context clearly indicates otherwise.

[0009] The term "electrically connected" may describe a permanent, low-resistance connection between electrically connected elements, for example, a direct contact between the elements in question or a low-resistance connection via a metal and / or heavily doped semiconductor material. The term "electrically coupled" may encompass that one or more intermediate elements configured for signal and / or power transmission may be connected between the electrically coupled elements, for example, elements that are controllable to temporarily provide a low-resistance connection in a first state and a high-resistance electrical decoupling in a second state. An ohmic contact is a non-rectifying electrical junction.

[0010] When two elements A and B are combined using "or," this should be understood to reveal all possible combinations, i.e., only A, only B, and both A and B, unless explicitly or implicitly defined otherwise. An alternative formulation for the same combinations is "at least one of A and B" or "A and / or B." The same applies, mutatis mutandis, to combinations of more than two elements.

[0011] Ranges specified for physical dimensions include the limiting values. For example, a range for a parameter y from a to b is a ≤ y ≤ b. The same applies to ranges with a limit such as "at most" and "at least."

[0012] The main components of a layer or structure made of a chemical compound or alloy are those elements whose atoms form the chemical compound or alloy. For example, silicon (Si) and carbon (C) are the main components of a silicon carbide (SiC) layer.

[0013] The term "on" should not be interpreted to mean only "directly on." Rather, when an element is positioned "on" another element (e.g., a layer "on" another layer or "on" a substrate), another component (e.g., another layer) may be positioned between the two elements (e.g., another layer may be positioned between a layer and a substrate if the layer is "on" the substrate).

[0014] The description and drawings merely illustrate the principles of the disclosure. Furthermore, any examples provided herein are primarily intended to be illustrative only, to assist the reader in understanding the principles of the disclosure and the concepts contributed by the inventor(s) to advance the prior art. All statements herein that recite principles, aspects, and embodiments of the disclosure, as well as specific examples thereof, are intended to include equivalents thereof.

[0015] Some of the following examples are described in connection with a silicon carbide substrate. Alternatively, another wide-bandgap semiconductor substrate, such as a wide-bandgap wafer, may be processed, for example, one having a wide-bandgap semiconductor material other than silicon carbide. The wide-bandgap semiconductor wafer may have a bandgap larger than the bandgap of silicon (1.12 eV). For example, the wide-bandgap semiconductor wafer may be a gallium arsenide (GaAs) wafer or a gallium nitride (GaN) wafer.

[0016] The first conductivity type may be p-type, and the second conductivity type may be n-type. Likewise, the first conductivity type may be n-type, and the second conductivity type may be p-type.

[0017] It should be understood that the disclosure of multiple steps, processes, operations, steps, or functions disclosed in the specification or claims should not be construed as occurring within the specific order unless explicitly or implicitly indicated otherwise, e.g., by terms such as "thereafter," for example, for technical reasons. Therefore, the disclosure of multiple steps or functions does not limit them to any particular order unless such steps or functions are not interchangeable for technical reasons. Further, in some examples, a single step, function, process, operation, or step may include or be broken down into multiple sub-steps, functions, processes, operations, or steps.Such sub-steps may be included and form part of the disclosure of that single step unless they are explicitly excluded.

[0018] An example of a method for manufacturing a semiconductor device will be described with reference to the flowchart of Fig. 1 illustrates.

[0019] Process feature S100 comprises forming a doped region of a first conductivity type in a SiC semiconductor body, including introducing dopants of the first conductivity type into the SiC semiconductor body through at least one ion implantation process. Forming the doped region further comprises introducing dopants of the first conductivity type into the SiC semiconductor body through at least one plasma doping process. A penetration depth of the dopants introduced through the at least one ion implantation process is greater than a penetration depth of the dopants introduced through the at least one plasma doping process.

[0020] Process feature S110 includes forming a contact material on a contact surface area of ​​the doped region. The contact surface area includes the dopants introduced by at least the plasma doping process.

[0021] The at least one ion implantation process can be performed before or after the at least one plasma doping process. If multiple ion implantation and / or multiple plasma doping processes are performed to form the doped region, one or more ion implantation processes can be performed between plasma doping processes, or vice versa.

[0022] The semiconductor device may, for example, be part of an integrated circuit or may be a discrete semiconductor device or a semiconductor module. The semiconductor device may, for example, be or comprise an insulated gate field-effect transistor (IGFET) such as a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT) or a junction field-effect transistor (JFET). The semiconductor device may be a vertical power semiconductor device with a load current flow between the first surface and a second surface opposite the first surface along a vertical direction. The vertical power semiconductor device may be configured to conduct currents of more than 1 A, or more than 10 A, or more than 30 A, or more than 50 A, or more than 75 A, or even more than 100 A, and may further be configured to conduct voltages between load electrodes, e.g.between the collector and emitter of an IGBT or between the drain and source of a MOSFET or JFET, in the range of several hundred to several thousand volts, e.g., 400 V, 650 V, 1.2 kV, 1.7 kV, 3.3 kV, 4.5 kV, 5.5 kV, 6 kV, 6.5 kV, 10 kV. The blocking voltage can, for example, correspond to a voltage class specified in a datasheet for the power semiconductor device.

[0023] The semiconductor device may be based on a SiC semiconductor body made of a crystalline SiC material. The crystalline SiC material may, for example, have a hexagonal crystal lattice. For example, the semiconductor material may be 2H-SiC (2H polytype SiC), 6H-SiC, or 15R-SiC. According to one example, the semiconductor material is 4H polytype silicon carbide (4H-SiC). The SiC semiconductor body may comprise or consist of a semiconductor substrate having no, one, or more than one semiconductor layer, e.g., epitaxially grown layers, thereon. One of the semiconductor layers may, for example, be a doped semiconductor layer of a current spreading layer.

[0024] The first surface may define a front surface or a top surface of the SiC semiconductor body, and the SiC semiconductor body may further have a second surface, which may, for example, be a back surface or a rear surface of the SiC semiconductor body. The SiC semiconductor body may, for example, be attached to a lead frame via the second surface. Bond pads may, for example, be arranged over the first surface of the SiC semiconductor body, and bond wires may be bonded to the bond pads.

[0025] To achieve a desired current-carrying capacity, the SiC semiconductor device may be configured by a plurality of parallel-connected SiC semiconductor device cells. The parallel-connected SiC semiconductor device cells may, for example, be SiC semiconductor device cells formed in the shape of a strip or a strip segment. Of course, the SiC semiconductor device cells may also have any other shape, e.g., circular, elliptical, polygonal, such as hexagonal or octahedral. The semiconductor device cells may be arranged in a transistor cell region of the SiC semiconductor body. The transistor cell region may be a region in which an emitter region of an IGBT (or a source region of a MOSFET or JFET) and a collector region of an IGBT (or a drain region of a MOSFET or JFET) are arranged opposite each other along a vertical direction.In the transistor cell region, a load current can enter or leave the SiC semiconductor body of the semiconductor device, e.g., via contact plugs or contact lines on the top surface of the mesa. The semiconductor device may further comprise an edge termination region, which may comprise a termination structure. In a blocking mode or in a reverse-biased mode of the semiconductor device, the blocking voltage between the transistor cell region and a field-free region drops laterally across the termination structure. The termination structure may have a higher or slightly lower voltage blocking capability than the transistor cell region. The termination structure may, for example, comprise a junction termination extension (JTE) with or without a variation of lateral doping (VLD), one or more laterally separated guard rings, or any combination thereof.

[0026] The at least one plasma doping process can be any plasma-based doping process that enables high-dose implantations at low energies. Plasma doping processes are also known as PLAD (plasma doping) or PIII (plasma immersion ion implantation). These methods enable precise doping of a semiconductor body. For example, conformal doping of the portion of the semiconductor body can be achieved by applying a voltage to a substrate surrounded by a radio-frequency (RF) plasma comprising a dopant gas. Collisions between ions and neutral atoms, as well as the substrate bias, lead to a broad annular distribution of the dopants, enabling nearly homogeneous doping across the trench sidewalls. A small vertical gradient of the doping dose in the portion of the semiconductor body can also be achieved through plasma doping.In plasma doping, the SiC semiconductor body, e.g., a semiconductor wafer, is exposed to a plasma containing dopant ions. These ions are accelerated toward the substrate by an electric field and are implanted into an exposed surface of the substrate. The implanted dose can be adjusted or controlled via DC voltage pulses, e.g., negative voltage pulses. A Faraday system allows the dose to be adjusted or controlled. For example, two sets of coils, a horizontal coil and a vertical coil, can generate the plasma and maintain it homogeneous. The ion density can be adjusted by adjusting the distance between the coils and the substrate. The interaction between the vertical coils and the horizontal coils allows the homogeneity and ion density to be adjusted or controlled.The penetration depth of the dopants into the semiconductor body and the implantation dose can be adjusted via a pulsed DC voltage applied between the SiC semiconductor substrate or body and a surrounding shielding ring.

[0027] Forming the doped region may include introducing n- and / or p-type dopants into the SiC semiconductor body. For example, dopants in a semiconductor body comprising SiC may include Al, B, Be, Ga, or any combination thereof for p-type doping, and N, P, or any combination thereof for n-type doping. If the doped region is formed by a combination of plasma doping and ion implantation processes, where the ion implantation process has a comparatively greater penetration depth of the ions, the formation process of the doped region may be improved with respect to the overall functional purpose of the doped region.Since different regions of the doped region may be assigned to different functional purposes, the properties of these different regions may be improved by adapting the formation process to the function to be achieved by the respective region of a continuous doped region. For example, the at least one plasma doping process enables the optimization of the region of the doped region in which a low-resistance contact to n- and / or p-SiC is to be achieved. Since the plasma doping process inherently dopes the surface region with high dose and homogeneity within one process step or alternatively by applying multiple plasma doping processes for a broader doping profile, an undesirable multitude of ion implantations with different inclination angles (e.g.undesirable in terms of manufacturing costs and / or manufacturing time and / or homogeneity of the dopant distribution) can be avoided in order to optimize the area of ​​the doped region relevant for the formation of ohmic contacts. Since dopants do not diffuse to a large extent in SiC, this can further help to increase the electrically active dopant concentration up to its solubility limit, so that the homogeneity of the electrically active dopant concentration along the contact surface, e.g., trench sidewall, is excellent, which is typically not the case for lower surface concentrations. Furthermore, the total doping concentration (which is the sum of electrically active and non-active dopants) along trench sidewalls is also more homogeneous the higher the implantation dose. This helps to achieve ohmic contact with transition metals such as titanium or aluminum.This can also solve the need to use metals of the critical material (CM class) such as nickel.

[0028] For example, the method may further comprise forming a first trench in the SiC semiconductor body from a first surface of the SiC semiconductor body. The dopants introduced into the SiC semiconductor body by the at least one plasma doping process may be introduced through a bottom and sidewalls of the first trench. The dopants introduced into the SiC semiconductor body by the at least one plasma doping process may define a highly doped contact region of the doped region configured to reduce a contact resistance between the doped region and the contact material. The dopants of the doped region introduced by the at least one ion implantation process may define at least one functional region of the doped region configured to fulfill a functional purpose, e.g.an electric field shielding function and / or a threshold voltage adjustment function and / or a breakdown voltage adjustment function and / or a conductivity resistance adjustment function. The formation of the contact region of the doped area by the at least one plasma doping process can not only avoid a large number of ion implantations with different ion implantation tilt angles and other disadvantages, but can also enable a uniform and high doping concentration at the contact surface.

[0029] For example, after forming the first trench and before introducing the dopants through the at least one plasma doping process, the method may further comprise processing the bottom and sidewalls of the first trench through a sputter etching process. This may enable the removal of a native oxide from the bottom and sidewalls of the first trench. Thus, unwanted accumulation of introduced dopants in the native oxide may be avoided. Alternatively, an RF treatment may be applied prior to the plasma doping process.

[0030] For example, processing the SiC semiconductor body through the sputter etching process and the at least one plasma doping process can be performed in the same processing facility. This can help minimize the time between the removal of the native oxide and the at least one plasma doping process.

[0031] For example, the method may further comprise electrically activating the dopants introduced by the at least one plasma doping process by an annealing process comprising temperatures in the range of 1500°C to 1800°C, or from 1500°C to 1700°C, or from 1500°C to 1600°C. For example, annealing Al or P or N at temperatures around 1600°C for a duration of less than 1 hour, e.g., 30 minutes, may result in electrical activation of more than 95% of the introduced dopants. Therefore, an annealing temperature of less than 1800°C, or less than 1700°C, or even less than 1600°C may be used to electrically activate the implanted dopants in order to minimize undesired outdiffusion of the implanted dopants.

[0032] For example, the method may further comprise, after introducing the dopants by the at least one plasma doping process and before electrically activating the dopants introduced by the at least one plasma doping process by an annealing process, forming an auxiliary layer on the bottom and sidewalls of the first trench. The auxiliary layer may have a melting point greater than 1850°C. For example, the auxiliary layer may act as an outdiffusion barrier layer that prevents dopants introduced by the at least one plasma doping process from outdiffusion through the bottom or sidewalls of the first trench. Furthermore, the auxiliary layer may prevent a significant reduction in the surface concentration of the introduced dopants. This may enable the improvement of the ohmic contact properties between the doped region and the contact material.

[0033] For example, a material of the auxiliary layer may comprise at least one of Si3N4 or Al2O3 or AlN or allotropes of carbon, e.g., graphene with melting points at about 1900 °C (e.g., Si3N4) or higher (e.g., Al2O3 or AlN or allotropes of carbon).

[0034] For example, the method may further comprise forming a contact layer on the bottom and sidewalls of the first trench. The contact material of the contact layer may comprise a transition metal and / or an alloy of a transition metal.

[0035] For example, the transition metal may comprise at least one of Ni, Al, Ti, e.g., NiAl.

[0036] For example, the method may further comprise forming a second trench simultaneously with the first trench. The method may further comprise at least partially filling or lining the second trench with a protective material prior to introducing the dopants into the SiC semiconductor body by the at least one plasma doping process through a bottom and sidewalls of the first trench. For example, the protective material may be polycrystalline silicon and / or a dielectric material such as a sacrificial oxide.

[0037] For example, the method may further comprise removing the protective material from the second trench. The method may further comprise forming a trench gate structure in the second trench. Forming the trench gate structure in the second trench, e.g., a gate trench, may comprise forming a trench gate dielectric in the second trench, e.g., by thermal oxidation or deposition. Forming the trench gate structure may further comprise forming a trench gate electrode on the gate-trench dielectric. Forming the trench gate structure may further comprise, for example, a post-oxidation anneal in a nitrogen-containing atmosphere. The trench gate electrode may comprise one or a stack of conductive materials, e.g., highly doped polycrystalline silicon and / or carbon and / or metal or metal alloy.

[0038] For example, the method may further comprise forming a patterned mask layer on the first surface of the SiC semiconductor body prior to introducing the dopants of the first conductivity type into the SiC semiconductor body by the at least one plasma doping process. The dopants of the first conductivity type may be introduced into the SiC semiconductor body by the at least one plasma doping process through openings in the patterned mask layer. The patterned mask layer may be formed, for example, as a patterned hard mask layer, a patterned resist layer, or a combination thereof. This allows a highly doped contact region to be produced on the first surface of the SiC semiconductor body.

[0039] For example, after introducing the dopants into the SiC semiconductor body by the at least one plasma doping process, the method may further comprise forming a trench in the SiC semiconductor body from the first surface of the SiC semiconductor body. Thereafter, the method may further comprise introducing at least a portion of the dopants of the first conductivity type into the SiC semiconductor body by the at least one ion implantation process.

[0040] For example, the trench may be further processed as a gate trench, e.g., by forming a trench gate dielectric and a trench gate electrode in the gate trench.

[0041] For example, prior to forming the doped region, the method may further comprise forming at least one doped layer by introducing dopants into the SiC semiconductor body through a first surface of the SiC semiconductor body. For example, the dopants of the doped layer may be introduced into the SiC semiconductor body through at least one ion implantation process that is planar or unmasked with respect to a transistor cell region of the semiconductor device.

[0042] The at least one doped layer may be or comprise, for example, a source layer or a body layer or a current spreading layer or any combination thereof.

[0043] For example, body regions can be formed by patterning the body layer using a trench etching process. Similarly, source regions can be formed by patterning the source layer using the trench etching process. The trench etching process can first etch through the source layer and then through the body layer. Each of the body regions can, for example, be adjacent to one of two opposite sidewalls of the trench.

[0044] For example, the at least one plasma doping process can be carried out in a process facility at temperatures in the range of 300 °C to 700 °C.

[0045] Details regarding the structure or function or technical benefits of features described above also apply to the exemplary methods described below. Processing the SiC semiconductor body may include one or more optional additional features corresponding to one or more aspects mentioned in connection with the proposed concept or one or more examples described above or below.

[0046] The process features may include subprocesses. For example, some or all subprocesses of one process feature described herein may be performed before, after, or between subprocesses of another process feature described herein.

[0047] The schematic sectional view of Fig. 2A illustrates process features of an exemplary method of manufacturing a semiconductor device 100 based on the method of Fig. 1.

[0048] A first trench 106 is formed in a SiC semiconductor body 102 from a first surface 1081 of a SiC semiconductor body 102. For example, the first trench 106 may be formed by an etching process using a patterned mask layer 115, e.g., a hard mask. After forming the first trench 106, dopants of the first conductivity type are introduced into the SiC semiconductor body 102 by at least one plasma doping process 104 through a bottom side 1061 and through sidewalls 1062 of the first trench 106. As a result, dopants of a first region 1181 of a doped area 118 are introduced into the SiC semiconductor body 102. The first region 1181 may, for example, define a highly doped contact area.Further dopants of the first conductivity type may be introduced into the SiC semiconductor body 102 at a greater penetration depth than the dopants of the first region 1181 by at least one ion implantation process. The at least one ion implantation process may be performed before and / or after the at least one plasma doping process 104, e.g., by tilted and / or untilted ion implantation(s). After the at least one plasma doping process and after the at least one ion implantation process has been performed, an optional auxiliary layer 116, indicated by a dashed line, may be formed on the bottom side 1061 and on the sidewalls 1062 of the first trench 106 in order to avoid or minimize outdiffusion of the introduced dopants during subsequent thermal processing, e.g., electrical activation of the introduced dopants (not shown).

[0049] The schematic sectional view of Fig. 2B illustrates process features of another exemplary method of manufacturing a semiconductor device 100 based on the method of Fig. 1. The Fig. 2A and Fig. 2B may be combined to form doped regions at various positions in the SiC semiconductor body 102 by doping processes each comprising at least one plasma doping process.

[0050] With reference to Fig. 2B, a patterned mask layer 114 is formed on the first surface 1081 of the SiC semiconductor body 102. Thereafter, dopants of the first conductivity type are introduced into the SiC semiconductor body 102 by at least one plasma doping process 104 through an opening 1141 in the patterned mask layer 114. As a result, dopants of a first region 1181 of a doped area 118 are introduced into the SiC semiconductor body 102. The first region 1181 may define a highly doped contact area for an n- or p-doped area, which is electrically connected, for example, by a contact plug or a contact line, to a wiring area above the first surface 108. Further dopants of the first conductivity type can be introduced into the SiC semiconductor body 102 at a greater penetration depth than the dopants of the first region 1181 by at least one ion implantation process.The at least one ion implantation process can be performed before and / or after the at least one plasma doping process 104, e.g., by tilted and / or untilted ion implantation(s). After the at least one plasma doping process and after the at least one ion implantation process has been performed, an auxiliary layer can be formed on the first surface 1081 of the SiC semiconductor body 102, e.g., after removing the patterned mask layer 114, in order to avoid or minimize outdiffusion of the introduced dopants during subsequent thermal processing, e.g., electrical activation of the introduced dopants (not shown).

[0051] The schematic sectional views of Fig. 3A to Fig. 3E illustrate process features of an exemplary method of manufacturing a semiconductor device 100 based on the method of Fig. 1 and the Fig. 2A illustrated process characteristics.

[0052] With reference to Fig. 3A is formed before the doped region 118 of Fig. 2A, at least one doped layer is formed by introducing dopants into the SiC semiconductor body 102 through the first surface 1081 of the SiC semiconductor body 102, e.g., by one or more ion implantation processes. The ion implantation(s) for forming the at least one doped layer may be unmasked or covering with respect to a transistor cell region of the semiconductor device. In the illustrated example, the at least one doped layer is formed by an n +-doped source layer 120, a p-doped body layer 122, and an n-doped current spreading layer 124. The n-doped current spreading layer 124 has a higher doping concentration than a background doping concentration of the SiC semiconductor body 102 adjacent to the n-doped current spreading layer 124. As an alternative to forming the n-doped current spreading layer 124 by ion implantation, the n-doped current spreading layer 124 may also be formed by a layer deposition process, including, for example, in-situ doping.

[0053] With reference to Fig. 3B, first and second trenches 106, 110 are formed in the SiC semiconductor body 102 from a first surface 1081 of the SiC semiconductor body 102 using the patterned mask layer 115. For example, the first and second trenches 106, 110 may be formed by one or more etching processes. The formation of the first and second trenches 106, 110 further patterns or divides the source layer 120 into source regions 1201. The formation of the first and second trenches 106, 110 further patterns or divides the body layer 122 into body regions 1221.

[0054] With reference to Fig. 3C, a protective material 112 is formed in the second trench 110. The protective material 112 may fill the second trench 110 (as shown in Fig. 3C) or may line or partially fill the second trench 110 and optionally parts of the first trench 106 (not shown). P-type dopants are introduced into the SiC semiconductor body 102 through a bottom surface 1061 and sidewalls 1062 of the first trench 106 by at least one plasma doping process 104. As a result, dopants of a first region 1181 of a doped area 118 are introduced into the SiC semiconductor body 102.

[0055] With reference to Fig. 3D, dopants are introduced into the SiC semiconductor body 102 by at least one tilted ion implantation process I2t and / or non-tilted ion implantation process I2nt through a bottom 1061 and / or sidewalls 1062 of the first trench 106. As a result, p-type dopants of a second region 1182 of the doped area 118 are introduced into the SiC semiconductor body 102.

[0056] The Fig. 3D shown at least one ion implantation process I2t, I2nt can also be carried out before or at least partially before the Fig. 3C. Furthermore, prior to the at least one plasma doping process 104, cleaning process(es), e.g., for removing the native oxide, and / or auxiliary layer(s), e.g., scattering oxide, may be formed in the first trench 106.

[0057] Further process features follow, e.g., as described in the examples above. The further process features may include, among others, diffusion barrier deposition, electrical activation of the introduced dopants by thermal annealing, formation of a trench gate structure in the second trench, and formation of a wiring region over the first surface and the second surface of the SiC semiconductor substrate.

[0058] With reference to Fig. 3E, after removing the protective material 112 from the second trench 110, e.g., gate trench, a trench-gate structure 126 is formed with a trench-gate dielectric 1261 and a trench-gate electrode 1262. An intermediate dielectric 128 is formed on the first surface 1081 of the SiC semiconductor body 102 as part of a wiring region. A contact material 129, e.g., a conductive fill material, is formed on a contact surface area of ​​the doped region 118, e.g., on a bottom surface and sidewalls of the first trench 106. The contact material 129 is connected to a wiring layer 130, e.g., a metal layer. For example, the wiring layer 130 may be a source or emitter electrode S, which may also be electrically connected to the source regions 1201 (not illustrated).A wiring layer defining a drain or collector electrode D is also formed on the second surface of the SiC semiconductor substrate 102 for electrically connecting a drift structure 132 in the SiC semiconductor body 102 to the drain or collector electrode D.

[0059] The schematic sectional views of Fig. 4A to Fig. 4B illustrate process features of an exemplary method of manufacturing a semiconductor device 100 based on the method of Fig. 1 and the Fig. 2B illustrated process characteristics.

[0060] With reference to Fig. 4A and similar to those referred to in Fig. 3A, at least one doped layer is formed by introducing dopants into the SiC semiconductor body 102 through a first surface 1081 of the SiC semiconductor body 102, e.g., by one or more ion implantation processes. The ion implantation(s) for forming the at least one doped layer may be unmasked or covering with respect to a transistor cell region of the semiconductor device 100. In the illustrated example, the at least one doped layer is covered by an n +-doped source layer 120, a p-doped body layer 122, and an n-doped current spreading layer 124. The n-doped current spreading layer 124 has a higher doping concentration than a background doping concentration of a first region 1021 of the semiconductor body 102 adjacent to the n-doped current spreading layer 124. As an alternative to forming the n-doped current spreading layer 124 by ion implantation, the n-doped current spreading layer 124 may also be formed by a layer deposition process. The first region 1021 may be formed by layer deposition on a second region 1022 of the SiC semiconductor body, e.g., on a highly doped SiC substrate.

[0061] A structured mask layer 114 is formed on the first surface 1081 of the SiC semiconductor body 102. Thereafter, p-types of the first conductivity type are introduced into the SiC semiconductor body 102 by at least one plasma doping process 104 through an opening 1141 in the structured mask layer 114. As a result, dopants of the p-type of a p + -doped first region 1181 of a p-doped region 118 is introduced into the SiC semiconductor body 102. The first region 1181 may define a highly doped contact region for a p-doped region 118, which is electrically connected to a wiring region above the first surface 108, for example, by a contact plug or a contact line on the first surface 1081. The first region 1181 may comprise counter-doped regions of the n + -doped source layer 120. A future gate trench position is indicated by a dashed line.

[0062] With reference to Fig. 4B, a gate trench 134 is formed into the SiC semiconductor body 102 from a first surface 1081 of the SiC semiconductor body 102 using a patterned mask layer 115. For example, the gate trench 134 may be formed by one or more etching processes. The formation of the gate trench 134 patterns or divides the source layer 120 into source regions 1201. The formation of the gate trench 134 further patterns or divides the body layer 122 into body regions 1221.

[0063] After forming a sacrificial layer 136, e.g., a sacrificial oxide layer, on the bottom and sidewalls of the gate trench 134, further p-type dopants are introduced into the SiC semiconductor body 102 by at least one tilted ion implantation I2t to form a second region 1182 of the doped region 118 at a greater penetration depth than the dopants of the first region 1181. The second region 1182 is in Fig. 4B is illustrated by a combination of two subregions associated with ion implantations with different tilt angles and / or different ion implantation energies.

[0064] Further process features follow, e.g., as described in the examples above. The further process features may include, among others, removing the sacrificial layer, electrically activating the introduced dopants by thermal annealing, forming a gate structure in the gate trench, forming a contact material on the first region by a contact plug or a contact line, forming a wiring region over the first surface and the second surface of the SiC semiconductor substrate 102. The semiconductor device 100 based on the process features of Fig. 4A and Fig. 4B may be a trench transistor with a channel region only on one of two opposite sidewalls of the gate trench.

[0065] The aspects and features mentioned and described together with one or more of the previously described examples and figures may also be combined with one or more of the other examples to replace a similar feature of the other example or to additionally incorporate the feature into the other example.

[0066] Although specific embodiments have been illustrated and described herein, it will be apparent to those skilled in the art that a variety of alternative and / or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.

Claims

[1] A method of forming a semiconductor device (100), the method comprising: Forming a doped region (118) of a first conductivity type in a SiC semiconductor body (102), comprising: Introducing dopants of the first conductivity type into the SiC semiconductor body (102) by at least one ion implantation process (I2nt, I2t); Introducing dopants of the first conductivity type into the SiC semiconductor body (102) by at least one plasma doping process (104), wherein a penetration depth of the dopants introduced by the at least one ion implantation process (I2nt, I2t) is greater than a penetration depth of the dopants introduced by the at least one plasma doping process (104); and Forming a contact material (129) on a contact surface area of ​​the doped region (118), wherein the contact surface area comprises the dopants introduced by at least the plasma doping process (104), and further comprising Forming a first trench (106) in the SiC semiconductor body (102) from a first surface (1081) of the SiC semiconductor body (102), wherein the dopants introduced into the SiC semiconductor body by the at least one plasma doping process (104) are introduced through a bottom side (1061) and side walls (1062) of the first trench (106). [2] Method according to the preceding claim, further comprising, after forming the first trench (106) and before introducing the dopants by the at least one plasma doping process (104), processing the bottom (1061) and the side walls (1062) of the first trench (106) by a sputter etching process. [3] Method according to the preceding claim, wherein the processing of the SiC semiconductor body (102) is carried out by the sputter etching process and by the at least one plasma doping process (104) in the same process device. [4] Method according to one of the preceding claims, further comprising electrically activating the dopants introduced by the at least one plasma doping process (104) by an annealing process comprising temperatures in the range of 1500 °C to 1800 °C. [5] Method according to the preceding claim, further comprising, after the introduction of the dopants by the at least one plasma doping process (104) and before the electrical activation of the dopants introduced by the at least one plasma doping process (104) by an annealing process, forming an auxiliary layer (116) on the bottom side (1061) and on the side walls (1062) of the first trench (106), wherein the auxiliary layer (116) has a melting point of greater than 1850°C. [6] Method according to the preceding claim, wherein a material of the auxiliary layer (116) comprises at least one of Si3N4 or Al2O3 or AIN or allotropes of carbon. [7] The method of any one of claims 2 to 6, further comprising forming a contact layer on the bottom and sidewalls of the first trench (106), wherein the contact material (129) of the contact layer comprises a transition metal and / or an alloy of a transition metal. [8] A process according to the preceding claim, wherein the transition metal comprises at least one of Ni, Al, Ti. [9] Method according to one of the two preceding claims, further comprising forming a second trench (110) simultaneously with the first trench (106) and at least partially filling or lining the second trench (110) with a protective material (112) before introducing the dopants into the SiC semiconductor body (102) by the at least one plasma doping process (104) through a bottom (1061) and side walls (1062) of the first trench (106). [10] The method of the preceding claim, further comprising removing the protective material (112) from the second trench (110); and forming a trench gate structure (126) in the second trench (110). [11] A method of forming a semiconductor device (100), the method comprising: Forming a doped region (118) of a first conductivity type in a SiC semiconductor body (102), comprising: Introducing dopants of the first conductivity type into the SiC semiconductor body (102) by at least one ion implantation process (I2nt, I2t); Introducing dopants of the first conductivity type into the SiC semiconductor body (102) by at least one plasma doping process (104), wherein a penetration depth of the dopants introduced by the at least one ion implantation process (I2nt, I2t) is greater than a penetration depth of the dopants introduced by the at least one plasma doping process (104); and Forming a contact material (129) on a contact surface area of ​​the doped region (118), wherein the contact surface area comprises the dopants introduced by at least the plasma doping process (104), and further comprising before introducing the dopants of the first conductivity type into the SiC semiconductor body by the at least one plasma doping process (104), forming a structured mask layer (114) on the first surface (1081) of the SiC semiconductor body (102), wherein the dopants of the first conductivity type are introduced into the SiC semiconductor body (102) by the at least one plasma doping process (104) through openings (1141) in the structured mask layer (114). [12] Method according to the preceding claim, further comprising after introducing the dopants into the SiC semiconductor body (102) by the at least one plasma doping process (104), forming a trench in the SiC semiconductor body (102) from the first surface (1081) of the SiC semiconductor body (102); and thereafter Introducing at least a portion of the dopants of the first conductivity type into the SiC semiconductor body (102) by the at least one ion implantation process (I2t, I2nt). [13] The method of any preceding claim, further comprising, prior to forming the doped region (118), forming at least one doped layer (120, 122, 124) by introducing dopants into the SiC semiconductor body (102) through a first surface (1081) of the SiC semiconductor body (102). [14] The method according to the preceding claim, wherein the at least one doped layer (120, 122, 124) comprises a source layer (120) or a body layer (122) or a current spreading layer (124) or any combination thereof. [15] Method according to the preceding claim, wherein Body regions (1221) are formed by structuring the body layer (122) by a trench etching process, and / or Source regions (1201) are formed by structuring the source layer (120) by the trench etching process. [16] Method according to one of the preceding claims, wherein the at least one plasma doping process (104) is carried out in a process device at temperatures in the range of 300 °C to 700 °C.

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