GPU-INITIATED DATA ACCESS TO A SCALED STORAGE

Abstract

Devices, systems, and methods for using parallel processing units (“PPUs”) to perform data accesses in response to data access requests are disclosed. The data accesses can be performed by accessing at least one first section of data stored at at least one first location of data locations, provided the first location is on a first level of a plurality of data levels accessible to the PPU(s), and by causing a server interface to access at least one second section of the data stored at at least one second location of data locations, provided the second location is on a second level of the plurality of data levels. The data access request(s) can be made via an API. The data accesses can be performed by a client, and the server interface can be implemented by a server.The client(s) and server(s) can be implemented on a single node and can be paused and migrated to other nodes during execution. The client(s) can implement synchronous and / or asynchronous interfaces.

Description

TECHNICAL FIELDAt least one embodiment relates to using one or more parallel processing units ("PPU(s)"), such as one or more graphics processing units ("GPU(s)"), to initiate data access (e.g., by performing read and / or write (put) operations). The PPU(s) may implement a client interface to access data from at least one storage location (e.g., cache(s) stored in volatile memory and / or nonvolatile data storage). One or more applications may use one or more application programming interfaces ("APIs") to enable data access (e.g., by generating the client interface). In at least one embodiment, a computer system (e.g., in a data center) implements various novel methods described herein.BACKGROUNDIn a data center, developers and / or users may process huge amounts of data that are physically and / or logically distributed across one or more systems, e.g., across multiple storage levels that may include memory. Distribution of data across one or more systems may negatively impact performance of data access, restrict bandwidth, limit the number of I / O operations that may be performed per second, increase overhead, and / or consume resources. For example, synchronization between concurrently executing processes may degrade data access performance. As another example, processing amounts of data that are too large to be stored in a GPU memory and / or a CPU memory of one or more systems may cost time and / or resources. Accordingly, the processes used for data access can be improved.BRIEF DESCRIPTION OF THE DRAWINGSFIG. 1A is a block diagram illustrating an example system that may be used to implement an architecture illustrated in FIG. 1B, in accordance with at least one embodiment; FIG. 1B is a block diagram illustrating the architecture according to at least one embodiment; FIG. 2 is a block diagram illustrating example components that may be used to implement the architecture illustrated in FIG. 1B, according to at least one embodiment; FIG. 3 is a block diagram illustrating example components that may be used to implement a level view of the architecture shown in FIG. 1B, according to at least one embodiment; FIG. 4 is a block diagram illustrating parallel processing unit ("PPU") initiated data access, according to at least one embodiment; FIG. 5 is a block diagram illustrating a driver and / or runtime environment having one or more libraries to provide one or more application programming interfaces ("APIs"), according to at least one embodiment; FIG. 6 illustrates example modules that may be executed by one or more processors of the system of FIG. 1A, according to at least one embodiment; FIG. 7 is a method flow diagram illustrating a method that may be used to implement PPU-initiated data access, according to at least one embodiment; FIG. 8 illustrates a distributed system according to at least one embodiment; FIG. 9 illustrates an example data center, according to at least one embodiment; FIG. 10 illustrates a client-server network according to at least one embodiment; FIG. 11 illustrates an example of a computer network according to at least one embodiment; FIG. 12A illustrates a networked computer system according to at least one embodiment; FIG. 12B illustrates a networked computer system according to at least one embodiment; FIG. 12C illustrates a networked computer system according to at least one embodiment; FIG. 13 illustrates one or more components of a system environment in which services may be offered as third party network services, according to at least one embodiment, FIG. 14 illustrates a cloud computing environment, according to at least one embodiment; FIG. 15 illustrates a set of functional abstraction layers provided by a cloud computing environment, according to at least one embodiment; FIG. 16 illustrates a chip-level supercomputer, in accordance with at least one embodiment; FIG. 17 illustrates a rack module level supercomputer, in accordance with at least one embodiment; FIG. 18 illustrates a rack-level supercomputer, in accordance with at least one embodiment; FIG. 19 illustrates an overall system level supercomputer in accordance with at least one embodiment; FIG. 20A illustrates inference and / or training logic, according to at least one embodiment; FIG. 20B illustrates inference and / or training logic, according to at least one embodiment; FIG. 21 illustrates training and deployment of a neural network, according to at least one embodiment; FIG. 22 illustrates an architecture of a system of a network, according to at least one embodiment; FIG. 23 illustrates an architecture of a system of a network, according to at least one embodiment; FIG. 24 illustrates a control-level protocol stack, according to at least one embodiment; FIG. 25 illustrates a user-level protocol stack, according to at least one embodiment; FIG. 26 illustrates components of a core network according to at least one embodiment; FIG. 27 illustrates components of a system for supporting network function virtualization (NFV), according to at least one embodiment; FIG. 28 illustrates a processing system according to at least one embodiment; FIG. 29 illustrates a computer system according to at least one embodiment; FIG. 30 illustrates a system according to at least one embodiment; FIG. 31 illustrates an example integrated circuit according to at least one embodiment; FIG. 32 illustrates a computing system according to at least one embodiment; FIG. 33 illustrates an APU according to at least one embodiment; FIG. 34 illustrates a CPU according to at least one embodiment; FIG. 35 illustrates an example accelerator integration slice, according to at least one embodiment; FIGS. 36A-36B illustrate example graphics processors, according to at least one embodiment; FIG. 37A illustrates a graphics core, according to at least one embodiment; FIG. 37B illustrates a GPCPU, according to at least one embodiment; FIG. 38A illustrates a parallel processor according to at least one embodiment; FIG. 38B illustrates a processing cluster according to at least one embodiment; FIG. 38C illustrates a graphics multiprocessor according to at least one embodiment; FIG. 39 illustrates a software stack of a programming platform, according to at least one embodiment; FIG. 40 illustrates a CUDA implementation of a software stack of FIG. 39, according to at least one embodiment; FIG. 41 illustrates a ROCm implementation of a software stack of FIG. 39, according to at least one embodiment; FIG. 42 illustrates an OpenCL implementation of a software stack of FIG. 39, according to at least one embodiment; FIG. 43 illustrates software supported by a programming platform, according to at least one embodiment; and FIG. 44 illustrates compiling code for execution on programming platforms of FIGS. 39-42 in accordance with at least one embodiment.DETAILED DESCRIPTIONIn the following description, numerous specific details are set forth in order to provide a more thorough understanding of at least one embodiment. However, it will be apparent to those skilled in the art that the inventive concepts may be practiced without one or more of these specific details.In a data center, developers and / or users may process a huge amount of data that is too large to be stored on a single memory or a collective memory of a group of compute nodes (e.g., in the data center). Therefore, the data may be physically and / or logically distributed. For example, the data may be physically and / or logically distributed across one or more different systems and / or across multiple types of memory. The referenced data may be stored locally and / or decentrally and in a volatile memory and / or a data memory (e.g., a non-volatile memory). Moreover, the data may be stored in one or more formats, e.g., in one or more formats used by a simple storage service ("S3"), objects, files, etc., and / or stored by various systems (e.g., from various providers).As more and faster processors are used to improve computing power, it may happen that these processors need to wait for data if data access is not fast enough (referred to as "data starving"). Traditionally, to avoid data shortage, data access rates have had to increase in proportion to improved processor performance. Data access performance may be measured as the number of input / output operations per second ("IOPS"). Unfortunately, synchronization between concurrent processes, low throughput of conventional operating systems and network services, and / or limited bandwidth of connections can negatively impact data access performance.FIG. 1A is a block diagram illustrating an example system 100 that may be used to implement an architecture 102 (see FIG. 1B ), in accordance with at least one embodiment. FIG. 1B is a block diagram illustrating the architecture 102, according to at least one embodiment. The architecture 102 may be used by an application 146 to access data that is too large for one or more of the nodes 120 (see FIG. 1A ) executing the application 146, using "load and store" instructions or operations, which may also be referred to as "load / store" instructions. Load / store instructions move data between memory on / executing the application 146 and one or more registers of / executing the application 146. If data cannot be accessed with the load / store instructions, the application 146 may use a client API 150 to access the data. The client API 150 may be executed by one or more PPUs 132 (see FIG. 1A ) and may be used to access volatile memory and / or nonvolatile data storage that is local and / or remote with respect to the node / s executing the application 146. The architecture 102 may achieve high IOPS values, particularly in fine-grained (fine-trained) accesses. Such access may be performed by one or more computing accelerators, such as the PPU(s) 132. In such embodiments, the client APl 150 may be used to perform many (e.g., at least 100) parallel data accesses, which may be particularly advantageous when accessing relatively small amounts of data (e.g., data small enough to perform at least 100 parallel data accesses in parallel on multiple threads within a node or in parallel by the node / s implementing / en the application 146). For example, the client APL 150 may be used to perform at least 100, at least 1,000, or any number of desired parallel data accesses. At least in some of the nodes 120, computing accelerators such as the PPU(s) 132 may be used to initiate data access (e.g., data storage) and perform network I / O. Thus, in at least one embodiment, architecture 102 may be used to perform GPU-initiated data access with respect to local(s) and / or remote(s) memory(s) and / or data storage. Using the PPU(s) 132 to initiate data access may help avoid data shortage within the system 100 (see FIG. 1A ).The storage and / or storage accessed by the client API 150 may be organized into one or more data planes. For example, a first data plane may include volatile memory (e.g., CPU memory, PPU memory, GPU memory, and / or the like) residing on the node / s that implement / en the application 146. A second data plane may include volatile memory (e.g., CPU memory, PPU memory, GPU memory, and / or the like) residing on one or more of the nodes 120 (see FIG. 1A ) that implement / enact a server 154. A third level of data may include non-volatile memory (e.g., one or more non-volatile memory express ("NVMe") devices and / or the like) residing on the node / s implementing / en the server 154. A fourth level of data may include non-volatile memory (e.g., one or more NVMe devices and / or the like) present in the system 100, but not located on the node / s implementing / en the server 154. A fifth level of data may include nonvolatile memory (e.g., remote memory 182) present in one or more backup storage systems 180. As a non-limiting example, the application 146 may access the memory and / or storage at one of the data levels by providing a key to the client API 150 that the client API 150 uses to view the value corresponding to the key. The key may be associated with or identify particular data, and the value may indicate where the data may be retrieved from the client APl 150. In addition to or in place of a key-value relationship, a memory interface and / or a graph view interface may be used.One or more of the data planes may include one or more devices previously used only for persistent non-volatile storage. Such devices may not have been conventionally used in a caching role and / or may be addressed as a volatile memory. Application 146 may use client APl 150 to access such devices as being a cache stored in volatile memory. Thus, the client API 150 may make data stored in any memory and / or storage appear to the application 146 as if the data is stored in volatile memory on the node / s implementing / en of the application 146.Because the applications executed by the system 100 may use the client API 150 to access data, the client APl 150 may be used to improve and / or optimize data operations (e.g., storage, retrieval, update, etc.). For example, the client API 150 may use one or more transformations to improve and / or optimize data operations. The transformation(s) may be controlled by one or more agents other than the application 146, e.g., an administrator of the data center (e.g., arranging encryption, etc.).Referring to FIG. 1A, the system 100 may include one or more computing devices 104. As a non-limiting example, the computing device(s) 104 may be part of a data center 106, cloud computing system, and / or the like. If the computing device(s) 104 includes (include) multiple computing devices, the computing device(s) 104 may be connected together to form an internal network 108. The internal network 108 may include one or more network devices (not shown), such as switches and / or routers, that route the data traffic on the internal network 108 to and from one or more of the computing device(s) 104. The network device(s) (not shown) may / may route the traffic between two or more of the plurality of servers, for example. The computing device(s) 104 may each implement one or more nodes 120.The computing device(s) 104 may be / may be connected (e.g., via the internal network 108) to an external network 110 (e.g., the Internet) that connects one or more external computing devices 114 to the computing device(s) 104. The computing device(s) 104 and / or the internal network 108 may be connected to the external network 110 via one or more network gateway devices 112 that forward traffic between the external network 110 and the computing device(s) 104 (e.g., via the internal network 108). The network gateway device(s) 112 may / may be characterized as providing an interface between the external network 110 (e.g., the Internet) and the computing device(s) 104 (e.g., via the internal network 108).In at least some embodiments, architecture 102 (see FIG. 1B ) is implemented as a federation architecture. A federation architecture includes two or more separate networks and / or two or more computer systems sharing resources (e.g., memories, network services, and / or gateways) managed by a management framework 116 that passes through consistent configuration and policies. For example, within the architecture 102, the computing device(s) 104 and the external computing device(s) 114 may share memory and / or storage resources.Each of the nodes 120 may include or have access to one or more processors 122, a memory 124, and a network interface 128. The processor(s) 122 may include one or more central processing units ("CPU(s)") 130 and / or one or more parallel processing units ("PPU(s)") 132, such as one or more graphics processing units ("GPU(s)") or other suitable processing units that may be used to execute various methods in parallel. The processor(s) 122 may be / may be implemented, for example, by a main CPU complex, one or more microprocessors, one or more microcontrollers, the PPU(s) 132 (e.g., GPU(s)), one or more computing devices ("DPU(s)"), one or more arithmetic logic units ("ALU(s)"), and / or the like. The memory 124 (e.g., one or more non-transitory processor readable media) may store processor executable instructions 134, which when executed by the processor(s) 122, implement at least a portion of the architecture 102 and / or the like. For example, the instructions 134 may include the modules 604- 610 (see FIG. 6 ). As further non-limiting examples, the memory 124 (e.g., one or more non-volatile processor readable media) may be implemented using volatile memory (e.g., dynamic random access memory ("DRAM")) and / or non-volatile memory (e.g., hard disk, solid state device ("SSD"), and / or the like). The processor(s) 122 may include one or more circuits that execute at least a portion of the instructions 134 stored in the memory 124. The network interface 128 may include a network interface card ("NIC"), a network interface controller, a network adapter, and / or the like. At least some of the nodes 120 may use their respective network interfaces to communicate with each other over the internal network 108. At least some of the nodes 120 may use their respective network interfaces to communicate with the external computing device(s) 114 via the external network 110. The processor(s) 122, the network interface 128, and / or the memory 124 may communicate with each other via one or more connections 136, for example, via a bus, a peripheral component interconnect express ("PCIe") connection (or a bus), and / or the like.Within the architecture 102 (see FIG. 1B ), the PPU(s) 132 (e.g., GPU(s)) of at least some of the nodes 120 may directly initiate data access (input and / or output) to and / or from one or more memories and / or one or more data memories. In at least one embodiment, PPU(s) 132, rather than CPU(s) 130, may decide when to access memory and / or data store and which data to access. Such access may support higher throughput (e.g., a larger number of IOPS) for large amounts of small data access requests. Such access may be used to refer to a data space that exceeds the available storage space of the PPU(s) 132 and / or the available storage space of a distributed set of CPUs.Referring to FIG. 1B, the architecture 102 includes a collection of one or more hardware and / or software computing devices (e.g., one or more of the computing device(s) 104) shown in FIG. 1A having instructions (e.g., the instructions 134 shown in FIG. 1A ) that, when executed, perform one or more communication methods such as those described herein. In at least one embodiment, architecture 102 is a software program executing on computer hardware, an application executing on computer hardware, and / or variations thereof. One or more methods of the system 100 are performed by any suitable processing system or unit (e.g., a graphics processing unit (GPU), a general purpose GPU (GPGPU), a parallel processing unit (PPU), a central processing unit (CPU)), a computing unit (DPU), and / or the like) as described below, and in any suitable manner, including sequentially, in parallel, and / or variations thereof.In at least one embodiment, architecture 102 may be implemented, at least in part, by modules (e.g., modules 604- 610 shown in FIG. 6 ), at least a portion of which may be included in instructions 134 (see FIG. 1A ) stored in each of nodes 120 (see FIG. 1A ). A module includes any combination of any type of logic (e.g., software, hardware, firmware) and / or circuitry configured to perform a function as described. A module includes one or more circuits that are part of a larger system (e.g., an integrated circuit ("IC"), a system-on-a-chip ("SoC"), a CPU, a GPU, a DPU, etc.). A controller includes any combination of any type of logic (e.g., software, hardware, firmware) and / or circuitry configured to perform a function as described. Software includes software packages, code, programming languages, drivers, instructions, instruction sets, or a combination thereof. Hardware includes hardwired circuits, programmable circuits, state machine circuits, fixed function circuits, execution units, firmware with stored instructions executed by programmable circuits, or a combination thereof.In at least one embodiment, architecture 102 includes a machine, where machine includes a module and / or logic unit as further described herein. A component of the architecture 102 includes a module and / or logic unit as further described herein. A machine includes software logic, firmware logic, hardware logic, or a combination thereof configured to provide any function as further described herein. A component of the architecture 102 includes software logic, firmware logic, hardware logic, or a combination thereof configured to provide any function as further described herein. Operations performed by hardware and / or firmware may alternatively be implemented via a software module, which may be configured as a software package, code, and / or instruction set. A logic unit may also use a portion of the software to implement its function.A logic unit includes firmware logic, hardware logic, or a combination thereof configured to provide each function as further described herein. A logic unit includes circuitry that is part of a larger system (e.g., IC, SoC, CPU, GPU, DPU). For example, a logic unit includes logic circuitry for implementing firmware and / or hardware to perform GPU-initiated storage.Referring to FIG. 1B, the architecture 102 may be divided or divided into a user view 140, a planar view 142, and a backup storage view 144. The architecture 102 may use one or more APIs to enable storage and / or retrieval of data initiated by the GPU and perform other operations. One or more applications (e.g., application 146) execute within user view 140, and each of the applications may include one or more application interfaces (e.g., application interface 148) that each access data. Thus, various application interfaces (e.g., preferably by the application(s)) may access data within the architecture 102. The application(s) may execute one or more work(s) and access data during execution of the work(s).The application(s) and / or user view 140 may abstract the storage location(s) of the accessed data. The application(s) may / may relate, for example, to one or more storage locations using one or more variable names defined by the application 146 (e.g., by a user). At least a portion of the data may be stored in a memory (e.g., volatile memory) and / or a data store (e.g., non-volatile memory). At least a portion of the data may be stored locally and / or decentrally.The application 146 may send a request to the planar view 142 to access data when the application 146 cannot access the data by using at least one direct memory load / store instruction (e.g., moving data between the memory 124 of the node 120 implementing the application 146 and one or more registers). In other words, the application 146 may send the request when the particular data is not stored in one or more registers or in the memory 124 (e.g., a "get" operation) or, in the case of a "put" operation, is too large to be stored in one or more registers or in the memory 124. For example, the particular data may be stored in distributed storage and / or storage (e.g., because the data is too large to be stored in the memory 124 of the node / nodes that implement / en the application 146, and / or in the registers of the node). In such embodiments, the data may be stored in one or more memory(s) or storage locations associated with one or more nodes that do not implement the application 146.The planar view 142 is disposed between the user view 140 and the backup storage view 144. The planar view 142 locates data requested by the application(s) (e.g., application 146) via the data planes and performs data access. Thus, the planar view 142 may implement the abstraction of the data storage locations provided by the user view 140, which may allow the application interface(s) (e.g., the application interface 148) to perform memory, network, and / or memory accesses. The memory and / or storage accessed by the planar view 142 may be of any size and may include any number of planes and / or devices.The planar view 142 may be implemented, at least in part, by a library and / or the client API 150. The application(s) may / may use a library and / or the client API 150 to access particular data. The client APl 150 may be used to access data storage (e.g., non-volatile storage), storage (e.g., volatile storage) to obtain data, key values, files, objects, and / or the like. For example, the applications may use the client APl 150 to access data stored in CPU memory, GPU memory, block memory, object memory, file memory, and / or the like.Planar view 142 includes one or more clients (e.g., client 152) and / or one or more servers (e.g., server 154). The library and / or client APl 150 may implement the client(s) (e.g., client 152). The planar view 142 may also include a local non-volatile memory 156, which may implement remote private storage. The client(s) receives (receive) data access requests from one or more requesters, such as the application interface(s) (e.g., application interface 148). The client(s) may(s) translate the abstract storage locations used by the application interface(s) (e.g., the application interface 148) to obtain addresses or storage locations usable by the server(s) and may(s) forward the usable storage locations to the server(s) along with a data access request. For example, the client 152 may include and / or access information mapping application-defined variable names (e.g., defined in a global namespace) to storage locations or addresses of the corresponding underlying data. The client(s) (e.g., client 152) may / may each include a client interface 158, one or more client PPU caches 160 (e.g., stored in a PPU memory), and one or more optional client CPU cache(s) 162 (e.g., stored in a CPU memory). The client interface 158 may include a PPU cache manager 164. The PPU cache manager 164 may use the translated memory locations to access the client PPU cache(s) 160 and / or the optional client CPU cache(s) 162 when the translated memory locations indicate that the data is stored therein. On the other hand, if the translated memory locations indicate that the data is not stored in either the client PPU cache(s) 160 or the optional client CPU cache(s) 162, the PPU cache manager 164 may send a data access request to the server / s.The client(s) or portions thereof may be implemented by the PPU(s) 132 of the respective node / node 120 implementing / en. Thus, the application(s) may send data access requests directly to the PPU(s) 132, which may translate the data access requests to determine data storage locations, and either locally access the data or forward data access requests including the translated data access requests to the server(s).The server(s) (e.g., server 154) implements (implement) one or more services or processes that execute the data access requests (e.g., write and / or read operations). The server / s may each include a server interface 170, one or more optional server PPU cache(s) 172 (e.g., stored in a PPU memory), one or more optional server CPU cache(s) 174 (e.g., stored in a CPU memory), and optional nonvolatile memory 176 (e.g., one or more SSDs, a dedicated local NVMe memory, and / or the like). The server interface 170 may include a global dispatcher 166 and a disk cache agent 178.The planar view 142 may be used to format data or otherwise adjust the memory to achieve the desired performance and / or spatial efficiency. For example, the client 152 may compress and / or encrypt the data before it is stored. Moreover, a particular format used in volatile memory or non-volatile memory within the planar view 142 may be tailored for performance and / or efficient resource usage based on one or more APIs used to interact with the user view 140 and / or one or more APIs and / or data formats used in the backup storage view 144.Backup storage view 144 includes backup storage system(s) 180 that stores / stores data external to system 100 (see FIG. 1A ) in remote storage 182, which may include remote file and / or object storage. The backup storage system(s) 180 may / may be implemented by the external computing device(s) 114 (see FIG. 1A ). The backup storage system(s) 180 may(s) store data in the form of files, objects, key values, and / or the like. As mentioned above, the user view 140 may abstract the location(s) of the accessed data. Thus, the user view 140 may abstract storage locations within the local non-volatile memory 156 and / or the remote memory 182. The client(s) may / may translate the abstract storage locations used by the application interface(s) (e.g., application interface 148) to obtain addresses or storage locations usable by the server(s). The server / s may use the translated memory locations to access the optional server PPU cache(s) 172, the optional server CPU cache(s) 174, the optional nonvolatile memory 176, and / or the local nonvolatile memory 156. To access data stored in the remote memory 182, the server / servers may translate the translated memory locations received from the client(s) to obtain addresses or memory locations usable by the backup storage system(s) 180, and may / may forward data access requests to the backup storage system(s) 180 executing the backup storage system(s) 180. The server / s can / can be used to access any type of backup storage system without making changes to the backup storage system. The server(s) (e.g., server 154) may interact (may) with the backup storage system(s) 180 by applying (applying) any method including, for example, a pre-charge method, a periodic charge / spill method, and / or a fully dynamic continuous remote access method.The application(s) and / or user view 140 may use the planar view 142 to access data stored in one or more devices previously used only for persistent non-volatile storage. These devices may be components of the planar view 142 and / or the backup storage system / s 180. The planar view 142 may make such devices appear to the application(s) and / or the user view 140 as if the devices were performing a caching function. Thus, from the view of the application(s) and / or user view 140, non-volatile memory may be accessed as if the memory were a cache stored in volatile memory. In other words, within the architecture 102, all memory and storage (e.g., at all data levels) may be accessed via the planar view 142, and the client interface 158 may make the (non-volatile) memory (storage) appear as being a (volatile) memory (memory). In at least some of the nodes 120, computing accelerators, such as the PPU(s) 132, may be used to initiate data access (e.g., data storage) and perform network I / O.Within the architecture 102, the instructions 134 (see FIG. 1A ) of the node / s (e.g., one or more of the nodes 120 shown in FIG. 1A ) implementing an application (e.g., the application 146) may include application instructions that, when executed by the processor(s) 122 of the node / s, implement the application. The instructions may also include the client API 150. The instructions 134 of the node / s (e.g., one or more of the nodes 120) implementing a client (e.g., the client 152) may include client instructions (e.g., the client API 150) that, when executed by the processor(s) 122 of the node / s, implement the client. The instructions 134 of the node / s (e.g., one or more of the nodes 120) implementing a server (e.g., the server 154) may include server instructions that, when executed by the processor(s) 122 of the node / s, implement the server.The application(s), client(s) and / or server / s may each be implemented with one or more computing devices and / or one or more virtual machines ("VM(s)"). The client(s) and / or the server / s may be / may each be implemented by one or more of the nodes 120 (see FIG. 1A ). The application 146 may be executed by the same node implementing the client 152, the same node implementing the server 154, or by another one or more of the nodes 120. The client(s) and the server(s) (e.g., the client 152 and the server 154) may be isolated from each other (e.g., implemented on different ones of the nodes 120) to provide resource independence and / or security isolation. Alternatively, the client 152 and the server 154 may be executed by the same node or nodes. The client 152 and / or the server 154 may be executed by any number of nodes 120. Multiple ones of the applications may execute on one or more nodes, multiple ones of the clients may execute on one or more nodes, and / or multiple ones of the servers may execute on one or more nodes. The client interface(s) may / may be isolated from the server interface(s) (e.g., implemented on different nodes 120). The client interface(s) may therefore be characterized as being remote from the server interface(s).The application(s) may be associated with a library (e.g., client API 150) that implements client 152. Thus, in at least one embodiment, application 146 and client 152 may be implemented by the same process. The server 154 may be implemented by a process different from the process implementing the application 146 and the client 152. As another non-limiting example, the client 152 may be implemented in a daemon that may be invoked by the application 146. Thus, the application 146 may not be connected to the client 152 but may invoke the client 152 that may be implemented by a process different from the process that implements the application 146.Referring to FIG. 1A, when the processor(s) 122 of the node / node(s) (e.g., one or more of the nodes 120) executing / executing the application 146 determines / determine that the application 146 cannot access particular data by using at least one direct memory load / store command, the application interface 148 may invoke a function within the client APl 150 requesting access to the particular data. The request is received by the client interface 158 implemented by the client API 150 and forwarded to the PPU cache manager 164. The client interface 158 and / or the PPU cache manager 164 may translate the request to determine data locations.The client interface 158 may translate the data storage location and send an access request for the translated data storage location to the server interface 170 of one of the servers 154. Optionally, the server interface 170 may translate the data storage location included in the request to obtain a translated data storage location that the server interface 170 uses to access the data. Then, the server interface 170 sends an acknowledgement or notification to the client interface 158 that can notify the application interface 148 that the data has been accessed and / or sends the portion of the data to the application interface 148.The client(s) may / may send one or more data access requests to the client(s) itself. During asynchronous data access, for example, client 152 (e.g., executed by a first process or thread executed by PPU(s) 132) may generate a new data access request and invoke the function within client APl 150 requesting access to data. The function may cause execution of a second process or thread by the PPU(s) 132. The first thread may query to determine when the second thread has completed data access. As another non-limiting example, two or more of the clients may communicate directly with each other. Thus, a first client may send one or more data access requests to a second client. The second client may inform the first client when the data access is completed.As mentioned above, the architecture 102 includes one or more interfaces, such as the application interface 148, the client interface 158, and the server interface 170. For example, the application interface 148, the client interface 158, and / or the server interface 170 may each be implemented as an interface, as shown in FIGS. 8-44. The application interface 148 may enable interactions between hardware and / or software to perform, for example, one or more operations.The client PPU cache(s) 160, optional client CPU cache(s) 162, optional server PPU cache(s) 172, and / or optional server CPU cache(s) 174 may be stored in volatile memory. The client interface 158 may access data stored in the client PPU cache(s) 160 and / or the optional client CPU cache(s) 162. The server interface 170 may access data stored in the optional server PPU cache(s) 172 and / or the optional server CPU cache(s) 174. The server 154 may access the optional non-volatile memory 176 and / or the local non-volatile memory 156 (e.g., one or more remote SSDs, a dedicated remote NVMe, and / or the like). The server interface 170 may access data stored in the local non-volatile memory 156 and / or the optional non-volatile memory 176 (e.g., according to a protocol such as using NVMe). The server interface 170 may access the remote storage 182 via a protocol (e.g., NVMe) and / or via the backup storage system(s) 180. The remote memory 182 may be stored by one or more devices or devices that may have specialized hardware interfaces to the underlying data storage media, and the specialized hardware interfaces may increase the number of IOPs available for performing interactions and / or data access. With respect to the client interface 158, the client PPU cache(s) 160 and optional client CPU cache(s) 162 may be implemented on the same node that implements the client interface 158. With respect to the client interface 158, the optional server PPU cache(s) 172 and optional server CPU cache(s) 174 may also be implemented on another node that implements a particular server interface.Execution of the application 164 may be suspended and resumed on one or more different computing device(s) 104 and / or one or more nodes 120. In other words, the application 146 may be migrated (e.g., by a hypervisor) within the system 100. During such migration, only application 164 may be suspended and resumed. As another non-limiting example, the application 146 and one or more of the clients (e.g., the client 152) used by the application 146 may be suspended and resumed during migration. In a further non-limiting example, the application 146, one or more of the clients used by the application 146 (e.g., the client 152), and one or more servers used by the application 146 (e.g., the server 154) may be suspended and resumed during migration. Moreover, the client(s) (e.g., client 152) may / may provide data to application 146 by using / using hardware (e.g., volatile memory) that is different from the hardware enabled during migration. Any data stored on the hardware to be released during migration may be stored and restored elsewhere.The system 100 (see FIG. 1A ) performs a method including launching at least one process on at least one PPU (e.g., the PPU(s) 132) and using the server interface 170 implemented by at least one process to access the data from at least one memory and / or storage location and / or perform operations otherwise described herein. The system 100 may perform a method 700 (see FIG. 7 ) that stores data based at least in part on at least one protocol. The system 100 may include hardware and / or be used in conjunction with the hardware illustrated in FIGS. 8-44, for example, to access data and / or otherwise perform operations described herein.FIG. 2 is a block diagram illustrating example components 200 that may be used to implement architecture 102 (see FIG. 1B ), in accordance with at least one embodiment. The example components 200 may include a collection of one or more hardware and / or software computing resources with instructions that, when executed, perform one or more communication methods as described herein. In at least one embodiment, example components 200 are components of one or more software programs executing on computer hardware, one or more applications executing on computer hardware, and / or variations thereof. One or more methods of the example components 200 are performed by any suitable processing system or unit (e.g., a GPU, GPGPU, PPU, CPU, DPU, and / or the like) as described below, and in any suitable manner, including sequentially, in parallel, and / or variations thereof.The application 146 accesses a particular one of the client interface(s) (e.g., the client interface 158) via the client APl 150 by invoking functions (e.g., CUDA functions) that, when executed by the PPU(s) 132 (see FIG. 1A ), perform memory input and / or output operations (e.g., read instructions, put instructions, and / or the like) depicted in FIG. 3 as input and / or output ("I / O") processing operation(s) 310H. Referring to FIG. 2, the client interface 158 may access a particular one of the server interface(s) (e.g., the server interface 170), which in turn may access the remote memory 182 and / or the backup storage system(s) 180. As needed, one or more first translation operations (e.g., API / xlate 210A) may be used to enable communication between the application interface(s) 148 and the client interface(s) 158, and / or one or more second translation operations (e.g., xlate 212G) may be used to enable communication between the server interface(s) 170 and the backup storage system(s). Thus, the server interface(s) 170 may / may be used by different applications to access data stored in any number of different backup storage systems 180. The client interface(s) 158 may each include one or more operations that use an API (e.g., to invoke an API function) to access at least a portion of the first translation operation(s). The first translation operation(s) may / may map (e.g., using an API) the storage location provided by the application interface 148 to a translated storage location accessible to the client interface 158 and / or the server interface 170. For example, the application interface 148 may provide a key to the client interface 158 that the first translation operation(s) may convert or otherwise translate to a value (e.g., a data storage location). The first translation operation(s) may / may map a first value (e.g., a key), which may be, e.g., an IP address, a storage field, a URL, an HTTP value, or any other value, to a second value, such as an IP address, a storage field, a URL, an HTTP value, or any other value. The first translation operation(s) (e.g., the API / xlate 210A) may / may be performed based at least in part on a translation type, interface information, an IP address, and / or other information that may be used to perform the translation.The client interface 158 may include and / or have access to an API and / or the first translation operation(s) (e.g., the API / xlate 210A), data access operations (e.g., get / put 210B) using the translated output of the first translation operation(s), the client PPU cache(s) 160, (a) pre-processing operation(s) 210D, and a request-response service 210E. The data access operations (e.g., get / put 210B) and / or the request response service 210E may be provided by the PPU cache manager 164 (see FIG. 1B ). The client interface 158 may not have direct access to the local non-volatile memory 156 (e.g., remote private memory) and / or the remote memory 182 implemented by the backup storage system(s) 180. Instead, the client interface 158 may communicate with the server interface 170 that communicates with the local non-volatile memory 156 (e.g., using NVMe, remote direct memory access ("RDMA")), the remote memory 182 stored by the backup storage system(s) 180. Communication with the remote memory 182 may be via, for example, an S3 interface. An RDMA may be used to transfer data between the client interface 158 and the server interface 170.Within the system 100 (see FIG. 1A ), the data storage and transmission may be performed, for the most part, by the client interface(s) (e.g., the client interface 158) and / or the server interface(s) (e.g., the server interface 170), which are performed (e.g., in one or more user spaces) isolated from each other to protect the server interface(s) from the application(s) (e.g., the application 146). The server interface(s) 170 may include query service operations 212A serving data requests, compute operations 212B for computing data, at least one optional cache 212C (e.g., the optional server PPU cache(s) 172 and / or the optional server CPU cache(s) 174), preprocessing operations 212D, a query response service 212E, a memory interface 212F, and / or the second translation operation(s) (e.g., thexlate 212G). The global dispatcher 166 may execute the request response service 212E and use the request response service 212E to access the server PPU cache(s) 172, the server CPU cache(s) 174, the local non-volatile memory 156, the optional non-volatile memory 176, and / or the remote memory 182. The computational operations 212B may perform an extraction and / or transformation of the data. The computational operations 212B may compute at least a portion of the requested data.For example, if the client 152 determines that the data is stored at one or more particular locations (e.g., the optional server PPU cache(s) 172, the optional server CPU cache(s) 174, the optional non-volatile memory 176, the local non-volatile memory 156, and / or the remote memory 182), but only a portion of the data is actually stored at the particular location(s), the server 154 may use the computational operations 212B to calculate the portion not stored at the particular location(s). Global dispatcher 166 and / or disk cache agent 178 may perform compute operations 212B. The disk cache agent 178 may perform the memory interface 212F and / or the second translation operation(s) (e.g., the disk 212G), and may use the memory interface 212F and / or the second translation operation(s) to access the remote memory 182.In at least one embodiment, client 152 may perform at least a portion of compute operations 212B. For example, if the client 152 determines that the data is stored at one or more particular location(s) 160 (e.g., the client PPU cache(s) and / or the optional client CPU cache(s) 162), but only a portion of the data is actually stored at the particular location(s), the client 152 may use the compute operations 212B to compute the portion not stored at the particular location(s).In the illustrated embodiment, the compute operations 212B occur within the planar view 142, but in some embodiments, at least a portion of the compute operations 212B may be performed by the backup storage view 144. For example, if the client 152 determines that the data is stored in the remote memory 182, but only a portion of the data is actually stored in the remote memory 182, one or more of the backup storage systems 180 may use the computational operations 212B to compute the portion that is not stored in the remote memory 182.The client 152, the server 154, and / or the backup storage system(s) 180 may (may) use the compute operations 212B to compute a portion of the data for which access was requested if the client 152, the server 154, and / or the backup storage system(s) 180 determines (determine) that access to the data would take too long (e.g., if the data access took more than a threshold time).Execution of the client and server interfaces 158 and 170 in user areas (e.g., rather than kernel mode) may be advantageous for parallelism and throughput of the computing device(s) 104 (see FIG. 1A ). The client interface 158 and / or the server interface 170 may be adapted to achieve desired data storage and transfer objectives, such as efficient data transport and / or storage. The use of the PPU(s) 132 (see FIG. 1A ) to access the data and decouple the user view 140, the planar view 142, and the backup storage view 144 from each other may enable parallelism (e.g., 64 queues of up to 64k instructions per queue) while accessing the local nonvolatile memory 156 (e.g., remote private memory) and / or the remote memory 182 implemented by the backup storage system(s) 180.In at least one embodiment, a requester (e.g., application interface 148, client interface 158, and / or the like) may call client interface 158 that may receive input data immediately (e.g., from client PPU cache(s) 160, optional client CPU cache(s) 162, and / or server interface 170), and provide input data to requester. As mentioned above, the PPU(s) 132 may process the request received from the client interface 158 and, if desired, forward a data access request to the server interface 170 (which may be done by the PPU(s) 132 of a node that is separate from the node executing the client 152). In such embodiments, a thread or process that requested the data (e.g., from the server interface 170) may simply wait until the data is received, which may be referred to as synchronous data access. On the other hand, a first thread or process may cause another second thread or process to be created that requests and waits for the data as the first thread or process continues to run, which may be referred to as asynchronous data access. The client interface 158 asynchronously provides a notification (e.g., about success, failure, etc.) to a recipient (e.g., the data), and the requester may query a particular location for the notification. The recipient may be a consumer of the data accessed by the client 152 and / or the server 154.At least in certain circumstances, the client interface(s) 158 may access input data without including the server interface(s). For example, if the input data is stored in the client PPU cache(s) 160, the client interface 158 may provide the input data to the recipient(s) from the client PPU cache(s) 160 without including any of the server interface(s). As another non-limiting example, if the optional client CPU cache(s) 162 is / are present and the input data is stored in the optional client CPU cache(s) 162, the client interface 158 may obtain the input data from the optional client CPU cache(s) 162 and provide the input data to the recipient(s) without including any of the server interfaces. If the input data is not stored in the client PPU cache(s) 160 or the optional client CPU cache(s) 162, the client interface 158 may request the input data from the server interface 170. The server interface 170 may obtain the input data from the optional server PPU cache(s) 172, the optional server CPU cache(s) 174, the optional non-volatile memory 176, the local non-volatile memory 156 (e.g., a remote private memory), and / or the remote memory 182 implemented by the backup storage system(s) 180. The client PPU cache(s) 160 may be(are) characterized as communicating with, and / or being (are) supported by, the optional client CPU cache(s) 162, the optional server PPU cache(s) 172, the optional server CPU cache(s) 174, the optional nonvolatile memory 176, the local nonvolatile memory 156 (e.g., a remote private memory), and / or the remote memory 182 implemented by the backup storage system(s) 180.After the server interface 170 receives the input data, the server interface 170 may transmit the input data to the client interface 158. The client interface 158 may communicate the completion message to the recipient. For example, the recipient may be the requester, and the client interface 158 may communicate the completion to the requester (e.g., the application 146 executing on the user view 140). The requester may be a CUDA kernel function executing on a GPU (e.g., one of the PPU(s) 132).The system 100 (see FIG. 1A ) may perform a method including launching at least one process on at least one PPU (e.g., PPU(s) 132) shown in FIG. 1A and using the server interface 170 implemented by at least one process to access and / or otherwise perform operations described herein the data from at least one storage location (e.g., the optional server PPU cache(s) 172, the optional server CPU cache(s) 174, the optional nonvolatile memory 176, the local nonvolatile memory 156, and / or the remote memory 182). For example, a system 100 is further illustrated in FIGS. 1B-6 for accessing data (e.g., from at least one storage location and / or at least one storage location) and / or for performing operations otherwise described herein. The system 100 may perform a method 700 (see FIG. 7 ) of storing data based at least in part on one or more protocols. The system 100 may include hardware and / or be used in conjunction with the hardware illustrated in FIGS. 8-44, for example, to access data and / or otherwise perform operations described herein.FIG. 3 is a block diagram illustrating example components 300 that may be used to implement level view 142, according to at least one embodiment. As shown in FIG. 3, the client interface 158 may include the first translation operation(s) (e.g., API / xlate 310A), the data access operations (e.g., get / put 310B) performed using the translated output of the first translation operation(s), the client PPU cache(s) 160, and the I / O processing operation(s) 310H. In the depicted embodiment, the client PPU cache(s) 160 may include a PPU memory cache 310C and / or a PPU data cache 310D. I / O processing operation(s) 310H may be performed by request response service 210E (see FIG. 2 ), which may be provided by PPU cache manager 164 (see FIG. 1B ). I / O processing operation(s) 310H may include pre-processing operations 210D (see FIG. 2 ).The server interface 170 may include cache pre-processing 310E, optional server PPU cache(s) 172, local memory (e.g., NVMe) pre-processing 310Q, import and / or export operations 310R to be performed with respect to the local non-volatile memory 156, a memory interface 310F, and / or the second translation operation(s) (e.g.,xlate 310G). Global dispatcher 166 (see FIG. 1B ) may perform cache pre-processing 310E and determine when to forward a request to disk cache agent 178. Cache pre-processing 310E may include query service operations 212A (see FIG. 2 ) and compute operations 212B (see FIG. 2 ). In the depicted embodiment, the optional server PPU cache(s) 172 may include a PPU memory cache 310J and / or a PPU data cache 310L. The server 154 may include a CPU memory 310M that may store the optional server CPU cache(s) 174. In the illustrated embodiment, the optional server CPU cache(s) 174 / s includes a CPU memory cache 310N and / or a CPU data cache 3100. The CPU memory 310M may store operations for performing memory management (e.g., a write coalescer 310P). The disk cache agent 178 (see FIG. 1B ) may perform the local memory preprocessing 3100 and / or the import and / or export operations 310R, which may be components of the request-response service 212E (see FIG. 2 ). The disk cache agent 178 may use the local memory preprocessing 310Q and / or the import and / or export operations 310R to access the local non-volatile memory 156 and / or the optional non-volatile memory 176. The disk cache agent 178 may perform the memory interface 310F and / or the second translation operation(s) (e.g., thexlate 310G), and may use the memory interface 310F and / or the second translation operation(s) (e.g., thexlate 310G) to access the remote memory 182.When implemented by the PPU(s) 132 (see FIG. 1A ), the server interface 170 may directly initiate access to memory and / or storage, where the PPU(s) 132 is / are an agent that decides / n when and which data to access. PPU-initiated storage (e.g., initiated by one or more GPUs) may support higher throughput (e.g., measured in IOPS) for large amounts of data that reference a data area that exceeds the space available in GPU memory (e.g., volatile memory) and / or is available in a distributed set of volatile CPU memory (e.g., volatile and / or nonvolatile memory).As mentioned with reference to FIG. 1B, an RDMA may be used to transfer data between the client interface 158 and the server interface 170. Moreover, one or more storage backups (e.g., by the RDMA) may be used to isolate the client interface 158 from the server interface 170. For example, local non-volatile memory 156 (e.g., NVMe memory) may not be directly accessible by one of nodes 120 (see FIG. 1A ) executing a client (e.g., client 152). Communication protocols, such as NVMe protocols, may be extended to increase simultaneity and / or increase IOPs rates for requests sent by PPU processes or threads (e.g., GPU threads). Throughput may be increased with respect to the client PPU cache(s) 160. The PPU(s) 132 (e.g., a GPU) of the node 120 implementing the client 152 may invoke the client API 150 to store and / or access one or more data packets (e.g., received from the network interface 128 of the node 120 implementing the client 152 and / or the application 146). The client PPU cache(s) 160 that may / may be supported by caches 162, 172, and 174, nonvolatile memory 156 and 176, and remote memory 182 may also be supported by a memory system that may extend symmetric hierarchical memory contexts ("SHMEM") contexts) that may include registration of NVMe protocols for a device memory. The NVMe protocols may be modified to increase the simultaneity of PPU processes or threads (e.g., GPU threads).The system 100 may be used to perform one or more operations that may result in optimizations, accelerations, reduced latency, increased security (e.g., by isolating the client 152 with respect to the server 154), failsafety (e.g., abstractions from fault-prone memories), changes in cost (e.g., tiering), increased persistence (e.g., NVMe wear management), and trade-off optimization. The system 100 may perform the access and / or storage of data such that operations performed may be based at least in part on comprehensive tradeoffs in resource management between compute cores or groups of threads on a processor (e.g., CPU, GPU, DPU, or other described processors), memory (e.g., capacity, bandwidth, data mover, or other memory characteristics), and / or memory resources used for optimization.The client interface 158 may be synchronous (e.g., blocking) or asynchronous (e.g., non-blocking). For example, the application 146 may execute one or more processes or threads and request data about each of the threads. The application 146 forwards data requests to the client 152 (e.g., using the client API 150), which in synchronous (e.g., blocking) implementations may keep each thread waiting for the requested data. In some synchronous implementations, the client 152 may wait the thread(s) until the data is available and return an error code indicating whether the data has been successfully accessed (e.g., upon success) or the data access has failed (e.g., upon an error). Thus, processing by the application 146 may be blocked until data is provided or a period of time passes, and the values (e.g., error codes) returned by the client 152 to the application 146 may include error codes that indicate success and / or failure. In some synchronous implementations, the client 152 may end the data access request after a predetermined amount of time if the data is not available. For example, the client 152 may end the data access request when the data is not readily available (e.g., not stored in the client PPU cache(s) 160). Such implementations may return an error code indicating whether the data was successfully accessed (e.g., success), whether the data was not successfully accessed (e.g., failure), or whether the access has continued too long because the data was stored too far (e.g., not in proximity). Thus, the client 152 cannot wait until accessing (e.g., receiving) the data. As further non-limiting examples of synchronous implementations, when the client 152 completes the data access, it may initiate a prefetch operation, thereby making the data more readily available for a subsequent data request (e.g., upon completion of a previous).As mentioned above, the client interface 158 may be asynchronous (e.g., non-blocking). In some asynchronous (non-blocking) implementations, the application 146 may execute one or more processes or threads that each request a single item of data in each of the threads, and the client 152 may generate a notification that is sent to the application interface 148 when the data for all threads has been accessed (e.g., received in registers, memory, or memory accessible by the application 146) or a fault is detected. In some asynchronous (non-blocking) implementations, the application 146 may execute a process or thread that requests a set of data, and the client 152 may generate a notification to send to the application interface 148 when the set of data for the thread has been accessed (e.g., received) or an error has been detected. A thread initiated by the client interface 158 may process and complete the request. For example, the thread may determine that the data is not stored in the client PPU cache(s) 160 (e.g., a GPU cache miss) and may initiate a request to the server 154. The server 154 may optionally generate a data access request to the optional non-volatile memory 176, the local non-volatile memory 156, and / or the remote memory 182. Decoupling execution of this data access request from the request received from application 146 allows the requesting thread of the application to perform other tasks while the data is being processed by server 154. This processing may include retrieving the data and may include performing one or more other operations (e.g., on the data while the data is being read and / or written). As non-limiting examples, the operation(s) may include encryption, decryption, compression, decompression, or any other type of transformation. The message may indicate that these operations have been completed.As mentioned above, a notification may be sent to the application 146 during asynchronous (e.g., non-blocking) operations and may indicate that one or more data items are available or an error has been detected. As non-limiting examples, a notification may include a future (e.g., a C++ future) returned by an API (e.g., client API 150) and / or a variable stored in user-managed storage (e.g., application 146 may provide a pointer to the location at which client 152 is to store the notification or a pointer to the location at which the notification is stored).One or more calls to the client API 150 may each have a unique indicator or share one or more indicators. The indicator(s) may / may indicate where a message is stored. For example, successive data elements (e.g., having a predetermined size) may correspond to successive memory locations, and the successive data elements may each include a unique indicator stored in a corresponding one of the successive memory locations. As a non-limiting example, successive access means may correspond to successive memory locations, and each of the successive access means (e.g., threads) may use an indicator stored in a corresponding one of the successive memory locations. Alternatively or additionally, the successive access means (e.g., threads) may share a single indicator, such as a counter. For example, to share a single indicator, the counter is first set equal to the number of elements / threads sharing the same indicator. The counter may count down to zero or up to zero from a negative number. Thus, multiple calls may be mapped to a common indicator (e.g., stored in a predetermined common memory location), and the common indicator may reference multiple values stored, e.g., in consecutive memory locations.Notifications may include granularities, such as a single data element and / or a collection of data elements (e.g., elements that are stored contiguous to memory and / or stored contiguous to a requesting thread). For example, a bit or variable may be used to indicate a successor error with respect to a single data element. For example, if a bit is used, the message may indicate success if the bit is set to one and may indicate failure if the bit is set to zero. A collection of data items cannot be indicated as complete until all items are available. For example, if the elements are stored continuously in memory, the granularity may vary from one bit to a definable memory block size or other values. If the items are stored contiguous from a requesting thread, the granularity may vary from one warp across a thread block to a user definable granularity. By way of non-limiting example, a user-definable granularity may include an assignment to a particular hierarchical software or hardware construction. In some embodiments, notifications may be provided individually per thread, uniformly over at least a portion of the threads, or any hierarchical combination therebetween.A thread may generate a data access request for data stored in the client PPU cache(s) 160. For example, one or more threads may issue data access requests to the PPU memory cache 310C and / or the PPU data cache 310D (see FIG. 3 ). One or more variables may signal completion of the data access request(s) via a notification. One or more threads may / may synchronously wait for data from a remote source, respond to no data being proximate, and / or pass processing to another thread belonging to an access engine (e.g., client 152), e.g., in a decoupled manner.FIG. 4 is a block diagram 400 illustrating PPU-initiated data access, according to at least one embodiment. In FIG. 4, local non-volatile memory 156 is shown to include one or more native (captiv) local storage devices 412 (e.g., NVMe device(s)), and remote memory 182 is shown to include a file system 414. As described herein, client 152 (shown as arrow 403) (see FIG. 1B ) receives a data access request from a requester or request generator 402 (e.g., application 146, client 152, and / or the like). The PPU cache manager 164 (within the planar view 142) may manage the client PPU cache(s) 160 and access data stored therein. The PPU cache manager 164 may access data stored in the client PPU cache(s) 160 and / or the optional client CPU cache(s) 162 in response to the data access request, and / or may forward a data access request to the server 154 (see FIG. 1B ). When the PPU cache manager 164 accesses the data in the client PPU cache(s) 160 and / or the optional client CPU cache(s) 162, the PPU cache manager 164 may provide a notification and / or accessed data to a PPU (e.g., GPU) consumer 416 (shown as arrow 404).When the PPU cache manager 164 forwards (illustrated arrow 405) the data access request to the server 154 (see FIG. 1B ), the global dispatcher 166 implemented by the server 154 may instruct a CPU 410A and / or GPU 410B to access data stored in the optional server PPU cache(s) 172 (see FIG. 1B ), the optional server CPU cache(s) 174 (see FIG. 1B ), and / or the optional non-volatile memory 176 (see FIG. 1B ). For example, in FIG. 4, arrow 406 illustrates global dispatcher 166 causing access to data in optional server CPU cache(s) 174, and arrow 407 shows a notification and / or the accessed data being provided to PPU consumer 416. If global dispatcher 166 determines that the requested data is not stored at any of these locations, global dispatcher 166 may send a request to disk cache agent 178 (shown as arrow 408) to access the data from own (captive) local device(s) 412 (e.g., local non-volatile memory 156) and / or file system 414 (e.g., remote memory 182). Arrow 409 represents how disk cache agent 178 provides a notification and / or the accessed data to PPU consumer 416.As non-limiting examples, data may be moved within system 100 (see FIG. 1A ) using a request method, a prefetch method, a destage method (spill), and / or a destage and retrieve method (spill and refilling). In performing the request method, the system 100 moves data in direct response to a read or write request. In the pre-fetch method, the system 100 fetches (pre-fetch) data in anticipation of future reads (e.g., sequentially or stepwise). The pre-fetch may be performed according to path-based predictions corresponding to the predictions used for the branch prediction. Which data to use next can be predicted based on the call stack (call stack) and / or using a Kl model as described in Figures 8-44, which can be generalized to a variety of design alternatives. In performing the offload method, the system 100 may write data to the non-volatile memory to create more space in the client PPU cache(s) 160 and / or other caches within the system 100. The system 100 may proactively (e.g., when the available capacity in the client PPU cache(s) 160 has fallen below a threshold) or reactively (e.g., in response to a demand request) perform the offload method. The caches 160, 162, 172, and 174, the nonvolatile memories 156 and 176, and the remote memory 182 may be grouped into levels (tier). For example, a client level may include the client PPU cache(s) 160 and the optional client CPU cache(s) 162, if present. A server level may include caches 172 and 174 (if present), optional non-volatile memory 176 (if present), and local non-volatile memory 156. An external layer may include remote memory 182. In performing the method of swapping and retrieving, the system 100 in the closer layers prefers data that has recently been written and is likely to be reread.The client interface 158 may prefetch data by separating a pending request list from the allocation of memory for the requested data. In this manner, the client 152 may suspend or delay allocation of memory for an pending request so as not to keep (or reserve) a cache line (or space in a cache such as the client PPU cache(s) 160), while waiting for the data to fill the cache line, which could result in a deadlock. Instead, cache lines may be allocated if the data with which they are to be filled has already been returned (or, e.g., just before being returned). In this way, the PPU(s) 132 may wait to allocate storage space in a cache (e.g., the client PPU cache(s) 160) for the data until the server interface 170 accesses the data (e.g., returns the data to the PPU(s) 132 and / or the client API 150). Waiting for the allocation of cache lines may increase throughput for short latency requests and / or avoid delays arising from waiting for long latency requests that are processed in sequence. The client 152 may include one or more pending consumption counters used in pre-fetch. When the client 152 receives a request, it can view a list of pending requests and increment the pending consumption count for that request. The pending consumption counter may be decremented for each pending request when the pending request is completed. The client 152 may wait to release a cache entry or line until the pending consumption counter goes to zero to avoid the possibility of a release just prior to a pending use. One or more APIs may be used to query the pending consumption counter for a particular request or to clear the pending consumption counter when it is determined programmatically that consumption is of low probability or priority. Intermediate phases may be made stateless (e.g., to avoid a wait scenario) by tracking the entire state in a pending request buffer. The size of the pending request buffer may be determined using, for example, Little's Law (Little's Law) (e.g., buffer size>= Ausgabe Rate* Latenzzeit for the service).The client interface 158 may perform transformations on the data, such as moving data between levels (e.g., client level, server level, and / or external level) or to remote storage. Non-limiting examples of such transformations may include encryption, compression, and / or reduction. One or more transformations may be accelerated by the PPU(s) 132 (e.g., a GPU) and / or additional computing elements such as one or more DPU(s). Encryption and compression may be applied to data transferred between levels or data residing in any memory structure including caches (e.g., caches 160, 162, 172, and 174), nonvolatile memories 156 and 176 (e.g., NVMe), and / or remote memory 182. Data stored in or moved between levels may be monitored with one or more applications, e.g., a resource characterization application, a power characterization application, a verification and compliance application, an application that trains data models, and / or an anomaly detection application that uses Kl inference.Referring to FIG. 1B, the system 100 (see FIG. 1A ) may implement a confidential computing environment in which protected data exists in and belongs to a trusted execution environment. The architecture 102 may be used to extend the trusted execution environment to the client 152 and the server 154, such that data stored on the server 154 may be associated with the trusted execution environment that includes the client 152, but not other clients sharing the same server. As another non-limiting example, the application 146 may execute in at least one trusted execution environment and may use the client API 150 to extend one or more of these trusted execution environment(s) to include the client 152, the server 154, the backup storage system(s) 180, and / or other levels (e.g., the server PPU cache(s) 172, the server CPU cache(s) 174, the optional non-volatile memory 176, the local non-volatile memory 156, and / or the remote memory 182).FIG. 5 is a block diagram 500 illustrating a driver and / or runtime environment, including one or more libraries to provide one or more APIs, according to at least one embodiment. One or more software programs 502 may include one or more software modules. The software module is moreover not finally described in FIG. 5. One or more APIs 510 (e.g., the client API 150 shown in FIG. 1B ) may include one or more sets of software instructions, which, when executed, may cause one or more processors (e.g., the processor(s) 122) shown in FIGS. 1B and 6 to perform one or more computational operations. The API(s) 510 may be distributed or otherwise provided as part of one or more libraries 506, runtime environments 504, drivers 504, and / or another grouping of software and / or executable code as further described herein. The API(s) 510 may / may perform one or more computing operations in response to the call by the software program(s) 502 (e.g., the application 146 shown in FIGS. 1B and 2 ). The software program(s) 502 may include a collection of software code, instructions, instructions, or other text sequences to direct a computing device (e.g., one of the computing device(s) 104) to perform one or more computing operations and / or to invoke one or more other sets of instructions, such as the API(s) 510 or API functions 512, for execution. The functionality provided by the API(s) 510 may include software functions 512, such as those that may be used to accelerate one or more portions of the software program / s 502 using one or more PPUs (e.g., the PPU(s) 132), such as one or more GPUs.The API(s) 510 may / may be implemented using hardware interfaces to one or more circuits that may be used to perform one or more computational operations. The API(s) 510 described herein may / may be implemented as one or more circuits to perform one or more methods described in connection with FIGS. 1A-44. The software program(s) 502 may include instructions that, when executed, cause one or more hardware devices and / or circuits to perform one or more methods further described in connection with FIGS. 1A-44.The software program(s) 502, such as user-implemented software programs, may (may) use the API(s) 510 to perform various computational operations, such as a memory reservation, matrix multiplication, arithmetic operations, or any computational operation performed by PPUs (e.g., the (s) PPU(s) 132), such as GPUs, as further described herein. The API(s) 510 may / may provide a set of callable functions 512, referred to herein as APIs, API functions, and / or functions that individually perform one or more computational operations, such as parallel computing related computational operations. For example, in one embodiment, the API(s) 510 provides functions 512 for accessing or storing data in memory.The software program(s) 502 may interact or otherwise communicate with the API(s) 510(s) to perform one or more computational operations using one or more PPUs, such as GPUs. One or more computational operations using one or more PPUs may include at least one or more groups of computational operations that are accelerated by execution at least in part by the one or more PPUs. The software program(s) 502 may interact with the API(s) 510(s) to perform audio-to-text processing.An interface is a software instruction that, when executed, provides access to one or more functions 512 provided by the API(s) 510. The software program(s) 502 may use a local interface when a software developer compiles the software program(s) 502 in conjunction with one or more libraries 506 that include(s) or otherwise provide (provide) access to the API(s) 510. The software program(s) 502 may(s) be statically compiled in conjunction with precompilation libraries 506 or noncompilation source code having instructions for executing the API(s) 510. The software program(s) 502 may(s) be compiled dynamically, and the one or more software programs use a linker to connect to one or more precompilation libraries 506 having the API(s) 510.The software program(s) 502 may use a remote interface when a software developer executes a software program that uses or otherwise communicates with a library 506 having the API(s) 510 via a network or other remote communication medium. One or more libraries 506 may include the API(s) 510 that are executed by a remote computing service, such as a provider of computing services. In another embodiment, one or more libraries 506 comprising the API(s) 510 may be executed by any other computer host that provides the API(s) 510 to the software program(s) 502.A processor (e.g., one or more of the processors 122) may execute or use the software program(s) 502 by invoking, using, executing, or otherwise implementing the API(s) 510 to allocate and otherwise manage memory 514 to be used by the software program(s) 502. The software program(s) 502 may(s) use the API(s) 510 to allocate and otherwise manage memory 514 used by one or more portions of the software program(s) 502 that is(are) accelerated using one or more PPUs, such as GPUs or another accelerator or processor further described herein. The software program(s) 502 may request a neural network to perform data storage and / or access using functions 512 provided by the API(s) 510, in one embodiment.The API(s) 510 includes / do an API to enable parallel computing. The API(s) 510 includes / do any other API that is further described herein. The API(s) 510 may / may be provided by a driver and / or runtime environment 504. The API(s) 510 may / may be provided by a CUDA user mode driver. The API(s) 510 may / may be provided by a CUDA runtime environment. The driver 504 is comprised of data values and software instructions that, when executed, may perform or otherwise enable operation of one or more functions 512 of the API(s) 510 during loading and execution of one or more portions of a software program 502. A runtime environment 504 is comprised of data values and software instructions that, when executed, may perform or otherwise enable execution of one or more functions 512 of the API 510 during execution of the software program / s 502. The software program(s) 502(s) may utilize the API(s) 510 implemented or otherwise provided by the driver and / or runtime environment 504 to perform combined arithmetic operations by the software program(s) 502 during execution by one or more PPUs, such as GPUs.The software program(s) 502 may use the API(s) 510 provided by the driver and / or runtime environment 504 to perform combined arithmetic operations of one or more PPUs, such as GPUs. The API(s) 510 may / may provide combined arithmetic operations by the driver and / or runtime environment 504, as described above. The software program(s) 502 may utilize the API(s) 510 provided by a driver and / or runtime environment 504 to allocate or otherwise reserve one or more blocks of memory 514 to one or more PPUs, e.g., GPUs. The software program(s) 502 may utilize the API(s) 510 provided by the driver and / or runtime environment 504 to allocate or otherwise reserve blocks of the memory 514. The API(s) 510 may call a neural network to perform a function that selects one or more libraries using slit information as described in connection with FIGS. 1A-44.FIG. 6 illustrates example modules 600 that may be executed by the processor(s) 122, in accordance with at least one embodiment. The processor(s) 122 may perform one or more methods as described herein to access data, store data, and / or perform other operations described herein. Processor(s) 122 may execute one or more methods as described herein to access data, store data, and / or otherwise perform operations described herein. The processor(s) 122 may(s) perform the operation of allocating data access and / or storing data by one or more methods as described in connection with FIGS. 1A and 1B. The processor(s) 122 perform(s) one or more methods as described in connection with FIGS. 1A-7.Processor(s) 122 includes(s) one or more processors as described in connection with FIGS. 8-44. The processor(s) 122 may / may be any suitable processing unit and / or combination of processing units, such as one or more CPUs, GPUs, DPUs, GPGPUs, PPUs, and / or variations thereof. The processor(s) 122 includes / have an API module 604, a protocol module 606, a runtime module 608, and / or an encryption module 610. The API module 604, the protocol module 606, the runtime module 608, and / or the encryption module 610 may be distributed among multiple processors that communicate over a bus, network, by writing to shared memory, and / or any suitable communication method as described herein.As used in any implementation described herein, a module refers to any combination of software logic, firmware logic, hardware logic, and / or circuitry configured to provide the functionality described herein, unless context dictates otherwise or expressly indicates the contrary. Software may be embodied as a software package, code, and / or instruction set or instructions, and "hardware" as described herein in one embodiment may include, for example, singly or in any combination, hardwired circuits, programmable circuits, state machine circuits, fixed function circuits, execution units, and / or firmware storing instructions executed by programmable circuits. Modules may be configured collectively or individually as circuits that are part of a larger system, e.g., an integrated circuit (IC), a system-on-a-chip (SoC), etc. A module performs one or more methods in connection with any suitable processing unit and / or combination of processing units, such as one or more CPUs, GPUs, GPGPUs, DPUs, PPUs, and / or variations thereof.The API module 604 is a module that can execute one or more APIs (e.g., the client API 150), e.g., to use an API to perform communication methods, access or store data, and / or perform other operations described herein. The API module 604 may perform one or more methods as described herein by including or otherwise encoding at least instructions that cause or otherwise be used to perform the one or more methods (e.g., by the processor(s) 122). The API module 604 may send one or more notifications (e.g., through one or more systems as described in connection with FIGS. 1A-44). The API module 604 includes performing APIs to store and / or access data. The runtime environment executes the API module 604 as described in connection with FIG. 5.A protocol module 606 is a module that can provide information about one or more protocols for storing and / or accessing data, such as an NVMe protocol described in FIGS. 1A-7. The protocol module 606 may perform one or more methods as described herein by including or otherwise encoding at least instructions that cause or otherwise be used to perform the one or more methods (e.g., by the processor(s) 122). The protocol module 606, in conjunction with the API module 604, may provide information for an API based at least in part on a protocol. The protocol module 606 may indicate methods for storing and / or accessing data based at least in part on a protocol by one or more methods as described in connection with FIGS. 1A-7.The runtime module 608 is a module that may include data storage or access based at least in part on the use of an API. The runtime module 608 can perform one or more methods as described herein by including or otherwise encoding at least instructions that cause or otherwise be used to perform the one or more methods (e.g., by the processor(s) 122). The runtime module 608 can implement an API as described herein that stores or accesses data. The runtime module 608 may include execution of an architecture (e.g., the architecture 102) as described in connection with FIGS. 1A-7.The encryption module 610 is a module capable of performing encryption. The encryption module 610 may perform one or more methods as described herein by including or otherwise encoding at least instructions that cause or otherwise be used to perform the one or more methods (e.g., by the processor(s) 122). The encryption module 610 may encrypt information between one or more interfaces of a federation architecture. The encryption module 610 may encrypt data to improve the security of the data, for example. The encryption module 610 may perform encryption in connection with data storage and access using one or more methods as described in connection with FIGS. 1A-7.FIG. 7 is a method flow diagram illustrating a method 700 that may be used to implement a PPU-initiated data access, in accordance with at least one embodiment. In at least one embodiment, a portion or entire method 700 (or other methods described herein, or variations and / or combinations thereof) is performed under control of one or more computer systems configured with computer-executable instructions and implemented as code (e.g., computer-executable instructions, one or more computer programs, or one or more applications) that are collectively executed on one or more processors by hardware, software, or combinations thereof. In at least one embodiment, code is stored on a computer readable storage medium in the form of a computer program having a plurality of computer readable instructions executable by one or more processors. In at least one embodiment, computer readable storage medium is a non-transitory computer readable medium. In at least one embodiment, at least some computer readable instructions that may be used to perform method 700 are not exclusively stored using transitory signals (e.g., a propagating transitory electrical or electromagnetic transmission). In at least one embodiment, a non-transitory computer readable medium does not necessarily include non-transitory data storage circuits (e.g., buffers, caches, and queues) within transitory signal transceivers. In at least one embodiment, method 700 is executed at least partially on a computer system as described elsewhere in this disclosure. In at least one embodiment, logic (e.g., hardware, software, or a combination of hardware and software) performs method 700.In a first block 702, one or more applications (e.g., application 146) invokes client API 150. As a non-limiting example, the application(s) may call the client APl 150 when the application(s) cannot access data / can be accessed using at least one direct memory load / store instruction (e.g., moving data between the memory 124 of the node 120 implementing the application(s) and one or more registers). In other words, the application(s) may call the client APl 150 when certain data is not stored in one or more registers or memory 124 of the node 120 implementing the application(s) (e.g., for a "get" operation) or, in the case of a "put" operation, is not to be stored in one or more registers or memory 124 of the node 120 implementing the application(s). The application(s) (e.g., application 146) may / may request data access upon invoking the client API 150.In block 704, the PPU(s) 132 executes / en the client interface 158 by executing / en at least one function (e.g., a CUDA kernel) of the invoked client API 150.In block 706, the client interface 158 checks one or more local caches (e.g., the client PPU cache(s) 160, the client CPU cache(s) 162, and / or the like) for the requested data. For example, the client interface 158 may look up the determined data in a name space table to determine its virtual or physical location within the system 100 and backup storage system / s 180.In decision block 708, it is determined whether the determined data is missing from the local caches. The decision at decision block 708 is "no" if the determined data is stored in one or more of the local caches. Otherwise, the decision in decision block 708 is "yes.". If the decision in decision block 708 is "no", then in a block 710, the client interface 158 performs the data access. Then, the client interface 158 proceeds to a decision block 716.On the other hand, if the decision at decision block 708 is "yes", the client interface 158 forwards a data access request to the server interface 170 at block 712. Then, in a block 714, the server interface 170 performs the data access and proceeds to the decision block 716.In decision block 716, it is determined whether data access from the client interface 158 or the server interface 170 is performed asynchronously. The decision at decision block 716 is "yes" if the data access is asynchronous. Otherwise, the decision at decision block 716 is "no.".If the decision in decision block 716 is "no", method 700 may end after decision block 716. On the other hand, if the decision at decision block 716 is "yes", the client interface 158 or the server interfaces 170 may transmit one or more notifications to at least one recipient (or consumer) of the particular data at block 718. The notification(s) indicate whether the data access has been successfully completed. Then, the method 700 may end after block 718.A system may perform method 700 including launching at least one process on at least one PPU and using a server interface implemented by at least one process to access the data from at least one storage location and / or otherwise perform operations described herein. For example, system 100 (see FIG. 1A ) may perform method 700 to access data from at least one storage location and / or perform other operations described herein. The hardware illustrated in FIGS. 8-44 may use method 700 to access data and / or otherwise perform operations described herein, for example.Servers and Data CentersThe following figures set forth, without limitation, example network servers and data center-based systems that may be used to implement at least one embodiment.FIG. 8 illustrates a distributed system 800 according to at least one embodiment. In at least one embodiment, distributed system 800 includes one or more client computing devices 802, 804, 806, and 808 configured to execute and operate a client application, such as a web browser, a proprietary client, and / or variations thereof, over one or more networks 810. In at least one embodiment, server 812 may be communicatively coupled to remote client computing devices 802, 804, 806, and 808 via network 810.In at least one embodiment, server 812 may be configured to execute one or more services or software applications, such as services and applications that may manage single sign-on (SSO) session activities across multiple data centers. In at least one embodiment, server 812 may also provide other services or may include software applications that are not virtual and virtual environments. In at least one embodiment, these services may be offered to users of client computing devices 802, 804, 806, and / or 808 as web-based or cloud services or in a software as a service (SaaS) model. In at least one embodiment, users operating client computing devices 802, 804, 806, and / or 808 may, in turn, utilize one or more client applications to interact with server 812 to utilize services provided by these components.In at least one embodiment, software components 818, 820, and 822 of system 800 are implemented on server 812. In at least one embodiment, one or more components of system 800 and / or services provided by these components may also be implemented by one or more of client computing devices 802, 804, 806, and / or 808. In at least one embodiment, users operating client computing devices may then use one or more client applications to use services provided by these components. In at least one embodiment, these components may be implemented in hardware, software, firmware, or combinations thereof. It should be appreciated that various different system configurations are possible, which may be different from the distributed system 800. The embodiment shown in FIG. 8 is thus an example of a distributed system for implementing an embodiment of a system and is not intended to be limiting.In at least one embodiment, client computing devices 802, 804, 806, and / or 808 may include various types of computing systems. In at least one embodiment, a client computing device may include portable devices (e.g., a iPhone® mobile phone, a iPad® a computer tablet, a personal digital assistant (PDA)), or portable devices (e.g., a Google Glass® with head mounted display) running software such as Microsoft Windows Mobile® and / or a variety of mobile operating systems such as iOS, Windows Phone, Android, BlackBerry 10, Palm OS, and / or variations thereof. In at least one embodiment, devices may support various applications, such as various Internet-related applications, email, short message service (SMS) applications, and may use various other communication protocols. In at least one embodiment, client computing devices may also include general-purpose personal computers, including, by way of example, personal computers and / or laptop computers running various versions of Microsoft Windows® Apple Macintosh® and / or Linux operating systems. In at least one embodiment, client computing devices may be workstation computers running any of a variety of commercially available UNIX® or UNIX-like operating systems, including, without limitation, a variety of GNU / Linux operating systems, such as Google Chrome OS. In at least one embodiment, client computing devices may also include electronic devices, such as a thin client computer, an Internet-enabled gaming system (e.g., a Microsoft Xbox game console with or without a Kinect® gesture input device), and / or a personal communication device capable of communicating via network(s) 810. Although the distributed system 800 is shown as having four client computing devices in FIG. 8, any number of client computing devices may be supported. Other devices, such as devices with sensors, etc., may interact with the server 812.In at least one embodiment, network(s) 810 in distributed system 800 may be any type of network that may support data communications using any of a variety of available protocols, including, without limitation, transmission control protocol / Internet protocol (TCP / IP), system network architecture (SNA), Internet Packet Exchange (IPX), AppleTalk, and / or variations thereof. In at least one embodiment, network(s) 810 may be a local area network (LAN), Ethernet, token ring, wide area network, Internet, virtual network, virtual private network (VPN), intranet, extranet, public switched telephone network (PSTN), infrared network, wireless network (e.g., a network operating in accordance with any of Institute of Electrical and Electronics (IEEE) 802.11, Bluetooth® and / or any other wireless protocol) protocols, and / or any combination of these and / or other networks.In at least one embodiment, server 812 may be comprised of one or more general purpose computers, specialized server computers (including, by way of example, personal computer (PC) servers, UNIX® servers, midrange servers, mainframes, rack-mounted servers, etc.), server farms, server clusters, or any other suitable arrangement and / or combination. In at least one embodiment, server 812 may include one or more virtual machines running virtual operating systems or other computing architectures with virtualization. In at least one embodiment, one or more flexible pools of logical storage devices may be virtualized to manage virtual storage devices for a server. In at least one embodiment, virtual networks may be controlled by server 812 using software-defined networks. In at least one embodiment, server 812 may be configured to execute one or more services or software applications.In at least one embodiment, server 812 may execute any operating system as well as any commercially available server operating system. In at least one embodiment, server 812 may also execute any of a variety of additional server applications and / or mid-tier applications, including hypertext transport protocol (HTTP) servers, file transfer protocol (FTP) servers, common gateway interface (CGI) servers, JAVA® servers, database servers, and / or variations thereof. In at least one embodiment, example database servers include, without limitation, those commercially available from Oracle, Microsoft, Sybase, IBM (International Business Machines), and / or variations thereof.In at least one embodiment, server 812 may include one or more applications to analyze and consolidate data feeds and / or event updates received from users of client computing devices 802, 804, 806, and 808. In at least one embodiment, data feeds and / or event updates may include, but are not limited to, Twitter® feeds, Facebook® updates, or real-time updates received from one or more third-party information sources, and continuous data streams that may include real-time events related to sensor data applications, financial tickers, network performance measurement tools (e.g., network monitoring and traffic management applications), clickstream analysis tools, automotive traffic monitoring, and / or variations thereof. In at least one embodiment, server 812 may also include one or more applications to display data feeds and / or event updates via one or more display devices of client computing devices 802, 804, 806, and 808.In at least one embodiment, distributed system 800 may also include one or more databases 814 and 816. In at least one embodiment, databases may provide a mechanism for storing information, such as user interaction information, usage pattern information, adaptation rule information, and other information. In at least one embodiment, databases 814 and 816 may be located in a plurality of locations. In at least one embodiment, one or more of databases 814 and 816 may reside on a non-transitory storage medium locally on (and / or in) server 812. In at least one embodiment, databases 814 and 816 may be remote from server 812 and communicate with server 812 over a network-based or dedicated connection. In at least one embodiment, databases 814 and 816 may reside in a storage-area network (SAN). In at least one embodiment, all necessary files for performing functions attributed to server 812 may be stored locally on server 812 and / or remotely as needed. In at least one embodiment, databases 814 and 816 may include relational databases, such as databases configured to store, update, and retrieve data in response to SQL formatted commands.In at least one embodiment, one or more of systems shown in FIG. 8 are used to perform operations described herein, such as PPU-initiated data access. In at least one embodiment, one or more systems shown in FIG. 8 are used to implement one or more systems and / or methods described in connection with FIGS. 1A-7. In at least one embodiment, server 812 may be used to implement at least one of computer systems 104 (see FIG. 1A ), management framework 116 (see FIG. 1A ), and / or at least one of external computer systems 114 (see FIG. 1A ). In at least one embodiment, network(s) 810 may be used to implement at least a portion of internal network 108 and / or external network 110. In at least one embodiment, client computing devices 802, 804, 806, and / or 808 may be used to implement at least one of computer systems 104 (see FIG. 1A ), management framework 116 (see FIG. 1A ), and / or at least one of external computer systems 114 (see FIG. 1A ). In at least one embodiment, at least a portion of system(s) depicted in FIG. 8 is used to implement one or more of systems, methods, functions, and / or processes described in connection with FIGS. 1A-7. For example, in at least one embodiment, at least one component shown or described in FIG. 8 is used to access data according to one or more methods, functions, and / or processes described with respect to any of FIGS. 1A-7.FIG. 9 illustrates an example data center 900, according to at least one embodiment. In at least one embodiment, data center 900 includes, without limitation, a data center infrastructure layer 910, a framework layer 920, a software layer 930, and an application layer 940.In at least one embodiment, as shown in FIG. 9, data center infrastructure layer 910 may include resource orchestrator 912, grouped computing resources 914, and node computing resources ("node CRs") 916( 1)- 916(N), where "N" represents any integer positive number. In at least one embodiment, node CRs 916( 1)- 916(N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays ("FPGAs"), graphics processors, etc.), memory devices (e.g., dynamic read-only memory), data storage devices (e.g., solid state or hard disk drives), network input / output ("NW I / O") devices, network switches, virtual machines ("VMs"), power modules, and cooling modules, etc. In at least one embodiment, one or more node CRs among node CRs 916( 1)- 916(N) may be a server having one or more of above-mentioned computing resources.In at least one embodiment, grouped computing resources 914 may include separate groupings of node CRs residing in one or more racks (not shown) or multiple racks residing in data centers at different geographic locations (also not shown). Separate groupings of node CRs within the grouped computing resources 914 may include grouped computing, network, memory, or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, multiple node CRs including CPUs or processors may be grouped into one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.In at least one embodiment, resource orchestrator 912 may configure or otherwise control one or more node CRs 916( 1)- 916(N) and / or grouped computing resources 914. In at least one embodiment, resource orchestrator 912 may include a software design infrastructure ("SDI") manager for data center 900. In at least one embodiment, resource orchestrator 912 may include hardware, software, or a combination thereof.In at least one embodiment, as shown in FIG. 9, framework layer 920 includes, without limitation, a task scheduler 932, a configuration manager 934, a resource manager 936, and a distributed file system 938. In at least one embodiment, framework layer 920 may include a framework to support software 952 of software layer 930 and / or one or more application(s) 942 of application layer 940. In at least one embodiment, software 952 or application(s) 942 may each include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, framework layer 920 may be any type of free and open source software web application framework, such as, but not limited to, Apache SparkTM (hereafter "Spark"), which distributed file system 938 may utilize for large scale data processing (e.g., "Big Data"). In at least one embodiment, task scheduler 932 may include a spark driver to facilitate scheduling workloads supported by different layers of data center 900. In at least one embodiment, configuration manager 934 may be capable of configuring different layers, such as software layer 930 and framework layer 920, including spark and distributed file system 938, to support large volume computing. In at least one embodiment, resource manager 936 may be capable of managing clustered or grouped computing resources mapped or allocated to support distributed file system 938 and task scheduler 932. In at least one embodiment, clustered or grouped computing resources may include grouped computing resource 914 at data center infrastructure layer 910. In at least one embodiment, resource manager 936 may coordinate with resource orchestrator 912 to manage these mapped or allocated computing resources.In at least one embodiment, software 952 included in software layer 930 may include software used by at least portions of node CRs 916( 1)- 916(N), grouped computing resources 914, and / or distributed file system 938 of framework layer 920. One or more types of software may include, but are not limited to, software for browsing internet web pages, software for scanning emails for viruses, database software, and software for streaming video content.In at least one embodiment, application(s) 942 included in application layer 940 may include one or more types of applications used by at least portions of node CRs 916( 1)- 916(N), grouped computing resources 914, and / or distributed file system 938 of network layer 920. In at least one embodiment, one or more types of applications may include, without limitation, CUDA applications, 5G network applications, artificial intelligence applications, data center applications, and / or variations thereof.In at least one embodiment, any of configuration manager 934, resource manager 936, and resource orchestrator 912 may implement any number and type of self-modifying actions based on any amount and type of data captured in any technically feasible manner. In at least one embodiment, self-modifying actions may free a data center operator of data center 900 from making potentially bad configuration decisions, and may avoid portions of a data center being underutilized and / or degraded in performance.In at least one embodiment, one or more of systems shown in FIG. 9 are used to perform operations described herein, such as PPU initiated data access. In at least one embodiment, one or more systems shown in FIG. 9 are used to implement one or more systems and / or methods described in connection with FIGS. 1A-7. In at least one embodiment, data center 900 may be used to implement data center 106 (see FIG. 1A ) of system 100 (see FIG. 1A ) and / or grouped computing resources 914 and / or one or more of nodes C. R. 916( 1)- 916(N) may be used to implement at least one of computer systems 104 (see FIG. 1A ), management framework 116 (see FIG. 1A ), and / or at least one of external computer systems 114 (see FIG. 1A ). In at least one embodiment, at least a portion of system(s) depicted in FIG. 9 is used to implement one or more of systems, methods, functions, and / or processes described in connection with FIGS. 1A-7. For example, in at least one embodiment, at least one component shown or described in FIG. 9 is used to access data according to one or more methods, functions, and / or processes described with respect to any of FIGS. 1A-7.FIG. 10 illustrates a client-server network 1004 formed by a plurality of network-server computers 1002 interconnected, according to at least one embodiment. In at least one embodiment, in a system 1000, each network server computer 1002 stores data accessible by other network server computers 1002 and client computers 1006 and networks 1008 connected in a wide area network 1004. In at least one embodiment, configuration of a client-server network 1004 may change over time as client computers 1006 and one or more networks 1008 connect to and disconnect from a network 1004 and as one or more backbone-server computers 1002 are added to or removed from a network 1004. In at least one embodiment, when a client computer 1006 and a network 1008 are connected to network server computers 1002, client server network includes such a client computer 1006 and a network 1008. In at least one embodiment, computer includes any device or machine capable of accepting data, applying prescribed processes to data, and providing results of processes.In at least one embodiment, client-server network 1004 stores information accessible by network-server computers 1002, remote networks 1008, and client computers 1006. In at least one embodiment, network server computers 1002 are mainframe computers, minicomputers, and / or microcomputers, each with one or more processors. In at least one embodiment, server computers 1002 are interconnected by wired and / or wireless transmission media, such as conductive wires, fiber optic cables, and / or microwave transmission media, satellite transmission media, or other conductive, optical, or electromagnetic wave transmission media. In at least one embodiment, client computers 1006 access a network server computer 1002 through a similar wired or wireless transmission medium. In at least one embodiment, a client computer 1006 may connect to a client-server network 1004 using a modem and a standard telephone communication network. In at least one embodiment, alternative carrier systems such as cable and satellite communication systems may also be used to connect to client-server network 1004. In at least one embodiment, other non-public or time-shared carrier systems may be used. In at least one embodiment, network 1004 is a global information network, such as Internet. In at least one embodiment, network is a non-public intranet using protocols similar to Internet, but with additional security features and restricted access controls. In at least one embodiment, network 1004 is a non-public or semi-private network using proprietary communication protocols.In at least one embodiment, client computer 1006 is any end-user computer and may also be a mainframe computer, minicomputer, or microcomputer having one or more microprocessors. In at least one embodiment, server computer 1002 may sometimes function as a client computer that accesses another server computer 1002. In at least one embodiment, remote network 1008 may be a local area network, a network added to a wide area network by an independent service provider (ISP) for Internet, or another group of computers connected by wired or wireless transmission media having a configuration that is either fixed or changes over time. In at least one embodiment, client computers 1006 may connect to and access a network 1004 independently or via a remote network 1008.In at least one embodiment, one or more of systems shown in FIG. 10 are used to perform operations described herein, such as PPU-initiated data access. In at least one embodiment, one or more systems shown in FIG. 10 are used to implement one or more systems and / or methods described in connection with FIGS. 1A-7. In at least one embodiment, system 1000 may be used to implement system 100 (see FIG. 1A ), client server network 1004 may be used to implement internal network 108, and / or plurality of network server computers 1002 may be used to implement at least one of computer systems 104 (see FIG. 1A ), management framework 116 (see FIG. 1A ), and / or at least one of external computer systems 114 (see FIG. 1A ). In at least one embodiment, network(s) 1008 may be used to implement at least a portion of external network 110, and / or client computers 1006 may be used to implement at least one of external computing devices 114. In at least one embodiment, at least a portion of system(s) depicted in FIG. 10 is used to implement one or more of systems, methods, functions, and / or processes described in connection with FIGS. 1A-7. For example, in at least one embodiment, at least one component shown or described in FIG. 10 is used to access data according to one or more methods, functions, and / or processes described with respect to any of FIGS. 1A-7.FIG. 11 illustrates a computer network 1108 connecting one or more computing machines, in accordance with at least one embodiment. In at least one embodiment, network 1108 may be any type of electronically connected group of computers, including, for example, the following networks: Internet, intranet, local area networks (LAN), wide area networks (WAN), or an interconnected combination of these types of networks. In at least one embodiment, connectivity within a network 1108 may be remote modem, Ethernet (IEEE 802.3), token ring (IEEE 802.5), fiber distributed datalink interface (FDDI), asynchronous transfer mode (ATM), or any other communication protocol. In at least one embodiment, computing devices connected to a network may be a desktop, a server, a portable device, a handheld device, a set-top box, a personal digital assistant (PDA), a terminal, or any other desired type or configuration. In at least one embodiment, network-connected devices may vary widely depending on their functionality in processing power, internal memory, and other performance aspects. In at least one embodiment, communication within a network and to or from computing devices connected to a network may be either wired or wireless. In at least one embodiment, network 1108 may at least partially include world wide public Internet, which generally connects a plurality of users according to a client-server model according to a transmission control protocol / Internet Protocol (TCP / IP) specification. In at least one embodiment, client-server network is a prevalent model for communication between two computers. In at least one embodiment, a client computer ("client") issues one or more commands to a server computer ("server"). In at least one embodiment, server executes client commands by accessing available network resources and returning information to a client according to client commands. In at least one embodiment, client computer systems and network resources resident on network servers are assigned a network address for identification during communication between elements of a network. In at least one embodiment, communications from other network-connected systems to servers include a network address of a relevant server / network resource as part of communication, such that a suitable destination of data or request is identified as a recipient. In at least one embodiment, when a network 1108 includes global Internet, a network address is an IP address in a TCP / IP format that can route data at least in part to an email account, a website, or other server-resident Internet tool. In at least one embodiment, information and services resident on network servers may be available to a web browser of a client computer via a domain name (e.g., www.site.com) associated with an IP address of a network server.In at least one embodiment, a plurality of clients 1102, 1104, and 1106 are connected to a network 1108 via respective communication links. In at least one embodiment, each of these clients may access a network 1108 via any desired form of communication, such as via a dial-up modem connection, a wired connection, a digital subscriber line (DSL), a wireless or satellite connection, or any other form of communication. In at least one embodiment, each client may communicate using any machine compatible with a network 1108, such as a personal computer (PC), workstation, dedicated terminal, personal data assistant (PDA), or other similar device. In at least one embodiment, clients 1102, 1104, and 1106 may or may not be in a same geographic area.In at least one embodiment, a plurality of servers 1110, 1112, and 1114 are connected to a network 1108 to serve clients communicating with a network 1108. In at least one embodiment, each server is typically a powerful computer or device that manages network resources and responds to client commands. In at least one embodiment, servers include computer readable storage media such as hard disk drives and RAM memories that store program instructions and data. In at least one embodiment, servers 1110, 1112, 1114 execute application programs that respond to client commands. In at least one embodiment, server 1110 may execute a web server application to respond to client requests for HTML pages, and may also execute a mail server application to receive and forward electronic mail. In at least one embodiment, other application programs, such as an FTP server or a media server for streaming audio / video data to clients, may also be executed on a server 1110. In at least one embodiment, different servers may be dedicated to performing different tasks. In at least one embodiment, server 1110 may be a dedicated web server that manages resources related to web sites for various users, while server 1112 may be dedicated to providing electronic mail (e-mail) management. In at least one embodiment, other servers may be dedicated to media (audio, video, etc.), a file transfer protocol (FTP), or a combination of any two or more services typically available or provided over a network. In at least one embodiment, each server may be located at a location that is identical to or different from the other server. In at least one embodiment, there may be multiple servers that perform mirrored tasks for users, thereby reducing data jams or minimizing traffic routed to and from a single server. In at least one embodiment, servers 1110, 1112, 1114 are under control of a webhosing provider in a third party enterprise for maintaining and providing third party content via a network 1108.In at least one embodiment, web hosting providers provide services to two different types of clients. In at least one embodiment, one type, which may be referred to as browsers, requests content from servers 1110, 1112, 1114, such as web pages, email messages, video clips, etc. In at least one embodiment, a second type, which may be referred to as user, instructs a web hosting provider to maintain a network resource, such as a web page, and make it available to browsers. In at least one embodiment, users contract with a web hosting provider to make storage space, processor capacity, and communication bandwidth available for their desired network resource according to a set of server resources a user wants to use.In order for a web hosting provider to provide services to these two clients, application programs that manage network resources hosted by servers must be properly configured, in at least one embodiment. In at least one embodiment, program configuration process includes defining a set of parameters that at least partially control application program response to browser requests and that also at least partially define server resources available to a particular user.In one embodiment, an intranet server 1116 is in communication with a network 1108 via a communication link. In at least one embodiment, intranet server 1116 is in communication with a server manager 1118. In at least one embodiment, server manager 1118 includes a database of application program configuration parameters used in servers 1110, 1112, 1114. In at least one embodiment, users modify database 1120 via intranet 1116 and server manager 1118 interacts with servers 1110, 1112, 1114 to modify application program parameters to conform to a content of a database. In at least one embodiment, a user logs on to an intranet server 1116 by connecting to an intranet 1116 via computer 1102 and inputting authentication information such as a username and password.In at least one embodiment, an intranet server 1116 authenticates a user when a user wants to log in for a new service or modify an existing service, and provides a user with an interactive screen / control panel that allows a user to access configuration parameters for a particular application program. In at least one embodiment, a user is presented with a series of modifiable text fields describing aspects of a configuration of a user website or other network resource. In at least one embodiment, if a user desires to increase storage reserved on a server for its website, a field is provided to a user in which a user specifies a desired storage location. In at least one embodiment, an intranet server 1116 updates a database 1120 in response to receipt of this information. In at least one embodiment, server manager 1118 forwards this information to an appropriate server and a new parameter is used during application program operation. In at least one embodiment, an intranet server 1116 is configured to provide users with access to configuration parameters of hosted network resources (e.g., web pages, email, FTP sites, media sites, etc.) for which a user has completed a contract with a web hosting service provider.In at least one embodiment, one or more of systems shown in FIG. 11 are used to perform operations described herein, such as PPU-initiated data access. In at least one embodiment, one or more systems shown in FIG. 11 are used to implement one or more systems and / or methods described in connection with FIGS. 1A-7. In at least one embodiment, system 1100 may be used to implement system 100 (see FIG. 1 ), and / or at least one of servers 1110, 1112, 1114 may be used to implement at least one of computer systems 104 (see FIG. 1A ), management framework 116 (see FIG. 1A ), and / or at least one of external computer systems 114 (see FIG. 1A ). In at least one embodiment, network(s) 1108 may be used to implement at least a portion of internal network 108, at least a portion of external network 110, and / or one or more of clients 1102, 1104, and 1106 may be used to implement at least one of computing systems 104 (see FIG. 1A ), management framework 116 (see FIG. 1A ), and / or at least one of external computing systems 114 (see FIG. 1A ). Alternatively or additionally, the intranet server 1116 and / or the server manager 1118 may be used to implement the internal network 106 (see FIG. 1 ), at least one of the computer systems 104 (see FIG. 1A ), the management framework 116 (see FIG. 1A ), and / or at least one of the external computer systems 114 (see FIG. 1A ). In at least one embodiment, at least a portion of system / systems shown in FIG. 11 is used to implement one or more systems, methods, functions, and / or processes described in connection with FIGS. 1A-7. For example, in at least one embodiment, at least one component illustrated or described in FIG. 11 is used to access data according to one or more methods, functions, and / or processes described with respect to any of FIGS. 1A-7.FIG. 12A illustrates a networked computer system 1200A, according to at least one embodiment. In at least one embodiment, networked computer system 1200A includes a plurality of nodes or personal computers ("PCs") 1202, 1118, 1220. In at least one embodiment, personal computer or node 1202 includes a processor 1214, memory 1216, video camera 1204, microphone 1206, mouse 1208, speakers 1210, and monitor 1212. For example, in at least one embodiment, PCs 1202, 1118, 1220 may each execute one or more desktop servers of an internal network within a given company, or may be servers of a general network that is not limited to a specific environment. In at least one embodiment, there is one server per PC node of a network, such that each PC node of a network represents a particular network server having a particular network URL address. In at least one embodiment, each server uses a default web page for that server's user, which may itself contain embedded URLs pointing to other user's bottom pages on that server or to other servers or pages on other servers in a network.In at least one embodiment, nodes 1202, 1118, 1220, and other nodes of a network are interconnected via medium 1222. In at least one embodiment, medium 1222 may be a communication channel, such as an Integrated Services Digital Network ("ISDN"). In at least one embodiment, various nodes of a networked computer system may be connected by a variety of communication media, including local area networks ("LAN"), plain-old telephone lines ("POTS"), sometimes referred to as public switched telephone networks ("PSTN"), and / or variations thereof. In at least one embodiment, different nodes of a network may also represent computer system users interconnected via a network, such as Internet. In at least one embodiment, each server in a network (executed by a particular node of a network in a given instance) has a unique address or identification within a network that can be specified in the form of a URL.Thus, in at least one embodiment, a plurality of multipoint conferencing units ("MCUs") may be used to transfer data to and from various nodes or "endpoints" of a conferencing system. In at least one embodiment, nodes and / or MCUs may be interconnected via an ISDN connection or via a local area network ("LAN"), in addition to various other communication media, such as nodes connected through Internet. In at least one embodiment, nodes of a conferencing system may generally be directly connected to a communication medium such as a LAN or through an MCU, and this conferencing system may include other nodes or elements such as routers, servers, and / or variations thereof.In at least one embodiment, processor 1214 is a programmable general purpose processor. In at least one embodiment, processors of nodes of networked computer system 1200A may also be special purpose video processors. In at least one embodiment, various peripheral devices and components of a node, such as those of node 1202, may differ from other nodes. In at least one embodiment, node 1218 and node 1220 may be identical to node 1202 or configured differently. In at least one embodiment, a node may be implemented on any suitable computer system in addition to PC systems.FIG. 12B illustrates a networked computer system 1200B, according to at least one embodiment. In at least one embodiment, system 1200B illustrates a network, such as a LAN 1224, that may be used to connect together a plurality of nodes that may communicate with each other. In at least one embodiment, a plurality of nodes are connected to LAN 1224, such as PC nodes 1222, 1228, 1230. In at least one embodiment, a node may also be connected to LAN via a network server or other means. In at least one embodiment, system 1200B includes other types of nodes or elements, including, for example, routers, servers, and nodes.FIG. 12C illustrates a networked computer system 1200C, according to at least one embodiment. In at least one embodiment, system 1200C illustrates a WWW system having communications over a backbone communication network, such as Internet 1232, that can be used to connect a plurality of nodes of a network together. In at least one embodiment, WWW is a set of protocols operating on Internet and allows a graphical interface system to operate on to access information over Internet. In at least one embodiment, a plurality of nodes are connected to Internet 1232 in WWW, such as PC nodes 1240, 1242, 1244. In at least one embodiment, a node interfaces with other nodes of WWW via a WWW HTTP server, such as servers 1234, 1236. In at least one embodiment, PC 1244 may be a PC that forms a node of network 1232 and itself executes its server 1236, although PC 1244 and server 1236 are separately shown in FIG. 12C for illustrative purposes.In at least one embodiment, WWW is a distributed application type characterized by WWW HTTP, the WWW protocol, which runs on Internet's transmission control protocol / Internet protocol ("TCP / IP"). Thus, in at least one embodiment, WWW may be characterized by a set of protocols (i.e., HTTP) running on Internet as its "backbone.".In at least one embodiment, a web browser is an application running on a node of a network that, in WWW-compatible network systems, allows users of a particular server or node to display such information, thus allowing a user to search for graphical and text-based files linked together via hypertext links embedded in documents or files available from servers in a network that understand HTTP. In at least one embodiment, a retrieved document may have various hypertext links embedded therein and a local copy of a page created locally for a retrieving user when a given web page of a first server associated with a first node is retrieved by a user using another server on a network such as Internet. In at least one embodiment, when a user clicks on a hypertext link, locally stored information regarding a selected hypertext link is typically sufficient to allow a user's machine to open a connection over Internet to a server indicated by a hypertext link.In at least one embodiment, more than one user may be coupled to each HTTP server, for example, via a LAN, such as LAN 1238, as illustrated with respect to WWW HTTP server 1234. In at least one embodiment, system 1200C may also include other types of nodes or elements. In at least one embodiment, a WWW HTTP server is an application running on a machine, such as a PC. In at least one embodiment, each user may be considered to have a unique "server" as illustrated with respect to PC 1244. In at least one embodiment, a server may be considered a server, such as WWW HTTP server 1234, which provides access to a network for a LAN or a plurality of nodes or a plurality of LANs. In at least one embodiment, there are a plurality of users, each having a desktop PC or nodes of a network, each desktop PC potentially manufacturing a server for a user thereof. In at least one embodiment, each server is associated with a specific network address or URL that, when accessed, provides a default web page for that user. In at least one embodiment, a web page may include other links (embedded URLs) pointing to other user's bottom sides on that server or to other servers on a network or pages on other servers on a network.Cloud Computing and ServicesThe following figures set forth, without limitation, example cloud-based systems that may be used to implement at least one embodiment.In at least one embodiment, cloud computing is a computing system style in which dynamically scalable and often virtualized resources are provided as a service over Internet. In at least one embodiment, users need not have any knowledge, skill, or control over technology infrastructure, which may be referred to as "in cloud" that they support. In at least one embodiment, cloud computing includes infrastructure-as-service, platform-as-service, software-as-service, and other variations that have a common routing motif of Internet dependency for satisfying user computing needs. In at least one embodiment, a typical cloud deployment, such as in a private cloud (e.g., enterprise network) or data center (DC) in a public cloud (e.g., Internet), may consist of thousands of servers (or, alternatively, VM), hundreds of Ethernet, Fibre Channel, or Fibre Channel over Ethernet (FCoE) ports, switching and storage infrastructure, etc. In at least one embodiment, cloud may also consist of a network service infrastructure such as IPsec-VPN hubs, firewalls, load balancers, wide area network (WAN) optimizers, etc. In at least one embodiment, remote participants may securely access cloud applications and services by connecting via a VPN tunnel, such as an IPsec-VPN tunnel.In at least one embodiment, cloud computing is a model for facilitating convenient on-demand network access to a shared pool of configurable computing resources (e.g., networks, servers, storage, applications, and services) that can be quickly provided and released with minimal overhead or service provider interaction.In at least one embodiment, cloud computing is characterized by on-demand self-service, in which a consumer may provide computing capabilities, such as server time and network storage, automatically as needed, on a single side without requiring human interaction with respective service providers. In at least one embodiment, cloud computing is characterized by wide network access in which capabilities are available over a network and accessed via standard mechanisms that promote use by heterogeneous thin or thick client platforms (e.g., mobile phones, laptops, and PDAs). In at least one embodiment, cloud computing is characterized by resource pooling in which a provider's computing resources are pooled to serve multiple consumers using a multi-tenant model, where different physical and virtual resources are dynamically allocated and re-allocated according to consumer demand. In at least one embodiment, a feel of location independence is that a customer generally does not have control or knowledge of an exact location of resources provided, but may be able to set location at a higher level of abstraction (e.g., country, state, or data center). In at least one embodiment, examples of resources include storage, processing, memory, network bandwidth, and virtual machines. In at least one embodiment, cloud computing is characterized by a fast elasticity, where capabilities may be provided fast and elastic, in some cases automatically, for fast scale-out and enabled fast for fast scale-in. In at least one embodiment, a consumer often appears to be unlimited in its capabilities available for provision and can be purchased in any amount at any time. In at least one embodiment, cloud computing is characterized by a measured service in which cloud systems automatically control and optimize resource usage by utilizing a measurement capability at a particular level of abstraction suitable for a type of service (e.g., storage, processing, bandwidth, and active user accounts). In at least one embodiment, resource usage may be monitored, controlled, and reported to provide transparency to both a provider and a consumer of a service being used.In at least one embodiment, cloud computing may be associated with different services. In at least one embodiment, cloud software as a service (SaaS) may refer to a service where a capability provided to a consumer is to use applications of a provider running on a cloud infrastructure. In at least one embodiment, applications are accessible from various client devices via a thin client interface, such as a web browser (e.g., web-based email). In at least one embodiment, consumer does not manage or control underlying cloud infrastructure, including network, servers, operating systems, storage, or even individual application functions, with possible exception to limited user-specific application configuration settings.In at least one embodiment, Platform as a Service (PaaS) may refer to a service where a capability provided to a consumer is to deploy consumer-created or acquired applications created using programming languages and tools supported by a provider to a cloud infrastructure. In at least one embodiment, consumer does not manage or control underlying cloud infrastructure, including networks, servers, operating systems, or storage, but has control over applications deployed and possibly application hosting environment configurations.In at least one embodiment, cloud infrastructure as a service (laaS) may refer to a service where a capability provided to a consumer is to provide processing, storage, network, and other basic computing resources, where a consumer is capable of deploying and executing arbitrary software, which may include operating systems and applications. In at least one embodiment, consumer does not manage or control underlying cloud infrastructure, but has control over operating systems, memory, deployed applications, and potentially limited control over selected network components (e.g., host firewalls).In at least one embodiment, cloud computing may be deployed in various ways. In at least one embodiment, a non-public cloud may refer to a cloud infrastructure operating exclusively for an organization. In at least one embodiment, a non-public cloud may be managed by an organization or third party provider and may exist inside or outside of operating site. In at least one embodiment, a community cloud may refer to a cloud infrastructure shared by multiple organizations and supporting a particular community that has shared concerns (e.g., goals, security requirements, policies, and compliance considerations). In at least one embodiment, a community cloud may be managed by an organization or third party provider and may exist inside or outside of operating site. In at least one embodiment, a public cloud may refer to a cloud infrastructure provided to a wide public or large industry group and owned by an organization providing cloud services. In at least one embodiment, a hybrid cloud may refer to a cloud infrastructure that is a composition of two or more clouds (non-public, community, or public) that remain stand-alone entities but are interconnected by standardized or proprietary technology that enables data and application portability (e.g., cloud bursting for load balancing between clouds). In at least one embodiment, a cloud computing environment is service-oriented with a focus on statelessness, low-level connectivity, modularity, and semantic interoperability.In at least one embodiment, one or more systems illustrated in one or more of FIGS. 12A-12C are used to perform operations described herein, such as PPU-initiated data access. In at least one embodiment, one or more of systems shown in FIGS. 12A-12C are used to implement one or more systems and / or methods described in connection with FIGS. 1A-7. In at least one embodiment, one or more of networked computer systems 1200A, 1200B, and 1200C may be used to implement system 100 (see FIG. 1 ). In at least one embodiment, at least one of PC nodes 1226, 1228, 1230, and / or at least one of PCs 1202, 1118, 1220, 1240, 1242 may be used to implement at least one of computer systems 104 (see FIG. 1A ), management framework 116 (see FIG. 1A ), and / or at least one of external computer systems 114 (see FIG. 1A ). In at least one embodiment, Internet 1232 may be used to implement at least a portion of external network 110, and / or PC 1244 may be used to implement at least one of external computing device(s) 114. Alternatively or additionally, LAN 1224 and / or LAN manager 1238 may be used to implement internal network 108 (see FIG. 1A). In at least one embodiment, medium 1222 may be used to implement internal network 108. In at least one embodiment, processor 1214 may be used to implement one or more of processors 122. In at least one embodiment, memory 1216 may be used to implement memory 124. In at least one embodiment, at least a portion of system / s illustrated in one or more of FIGS. 12A-12C is / are used to implement one or more systems, methods, functions, and / or processes described in connection with FIGS. 1A-7. For example, in at least one embodiment, at least one component illustrated or described in one or more of FIGS. 12A-12C is used to access data according to one or more methods, functions, and / or processes described with respect to one of FIGS. 1A-7.FIG. 13 illustrates one or more components of a system environment 1300 in which services may be offered as third party network services, in accordance with at least one embodiment. In at least one embodiment, a third-party network may be referred to as a cloud, cloud network, cloud computing network, and / or variations thereof. In at least one embodiment, system environment 1300 includes one or more client computing devices 1304, 1306, and 1308 that may be used by users to interact with a third-party network infrastructure system 1302 that provides third-party network services, which may be referred to as cloud computing services. In at least one embodiment, third party network infrastructure system 1302 may include one or more computers and / or servers.It should be appreciated that the third party network infrastructure system 1302 illustrated in FIG. 13 may include components other than those illustrated. Further, Fig. 13 illustrates an embodiment of a third party network infrastructure system. In at least one embodiment, third party network infrastructure system 1302 may have more or fewer components than shown in FIG. 13, may combine two or more components, or may have a different configuration or arrangement of components.In at least one embodiment, client computing devices 1304, 1306, and 1308 may be configured to operate a client application, such as a web browser, a proprietary client application, or another application, that may be used by a user of a client computing device to interact with third-party network infrastructure system 1302 to utilize services provided by third-party network infrastructure system 1302. Although the example system environment 1300 is shown as including three client computing devices, any number of client computing devices may be supported. In at least one embodiment, other devices, such as devices with sensors, etc., may interact with third party network infrastructure system 1302. In at least one embodiment, network(s) 1310 may enable communication and exchange of data between client computing devices 1304, 1306, and 1308 and third party network infrastructure system 1302.In at least one embodiment, services provided by third-party network infrastructure system 1302 may include a host of services provided to users of a third-party network infrastructure system upon request. In at least one embodiment, various services may also be offered, including, without limitation, online storage and backup solutions, web-based email services, hosted office suites, and document collaboration services, database management and processing, managed technical support services, and / or variations thereof. In at least one embodiment, services provided by a third party network infrastructure system may dynamically scale to meet users' needs.In at least one embodiment, a specific instantiation of a service provided by third party network infrastructure system 1302 may be referred to as a "service instance.". In at least one embodiment, generally, any service provided to a user via a communication network, such as Internet, from a third party network service provider system is referred to as a "third party network service.". In at least one embodiment, in a third party public network environment, servers and systems forming a third party network service provider's system are different from a customer's own local servers and systems. In at least one embodiment, third party network service provider system may host an application, and a user may order and use an application on demand via a communication network such as Internet.In at least one embodiment, a service in a third party computer network infrastructure may include protected computer network access to memory, a hosted database, a hosted web server, a software application, or other service provided to a user by a third party network manufacturer. In at least one embodiment, a service may include password protected access to remote storage in a third party network via Internet. In at least one embodiment, a service may include a web service-based hosted relational database and a script language middleware engine for private use by a networked developer. In at least one embodiment, a service may include access to an email software application hosted on third party network manufacturer's website.In at least one embodiment, third party network infrastructure system 1302 may include a suite of applications, middleware, and database service offerings that are provided to a customer in self-service, subscription-based, elastically scalable, reliable, highly available, and secure fashion. In at least one embodiment, third party network infrastructure system 1302 may also provide big data related computing and analytics services. In at least one embodiment, big data is used generally to refer to extremely large data sets that can be stored and manipulated by analysts and researchers to visualize large amounts of data, recognize trends, and / or otherwise interact with data. In at least one embodiment, big data and associated applications may be hosted and / or manipulated by an infrastructure system at many levels and at different scales. In at least one embodiment, dozens, hundreds, or thousands of parallel connected processors may act on such data to represent them or simulate external forces on data or what they represent. In at least one embodiment, these records may involve structured data, such as organized in a database or otherwise according to a structured model, and / or unstructured data (e.g., emails, images, data blobs (binary large objects), web pages, complex event processing). In at least one embodiment, by utilizing an embodiment's ability to relatively quickly concentrate more (or less) computing resources to a target, a third party network infrastructure system may be more readily available to perform tasks on large data sets based on demand from a business, government agency, research facility, private person, group of peer persons or organizations, or other entity.In at least one embodiment, third party network infrastructure system 1302 may be adapted to automatically provide, manage, and track customer subscription for services offered by third party network infrastructure system 1302. In at least one embodiment, third party network infrastructure system 1302 may provide third party network services via various deployment models. In at least one embodiment, services may be provided within a third party public network model where third party network infrastructure system 1302 is owned by an organization that sells third party network services and provides services to a wide public or different industrial companies. In at least one embodiment, services may be provided within a third party non-public network model in which third party network infrastructure system 1302 operates exclusively for a single organization and may provide services to one or more entities within an organization. In at least one embodiment, third-party network services may also be provided within a third-party community network model in which third-party network infrastructure system 1302 and services provided by third-party network infrastructure system 1302 are shared among multiple organizations in a contiguous community. In at least one embodiment, third party network services may also be provided in a hybrid third party network model that is a combination of two or more different models.In at least one embodiment, services provided by third-party network infrastructure system 1302 may include one or more services provided under software-as-service (SaaS) category, platform-as-service (PaaS) category, infrastructure-as-service (laaS) category, or other categories of services including hybrid services. In at least one embodiment, a customer may order one or more services provided by third party network infrastructure system 1302 via a subscription order. In at least one embodiment, third party network infrastructure system 1302 then performs processing to provide services in a subscription order of customer.In at least one embodiment, services provided by third party network infrastructure system 1302 may include, without limitation, application services, platform services, and infrastructure services. In at least one embodiment, application services may be provided by a third party network infrastructure system via a SaaS platform. In at least one embodiment, SaaS platform may be configured to provide third party network services that fall within a SaaS category. In at least one embodiment, SaaS platform may provide capabilities for creating and delivering a suite of on-demand applications on an integrated development and deployment platform. In at least one embodiment, SaaS platform may manage and control underlying software and infrastructure for providing SaaS services. In at least one embodiment, by utilizing services provided by a SaaS platform, customers may utilize applications executing in a third party network infrastructure system. In at least one embodiment, clients may purchase application services without having to purchase separate licenses and support. In at least one embodiment, various different SaaS services may be provided. In at least one embodiment, examples include, without limitation, services that provide solutions for sales performance management, enterprise integration, and business flexibility to large organizations.In at least one embodiment, platform services may be provided by third party network infrastructure system 1302 via a Paas platform. In at least one embodiment, PaaS platform may be configured to provide third party network services that fall within a PaaS category. In at least one embodiment, examples of platform services may include, without limitation, services that enable organizations to consolidate existing applications on a shared, shared architecture, as well as capability to create new applications that employ shared services provided by a platform. In at least one embodiment, PaaS platform may manage and control underlying software and infrastructure for providing PaaS services. In at least one embodiment, customers may purchase PaaS services provided by third party network infrastructure system 1302 without having to purchase customers separate licenses and support.In at least one embodiment, through use of services provided by a PaaS platform, customers may employ programming languages and tools supported by a third party network infrastructure system, and also control deployed services. In at least one embodiment, platform services provided by a third-party network infrastructure system may include database third-party network services, middleware third-party network services, and third-party network services. In at least one embodiment, database-third party network services may support common service deployment models that allow organizations to pool database resources and offer customers a database-as-service in the form of a database-third party network. In at least one embodiment, middleware third party network services may provide a platform for customers to develop and provide various business applications, and third party network services may provide a platform for customers to employ applications in a third party network infrastructure system.In at least one embodiment, various different infrastructure services may be provided by an laaS platform in a third party network infrastructure system. In at least one embodiment, infrastructure services enable management and control of underlying computing resources, such as memories, networks, and other basic computing resources, for customers utilizing services provided by a SaaS platform and a PaaS platform.In at least one embodiment, third party network infrastructure system 1302 may also include infrastructure resources 1330 for providing resources used to provide various services to customers of a third party network infrastructure system. In at least one embodiment, infrastructure resources 1330 may include pre-integrated and optimized combinations of hardware, such as servers, memory, and network resources to perform services provided by a Paas platform and a SaaS platform, and other resources.In at least one embodiment, resources in third party network infrastructure system 1302 may be shared among multiple users and dynamically re-allocated as needed. In at least one embodiment, users in different time zones may be allocated resources. In at least one embodiment, third party network infrastructure system 1302 may allow a first group of users in a first time zone to utilize resources of a third party network infrastructure system for a fixed number of hours, and then allow reallocation of same resources for another group of users located in a different time zone, thereby maximizing utilization of resources.In at least one embodiment, a series of internal shared services 1332 may be provided that are shared by various components or modules of third-party network infrastructure system 1302 to facilitate provision of services by third-party network infrastructure system 1302. In at least one embodiment, these internal shared services may include, without limitation, a security and identity service, an integration service, an enterprise repository service, an enterprise manager service, a virus scan and whitelist service, a high availability, backup, and restore service, third party network support enabled service, an email service, a notification service, a file transfer service, and / or variations thereof.In at least one embodiment, third party network infrastructure system 1302 may provide comprehensive management of third party network services (e.g., SaaS, PaaS, and laaS services) in a third party network infrastructure system. In at least one embodiment, third party network management functionality may include capabilities for providing, managing, and tracking a customer subscription received by third party network infrastructure system 1302, and / or variations thereof.In at least one embodiment, as shown in FIG. 13, third party network management functionality may be provided by one or more modules, such as a job management module 1320, a job orchestration module 1322, a job provision module 1324, a job management and monitoring module 1326, and an identity management module 1328. In at least one embodiment, these modules may include or be provided using one or more computers and / or servers, which may be general purpose computers, specialized server computers, server farm, server clusters, or any other suitable arrangement and / or combination.In at least one embodiment, a customer using a client device, such as client computing devices 1304, 1306, or 1308, may interact with third-party network infrastructure system 1302 by requesting one or more services provided by third-party network infrastructure system 1302 and issuing a subscription order for one or more services offered by third-party network infrastructure system 1302, in step 1334. In at least one embodiment, a customer may access a user interface (UI) of a third-party network, such as a third-party network UI 1312, a third-party network UI 1314, and / or a third-party network UI 1316, and issue a subscription order via those UIs. In at least one embodiment, job information received by third-party network infrastructure system 1302 in response to a customer issuing a job may include information identifying a customer and one or more services offered by third-party network infrastructure system 1302 that a customer desires to subscribe.In at least one embodiment, at step 1336, job information received from a customer may be stored in a job database 1318. In at least one embodiment, if a new job is involved, a new dataset for a job may be created. In at least one embodiment, job database 1318 may be one of multiple databases that are operated by third party network infrastructure system 1318 and operated in conjunction with other system elements.In at least one embodiment, at step 1338, job information may be passed to a job management module 1320, which may be configured to perform accounting and accounting functions related to a job, such as verifying a job and post-verification accounting of a job.In at least one embodiment, at step 1340, information regarding a job may be communicated to a job orchestration module 1322 configured to coordinate provision of services and resources for a job issued by a customer. In at least one embodiment, job orchestration module 1322 may use services of job provisioning module 1324 for provisioning. In at least one embodiment, job orchestration module 1322 enables management of business processes associated with each job and applies business logic to determine whether a job should proceed for provisioning.In at least one embodiment, after receiving a new subscription order, order orchestration module 1322 sends a request to order provisioning module 1324, to allocate resources and configure resources needed to satisfy a subscription order, at step 1342. In at least one embodiment, task provisioning module 1324 facilitates allocation of resources for services being ordered by a customer. In at least one embodiment, task provisioning module 1324 provides an abstraction level between third-party network services provided by third-party network infrastructure system 1300 and a physical implementation layer used to provide resources for providing requested services. In at least one embodiment, this allows job orchestration module 1322 to be isolated from implementation details, such as whether services and resources are actually provided in real-time or pre-provided and allocated / allocated only upon request.In at least one embodiment, once services and resources are provided, at step 1344, a notification may be sent to subscription customers indicating that a requested service is now ready for use. In at least one embodiment, information (e.g., a link) may be sent to a customer that enables a customer to begin using requested services.In at least one embodiment, at step 1346, a subscription order of a customer may be managed and tracked by an order management and monitoring module 1326. In at least one embodiment, job management and monitoring module 1326 may be configured to collect usage statistics regarding customer usage of subscribed services. In at least one embodiment, statistics may be collected for an amount of memory used, an amount of data transmitted, a number of users, and an amount of system operating time and system downtime, and / or variations thereof.In at least one embodiment, third party network infrastructure system 1300 may include an identity management module 1328 configured to provide identity services, such as access management and authorization services, in third party network infrastructure system 1300. In at least one embodiment, identity management module 1328 may control information about customers wishing to utilize services provided by third party network infrastructure system 1302. In at least one embodiment, such information may include information authenticating identities of such clients and information describing what actions these clients are authorized to take with respect to various system resources (e.g., files, directories, applications, communication ports, storage segments, etc.). In at least one embodiment, identity management module 1328 may also include managing descriptive information about each customer and how and by whom this descriptive information may be accessed and modified.In at least one embodiment, one or more of systems shown in FIG. 13 are used to perform operations described herein, such as PPU-initiated data access. In at least one embodiment, one or more systems shown in FIG. 13 are used to implement one or more systems and / or methods described in connection with FIGS. 1A-7. In at least one embodiment, system environment 1300 may be used to implement system 100 (see FIG. 1 ), third party network infrastructure system 1302 may be used to implement data center 106. In at least one embodiment, network(s) 1310 may be used to implement at least a portion of internal network 108 and / or at least a portion of external network 110. In at least one embodiment, at least one of client computing devices 1304, 1306, and 1308 may be used to implement at least one of computer systems 104 (see FIG. 1A ), management framework 116 (see FIG. 1A ), and / or at least one of external computer systems 114 (see FIG. 1A ). In at least one embodiment, at least a portion of system(s) depicted in FIG. 13 is used to implement one or more of systems, methods, functions, and / or processes described in connection with FIGS. 1A-7. For example, in at least one embodiment, at least one component illustrated or described in FIG. 13 is used to access data according to one or more methods, functions, and / or processes described with respect to any of FIGS. 1A-7.FIG. 14 illustrates a cloud computing environment 1402, according to at least one embodiment. In at least one embodiment, cloud computing environment 1402 includes one or more computer systems / servers 1404 with which computing devices such as a personal digital assistant (PDA) or cellular phone 1406A, a desktop computer 1406B, a laptop computer 1406C, and / or an automobile computer system 1406N communicate. In at least one embodiment, this allows infrastructure, platforms, and / or software to be offered as services by cloud computing environment 1402, such that each client does not have to maintain these resources separately. It should be appreciated that the types of computing devices 1406A-N shown in FIG. 14 are intended to be illustrative only and that the cloud computing environment 1402 may communicate with any type of computerized device over any type of network and / or network / addressable connection (e.g., via a web browser).In at least one embodiment, a computer system / server 1404, which may be referred to as a cloud computing node, is operable with numerous other general-purpose or special-purpose computing system environments or configurations. In at least one embodiment, computing systems, environments, and / or configurations that may be suitable for use with computer system / server 1404 include, but are not limited to, personal computer systems, server computer systems, thin clients, thick clients, pendants or laptop devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of above systems or devices, and / or variations thereof.In at least one embodiment, computer system / server 1404 may be described in a general context of computer system executable instructions, such as program modules, executed by a computer system. In at least one embodiment, program modules include routines, programs, objects, components, logic, data structures, etc., that execute particular tasks or implement particular abstract data types. In at least one embodiment, example computer system / server 1404 may be practiced in distributed cloud computing environments where tasks are performed by remote processing devices interconnected via a communication network. In at least one embodiment, in a distributed cloud computing environment, program modules may reside on both local and remote computer system storage media, including storage devices.In at least one embodiment, one or more of systems shown in FIG. 14 are used to perform operations described herein, such as PPU-initiated data access. In at least one embodiment, one or more systems illustrated in FIG. 14 are used to implement one or more systems and / or methods described in connection with FIGS. 1A-7. In at least one embodiment, cloud computing environment 1402 may be used to implement system 100 (see FIG. 1 ). In at least one embodiment, at least one of computer systems / servers 1404 may be used to implement at least one of computer systems 104 (see FIG. 1A ), management framework 116 (see FIG. 1A ), and / or at least one of external computer systems 114 (see FIG. 1A ). In at least one embodiment, Internet 1032 may be used to implement at least a portion of external network 110, and / or one or more of computing devices 1406A- 1406N may be used to implement at least one of external computing device(s) 114. In at least one embodiment, at least a portion of system / s shown in FIG. 14 is used to implement one or more systems, methods, functions, and / or processes described in connection with FIGS. 1A-7. For example, in at least one embodiment, at least one component illustrated or described in FIG. 14 is used to access data according to one or more methods, functions, and / or processes described with respect to any of FIGS. 1A-7.FIG. 15 illustrates a set of functional abstraction layers provided by the cloud computing environment 1402 (FIG. 14 ), in accordance with at least one embodiment. It should be understood in advance that the components, layers, and functions shown in FIG. 15 are intended for illustration only, and components, layers, and functions may vary.In at least one embodiment, hardware and software layer 1502 includes hardware and software components. In at least one embodiment, examples of hardware components include mainframes, various servers based on reduced instruction set computer (RISC) architecture, various computing systems, super computing systems, storage devices, networks, network components, and / or variations thereof. In at least one embodiment, examples of software components include network application server software, various application server software, various database software, and / or variations thereof.In at least one embodiment, virtualization layer 1504 provides an abstraction layer from which following example virtual entities may be provided: virtual servers, virtual storage, virtual networks including virtual private networks, virtual applications, virtual clients, and / or variations thereof.In at least one embodiment, management layer 1506 provides various functions. In at least one embodiment, resource provisioning provides dynamic conservation of computing resources and other resources used to perform tasks within a cloud computing environment. In at least one embodiment, consumption sensing provides usage tracking when resources are used within a cloud computing environment, and billing for consumption of those resources.In at least one embodiment, resources may include application software licenses. In at least one embodiment, security provides authentication for users and tasks as well as protection for data and other resources. In at least one embodiment, user interface provides users as well as system administrators access to a cloud computing environment. In at least one embodiment, service level management provides cloud computing resource allocation and management such that required service levels are met. In at least one embodiment, Service Level Agreement (SLA) management provides pre-placement for and purchase cloud computing resources that are expected to be requested in accordance with an SLA.In at least one embodiment, workload layer 1508 provides functionality for which a cloud computing environment is used. In at least one embodiment, examples of workloads and functions that may be provided by this layer include mapping and navigation, software development and management, educational services, data analytics and processing, transaction processing, and service provisioning.Supercomputers SupercomputersThe following figures set forth, without limitation, example supercomputer-based systems that can be used to implement at least one embodiment.In at least one embodiment, a supercomputer may refer to a hardware system having substantially parallelism and comprising at least one chip, where chips in a system are interconnected by a network and placed in hierarchically organized enclosures. In at least one embodiment, a large hardware system that fills a machine room with multiple racks, each including multiple board / rack modules, each including multiple chips, all interconnected by a scalable network, is a particular example of a supercomputer. In at least one embodiment, a single rack of such a large hardware system is at least one other example of a supercomputer. In at least one embodiment, a single die having considerable parallelism and including multiple hardware components may likewise be considered a supercomputer because as feature sizes decrease, an amount of hardware that may be integrated into a single die may also increase.FIG. 16 illustrates a chip-level supercomputer, in accordance with at least one embodiment. In at least one embodiment, within an FPGA or ASIC die, main computational effort is performed in finite state machines (1604), referred to as thread units. In at least one embodiment, task and synchronization networks (1602) connect state finite state machines and are used to dispatch threads and execute operations in proper order. In at least one embodiment, a partitioned multilevel cache hierarchy (1608, 1612) is accessed on a chip using memory networks (1606, 1610). In at least one embodiment, off-chip memory is accessed using memory controllers (1616) and an off-chip memory network (1614). In at least one embodiment, an I / O controller (1618) is used for cross-chip communication when a design does not fit into a single logic chip.In at least one embodiment, one or more of systems shown in FIG. 16 are used to perform operations described herein, such as PPU-initiated data access. In at least one embodiment, one or more systems shown in FIG. 16 are used to implement one or more systems and / or methods described in connection with FIGS. 1A-7. In at least one embodiment, supercomputer shown in FIG. 16 may be used to implement system 100 (see FIG. 1 ). For example, the supercomputer may be used to implement at least one of the computer systems 104 (see FIG. 1A ), the management framework 116 (see FIG. 1A ), and / or at least one of the external computer systems 114 (see FIG. 1A ). In at least one embodiment, supercomputer shown in FIG. 16 may be used to implement processor(s) 122. In at least one embodiment, at least a portion of system / systems shown in FIG. 16 is used to implement one or more systems, methods, functions, and / or processes described in connection with FIGS. 1A-7. For example, in at least one embodiment, at least one component shown or described in FIG. 16 is used to access data according to one or more methods, functions, and / or processes described with respect to any of FIGS. 1A-7.FIG. 17 illustrates a rack module level supercomputer, in accordance with at least one embodiment. In at least one embodiment, within a rack module, there are multiple FPGA or ASIC chips (1702) connected to one or more DRAM units (1704) that form a main accelerator memory. In at least one embodiment, each FPGA / ASIC chip is connected to its adjacent FPGA / ASIC chip using wide buses on a high speed differential signaling board (1706). In at least one embodiment, each FPGA / ASIC chip is also connected to at least one high speed serial communication cable.In at least one embodiment, one or more of systems shown in FIG. 17 are used to perform operations described herein, such as PPU-initiated data access. In at least one embodiment, one or more systems shown in FIG. 17 are used to implement one or more systems and / or methods described in connection with FIGS. 1A-7. In at least one embodiment, supercomputer shown in FIG. 26 may be used to implement system 100 (see FIG. 1 ). For example, the supercomputer may be used to implement at least one of the computer systems 104 (see FIG. 1A ), the management framework 116 (see FIG. 1A ), and / or at least one of the external computer systems 114 (see FIG. 1A ). In at least one embodiment, supercomputer shown in FIG. 26 may be used to implement processor(s) 122. In at least one embodiment, at least a portion of system / systems shown in FIG. 17 is used to implement one or more systems, methods, functions, and / or processes described in connection with FIGS. 1A-7. For example, in at least one embodiment, at least one component illustrated or described in FIG. 17 is used to access data according to one or more techniques, functions, and / or processes described with respect to any of FIGS. 1A-7.FIG. 18 illustrates a rack-level supercomputer, in accordance with at least one embodiment. FIG. 19 illustrates an overall system level supercomputer, in accordance with at least one embodiment. In at least one embodiment, referring to FIGS. 17 and 18, high speed or copper serial optical cables (1802, 1902) are used between rack modules in a rack and across racks throughout an entire system to implement a scalable, possibly incomplete, hypercube network. In at least one embodiment, one of FPGA / ASIC chips of an accelerator is coupled to a host system via a PCI Express link (1904). In at least one embodiment, host system includes a host microprocessor (1908) running a software portion of an application and memory comprised of one or more host memory DRAM units (1906) and maintained coherent with memory on an accelerator. In at least one embodiment, host system may be a separate module on one of racks or may be integrated into one of modules of a supercomputer. In at least one embodiment, a cube-connected cycle topology provides communication links to create a hypercube network for a large supercomputer. In at least one embodiment, a small group of FPGA / ASIC chips on a rack module may function as a single hypercube node, such that a total number of external connections of each group is increased compared to a single chip. In at least one embodiment, a group includes chips A, B, C, and D on a rack module with internal wide differential buses connecting A, B, C, and D in a torus organization. In at least one embodiment, there are 12 serial communication cables connecting a rack module to outside world. In at least one embodiment, chip A on a rack module is connected to serial communication cables 0, 1, 2. In at least one embodiment, chip B is connected to cables 3, 4, 5. In at least one embodiment, chip C is connected to 6, 7, 8. In at least one embodiment, chip D is connected to 9, 10, 11. In at least one embodiment, an entire group {A, B, C, D} forming a rack module may form a hypercube node within a supercomputer system with up to 212= 4096 rack modules (16384 FPGA / ASIC chips). In at least one embodiment, in order for chip A to be able to send a message on link 4 of group {A, B, C, D} to the outside, a message with an integrated differential wide bus link must first be routed to chip B. In at least one embodiment, a message arriving at link 4 (i.e., arriving at B) in a group {A, B, C, D} destined for chip A must also first be internally routed to a correct destination chip (A) within a group {A, B, C, D}. In at least one embodiment, parallel super computer systems of other sizes may also be implemented.In at least one embodiment, at least a portion of system / systems shown in FIG. 18 and / or 19 is used to perform operations discussed herein, such as PPU-initiated data access. In at least one embodiment, at least a portion of system / systems shown in FIGS. 18 and / or 19 is used to implement one or more systems and / or methods described in connection with FIGS. 1A-7. In at least one embodiment, supercomputer shown in FIG. 18 and / or supercomputer shown in FIG. 19 may be used to implement system 100 (see FIG. 1 ). For example, the supercomputer shown in FIGS. 18 and / or 19 may be used to implement at least one of the computer systems 104 (see FIG. 1A ), the management framework 116 (see FIG. 1A ), and / or at least one of the external computer systems 114 (see FIG. 1A ). In at least one embodiment, supercomputer shown in FIG. 18 and / or FIG. 19 may be used to implement processor(s) 122. In at least one embodiment, at least a portion of system / systems depicted in FIGS. 18 and / or 19 is used to implement one or more systems, methods, functions, and / or processes described in connection with FIGS. 1A-7. For example, in at least one embodiment, at least one component shown or described in FIGS. 18 and / or 19 is used to access data according to one or more methods, functions, and / or processes described with respect to any of FIGS. 1A-7.Artificial intelligenceThe following figures set forth, without limitation, exemplary artificial intelligence-based systems that may be used to implement at least one embodiment.FIG. 20A illustrates inference and / or training logic 2015 used to perform inference and / or training operations in association with one or more embodiments. Details regarding inference and / or training logic 2015 are provided below in connection with FIGS. 20A and / or 20B.In at least one embodiment, inference and / or training logic 2015 may include, without limitation, code and / or data storage 2001 to store forward and / or output weighting and / or input / output data and / or other parameters to configure neurons or layers of a neural network trained and / or used for inferencing in aspects of one or more embodiments. In at least one embodiment, training logic 2015 may include or be coupled to code and / or data storage 2001 to store graph code or other software for controlling timing and / or order in which weight and / or other parameter information is to be loaded to configure logic, including integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)). In at least one embodiment, code, such as graph code, loads weight or other parameter information into processor ALUs based on a neural network architecture to which such code corresponds. In at least one embodiment, code and / or data store 2001 stores weight parameters and / or input / output data of each layer of a neural network trained or used in connection with one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or inferencing using aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data store 2001 may be included in another on-chip or off-chip data store, including L1, L2, or L3 cache or system memory of a processor.In at least one embodiment, any portion of code and / or data store 2001 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or code and / or data store 2001 may be cache memory, dynamic random addressable memory ("DRAM"), static random addressable memory ("SRAM"), nonvolatile memory (e.g., flash memory), or other memory. In at least one embodiment, a choice of whether code and / or code and / or data store 2001 is internal or external to a processor, for example, or comprises DRAM, SRAM, flash, or other type of memory, may depend on available on-chip or off-chip memory, latency requirements of training and / or inferencing functions being performed, batch size of data used in inferencing and / or training a neural network, or a combination of these factors.In at least one embodiment, inference and / or training logic 2015 may include, without limitation, code and / or data storage 2005 to store backward and / or output weighting and / or input / output data corresponding to neurons or layers of a neural network trained and / or used for inferencing in aspects of one or more embodiments. In at least one embodiment, code and / or data store 2005 stores weight parameters and / or input / output data of each layer of a neural network trained or used in connection with one or more embodiments during backward propagation of input / output data and / or weight parameters during training and / or inferencing using aspects of one or more embodiments. In at least one embodiment, training logic 2015 may include or be coupled to code and / or data stores 2005 to store graph code or other software for controlling timing and / or order in which weight and / or other parameter information is to be loaded to configure logic, including integer and / or floating point units (collectively referred to as arithmetic logic units (ALUs)).In at least one embodiment, code, such as graph code, causes weight or other parameter information to be loaded into processor ALUs based on a neural network architecture to which such code corresponds. In at least one embodiment, any portion of code and / or data store 2005 may be included in another on-chip or off-chip data store, including L1, L2, or L3 cache or system memory of a processor. In at least one embodiment, any portion of code and / or data store 2005 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data store 2005 may be cache memory, DRAM, SRAM, nonvolatile memory (e.g., flash memory), or other memory. In at least one embodiment, a choice of whether code and / or data store 2005 is internal or external to a processor, or includes DRAM, SRAM, flash, or other type of memory, for example, may depend on available on-chip as compared to off-chip memory, latency requirements of training and / or inferencing functions being performed, batch size of data used in inferencing and / or training a neural network, or a combination of these factors.In at least one embodiment, code and / or data store 2001 and code and / or data store 2005 may be separate memory structures. In at least one embodiment, code and / or data store 2001 and code and / or data store 2005 may be a combined memory structure. In at least one embodiment, code and / or data memory 2001 and code and / or data memory 2005 may be partially combined and partially separate. In at least one embodiment, any portion of code and / or data store 2001 and code and / or data store 2005 may be included in another on-chip or off-chip data store, including L1, L2, or L3 cache or system memory of a processor.In at least one embodiment, inference and / or training logic 2015 may include, without limitation, one or more arithmetic logic unit(s) ("ALU(s)") 2010 including integer and / or floating point units to perform logical and / or mathematical operations based at least in part on or indicated by training and / or inference code (e.g., graph code), a result of which may produce activations (e.g., output values of layers or neurons within a neural network) stored in an activation memory 2020 and which are functions of input / output and / or weight parameter data stored in code and / or data memory 2001 and / or code and / or data memory 2005. In at least one embodiment, activations stored in activation memory 2020 are generated in accordance with linear algebraic and / or matrix-based mathematics performed by ALU(s) 2010 in response to executing instructions or other code, wherein weight values stored in code and / or data memory 2005 and / or data memory 2001 are used as operands along with other values, such as distortion values, gradient information, moments or other parameters or hyperparameters, any or all of which may be stored in code and / or data memory 2005 or code and / or data memory 2001 or other on-chip or off-chip memory.In at least one embodiment, ALU(s) 2010 are included within one or more processors or other hardware logic devices or circuits, while in another embodiment, ALU(s) 2010 may be external to a processor or other hardware logic device or circuit that uses it (e.g., a coprocessor). In at least one embodiment, ALUs 2010 may be included within execution units of a processor or otherwise within a bank of ALUs that execution units of a processor may access, either within same processor or distributed among different processors of different types (e.g., central processing units, graphics processing units, fixed function units, etc.). In at least one embodiment, code and / or data store 2001, code and / or data store 2005, and activation memory 2020 may share a processor or other hardware logic device or circuit, while in another embodiment, they may reside in different processors or other hardware logic devices or circuits, or in a combination of same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation memory 2020 may be included in other on-chip or off-chip data memory, including L1, L2, or L3 cache or system memory of a processor. Furthermore, the inference and / or training code may be stored with other code that is accessible by a processor or other hardware logic or circuitry and that is retrieved and / or processed using a processor's fetch, decode, scheduling, execute, commit, and / or other logic circuitry.In at least one embodiment, activation memory 2020 may be cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other memory. In at least one embodiment, activation memory 2020 may be located wholly or partially within or outside of one or more processors or other logic circuits. In at least one embodiment, a choice of whether activation memory 2020 is, for example, internal or external to a processor or includes DRAM, SRAM, flash, or other type of memory may depend on available on-chip as compared to off-chip memory, latency requirements of training and / or inferencing functions being performed, batch size of data used in inferencing and / or training a neural network, or a combination of these factors.In at least one embodiment, inference and / or training logic 2015 illustrated in FIG. 20A may be used in conjunction with an application specific integrated circuit ("ASIC"), such as a Google TensorFlow® processing unit, an GraphcoreTM inference processing unit (IPU), or an Intel Corp Nervana® (e.g., "Lake Crest") processor. In at least one embodiment, inference and / or training logic 2015 illustrated in FIG. 20A may be used in conjunction with central processing unit ("CPU") hardware, graphics processing unit ("GPU") hardware, or other hardware, such as field programmable gate arrays ("FPGAs").FIG. 20B illustrates inference and / or training logic 2015, in accordance with at least one embodiment. In at least one embodiment, inference and / or training logic 2015 may include, without limitation, hardware logic in which computing resources are dedicated or otherwise used exclusively in conjunction with weight values or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, inference and / or training logic 2015 illustrated in FIG. 20B may be used in conjunction with an application specific integrated circuit (ASIC), such as a Google TensorFlow® processing unit, a GraphcoreTM inference processing unit (IPU), or an Intel Corp Nervana® (e.g., "Lake Crest") processor. In at least one embodiment, inference and / or training logic 2015 illustrated in FIG. 20B may be used in conjunction with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware, such as field programmable gate arrays (FPGAs). In at least one embodiment, inference and / or training logic 2015 includes, without limitation, code and / or data store 2001 and code and / or data store 2005, which may be used to store code (e.g., graph code), weight values, and / or other information including distortion values, gradient information, momentum values, and / or other parameter or hyperparameter information. In at least one embodiment illustrated in FIG. 20B, each of code and / or data store 2001 and code and / or data store 2005 is associated with a dedicated computing resource, such as computing hardware 2002 and computing hardware 2006, respectively. In at least one embodiment, each of compute hardware 2002 and compute hardware 2006 includes one or more ALUs that perform mathematical functions, such as linear algebraic functions, only on information stored in code and / or data store 2001 and code and / or data store 2005, respectively, the result of which is stored in activation memory 2020.In at least one embodiment, each of code and / or data stores 2001 and 2005 and corresponding compute hardware 2002 and 2006, respectively, correspond to different layers of a neural network, such that resulting activation from one memory / compute pair 2001 / 2002 of code and / or data store 2001 and compute hardware 2002 is provided as input to a next memory / compute pair 2005 / 2006 of code and / or data store 2005 and compute hardware 2006 to reflect a conceptual organization of a neural network. In at least one embodiment, each of memory / compute pairs 2001 / 2002 and 2005 / 2006 may correspond to more than one layer of a neural network. In at least one embodiment, additional memory / compute pairs (not shown) subsequent to or parallel to memory / compute pairs 2001 / 2002 and 2005 / 2006 may be included in inference and / or training logic 2015.In at least one embodiment, at least a portion of system / systems depicted in FIGS. 20A and / or 20B is used to perform operations discussed herein, such as PPU-initiated data access. In at least one embodiment, at least a portion of system / systems shown in FIGS. 20A and / or 20B is used to implement one or more systems and / or methods described in connection with FIGS. 1A-7. In at least one embodiment, inference and / or training logic 2015 may be used to implement system 100 (see FIG. 1 ). For example, inference and / or training logic 2015 may be used to implement at least a portion of application 146 (see FIG. 1B ), at least a portion of client 152, and / or at least a portion of server 154. In at least one embodiment, inference and / or training logic 2015 may be implemented by one or more of computer systems 104 (see FIG. 1A ) and / or one or more of processors 122. In at least one embodiment, at least a portion of system / systems depicted in FIGS. 20A and / or 20B is used to implement one or more systems, methods, functions, and / or processes described in connection with FIGS. 1A-7. For example, in at least one embodiment, at least one component shown or described in FIGS. 20A and / or 20B is used to access data according to one or more methods, functions, and / or processes described with respect to any of FIGS. 1A-7.FIG. 21 illustrates training and deployment of a deep neural network, according to at least one embodiment. In at least one embodiment, trained neural network 2106 is trained using training dataset 2102. In at least one embodiment, training framework 2104 is a PyTor framework, whereas in other embodiments, training framework 2104 is a TensorFlow, Boost, Coffee, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training framework. In at least one embodiment, training framework 2104 trains an untrained neural network 2106, and enables it to be trained using processing resources described herein to generate a trained neural network 2108. In at least one embodiment, weights may be chosen randomly or by pretraining using a deep belief network. In at least one embodiment, training may be performed in either monitored, partially monitored, or unsupervised fashion.In at least one embodiment, non-trained neural network 2106 is trained using supervised learning, wherein training dataset 2102 includes an input paired with a desired output for an input, or wherein training dataset 2102 includes an input having a known output and an output of neural network 2106 is manually evaluated. In at least one embodiment, trained neural network 2106 is trained in a supervised manner and processes inputs from training dataset 2102 and compares resulting outputs to a set of expected or desired outputs. In at least one embodiment, errors are then back propagated through non-trained neural network 2106. In at least one embodiment, training framework 2104 adjusts weights that control non-trained neural network 2106. In at least one embodiment, training framework 2104 includes tools to monitor how well non-trained neural network 2106 converges to a model, such as trained neural network 2108 that is capable of generating correct responses, such as in result 2114, based on input data, such as a new dataset 2112. In at least one embodiment, training framework 2104 repeatedly trains untrained neural network 2106 while adjusting weights to refine an output of untrained neural network 2106 using a loss function and an adjustment algorithm such as stochastic gradient descent. In at least one embodiment, training framework 2104 trains untrained neural network 2106 until untrained neural network 2106 reaches a desired accuracy. In at least one embodiment, trained neural network 2108 may then be deployed to implement any number of machine learning operations.In at least one embodiment, non-trained neural network 2106 is trained using unsupervised learning, where non-trained neural network 2106 attempts to train itself using unlabeled data. In at least one embodiment, unsupervised learning training dataset 2102 includes input data without associated output data or ground truth data. In at least one embodiment, non-trained neural network 2106 may learn groupings within training dataset 2102 and determine how individual inputs relate to non-trained dataset 2102. In at least one embodiment, unsupervised training may be used to generate a self-organizing map in trained neural network 2108, which is capable of performing operations useful in reducing dimensionality of new dataset 2112. In at least one embodiment, unsupervised training may also be used to perform anomaly detection, which enables identification of data points in new dataset 2112 that deviate from normal patterns of new dataset 2112.In at least one embodiment, semi-supervised learning may be used, which is a technique in which training dataset 2102 includes a mixture of marked and unlabeled data. In at least one embodiment, training framework 2104 may be used to perform incremental learning, such as by transfer learning techniques. In at least one embodiment, incremental learning enables trained neural network 2108 to adapt to new dataset 2112 without forgeting knowledge contributed to trained neural network 2108 during initial training.In at least one embodiment, at least one or more of systems shown in FIG. 21 are employed to perform operations described herein, such as PPU-initiated data access. In at least one embodiment, at least one or more systems illustrated in FIG. 21 are used to implement one or more systems and / or methods described in connection with FIGS. 1A-7. In at least one embodiment, training and deep neural network deployment illustrated in FIG. 21 may be used to implement system 100 (see FIG. 1 ). For example, training and provisioning may be used to implement at least a portion of the application 146 (see FIG. 1B ), at least a portion of the client 152, and / or at least a portion of the server 154. In at least one embodiment, training and provisioning may be performed by one or more of computer systems 104 (see FIG. 1A ) and / or one or more of processors 122. In at least one embodiment, at least a portion of system / systems shown in FIG. 21 is used to implement one or more systems, methods, functions, and / or processes described in connection with FIGS. 1A-7. For example, in at least one embodiment, at least a portion of system / systems shown in FIG. 21 is used to access data according to one or more techniques, functions, and / or processes described with respect to any of FIGS. 1A-7.5G networksThe following figures set forth, without limitation, example 5G network-based systems that may be used to implement at least one embodiment.FIG. 22 illustrates an architecture of a system 2200 of a network, according to at least one embodiment. In at least one embodiment, system 2200 is shown to include user equipment (UE) 2202 and UE 2204. In at least one embodiment, UEs 2202 and 2204 are illustrated as smartphones (e.g., portable touchscreen mobile computing devices connectable to one or more cellular networks), but may also include any mobile or non-mobile computing device, such as personal data assistants (PDAs), pagers, laptop computers, desktop computers, handheld wireless devices, or any computing device having a wireless communication interface.In at least one embodiment, each of UEs 2202 and 2204 may include an Internet of Things (loT) UE that may include a network access layer configured for low power loT applications that utilize short lived UE connections. In at least one embodiment, an loT UE may utilize technologies such as machine-to-machine (M2M) or machine-type communication (MTC) to exchange data with an MTC server or device via a public land mobile network (PLMN), proximity-based service (ProSe), or device-to-device (D2D) communication, sensor networks, or loT networks. In at least one embodiment, an M2M or MTC data exchange may be a machine initiated data exchange. In at least one embodiment, an loT network describes connecting loT UEs, which may include uniquely identifiable embedded computing devices (within Internet infrastructure), to short-lived connections. In at least one embodiment, loT UEs may execute background applications (e.g., keep alive messages, status updates, etc.) to enable connections of an loT network.In at least one embodiment, UEs 2202 and 2204 may be configured to connect, e.g., communicatively couple, to a radio access network (RAN) 2216. In at least one embodiment, RAN 2216 may be, for example, an evolved universal mobile telecommunications system (UMTS), terrestrial radio access network (E-UTRAN), a NextGen RAN (NG RAN), or another type of RAN. In at least one embodiment, UEs 2202 and 2204 use links 2212 and 2214, respectively, each of which includes a physical communication interface or layer. In at least one embodiment, links 2212 and 2214 are illustrated as an air interface to enable communicative coupling, and may be implemented using cellular communication protocols such as a Global System for Mobile Communications (GSM) protocol, a Code Division Multiple Access (CDMA) network protocol, a Push-to-Talk (PTT) protocol, a PTT over Cellular (POC) protocol, a Universal Mobile Telecommunications System (UMTS) protocol, a 3GPP Long Term Evolution (LTE) protocol, a Fifth Generation (5G) protocol, The radio channels may be in accordance with a new radio (NR) protocol and variations thereof.In at least one embodiment, UEs 2202 and 2204 may further exchange communication data directly via a ProSe interface 2206. In at least one embodiment, ProSe interface 2206 may alternatively be referred to as a sidelink interface that includes one or more logical channels including, but not limited to, a physical sidelink control channel (PSCCH), physical sidelink shared channel (PSSCH), physical sidelink discovery channel (PSDCH), and physical sidelink broadcast channel (PSBCH).In at least one embodiment, UE 2204 is shown configured to access an access point (AP) 2210 via connection 2208. In at least one embodiment, link 2208 may comprise a local wireless link, such as a link conforming to any IEEE 802.11 protocol, wherein AP 2210 would comprise a wireless fidelity (WiFi®) router. In at least one embodiment, AP 2210 is shown connected to an Internet without connecting to a core network of a wireless system.In at least one embodiment, RAN 2216 may include one or more access nodes that enable connections 2212 and 2214. In at least one embodiment, these access nodes (AN) may be referred to as base stations (BS), NodeBs, evolved NodeBs (eNBs), next generation NodeBs (gNB), RAN nodes, etc., and may include ground stations (e.g., terrestrial access points) or satellite stations providing coverage within a geographic area (e.g., a cell). In at least one embodiment, RAN 2216 may include one or more RAN nodes to provide macrocells, e.g., macro RAN nodes 2218, and one or more RAN nodes to provide femtocells or picocells (e.g., cells with larger coverage areas, smaller user capacity, or larger bandwidth compared to macrocells), e.g., low power (LP) RAN nodes 2220.In at least one embodiment, any of RAN nodes 2218 and 2220 may terminate an air interface protocol and may be a first contact point for UEs 2202 and 2204. In at least one embodiment, any of RAN nodes 2218 and 2220 may perform various logical functions for RAN 2216, including, but not limited to, radio network controller (RNC) functions such as radio bearer management, uplink and downlink dynamic radio resource management, and packet scheduling and mobility management.In at least one embodiment, UEs 2202 and 2204 may be configured to communicate with each other or with any RAN node 2218 and 2220 over a multicarrier communication channel using orthogonal frequency division multiple access (OFDMA) communication signals according to various communication techniques, such as, but not limited to, an orthogonal frequency division multiple access (OFDMA) (e.g., for downlink communication) or a single carrier frequency division multiple access (SC-FDMA) (e.g., for uplink and proSe or sidelink communication) communication technique, and / or variations thereof. In at least one embodiment, OFDM signals may comprise a plurality of orthogonal subcarriers.In at least one embodiment, a downlink resource grid may be used for downlink transmissions from any of RAN nodes 2218 and 2220 to UEs 2202 and 2204, while uplink transmissions may use similar techniques. In at least one embodiment, a grid may be a time-frequency grid, referred to as a resource grid or time-frequency resource grid, which is a physical resource in a downlink in each time slot. In at least one embodiment, such a time-frequency-plane representation is a common practice for OFDM systems, making them intuitive for radio resource allocation. In at least one embodiment, each column and row of a resource grid corresponds to an OFDM symbol and an OFDM subcarrier, respectively. In at least one embodiment, a duration of a resource grid in a time domain corresponds to a time slot in a radio frame. In at least one embodiment, a smallest time-frequency unit in a resource grid is referred to as a resource element. In at least one embodiment, each resource grid comprises a series of resource blocks describing an assignment of certain physical channels to resource elements. In at least one embodiment, each resource block comprises a collection of resource elements. In at least one embodiment, in a frequency domain, this may represent a smallest amount of resources that may be currently allocated. In at least one embodiment, there are multiple different physical downlink channels that are transmitted using such resource blocks.In at least one embodiment, a physical downlink shared channel (PDSCH) may transmit user data and higher layer signaling to UEs 2202 and 2204. In at least one embodiment, a physical downlink control channel (PDCCH) may transmit information about a transport format and resource assignments related to PDSCH channel, among other things. In at least one embodiment, it may also inform UEs 2202 and 2204 of a transport format, resource allocation, and hybrid automatic repeat request (HARQ) information regarding an uplink shared channel. In at least one embodiment, downlink scheduling (allocating shared channel control and resource blocks to UE 2202 within a cell) may typically be performed at any of RAN nodes 2218 and 2220 based on channel quality information returned from any of UEs 2202 and 2204. In at least one embodiment, downlink resource assignment information may be transmitted on a PDCCH used (e.g., assigned) for each of UEs 2202 and 2204.In at least one embodiment, a PDCCH may use control channel elements (CCEs) to transmit control information. In at least one embodiment, complex valued PDCCH symbols may first be organized into quads before being allocated to resource elements, which may then be permuted using a sub-block interleaver for rate matching. In at least one embodiment, each PDCCH may be transmitted using one or more of these CCEs, where each CCE may correspond to nine sets of four physical resource elements known as resource element groups (REGs). In at least one embodiment, each REG may be associated with four Quadrature Phase Shift Keying (QPSK) symbols. In at least one embodiment, PDCCH may be transmitted using one or more CCEs depending on a size of downlink control information (DCI) and a channel state. In at least one embodiment, four or more different PDCCH formats may be defined in LTE with different numbers of CCEs (e.g., aggregation level, L=1, 2, 4, or 8).In at least one embodiment, an enhanced physical downlink control channel (EPDCCH) using PDSCH resources may be used for transmission of control information. In at least one embodiment, EPDCCH may be transmitted using one or more enhanced control channel elements (ECCEs). In at least one embodiment, each ECCE may correspond to nine sets of four physical resource elements known as extended resource element groups (EREGs). In at least one embodiment, in some situations, an ECCE may include a different number of EREGs.In at least one embodiment, RAN 2216 is shown communicatively coupled to a core network (CN) 2238 via an S1 interface 2222. In at least one embodiment, CN 2238 may be an evolved packet core (EPC) network, a nextGen packet core (NPC) network, or another type of CN. In at least one embodiment, S1 interface 2222 is split into two parts: S1-U interface 2226 that transfers traffic data between RAN nodes 2218 and 2220 and serving gateway (S-GW) 2230, and a S1 mobility management entity (MME) interface 2224 that is a signaling interface between RAN nodes 2218 and 2220 and MMEs 2228.In at least one embodiment, CN 2238 includes MMEs 2228, S-GW 2230, Packet Data Network (PDN) Gateway (P-GW) 2234, and a home subscriber server (HSS) 2232. In at least one embodiment, MMEs 2228 may be similar in function to a Serving General Packet Radio Service (GPRS) (SGSN) control plane of serving legacy support nodes. In at least one embodiment, MMEs 2228 may manage mobility aspects in access, such as gateway selection and tracking area list management. In at least one embodiment, HSS 2232 may include a database for network users, including subscription-related information, to aid in handling of communication sessions by a network entity. In at least one embodiment, CN 2238 may include one or more HSSs 2232, depending on a number of cellular subscribers, a capacity of equipment, an organization of a network, etc. In at least one embodiment, HSS 2232 may provide support for routing / roaming, authentication, authorization, name / address resolution, location dependencies, etc.In at least one embodiment, S-GW 2230 may terminate an S1 interface 2222 towards RAN 2216 and route data packets between RAN 2216 and CN 2238. In at least one embodiment, S-GW 2230 may be a local mobility anchor point for inter-RAN node handovers and may also provide an anchor for inter-3GPP mobility. In at least one embodiment, other responsibilities may include legal interception, charging, and enforcement of certain policies.In at least one embodiment, P-GW 2234 may terminate an SGi interface towards a PDN. In at least one embodiment, P-GW 2234 may route data packets between an EPC network 2238 and external networks, such as a network including application server 2240 (alternatively referred to as application function (AF)), via an Internet Protocol (IP) interface 2242. In at least one embodiment, application server 2240 may be an element offering applications that use IP bearer resources with a core network (e.g., UMTS Packet Services (PS) domain, LTE PS data services, etc.). In at least one embodiment, P-GW 2234 is shown communicatively coupled to an application server 2240 via an IP communication interface 2242. In at least one embodiment, application server 2240 may also be configured to support one or more communication services (e.g., voice over Internet Protocol (VolP) sessions, PTT sessions, group communication sessions, social network services, etc.) for UEs 2202 and 2204 via CN 2238.In at least one embodiment, P-GW 2234 may further be a node for policy enforcement and charging data. In at least one embodiment, policy and charging enforcement function (PCRF) 2236 is a policy and charging enforcement function of CN 2238. In at least one embodiment, in a non-roaming scenario, there may be a single PCRF in a Home Public Land Mobile Network (HPLMN) associated with a UE's Internet Protocol Connectivity Access Network (IP-CAN) session. In at least one embodiment, in a roaming scenario with local traffic abort, there may be two PCRFs associated with an IP-CAN session of a UE: a home PCRF (H-PCRF) within an HPLMN and a visited PCRF (V-PCRF) within a visited public land mobile network (VPLMN). In at least one embodiment, PCRF 2236 may be communicatively coupled to an application server 2240 via P-GW 2234. In at least one embodiment, application server 2240 may signal PCRF 2236 to indicate a new service flow and select an appropriate Quality of Service (QoS) and charging parameters. In at least one embodiment, 2236 may provide this rule in a Policy and Charging Enforcement Function (PCEF) (not shown) with a suitable Traffic Flow Template (TFT) and QoS class of identifier (QCI) beginning a QoS and charges as specified by application server 2240.In at least one embodiment, at least one or more of systems shown in FIG. 22 are used to perform operations described herein, such as PPU-initiated data access. In at least one embodiment, at least one or more systems illustrated in FIG. 22 are used to implement one or more systems and / or methods described in connection with FIGS. 1A-7. In at least one embodiment, system 2200 may be used to implement system 100 (see FIG. 1 ). For example, the system 2200 may be used to implement at least a portion of the external network 110 and / or the application server 2240 may be used to implement at least one of the computer systems 104 (see FIG. 1A ), the management framework 116 (see FIG. 1A ), and / or at least one of the external computer systems 114 (see FIG. 1A ). In at least one embodiment, at least one of UE 2202 and 2204 may be used to implement at least one of external computing device(s) 114. In at least one embodiment, at least a portion of system or systems shown in FIG. 22 is used to implement one or more systems, methods, functions, and / or processes described in connection with FIGS. 1A-7. For example, in at least one embodiment, at least a portion of system / systems shown in FIG. 22 is used to access data according to one or more methods, functions, and / or processes described with respect to any of FIGS. 1A-7.FIG. 23 illustrates an architecture of a system 2300 of a network, in accordance with some embodiments. In at least one embodiment, system 2300 is shown to include a UE 2302, a 5G access node or RAN node (shown as (R)AN node 2308), a user plane function (shown as UPF 2304), a data network (DN 2306) that may be, for example, operator services, Internet access, or third party services, and a 5G core network (5NB) (shown as CN 2310).In at least one embodiment, CN 2310 includes an authentication server function (AUSF 2314); an access and mobility function (AMF 2312); a session management function (SMF 2318); a network exposure function (NEF 2316); a policy control function (PCF 2322); a network function (NF) repository function (NRF 2320); a unified data management (UDM 2324); and an application function (AF 2326). In at least one embodiment, CN 2310 may also include other elements not shown, such as a structured data storage network function (SDSF), an unstructured data storage network function (UDSF), and variations thereof.In at least one embodiment, UPF 2304 may serve as an anchor point for intra-RAT and inter-RAT mobility, an external PDU session point of interfacing with DN 2306, and a branch point for supporting a multi-networked PDU session. In at least one embodiment, UPF 2304 may also perform packet routing and forwarding, packet inspection, enforce a portion of user-level policy rules, legal interception (UP collection) packets, perform traffic usage reports, QoS handling for user-level (e.g., packet filtering, gating, UL / DL rate enforcing), uplink traffic verification (e.g., SDF-to-QoS flow mapping), uplink and downlink packet buffering packet tagging, and downlink data notification initiation. In at least one embodiment, UPF 2304 may include an uplink classifier to assist in routing traffic flows to a data network. In at least one embodiment, DN 2306 may represent various network operator services, Internet access, or third party services.In at least one embodiment, AUSF 2314 may store data for authenticating UE 2302 and handle authentication-related functionality. In at least one embodiment, AUSF 2314 may enable a common authentication framework for different access types.In at least one embodiment, AMF 2312 may be responsible for registration management (e.g., registration of UE 2302, etc.), connection management, reachability management, mobility management, and legal interception of AMF-related events, and access authentication and authorization. In at least one embodiment, AMF 2312 may provide transport of SM messages to SMF 2318 and act as a transparent proxy for routing SM messages. In at least one embodiment, AMF 2312 may also provide for transport of short message service (SMS) messages between UE 2302 and an SMS function (SMSF) (not shown in FIG. 23). In at least one embodiment, AMF 2312 may function as a security anchor function (SEA), which may include interaction with AUSF 2314 and UE 2302 and receipt of an intermediate key created as a result of authentication process of UE 2302. In at least one embodiment using USIM-based authentication, AMF 2312 may retrieve security material from AUSF 2314. In at least one embodiment, AMF 2312 may also include a security context management (SCM) function that receives a key from SEA that it uses to derive access network specific keys. In at least one embodiment, AMF 2312 may also be a termination point of RAN CP interface (N2 reference point), a termination point of NAS (NI) signaling, and perform NAS encryption and integrity protection.In at least one embodiment, AMF 2312 may also support NAS signaling with a UE 2302 via an N3 Interworking Function (IWF) interface. In at least one embodiment, N3IWF may be used to provide access to untrusted entities. In at least one embodiment, N3IWF may be a termination point for N2 and N3 interfaces for control plane and user plane, respectively, and thus may handle N2 signaling from SMF and AMF for PDU sessions and QoS, encapsulate / de-encapsulate data packets for IPSec and N3 tunneling, mark N3 user plane packets in uplink, and enforce QoS according to N3 packet marking, considering QoS requirements associated with such a mark received via N2. In at least one embodiment, N3IWF may also forward uplink and downlink control plane NAS (NI) signaling between UE 2302 and AMF 2312, and forward uplink and downlink user plane packets between UE 2302 and UPF 2304. In at least one embodiment, N3IWF also provides mechanisms for IPsec tunnel establishment with UE 2302.In at least one embodiment, SMF 2318 may provide session management (e.g., session establishment, modification, and release, including maintaining tunnel between UPF and AN node); UE IP address assignment and management (including optional authorization); selection and control of UP function; configuration of traffic control at UPF to route traffic to proper destination; termination of interfaces to policy control functions; control of part of policy enforcement and QoS; legal interception (for SM events and interface to LI system); termination of SM parts of NAS messages; downlink data notification; Initiator of AN-specific SM information sent to the AN via AMF via N2; determine the SSC mode of a session. In at least one embodiment, SMF 2318 may include roaming functionality of: handling local enforcement to apply QoS SLAB (VPLMN); charging data collection and charging interface (VPLMN); legal interception (in VPLMN for SM events and interface to LI system); support for interaction with external DN for transporting signaling for PDU session authorization / authentication through external DN.In at least one embodiment, NEF 2316 may provide means for securely revealing services and capabilities provided by 3GPP network functions to third party, internal revealing / reduncing, application functions (e.g., AF 2326), edge computing or fog computing systems, etc. In at least one embodiment, NEF 2316 may authenticate, authorize, and / or throttle AFs. In at least one embodiment, NEF 2316 may also translate information exchanged with AF 2326 and information exchanged with internal network functions. In at least one embodiment, NEF 2316 may translate between an AF service identifier and internal 5GC information. In at least one embodiment, NEF 2316 may also receive information from other network functions (NF) based on disclosed capabilities of other network functions. In at least one embodiment, this information may be stored as structured data in NEF 2316 or in a data storage NF using standardized interfaces. In at least one embodiment, stored information may then be re-exposed by NEF 2316 to other NF and AF and / or used for other purposes, such as analyses.In at least one embodiment, NRF 2320 may support service discovery functions, receive NF discovery requests from NF instances, and provide information about discovered NF instances to NF instances. In at least one embodiment, NRF 2320 also maintains information about available NF instances and their supported services.In at least one embodiment, PCF 2322 may provide policy rules for control-level function(s) to enforce them, and may also support a unified policy framework to regulate network behavior. In at least one embodiment, PCF 2322 may also implement a front end (FE) to access subscription information relevant to policy decisions in a UDR of UDM 2324.In at least one embodiment, UDM 2324 may process subscription-related information to assist in handling communication sessions of network entities, and may store subscription data of UE 2302. In at least one embodiment, UDM 2324 may include two parts, an application FE and a user data repository (UDR). In at least one embodiment, UDM may include a UDM FE responsible for processing credentials, location management, subscription management, etc. In at least one embodiment, multiple different front ends may serve a same user in different transactions. In at least one embodiment, UDM FE accesses subscription information stored in a UDR and performs authentication access data processing; user identification handling; access entitlement; registration / mobility management; and subscription management. In at least one embodiment, UDR may interact with PCF 2322. In at least one embodiment, UDM 2324 may also support SMS management, where an SMS-FE implements similar application logic as discussed above.In at least one embodiment, AF 2326 may provide application impact on traffic routing, access to Network Capability Exposure (NCE), and interact with a policy framework for policy control. In at least one embodiment, NCE may be a mechanism that allows 5GC and AF 2326 to provide information to each other via NEF 2316 that may be used for edge computing implementations. In at least one embodiment, services of network operator and third party providers near UE 2302 access point may be hosted to achieve efficient service delivery through reduced end-to-end latency and loading on a transport network. In at least one embodiment, for edge computing implementations, 5GC may select a UPF 2304 proximate to UE 2302 and perform traffic control from UPF 2304 to DN 2306 via N6 interface. In at least one embodiment, this may be based on UE subscription data, UE location, and information provided by AF 2326. In at least one embodiment, AF 2326 may affect UPF (re)selection and traffic routing. In at least one embodiment, based on operator deployment, when AV 2326 is considered a trusted entity, a network operator may allow AV 2326 to interact directly with relevant NFs.In at least one embodiment, CN 2310 may include an SMSF, which may be responsible for SMS subscription checking and verification and forwarding SM messages to / from UE 2302 to / from other entities such as an SMS GMSC / IWMSC / SMS router. In at least one embodiment, SMS may also interact with AMF 2312 and UDM 2324 for a notification procedure that UE 2302 is available for SMS transmission (e.g., set a UE unreachable flag and notify UDM 2324 if UE 2302 is available for SMS).In at least one embodiment, system 2300 may include service-based interfaces: Namf: service-based interface shown by AMF; Nsmf: service-based interface shown by SMF; Nnef: service-based interface shown by NEF; Npcf: service-based interface shown by PCF; Nudm: service-based interface shown by UDM; Naf: service-based interface shown by AF; Nnrf: service-based interface shown by NRF; and Nausf: service-based interface shown by AUSF.In at least one embodiment, system 2300 may include reference points: N1: reference point between UE and AMF; N2: reference point between (R)AN and AMF; N3: reference point between (R)AN and UPF; N4: reference point between SMF and UPF; and N6: reference point between UPF and a data network. In at least one embodiment, there may be many more reference points and / or service-based interfaces between NF services in NF, however, these interfaces and reference points have been omitted for clarity. In at least one embodiment, an NS reference point may be between PCF and AF; an N7 reference point may be between PCF and SMF; an N11 reference point between AMF and SMF; etc. In at least one embodiment, CN 2310 may include an Nx interface, which is an inter-CN interface between MME and AMF 2312 to enable cooperation between CN 2310 and CN 7223.In at least one embodiment, system 2300 may include multiple RAN nodes (such as (R)AN nodes 2308), wherein an Xn interface is defined between two or more (R)AN nodes 2308 (e.g., gNBs) connected to 5NB 410, between an (R)AN node 2308 (e.g., gNB) connected to CN 2310, and an eNB (e.g., a macro RAN node), and / or between two eNBs connected to CN 2310.In at least one embodiment, Xn interface may include an Xn user plane (Xn-U) interface and an Xn control plane (Xn-C) interface. In at least one embodiment, Xn-U may provide non-guaranteed delivery of user plane PDU and support / provide data forwarding and flow control functionality. In at least one embodiment, Xn-C may provide management and error handling functionality, functionality for managing an Xn-C interface; mobility support for UE 2302 in a connected mode (e.g., CM-CONNECTED), including functionality for managing UE mobility for connected mode between one or more (R)AN nodes 2308. In at least one embodiment, mobility support may include context transfer from an old serving (R)AN node 2308 (source) to a new serving (R)AN node 2308 (destination); and control of user plane tunnels between old serving (R)AN node 2308 (source) to new serving (R)AN node 2308 (destination).In at least one embodiment, a protocol stack of an Xn-U may include a transport network layer built on an Internet Protocol (IP) transport layer and a GTP-U layer on a UDP and / or IP layer(s) to transmit user-level PDU. In at least one embodiment, Xn-C protocol stack may include an application layer signaling protocol (referred to as an Xn application protocol (Xn-AP)) and a transport network layer built on an SCTP layer. In at least one embodiment, SCTP layer may be located on an IP layer. In at least one embodiment, SCTP layer provides guaranteed delivery of application layer messages. In at least one embodiment, in a transport IP layer, point-to-point transmission is used to deliver signaling PDUs. In at least one embodiment, Xn-U protocol stack and / or an Xn-C protocol stack may be the same or similar to a user-level and / or control-level protocol stack (or stacks) shown and described herein.In at least one embodiment, at least one or more of systems shown in FIG. 23 are used to perform operations described herein, e.g., PPU-initiated data access. In at least one embodiment, at least one or more systems illustrated in FIG. 23 are used to implement one or more systems and / or methods described in connection with FIGS. 1A-7. In at least one embodiment, network implemented by system 2300 may be used to implement system 100 (see FIG. 1 ). In at least one embodiment, network implemented by system 2300 may be used to implement at least a portion of internal network 108 and / or at least a portion of external network 110. In at least one embodiment, UE 2302 may be used to implement at least one of computer systems 104 (see FIG. 1A ), management framework 116 (see FIG. 1A ), and / or at least one of external computer systems 114 (see FIG. 1A ). In at least one embodiment, at least a portion of system(s) depicted in FIG. 23 is used to implement one or more of systems, methods, functions, and / or processes described in connection with FIGS. 1A-7. For example, in at least one embodiment, at least a portion of system / systems shown in FIG. 23 is used to access data according to one or more methods, functions, and / or processes described with respect to any of FIGS. 1A-7.FIG. 24 is an illustration of a control-level protocol stack, according to at least one embodiment. In at least one embodiment, a control plane 2400 is shown as a communication protocol stack between UE 2202 (or alternatively, UE 2204), RAN 2216, and MME(s) 2228.In at least one embodiment, PHY layer 2402 may transmit or receive information used by MAC layer 2404 via one or more air interfaces. In at least one embodiment, PHY layer 2402 may further perform link adaptation or adaptive modulation and coding (AMC), power control, cell search (e.g., for initial synchronization and handover purposes), and other measurements used by higher layers, such as RRC layer 2410. In at least one embodiment, PHY layer 2402 may further perform error detection on transport channels, forward error correction (FEC) coding / decoding of transport channels, modulation / demodulation of physical channels, interleaving, rate matching, allocation to physical channels, and multiple-input multiple-output (MIMO) antenna processing.In at least one embodiment, MAC layer 2404 may perform mapping between logical channels and transport channels, multiplexing service data unit (SDU) of one or more logical channels onto transport blocks (TB) to be delivered to PHY via transport channels, de-multiplexing MAC SDU to one or more logical channels of transport blocks (TB) delivered from PHY via transport channels, multiplexing MAC SDU onto TB, scheduling information reports, hybrid automatic repeat request (HARD) error correction, and logical channel priorization.In at least one embodiment, RLC layer 2406 may operate in a variety of modes of operation including: transparent mode (TM), unacknowledged mode (UM), and acknowledged mode (AM). In at least one embodiment, RLC layer 2406 may perform an upper layer protocol data unit (PDU) transfer, automatic repeat request (ARQ) error correction for AM data transfers, and RLC SDU concatenation, segmentation, and reassembly for UM and AM data transfers. In at least one embodiment, RLC layer 2406 may also perform resegmentation of RLC data PDUs for AM data transfers, rearrange RLC data PDUs for UM and AM data transfers, detect duplicate data for UM and AM data transfers, discard RLC SDUs for UM and AM data transfers, detect protocol errors for AM data transfers, and perform RLC recovery.In at least one embodiment, PDCP layer 2408 may perform header compression and decompression of IP data, maintain PDCP sequence numbers (SN), perform sequential delivery of upper layer PDUs at lower layer recovery, eliminate duplicates of lower layer SDUs at lower layer recovery for radio bearers associated with RLC AM, encrypt and decrypt control plane data, perform integrity protection and integrity verification of control plane data, control timer-based discard of data, and perform security operations (e.g., encryption, decryption, integrity protection, integrity verification, etc.).In at least one embodiment, main services and functions of an RRC layer 2410 may include sending system information (e.g., in master information blocks (MIB) or system information blocks (SIB) related to a non-access stratum (NAS)); Transmitting system information related to an access stratum (AS), paging, establishment, maintenance and release of an RRC connection between a UE and E-UTRAN (e.g., RRC connection paging, RRC connection establishment, RRC connection modification and RRC connection release), establishment, configuration, maintenance and release of point-to-point radio bearers, security functions including key management, mobility between radio access technology (RAT), and measurement configuration for UE measurement reports. In at least one embodiment, MIBs and SIBs may include one or more information elements (IEs), each of which may include individual data fields or data structures.In at least one embodiment, UE 2202 and RAN 2216 may utilize a Uu interface (e.g., an LTE-Uu interface) to exchange control plane data via a protocol stack including PHY layer 2402, MAC layer 2404, RLC layer 2406, PDCP layer 2408, and RRC layer 2410.In at least one embodiment, non-access layer (NAS) protocols (NAS protocols 2412) form a highest layer of control plane between UE 2202 and MME(s) 2228. In at least one embodiment, NAS protocols 2412 support UE 2202 mobility and session management procedures to establish and maintain IP connectivity between UE 2202 and P-GW 2234.In at least one embodiment, Si application protocol (S1-AP) layer (Si-AP layer 2422) may support functions of a Si interface and include elemental procedures (EPs). In at least one embodiment, an EP is an interaction unit between RAN 2216 and CN 2228. In at least one embodiment, S1-AP layer services may comprise two groups: UE-associated services and non-UE-associated services. In at least one embodiment, these services perform functions including, but not limited to: E-UTRAN Radio Access Bearer (E-UTRAN Radio Access Bearer (E-RAB) management, UE capability indication, mobility, NAS signaling transport, RAN Information Management (RIM), and configuration transmission.In at least one embodiment, stream control transmission protocol (SCTP) layer (alternatively referred to as stream control transmission protocol / Internet protocol (SCTP / IP) LAYER) (SCTP layer 2420) may ensure reliable delivery of signaling messages between RAN 2216 and MME(s) 2228, based in part on an IP protocol supported by an IP layer 2418. In at least one embodiment, L2 layer 2416 and L1 layer 2414 may refer to communication links (e.g., wired or wireless) used by a RAN node and an MME to exchange information.In at least one embodiment, RAN 2216 and MME(s) 2228 may utilize an S1-MME interface to exchange control plane data via a protocol stack including an L1 layer 2414, an L2 layer 2416, an IP layer 2418, an SCTP layer 2420, and a Si-AP layer 2422.In at least one embodiment, at least one or more of systems shown in FIG. 24 are used to perform operations described herein, such as PPU-initiated data access. In at least one embodiment, at least one or more systems illustrated in FIG. 24 are used to implement one or more systems and / or methods described in connection with FIGS. 1A-7. In at least one embodiment, network implemented by system 2400 may be used to implement system 100 (see FIG. 1 ). In at least one embodiment, network implemented by system 2400 may be used to implement at least a portion of internal network 108 and / or at least a portion of external network 110. In at least one embodiment, UE 2402 may be used to implement at least one of computer systems 104 (see FIG. 1A ), management framework 116 (see FIG. 1A ), and / or at least one of external computer systems 114 (see FIG. 1A ). In at least one embodiment, at least a portion of system(s) depicted in FIG. 24 is used to implement one or more of systems, methods, functions, and / or processes described in connection with FIGS. 1A-7. For example, in at least one embodiment, at least a portion of system / systems shown in FIG. 24 is used to access data according to one or more methods, functions, and / or processes described with respect to any of FIGS. 1A-7.FIG. 25 is an illustration of a user-level protocol stack, according to at least one embodiment. In at least one embodiment, a user plane 2500 is shown as a communication protocol stack between a UE 2202, RAN 2216, S-GW 2230, and P-GW 2234. In at least one embodiment, user plane 2500 may use same protocol layers as control plane 2400. For example, in at least one embodiment, UE 2202 and RAN 2216 may utilize a Uu interface (e.g., an LTE-Uu interface) to exchange user plane data via a protocol stack including PHY layer 2402, MAC layer 2404, RLC layer 2406, and PDCP layer 2408.In at least one embodiment, General Packet Radio Service (GPRS) tunneling protocol for a user plane (GTP-U) LAYER (GTP-U layer 2504) may be used to transmit user data within a GPRS core network and between a radio access network and a core network. In at least one embodiment, for example, user data transported may be packets in any of formats IPv4, IPv6, or PPP. In at least one embodiment, UDP and IP security (UDP / IP) layers (UDP / IP layer 2502) may provide checksums for data integrity, port numbers for addressing different functions at a source and destination, and encryption and authentication for selected data flows. In at least one embodiment, RAN 2216 and S-GW 2230 may utilize an S 1-U interface to exchange user plane data via a protocol stack including L 1 layer 2414, L 2 layer 2416, UDP / IP layer 2502, and GTP-U layer 2504. In at least one embodiment, S-GW 2230 and P-GW 2234 may utilize an S5 / S8a interface to exchange user plane data via a protocol stack including L1 layer 2414, L2 layer 2416, UDP / IP layer 2502, and GTP-U layer 2504. In at least one embodiment, as discussed above with reference to FIG. 24, NAS protocols support mobility of UE 2202 and session management procedures to establish and maintain IP connectivity between UE 2202 and P-GW 2234.FIG. 26 illustrates components 2600 of a core network, according to at least one embodiment. In at least one embodiment, components of CN 2238 may be implemented in a physical node or separate physical nodes, including components for reading and executing instructions from a machine-readable or computer-readable medium (e.g., a non-transitory machine-readable storage medium). In at least one embodiment, network function virtualization (NFV) is used to virtualize one or all of network node functions described above via executable instructions stored on one or more computer readable storage media (described in more detail below). In at least one embodiment, a logical instantiation of CN 2238 may be referred to as a network slice 2602 (e.g., network slice 2602 includes presentation after HSS 2232, MME(s) 2228, and S-GW 2230). In at least one embodiment, a logical instantiation of a portion of CN 2238 may be referred to as a network sub-slice 2604 (e.g., network sub-slice 2604 is shown to include P-GW 2234 and PCRF 2236).In at least one embodiment, NFV architectures and infrastructures may be used to virtualize one or more network functions, alternatively performed by proprietary hardware, on physical resources comprising a combination of industry standard server hardware, storage hardware, or switches. In at least one embodiment, NFV systems may be used to perform virtual or reconfigurable implementations of one or more EPC components / functions.FIG. 27 is a block diagram illustrating components of a system 2700 for supporting network function virtualization (NFV), according to at least one embodiment. In at least one embodiment, system 2700 is illustrated as including a virtualized infrastructure manager (shown as VIM 2702), a network function virtualization infrastructure (shown as NFVI 2704), a VNF manager (shown as VNFM 2706), virtualized network functions (shown as VNF 2708), an element manager (shown as EM 2710), an NFV orchestrator (shown as NFVO 2712), and a network manager (shown as NM 2714).In at least one embodiment, VIM 2702 manages resources of NFVI 2704. In at least one embodiment, NFVI 2704 may include physical or virtual resources and applications (including hypervisors) used to execute system 2700. In at least one embodiment, VIM 2702 may manage a life cycle of virtual resources with NFVI 2704 (e.g., creation, maintenance, and mining of virtual machines (VMs) associated with one or more physical resources), track VM instances, track performance, track VM instances and associated physical resource failures and security, and expose VM instances and associated physical resources to other management systems.In at least one embodiment, VNFM 2706 may manage VNF 2708. In at least one embodiment, VNF 2708 may be used to perform EPC components / functions. In at least one embodiment, VNFM 2706 may manage a life cycle of VNF 2708 and track performance, fault, and security of virtual aspects of VNF 2708. In at least one embodiment, EM 2710 may track performance, error, and security of functional aspects of VNF 2708. For example, in at least one embodiment, tracking data of VNFM 2706 and EM 2710 may include performance measurement (PM) data used by VIM 2702 or NFVI 2704, in at least one embodiment. In at least one embodiment, both VNFM 2706 and EM 2710 may scale up / down an amount of VNF of system 2700.In at least one embodiment, NFVO 2712 may coordinate, authorize, release, and deploy resources of NFVI 2704 to provide a requested service (e.g., to execute an EPC function, component, or slice). In at least one embodiment, NM 2714 may provide a packet of end user functions with responsibility for management of a network that may include network elements with VNF, non-virtualized network functions, or both (management of VNF may occur via EM 2710).In at least one embodiment, at least one or more of systems shown in FIG. 27 are employed to perform operations described herein, such as PPU-initiated data access. In at least one embodiment, at least one or more systems illustrated in FIG. 27 are used to implement one or more systems and / or methods described in connection with FIGS. 1A-7. In at least one embodiment, system 2700 may be used to implement system 100 (see FIG. 1 ). In at least one embodiment, virtual network implemented by system 2700 may be used to implement at least a portion of internal network 108 and / or at least a portion of external network 110. In at least one embodiment, UE 2702 may be used to implement at least one of computer systems 104 (see FIG. 1A ), management framework 116 (see FIG. 1A ), and / or at least one of external computer systems 114 (see FIG. 1A ). In at least one embodiment, at least a portion of system / systems shown in FIG. 27 is used to implement one or more systems, methods, functions, and / or processes described in connection with FIGS. 1A-7. For example, in at least one embodiment, at least a portion of system / systems shown in FIG. 27 is used to access data according to one or more methods, functions, and / or processes described with respect to any of FIGS. 1A-7.Computer-Based SystemsThe following figures set forth, without limitation, example computer-based systems that may be used to implement at least one embodiment.FIG. 28 illustrates a processing system 2800 according to at least one embodiment. In at least one embodiment, processing system 2800 includes one or more processors 2802 and one or more graphics processors 2808, and may be a single processor desktop system, a multiprocessor workstation system, or a server system having a large number of processors 2802 or processor cores 2807. In at least one embodiment, processing system 2800 is a processing platform integrated into an integrated circuit system-on-a-chip ("SoC") for use in mobile, portable, or embedded devices.In at least one embodiment, processing system 2800 may include or be incorporated into a server-based gaming platform, a gaming console, a media console, a mobile gaming console, a handheld gaming console, or an online gaming console. In at least one embodiment, processing system 2800 is a cellular phone, a smart phone, a tablet computing device, or a mobile Internet device. In at least one embodiment, processing system 2800 may also include, be coupled to, or integrated with a wearable device, such as a smart watch wearable device, a smart eyeear device, an augmented reality device, or a virtual reality device. In at least one embodiment, processing system 2800 is a television or set-top box device that includes one or more processors 2802 and a graphical interface generated by one or more graphics processors 2808.In at least one embodiment, one or more processors 2802 each include one or more processor cores 2807 for processing instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of one or more processor cores 2807 is configured to process a specific instruction set 2809. In at least one embodiment, instruction set 2809 may enable complex instruction set computing ("CISC"), reduced instruction set computing ("RISC"), or very long instruction word computing ("VLIW"). In at least one embodiment, processor cores 2807 may each process a different instruction set 2809, which may include instructions to facilitate emulation of different instruction sets. In at least one embodiment, processor core 2807 may also include other processing devices, such as a digital signal processor ("DSP").In at least one embodiment, processor 2802 includes a cache memory ("cache") 2804. In at least one embodiment, processor 2802 may include a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory is shared among various components of processor 2802. In at least one embodiment, processor 2802 also uses an external cache (e.g., a Level 3("L3") cache or a Last Level Cache ("LLC")) (not shown) that may be shared by processor cores 2807 using known cache coherency techniques. In at least one embodiment, processor 2802 additionally includes a register bank 2806, which may include different types of registers for storing different types of data (e.g., integer registers, floating point registers, status registers, and an instruction pointer register). In at least one embodiment, register bank 2806 may include general purpose registers or other registers.In at least one embodiment, one or more processor(s) 2802 are coupled to one or more interface bus(s) 2810 to transmit communication signals, such as address, data, or control signals, between processor 2802 and other components in processing system 2800. In at least one embodiment, interface bus 2810, in one embodiment, may be a processor bus, such as a version of a direct media interface ("DMI") bus. In at least one embodiment, interface bus 2810 is not limited to a DMI bus, and may include one or more peripheral component interconnect buses (e.g., "PCI", PCI Express ("PCIe")), memory buses, or other types of interface buses. In at least one embodiment, processor(s) 2802 include an integrated memory controller 2816 and a platform controller hub 2830. In at least one embodiment, memory controller 2816 enables communication between a memory device and other components of processing system 2800, while platform controller hub ("PCH") 2830 provides connections to input / output ("I / O") devices via a local I / O bus.In at least one embodiment, memory device 2820 may be a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, a phase change memory device, or another suitable performance memory device to serve as processor memory. In at least one embodiment, memory device 2820 may operate as system memory for processing system 2800 to store data 2822 and instructions 2821 for use when one or more processors 2802 execute an application or process. In at least one embodiment, memory controller 2816 is also coupled to an optional external graphics processor 2812, which may communicate with one or more graphics processors 2808 in processors 2802 to perform graphics and media operations. In at least one embodiment, a display device 2811 may be connected to processor(s) 2802. In at least one embodiment, display device 2811 may include one or more of an internal display device, such as in a mobile electronic device or a laptop device, or an external display device connected via a display interface (e.g., DisplayPort, etc.). In at least one embodiment, display device 2811 may include a head mounted display ("HMD"), such as a stereoscopic display device for use in virtual reality ("VR") applications or augmented reality ("AR") applications.In at least one embodiment, platform controller hub 2830 enables peripherals to be connected to memory device 2820 and processor 2802 via a high-speed I / O bus. In at least one embodiment, I / O peripherals include an audio controller 2846, a network controller 2834, a firmware interface 2828, a wireless transceiver 2826, touch sensors 2825, and a data storage device 2824 (e.g., hard disk drive, flash memory, etc.). In at least one embodiment, data storage device 2824 may connect via a memory interface (e.g., SATA) or via a peripheral bus, such as PCI or PCIe. In at least one embodiment, touch sensors 2825 may include touch screen sensors, pressure sensors, or fingerprint sensors. In at least one embodiment, wireless transceiver 2826 may be a Wi-Fi transceiver, a Bluetooth transceiver, or a cellular network transceiver, such as a 3G, 4G, or long term evolution ("LTE") transceiver. In at least one embodiment, firmware interface 2828 enables communication with system firmware and may be, for example, a unified extensible firmware interface ("UEFI"). In at least one embodiment, network controller 2834 may enable network connection to a wired network. In at least one embodiment, a high performance network controller (not shown) is coupled to interface bus 2810. In at least one embodiment, audio controller 2846 is a multi-channel high definition audio controller. In at least one embodiment, system 2800 includes an optional legacy I / O controller 2840 to couple legacy devices (e.g., personal system 2 ("PS / 2")) to processing system 2800. In at least one embodiment, platform controller hub 2830 may also be connected to one or more universal serial bus ("USB") controllers 2842 connected to input devices, such as keyboard and mouse 2843 combinations, a camera 2844, or other USB input devices.In at least one embodiment, an instance of memory controller 2816 and platform controller hub 2830 may be integrated into a discrete external graphics processor, such as external graphics processor 2812. In at least one embodiment, platform controller hub 2830 and / or memory controller 2816 may be external to one or more processor(s) 2802. For example, in at least one embodiment, processing system 2800 may include an external memory controller 2816 and a platform controller hub 2830, which may be configured as a memory controller hub and a peripheral controller hub within a system chipset communicating with processor(s) 2802.In at least one embodiment, at least one or more of systems shown in FIG. 28 are used to perform operations described herein, such as PPU-initiated data access. In at least one embodiment, at least one or more systems illustrated in FIG. 28 are used to implement one or more systems and / or methods described in connection with FIGS. 1A-7. In at least one embodiment, processing system 2800 may be used to implement system 100 (see FIG. 1 ). For example, the processing system 2800 may be used to implement at least one of the computer systems 104 (see FIG. 1A ), the management framework 116 (see FIG. 1A ), at least one of the external computer systems 114 (see FIG. 1A ), and / or the network interface 128 (see FIG. 1A ). In at least one embodiment, at least one of processors 2802, graphics processor(s) 2808, processor core(s) 2807, and / or external graphics processor 2812 may be used to implement processor(s) 122 and / or processor of management framework 116 (see FIG. 1A ). In at least one embodiment, at least one of processors 2802, graphics processor(s) 2808, processor core(s) 2807, and / or external graphics processor 2812 may be used to implement PPU(s) 132. In at least one embodiment, network controller 2834 may be used to implement network interface 128. In at least one embodiment, instruction set 2809 and / or instructions 2821 may include instructions 134 and / or instructions for implementing management framework 116. In at least one embodiment, storage device 2820, data storage device 2824, and / or cache 2804 may be used to implement memory 124, management framework 116 memory, client PPU cache(s) 160, optional client CPU cache(s) 162, optional server PPU cache(s) 172, optional server CPU cache(s) 174, optional nonvolatile memory 176, local nonvolatile memory 156, backup storage system / s 180, and / or remote memory 182. In at least one embodiment, at least a portion of system or systems shown in FIG. 28 is used to implement one or more systems, methods, functions, and / or processes described in connection with FIGS. 1A-7. For example, in at least one embodiment, at least a portion of system / systems shown in FIG. 28 is used to access data according to one or more methods, functions, and / or processes described with respect to any of FIGS. 1A-7.FIG. 29 illustrates a computer system 2900 in accordance with at least one embodiment. In at least one embodiment, computer system 2900 may be a system with connected devices and components, an SOC, or a combination thereof. In at least one embodiment, computer system 2900 is formed with a processor 2902, which may include execution units to execute an instruction. In at least one embodiment, computer system 2900 may include, without limitation, a component, such as processor 2902, to employ execution units that include logic to perform algorithms for processing data. In at least one embodiment, computer system 2900 may include processors, such as PENTIUM® family of processors, microprocessors from XeonTM, Itanium® XScaleTM, and / or StrongARMTM, Intel® Core™ or Intel® Nervana™ available from Intel® Corporation of Santa Clara, California, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, and the like) may also be used. In at least one embodiment, computer system 2900 may execute a version of WINDOWS operating system available from Microsoft Corporation of Redmond, Washington, although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.In at least one embodiment, computer system 2900 may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants ("PDAs"), and portable personal computers. In at least one embodiment, embedded applications may include a microcontroller, a digital signal processor (DSP), a SoC, network computers ("NetPCs"), set-top boxes, network hubs, wide area network ("WAN") switches, or any other system capable of performing one or more instructions.In at least one embodiment, computer system 2900 may include, without limitation, a processor 2902, which may include, without limitation, one or more execution units 2908 that may be configured to execute a computed unified device architecture ("CUDA") program (CUDA® is developed by NVIDIA Corporation, Santa Clara, California). In at least one embodiment, a CUDA program is at least a portion of a software application written in a CUDA programming language. In at least one embodiment, computer system 2900 is a desktop or server system having a single processor. In at least one embodiment, computer system 2900 may be a multiprocessor system. In at least one embodiment, processor 2902 may include, without limitation, a CISC microprocessor, a RISC microprocessor, a VLIW microprocessor, a processor implementing a combination of instruction sets, or any other processor device, such as a digital signal processor, in at least one embodiment. In at least one embodiment, processor 2902 may be coupled to a processor bus 2910, which may transmit data signals between processor 2902 and other components in computer system 2900.In at least one embodiment, processor 2902 may include, without limitation, level 1 ("L1") internal cache memory ("cache") 2904. In at least one embodiment, processor 2902 may include a single internal cache or multiple levels of internal cache. In at least one embodiment, cache memory may be external to processor 2902. For example, in at least one embodiment, processor 2902 may also include a combination of both internal and external caches. In at least one embodiment, a register bank 2906 may store different types of data in different registers, including, without limitation, integer registers, floating point registers, status registers, and an instruction pointer register.In at least one embodiment, execution unit 2908 is also located within processor 2902, including without limitation logic for performing integer and floating point operations. Processor 2902 may also include read only memory ("ROM") for microcode ("μcode") that stores microcode for certain microinstruction. In at least one embodiment, execution unit 2908 may include logic to handle a packed instruction set 2909. In at least one embodiment, operations used by many multimedia applications using packed data in a general purpose processor 2902 may be performed by including packed instruction set 2909 in an instruction set of a general purpose processor 2902, along with associated circuitry, to execute instructions. In at least one embodiment, many multimedia applications may be accelerated and executed more efficiently by using full width data bus of a processor to perform operations on packed data, thereby eliminating the need to transfer smaller units of data across processor's data bus to perform one or more operations on one data element at a time.In at least one embodiment, execution unit 2908 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuitry. In at least one embodiment, computer system 2900 may include, without limitation, memory 2920. In at least one embodiment, memory 2920 may be implemented as a DRAM device, an SRAM device, flash memory device, or other memory device. The memory 2920 may store instruction(s) 2919 and / or data 2921 represented by data signals executable by the processor 2902.In at least one embodiment, a system logic chip may be coupled to processor bus 2910 and memory 2920. In at least one embodiment, a system logic chip may include, without limitation, a memory controller hub ("MCH") 2916, and processor 2902 may communicate with MCH 2916 via processor bus 2910. In at least one embodiment, MCH 2916 may provide high bandwidth storage path 2918 to memory 2920 for instruction and data storage as well as for storage of graphics commands, data, and textures. In at least one embodiment, MCH 2916 may route data signals between processor 2902, memory 2920, and other components in computer system 2900, and may bypass data signals between processor bus 2910, memory 2920, and a system I / O 2922. In at least one embodiment, system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, MCH 2916 may be coupled to memory 2920 via a high bandwidth memory path 2918, and graphics / video card 2912 may be coupled to MCH 2916 via an accelerated graphics port ("AGP") 2914 interconnect.In at least one embodiment, computer system 2900 may use system I / O 2922, which is a proprietary hub interface bus to couple MCH 2916 to I / O controller hub ("ICH") 2930. In at least one embodiment, ICH 2930 may provide direct connections to some I / O devices via a local I / O bus. In at least one embodiment, local I / O bus may include, without limitation, a high speed I / O bus for connecting peripherals to memory 2920, a chipset, and processor 2902. Examples may include, without limitation, an audio controller 2929, a firmware hub ("flash BIOS") 2928, a wireless transceiver 2926, a data storage 2924, a legacy I / O controller 2923 including a user input interface 2925 and a keyboard interface, a serial expansion port 2977 such as a USB, and a network controller 2934. The data storage 2924 may include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.In at least one embodiment, FIG. 29 illustrates a system including interconnected hardware devices or "chips.". In at least one embodiment, FIG. 29 may illustrate an example SoC. In at least one embodiment, devices illustrated in FIG. 29 may be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or a combination thereof. In at least one embodiment, one or more components of system 2900 are interconnected using compute express link ("CXL") connections.In at least one embodiment, at least one or more of systems shown in FIG. 29 are used to perform operations described herein, such as PPU-initiated data access. In at least one embodiment, at least one or more systems illustrated in FIG. 29 are used to implement one or more systems and / or methods described in connection with FIGS. 1A-7. In at least one embodiment, computer system 2900 may be used to implement system 100 (see FIG. 1 ). For example, the processing system 2900 may be used to implement at least one of the computer systems 104 (see FIG. 1A ), the management framework 116 (see FIG. 1A ), at least one of the external computer systems 114 (see FIG. 1A ), and / or the network interface 128 (see FIG. 1A ). In at least one embodiment, processor 2902 may be used to implement processor(s) 122 and / or management framework 116 processor (see FIG. 1A ). In at least one embodiment, processor 2902 may be used to implement PPU(s) 132. In at least one embodiment, network controller 2934 may be used to implement network interface 128. In at least one embodiment, instruction set 2919 may include instructions 134 and / or instructions for implementing management framework 116. In at least one embodiment, memory 2920, data store 2924, and / or cache 2904 may be used to implement memory 124, management framework memory 116, client PPU cache(s) 160, optional client CPU cache(s) 162, optional server PPU cache(s) 172, optional server CPU cache(s) 174, optional nonvolatile memory 176, local nonvolatile memory 156, backup storage system / s 180, and / or remote memory 182. In at least one embodiment, at least a portion of system or systems shown in FIG. 29 is used to implement one or more systems, methods, functions, and / or processes described in connection with FIGS. 1A-7. For example, in at least one embodiment, at least a portion of system / systems shown in FIG. 29 is used to access data according to one or more methods, functions, and / or processes described with respect to any of FIGS. 1A-7.FIG. 30 illustrates a system 3000 according to at least one embodiment. In at least one embodiment, system 3000 is an electronic device that utilizes a processor 3010. In at least one embodiment, system 3000 may be, for example and without limitation, a notebook, a tower server, a rack server, a blade server, a laptop, a desktop, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.In at least one embodiment, system 3000 may include, without limitation, a processor 3010 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, processor 3010 is coupled using a bus or interface, such as an I2C bus, a system management bus ("SMBus"), a low pin count ("LPC") bus, a serial peripheral interface ("SPI"), a high definition audio ("HDA") bus, a serial advance technology attachment ("SATA") bus, a USB (Versions 1, 2, or 3), or a universal asynchronous receiver / transmitter ("UART") bus. In at least one embodiment, FIG. 30 illustrates a system including interconnected hardware devices or "chips.". In at least one embodiment, FIG. 30 may illustrate an example SoC. In at least one embodiment, devices illustrated in FIG. 30 may be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or a combination thereof. In at least one embodiment, one or more components of FIG. 30 are interconnected using CXL interconnects.In at least one embodiment, FIG. 30 may include a display 3024; a touch screen 3025; a touchpad 3030; a near field communications unit ("NFC") 3045; a sensor hub 3040, a thermal sensor 3046; an express chipset ("EC") 3035; a trusted platform module ("TPM") 3038, BIOS / firmware / flash memory ("BIOS, FW Flash") 3022; a DSP 3060; a solid state disk ("SSD"); or a hard disk drive ("HDD") 3020, a wireless local area network ("WLAN") unit 3050, a Bluetooth unit 3052, a wireless wide area network ("WWAN") unit 3056, a global positioning system ("GPS") 3055, a camera ("USB 3.0 camera") 3054 such as a USB 3.0 camera, or a low power double data rate ("LPDDR") ("LPDDR3") unit 3015 implemented in, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.In at least one embodiment, other components may be communicatively coupled to processor 3010 by components discussed above. In at least one embodiment, accelerometer 3041, ambient light sensor ("ALS") 3042, compass 3043, and gyroscope 3044 may be communicatively coupled to sensor hub 3040. In at least one embodiment, a thermal sensor 3039, a fan 3037, a keyboard 3046, and a touchpad 3030 may be communicatively coupled to EC 3035. In at least one embodiment, speaker 3063, earphones 3064, and a microphone ("mic") 3065 may be communicatively coupled to an audio unit ("audio codec and class D-Verst.") 3064, which in turn may be communicatively coupled to DSP 3060. In at least one embodiment, audio unit 3064 may include, for example and without limitation, an audio coder / decoder ("codec") and a class D amplifier. In at least one embodiment, a SIM card ("SIM") 3057 may be communicatively coupled to WWAN unit 3056. In at least one embodiment, components such as WLAN unit 3050 and Bluetooth unit 3052, and WWAN unit 3056 may be implemented in a next generation form factor ("NGFF").In at least one embodiment, at least one or more of systems shown in FIG. 30 are used to perform operations described herein, such as PPU-initiated data access. In at least one embodiment, at least one or more systems illustrated in FIG. 30 are used to implement one or more systems and / or methods described in connection with FIGS. 1A-7. In at least one embodiment, computer system 3000 may be used to implement system 100 (see FIG. 1 ). For example, processing system 3000 may be used to implement at least one of computer systems 104 (see FIG. 1A ), management framework 116 (see FIG. 1A ), at least one of external computer systems 114 (see FIG. 1A ), and / or network interface 128 (see FIG. 1A ). In at least one embodiment, processor 3010 may be used to implement processor(s) 122 and / or management framework 116 processor (see FIG. 1A ). In at least one embodiment, processor 3010 may be used to implement PPU(s) 132. In at least one embodiment, at least a portion of system or systems shown in FIG. 30 is used to implement one or more systems, methods, functions, and / or processes described in connection with FIGS. 1A-7. For example, in at least one embodiment, at least a portion of system / systems shown in FIG. 30 is used to access data according to one or more methods, functions, and / or processes described with respect to any of FIGS. 1A-7.FIG. 31 illustrates an example integrated circuit 3100, according to at least one embodiment. In at least one embodiment, example integrated circuit 3100 is a SoC that may be fabricated using one or more IP cores. In at least one embodiment, integrated circuit 3100 includes one or more application processor(s) 3105 (e.g., CPUs), at least one graphics processor 3110, and may additionally include an image processor 3115 and / or a video processor 3120, any of which may be a modular IP core. In at least one embodiment, integrated circuit 3100 includes peripheral or bus logic including a USB controller 3125, a UART controller 3130, an SPI / SDIO controller 3135, and an I2S / I2C controller 3140. In at least one embodiment, integrated circuit 3100 may include a display device 3145 coupled to one or more of a high definition multimedia interface ("HDMI") controller 3150 and a mobile industry processor interface ("MIPI") display interface 3155. In at least one embodiment, storage may be provided by a flash memory subsystem 3160 that includes flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 3165 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits additionally include an embedded security engine 3170.In at least one embodiment, at least one or more of systems shown in FIG. 31 are employed to perform operations described herein, such as PPU-initiated data access. In at least one embodiment, at least one or more of systems shown in FIG. 31 are used to implement one or more systems and / or methods described in connection with FIGS. 1A-7. In at least one embodiment, integrated circuit 3100 may be used to implement system 100 (see FIG. 1 ). For example, integrated circuit 3100 may be used to implement at least one of computer systems 104 (see FIG. 1A ), management framework 116 (see FIG. 1A ), at least one of external computer systems 114 (see FIG. 1A ), and / or network interface 128 (see FIG. 1A ). In at least one embodiment, integrated circuit 3100 may be used to implement processor / processors 122 and / or processor of management framework 116 (see FIG. 1A ). In at least one embodiment, integrated circuit 3100 may be used to implement PPU(s) 132. In at least one embodiment, application processor(s) 3105, graphics processor(s) 3110, image processor 3115, and / or video processor 3120 may be used to implement PPU(s) 132. In at least one embodiment, flash memory subsystem 3160 may be used to implement memory 124, management framework 116 memory, client PPU cache(s) 160, optional client CPU cache(s) 162, optional server PPU cache(s) 172, optional server CPU cache(s) 174, optional nonvolatile memory 176, local nonvolatile memory 156, backup memory system / s 180, and / or remote memory 182. In at least one embodiment, at least a portion of system or systems shown in FIG. 31 is used to implement one or more systems, methods, functions, and / or processes described in connection with FIGS. 1A-7. For example, in at least one embodiment, at least a portion of system / systems shown in FIG. 31 is used to access data according to one or more methods, functions, and / or processes described with respect to any of FIGS. 1A-7.FIG. 32 illustrates a computing system 3200 according to at least one embodiment; In at least one embodiment, computing system 3200 includes a processing subsystem 3201 having one or more processor(s) 3202 and a system memory 3204 that communicates via an interconnect path that may include a memory hub 3205. In at least one embodiment, memory hub 3205 may be a separate component within a chipset component or may be integrated into one or more processor(s) 3202. In at least one embodiment, storage hub 3205 is coupled to an I / O subsystem 3211 via a communication link 3206. In at least one embodiment, I / O subsystem 3211 includes an I / O hub 3207 that may enable computing system 3200 to receive input from one or more input device(s) 3208. In at least one embodiment, I / O hub 3207 may enable a display controller, which may be included in one or more processor(s) 3202, to provide output to one or more display device(s) 3210A. In at least one embodiment, one or more display device(s) 3210A coupled to I / O hub 3207 may include a local, internal, or embedded display device.In at least one embodiment, processing subsystem 3201 includes one or more parallel processor(s) 3212 coupled to memory hub 3205 via a bus or other communication link 3213. In at least one embodiment, communication link 3213 may be any of any number of standards-based communication link technologies or protocols, such as, but not limited to, PCIe, or may be a proprietary communication interface or communication fabric. In at least one embodiment, one or more parallel processor(s) 3212 form a parallel or vector computational focused processing system that may include a large number of processing cores and / or processing clusters, such as a processor with many integrated cores. In at least one embodiment, one or more parallel processor(s) 3212 form a graphics processing subsystem that can output pixels to one or more display device(s) 3210A coupled via I / O hub 3207. In at least one embodiment, one or more parallel processor(s) 3212 may also include a display controller and a display interface (not shown) to enable direct connection to one or more display device(s) 3210B.In at least one embodiment, a system storage unit 3214 may be connected to I / O hub 3207 to provide a storage mechanism for computing system 3200. In at least one embodiment, an I / O switch 3216 may be used to provide an interface mechanism to enable connections between I / O hub 3207 and other components, such as a network adapter 3218 and / or a wireless network adapter 3219 that may be integrated into a platform and various other devices that may be added via one or more expansion device(s) 3220. In at least one embodiment, network adapter 3218 may be an Ethernet adapter or other wired network adapter. In at least one embodiment, wireless network adapter 3219 may include one or more of a Wi-Fi, Bluetooth, NFC, or other network device that includes one or more wireless radios.In at least one embodiment, computing system 3200 may include other components not expressly shown, including USB or other port connections, optical storage drives, video capture devices, and / or variations thereof, and may also be connected to I / O hub 3207. In at least one embodiment, communication paths interconnecting various components in FIG. 32 may be implemented using any suitable protocols, such as PCI-based protocols (e.g., PCIe), or other bus or point-to-point communication interfaces and / or protocol(s), such as NVLink high-speed interconnect, or interconnect protocols.In at least one embodiment, one or more parallel processors 3212 include circuitry optimized for graphics and video processing, including, for example, video output circuitry, and represents a graphics processing unit ("GPU"). In at least one embodiment, one or more parallel processor(s) 3212 include circuitry optimized for general purpose processing. In at least one embodiment, components of computing system 3200 may be integrated into one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processor(s) 3212, memory hub 3205, processor(s) 3202, and I / O hub 3207 may be integrated into a SoC integrated circuit. In at least one embodiment, components of computing system 3200 may be integrated into a single package to form a system in package ("SIP") configuration. In at least one embodiment, at least a portion of components of computing system 3200 may be integrated into a multi-chip module ("MCM"), which may be interconnected with other multi-chip modules to form a modular computing system. In at least one embodiment, I / O subsystem 3211 and display devices 3210B are omitted from computing system 3200.In at least one embodiment, at least one or more of systems shown in FIG. 32 are used to perform operations described herein, e.g., PPU-initiated data access. In at least one embodiment, at least one or more systems illustrated in FIG. 32 are used to implement one or more systems and / or methods described in connection with FIGS. 1A-7. In at least one embodiment, computing system 3200 may be used to implement system 100 (see FIG. 1 ). For example, computer system 3200 may be used to implement at least one of computer systems 104 (see FIG. 1A ), management framework 116 (see FIG. 1A ), at least one of external computer systems 114 (see FIG. 1A ) and / or network interface 128 (see FIG. 1A ). In at least one embodiment, processor(s) 3202 and / or parallel processor(s) 3212 may be used to implement processor(s) 122 and / or management framework 116 processor(s). In at least one embodiment, processor(s) 3202 and / or parallel processor(s) 3212 may be used to implement PPU(s) 132. In at least one embodiment, system memory 3204 may be used to implement memory 124, management framework 116 memory, client PPU cache(s) 160, optional client CPU cache(s) 162, optional server PPU cache(s) 172, optional server CPU cache(s) 174, optional nonvolatile memory 176, local nonvolatile memory 156, backup storage system / s 180, and / or remote memory 182. In at least one embodiment, at least a portion of system / systems shown in FIG. 32 is used to implement one or more of systems, methods, functions, and / or processes described in connection with FIGS. 1A-7. For example, in at least one embodiment, at least a portion of system / systems shown in FIG. 32 is used to access data according to one or more methods, functions, and / or processes described with respect to any of FIGS. 1A-7.Processing SystemsThe following figures set forth, without limitation, example processing systems that may be used to implement at least one embodiment.FIG. 33 illustrates an accelerated processing unit ("APU") 3300, according to at least one embodiment. In at least one embodiment, APU 3300 is developed by AMD Corporation of Santa Clara, California. In at least one embodiment, APU 3300 may be configured to execute an application program, e.g., a CUDA program. In at least one embodiment, APU 3300 includes, without limitation, core complex 3310, graphics complex 3340, fabric 3360, I / O interfaces 3370, memory controllers 3380, display controller 3392, and multimedia engine 3394. In at least one embodiment, APU 3300 may include, without limitation, any number of core complexes 3310, any number of graphics complexes 3350, any number of display controllers 3392, and any number of multimedia engines 3394 in any combination. For purposes of explanation, multiple instances of like objects are referred to herein with reference numerals identifying an object, and parenthesized numbers identify an instance where needed.In at least one embodiment, core complex 3310 is a CPU, graphics complex 3340 is a GPU, and APU 3300 is a processing unit that integrates on a single chip without limitation 3310 and 3340. In at least one embodiment, core complex 3310 may be assigned some tasks and graphics complex 3340 may be assigned other tasks. In at least one embodiment, core complex 3310 is configured to execute main control software associated with APU 3300, such as an operating system. In at least one embodiment, core complex 3310 is a master processor of APU 3300 that controls and coordinates operations of other processors. In at least one embodiment, core complex 3310 issues commands that control operation of graphics complex 3340. In at least one embodiment, core complex 3310 may be configured to execute host executable code derived from CUDA source code, and graphics complex 3340 may be configured to execute device executable code derived from CUDA source code.In at least one embodiment, core complex 3310 includes, without limitation, cores 3320( 1)- 3320( 4) and an L3 cache 3330. In at least one embodiment, core complex 3310 may include, without limitation, any number of cores 3320 and any number and type of caches in any combination. In at least one embodiment, cores 3320 are configured to execute instructions of a specific instruction set architecture ("ISA"). In at least one embodiment, each core 3320 is a CPU core.In at least one embodiment, each core 3320 includes, without limitation, a fetch / decode unit 3322, an integer execution engine 3324, a floating point execution engine 3326, and an L2 cache 3328. In at least one embodiment, fetch / decode unit 3322 fetches instructions, decodes such instructions, generates micro-operations, and sends separate microinstructions to integer execution engine 3324 and floating point execution engine 3326. In at least one embodiment, fetch / decode unit 3322 may simultaneously dispatch one microinstruction to integer execution engine 3324, and another microinstruction to floating point execution engine 3326. In at least one embodiment, integer execution engine 3324 performs integer and memory operations without limitation. In at least one embodiment, floating point engine 3326 performs floating point and vector operations without limitation. In at least one embodiment, fetch / decode unit 3322 sends microinstructions to a single execution engine that replaces both integer execution engine 3324 and floating point execution engine 3326.In at least one embodiment, each core 3320( i), where i is an integer representing a particular instance of core 3320, may access L2 cache 3328( i) included in core 3320( i). In at least one embodiment, each core 3320 included in core complex 3310( j), where j is an integer representing a specific instance of core complex 3310, is linked to other cores 3320 included in core complex 3310( j) via L3 cache 3330( j) included in core complex 3310( j). In at least one embodiment, cores 3320 included in core complex 3310( j), where j is an integer representing a particular instance of core complex 3310, may access entire L3 cache 3330( j) included in core complex 3310( j). In at least one embodiment, L3 cache 3330 may include, without limitation, any number of slices.In at least one embodiment, graphics complex 3340 may be configured to perform compute operations in a highly parallel manner. In at least one embodiment, graphics complex 3340 is configured to perform graphics pipeline operations, such as drawing commands, pixel operations, geometric computations, and other operations associated with rendering an image on a display. In at least one embodiment, graphics complex 3340 is configured to perform operations that do not relate to graphics. In at least one embodiment, graphics complex 3340 is configured to perform both operations related to graphics and operations not related to graphics.In at least one embodiment, graphics complex 3340 includes, without limitation, any number of compute units 3350 and an L2 cache 3342. In at least one embodiment, compute units 3350 share L2 cache 3342. In at least one embodiment, L2 cache 3342 is partitioned. In at least one embodiment, graphics complex 3340 includes, without limitation, any number of compute units 3350 and any number (including zero) and type of caches. In at least one embodiment, graphics complex 3340 includes, without limitation, any amount of dedicated graphics hardware.In at least one embodiment, each computing unit 3350 includes, without limitation, any number of SIMD units 3352 and shared memory 3354. In at least one embodiment, each SIMD unit 3352 implements a SIMD architecture and is configured to perform operations in parallel. In at least one embodiment, each compute unit 3350 may execute any number of thread blocks, but each thread block is executed on a single compute unit 3350. In at least one embodiment, a thread block includes, without limitation, any number of execution threads. In at least one embodiment, a working group is a thread block. In at least one embodiment, each SIMD unit 3352 executes a different warp. In at least one embodiment, a warp is a group of threads (e.g., 16 threads), where each thread in a warp belongs to a single thread block and is configured to process a different dataset based on a single set of instructions. In at least one embodiment, prediction may be used to deactivate one or more threads in a warp. In at least one embodiment, a path is a thread. In at least one embodiment, a work element is a thread. In at least one embodiment, a wavefront is a warp. In at least one embodiment, different wavefronts in a thread block may synchronize with each other and communicate via shared memory 3354.In at least one embodiment, fabric 3360 is a system interconnect that enables data and control transfers via core complex 3310, graphics complex 3340, I / O interfaces 3370, memory controllers 3380, display controller 3392, and multimedia engine 3394. In at least one embodiment, APU 3300 may include, without limitation, any amount and type of system interconnect, in addition to or in place of fabric 3360, that enables data and control transfers via any number and type of directly or indirectly connected components that may be located inside or outside APU 3300. In at least one embodiment, I / O interfaces 3370 represent any number and type of I / O interfaces (e.g., PCI, PCI extended ("PCI-X"), PCIe, gigabit Ethernet ("GBE"), USB, etc.). In at least one embodiment, various types of peripherals are coupled to I / O interfaces 3370. In at least one embodiment, peripherals coupled to I / O interfaces 3370 may include, without limitation, keyboards, mice, printers, scanners, joysticks, or other types of game controllers, media recording devices, external storage devices, network cards, etc.In at least one embodiment, display controller AMD 92 displays images on one or more display device(s), such as a liquid crystal display ("LCD"). In at least one embodiment, multimedia engine 3394 includes, without limitation, any amount and type of circuits related to multimedia, such as a video decoder, a video encoder, an image signal processor, etc. In at least one embodiment, memory controllers 3380 enable communications between APU 3300 and unified system memory 3390. In at least one embodiment, core complex 3310 and graphics complex 3340 share unified system memory 3390.In at least one embodiment, APU 3300 implements a storage subsystem that includes, without limitation, any set and type of memory controllers 3380 and storage devices (e.g., shared memory 3354) that may be associated with one component or shared by multiple components. In at least one embodiment, APU 3300 implements a cache subsystem that includes, without limitation, one or more cache memories (e.g., L2 caches 3428, L3 cache 3330, and L2 cache 3342), each of which may be reserved for or shared by any number of components (e.g., cores 3320, core complex 3310, SIMD units 3352, compute units 3350, and graphics complex 3340).In at least one embodiment, at least one or more of systems shown in FIG. 33 are used to perform operations described herein, such as PPU-initiated data access. In at least one embodiment, at least one or more systems illustrated in FIG. 33 are used to implement one or more systems and / or methods described in connection with FIGS. 1A-7. In at least one embodiment, APU 3300 may be used to implement system 100 (see FIG. 1A ). For example, the APU 3300 may be used to implement at least one of the computer systems 104 (see FIG. 1A ), the management framework 116 (see FIG. 1A ), at least one of the external computer systems 114 (see FIG. 1A ), and / or the network interface 128 (see FIG. 1A ). In at least one embodiment, APU 3300 may be used to implement processor(s) 122 and / or processor of management framework 116. In at least one embodiment, APU 3300 may be used to implement PPU(s) 132. In at least one embodiment, unified system memory 3390 may be used to implement memory 124, management framework 116 memory, client PPU cache(s) 160, optional client CPU cache(s) 162, optional server PPU cache(s) 172, optional server CPU cache(s) 174, optional nonvolatile memory 176, local nonvolatile memory 156, backup storage system / s 180, and / or remote memory 182. In at least one embodiment, at least a portion of system / systems shown in FIG. 33 is used to implement one or more of systems, methods, functions, and / or processes described in connection with FIGS. 1A-7. For example, in at least one embodiment, at least a portion of system / systems shown in FIG. 33 is used to access data according to one or more methods, functions, and / or processes described with respect to any of FIGS. 1A-7.FIG. 34 illustrates a CPU 3400 according to at least one embodiment. In at least one embodiment, APU 3400 is developed by AMD Corporation of Santa Clara, California. In at least one embodiment, CPU 3400 may be configured to execute an application program. In at least one embodiment, CPU 3400 is configured to execute main control software, such as an operating system. In at least one embodiment, CPU 3400 issues commands that control operation of an external GPU (not shown). In at least one embodiment, CPU 3400 may be configured to execute host executable code derived from CUDA source code and an external GPU may be configured to execute device executable code derived from CUDA source code. In at least one embodiment, CPU 3400 includes, without limitation, any number of core complexes 3410, fabric 3460, I / O interfaces 3470, and memory controllers 3480.In at least one embodiment, core complex 3410 includes, without limitation, cores 3420( 1)- 3420( 4) and an L3 cache 3430. In at least one embodiment, core complex 3410 may include, without limitation, any number of cores 3420 and any number and type of caches in any combination. In at least one embodiment, cores 3420 are configured to execute instructions of a particular ISA. In at least one embodiment, each core 3420 is a CPU core.In at least one embodiment, each core 3420 includes, without limitation, a fetch / decode unit 3422, an integer execution engine 3424, a floating point execution engine 3426, and an L2 cache 3428. In at least one embodiment, fetch / decode unit 3422 fetches instructions, decodes such instructions, generates micro-operations, and sends separate microinstructions to integer execution engine 3424 and floating point execution engine 3426. In at least one embodiment, fetch / decode unit 3422 may simultaneously dispatch one microinstruction to integer execution engine 3424, and another microinstruction to floating point execution engine 3426. In at least one embodiment, integer execution engine 3424 performs integer and memory operations without limitation. In at least one embodiment, floating point engine 3426 performs floating point and vector operations without limitation. In at least one embodiment, fetch / decode unit 3422 sends microinstructions to a single execution engine that replaces both integer execution engine 3424 and floating point execution engine 3426.In at least one embodiment, each core 3420( i), where i is an integer representing a particular instance of core 3420, may access L2 cache 3428( i) included in core 3420( i). In at least one embodiment, each core 3420 included in core complex 3410( j), where j is an integer representing a particular instance of core complex 3410, is linked to other cores 3420 in core complex 3410( j) via L3 cache 3430( j) included in core complex 3410( j). In at least one embodiment, cores 3420 included in core complex 3410( j), where j is an integer representing a particular instance of core complex 3410, may access entire L3 cache 3430( j) included in core complex 3410( j). In at least one embodiment, L3 cache 3430 may include, without limitation, any number of slices.In at least one embodiment, fabric 3460 is a system interconnect that enables data and control transfers across core complexes 3410( 1)- 3410(N) (N being an integer greater than zero), I / O interfaces 3470, and memory controllers 3480. In at least one embodiment, CPU 3400 may include, without limitation, any amount and type of system interconnects, in addition to or in place of fabric 3460 that enables data and control transfers via any number and type of directly or indirectly connected components that may be internal or external to CPU 3400. In at least one embodiment, I / O interfaces 3470 represent any number and type of I / O interfaces (e.g., PCI, PCI-X, PCIe, GBE, USB, etc.). In at least one embodiment, various types of peripherals are coupled to I / O interfaces 3470. In at least one embodiment, peripherals coupled to I / O interfaces 3470 may include, without limitation, displays, keyboards, mice, printers, scanners, joysticks, or other types of game controllers, media recording devices, external storage devices, network cards, etc.In at least one embodiment, memory controllers 3480 enable communications between CPU 3400 and system memory 3490. In at least one embodiment, core complex 3410 and graphics complex 3440 share system memory 3490. In at least one embodiment, CPU 3400 implements a memory subsystem that includes, without limitation, any set and type of memory controllers 3480 and memory devices that may be associated with or shared by a component. In at least one embodiment, CPU 3400 implements a cache subsystem that includes, without limitation, one or more cache memories (e.g., L2 caches 3428 and L3 caches 3430), each of which may be reserved for or shared by any number of components (e.g., cores 3420 and core complexes 3410).In at least one embodiment, at least one or more of systems shown in FIG. 34 are used to perform operations described herein, such as PPU-initiated data access. In at least one embodiment, at least one or more systems illustrated in FIG. 34 are used to implement one or more systems and / or methods described in connection with FIGS. 1A-7. In at least one embodiment, CPU 3400 may be used to implement system 100 (see FIG. 1 ). For example, the CPU 3400 may be used to implement at least one of the computer systems 104 (see FIG. 1A ), the management framework 116 (see FIG. 1A ), at least one of the external computer systems 114 (see FIG. 1A ), and / or the network interface 128 (see FIG. 1A ). In at least one embodiment, CPU 3400 may be used to implement processor(s) 122 and / or processor of management framework 116. In at least one embodiment, CPU 3400 may be used to implement PPU(s) 132. In at least one embodiment, system memory 3490 may be used to implement memory 124, management framework 116 memory, client PPU cache(s) 160, optional client CPU cache(s) 162, optional server PPU cache(s) 172, optional server CPU cache(s) 174, optional nonvolatile memory 176, local nonvolatile memory 156, backup storage system / s 180, and / or remote memory 182. In at least one embodiment, at least a portion of system / systems shown in FIG. 34 is used to implement one or more of systems, methods, functions, and / or processes described in connection with FIGS. 1A-7. For example, in at least one embodiment, at least a portion of system / systems shown in FIG. 34 is used to access data according to one or more methods, functions, and / or processes described with respect to any of FIGS. 1A-7.FIG. 35 illustrates an example accelerator integration slice 3590, according to at least one embodiment. As used herein, a "slice" includes a specified portion of processing resources of the accelerator integration circuit. In at least one embodiment, accelerator integration circuitry provides cache management, memory access, context management, and interrupt management services on behalf of a plurality of graphics processing engines included in a graphics acceleration module. The graphics processing engines may each include a separate GPU. Alternatively, the graphics processing engines may include different types of graphics processing engines within a GPU, such as graphics execution units, media processing engines (e.g., video encoders / decoders), samplers, and blit engines. In at least one embodiment, a graphics acceleration module may be a GPU having multiple graphics processing engines. In at least one embodiment, graphics processing engines may be single GPUs integrated on a common package, line card, or chip.An effective address range 3582 of the application within a system memory 3514 stores process elements 3583. In one embodiment, process elements 3583 are stored in response to GPU calls 3581 from applications 3580 executing on processor 3507. A process element 3583 includes the process status for the corresponding application 3580. A work descriptor ("WD") 3584 included in process element 3583 may be a single task requested by an application or may include a pointer to a queue of tasks. In at least one embodiment, WD 3584 is a pointer to a task request queue in application effective address range 3582.Graphics acceleration module 3546 and / or individual graphics processing engines may be shared among all or a subset of processes in a system. In at least one embodiment, an infrastructure to establish process status and send WD 3584 to graphics acceleration module 3546 to start a task in a virtualized environment may be included.In at least one embodiment, a dedicated process programming model is implementation specific. In this model, a single process has graphics acceleration module 3546 or a single graphics processing engine. Because the graphics acceleration module 3546 belongs to a single process, a hypervisor initializes the accelerator integration circuit for a owning partition and an operating system initializes the accelerator integration circuit for a owning process when the graphics acceleration module 3546 is assigned.In operation, a WD fetch unit 3591 in an accelerator integration slice 3590 fetches the next WD 3584 that includes an indication of the work to be done by one or more graphics processing engines of the graphics acceleration module 3546. Data from the WD 3584 may be stored in the registers 3545 and used by a memory management unit ("MMU") 3539, an interrupt management circuit 3547, and / or a context management circuit 3548 as illustrated. For example, MMU 3539 includes segment / page run circuitry for accessing segment / page tables 3586 within OS virtual address range 3585. The interrupt management circuit 3547 may process interrupt events ("INT") 3592 received from the graphics acceleration module 3546. In performing graphics operations, an effective address 3593, generated by a graphics processing engine, is translated to a real address by the MMU 3539.In one embodiment, a same set of registers 3545 are duplicated for each graphics processing engine and / or graphics acceleration module 3546, and may be initialized by a hypervisor or operating system. Each of these duplicated registers may be included in the accelerator integration slice 3590. Example registers that may be initialized by a hypervisor are shown in Table 1. Table 1 - Registers Initialized by Hypervisor Table 1 - Registers Initialized by Hypervisor1Slice Control Registers2Real Address (RA) Scheduled Process Area Pointer3Authority Mask Override Registers4Interrupt Vector Table Entry Offset5Interrupt Vector Table Entry Constraint6Status Register7ID of a logical partition8Hypervisor Accelerator Usage Record Pointers for Real Address (RA)9Memory Description RegisterExample registers that may be initialized by an operating system are shown in Table 2. Table 2 - Operating system initialized registers Table 2 - Operating system initialized registers1Process and Thread Identification2Effective Address (EA) Context Save / Restore Pointers3Virtual Address (VA) Accelerator Usage Record Pointers4Virtual Address (VA) Segment Table Pointer5Authority Mask6Work descriptorIn one embodiment, each WD 3584 is specific to a particular graphics acceleration module 3546 and / or graphics processing engine. It contains all information needed by a graphics processing engine to do work, or it may be a pointer to a storage location where an application has set up a command queue with work to perform.In at least one embodiment, at least one or more of systems shown in FIG. 35 are employed to perform operations described herein, such as PPU-initiated data access. In at least one embodiment, at least one or more systems illustrated in FIG. 35 are used to implement one or more systems and / or methods described in connection with FIGS. 1A-7. In at least one embodiment, system of FIG. 35 may be used to implement system 100 (see FIG. 1A ). For example, the system of FIG. 35 may be used to implement at least one of the computer systems 104 (see FIG. 1A ), the management framework 116 (see FIG. 1A ), at least one of the external computer systems 114 (see FIG. 1A ), and / or the network interface 128 (see FIG. 1A ). In at least one embodiment, processor 3507, graphics acceleration module 3546, and / or accelerator integration slice 3590 may be used to implement processor(s) 122 and / or processor of management framework 116. In at least one embodiment, processor 3507, graphics acceleration module 3546, and / or accelerator integration slice 3590 may be used to implement PPU(s) 132. In at least one embodiment, system memory 3514 may be used to implement memory 124, management framework 116 memory, client PPU cache(s) 160, optional client CPU cache(s) 162, optional server PPU cache(s) 172, optional server CPU cache(s) 174, optional nonvolatile memory 176, local nonvolatile memory 156, backup storage system / s 180, and / or remote memory 182. In at least one embodiment, at least a portion of system or systems shown in FIG. 35 is used to implement one or more systems, methods, functions, and / or processes described in connection with FIGS. 1A-7. For example, in at least one embodiment, at least a portion of system / systems shown in FIG. 35 is used to access data according to one or more methods, functions, and / or processes described with respect to any of FIGS. 1A-7.FIGS. 36A-36B illustrate example graphics processors, in accordance with at least one embodiment. In at least one embodiment, any of example graphics processors may be manufactured using one or more IP cores. In addition to what is illustrated, other logic and circuitry may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general purpose processor cores. In at least one embodiment, example graphics processors are for use in a SoC.FIG. 36A illustrates an example graphics processor 3610 of an SoC integrated circuit that may be fabricated using one or more IP cores, according to at least one embodiment. FIG. 36B illustrates an additional example graphics processor 3640 of an SoC integrated circuit that may be fabricated using one or more IP cores, according to at least one embodiment. In at least one embodiment, graphics processor 3610 of FIG. 36A is a low power graphics processor core. In at least one embodiment, graphics processor 3640 of FIG. 36B is a higher performance graphics processor core. In at least one embodiment, each of graphics processors 3610, 3640 may be a variant of graphics processor 510 of FIG. 5.In at least one embodiment, graphics processor 3610 includes a vertex processor 3605 and one or more fragment processor(s) 3615A- 3615N (e.g., 3615A, 3615B, 3615C, 3615D through 3615N- 1, and 3615N). In at least one embodiment, graphics processor 3610 may execute different shader programs via separate logic such that vertex processor 3605 is optimized to execute operations for vertex shader programs, while one or more fragment processor(s) 3615A- 3615N execute shading operations for fragments (e.g., pixels) for fragment or pixel shader programs. In at least one embodiment, vertex processor 3605 performs a vertex processing stage of a 3D graphics pipeline and generates primitive and vertex data. In at least one embodiment, fragment processor(s) 3615A- 3615N use primitive and vertex data generated by vertex processor 3605 to generate an image memory that is displayed on a display device. In at least one embodiment, one or more fragment processor(s) 3615A- 3615N are optimized to execute fragment shader programs as provided in an OpenGL API, which may be used to perform similar operations as a pixel shader program as provided in a Direct 3D APl.In at least one embodiment, graphics processor 3610 additionally includes one or more MMU(s) 3620A- 3620B, cache(s) 3625A- 3625B, and circuit interconnect(s) 3630A- 3630B. In at least one embodiment, one or more MMU(s) 3620A- 3620B provide a virtual physical address mapping for graphics processor 3610, including vertex processor 3605 and / or fragment processor / s 3615A- 3615N, that relate to vertex or image / texture data stored in memory in additio...

Claims

A method comprising: performing at least one data access by at least one parallel processing unit, PPU, in response to at least one data access request by: identifying one or more data locations; accessing at least one first portion of data stored at at least one first location of the one or more data locations when the first location is at a first level of a plurality of data levels accessible to the at least one PPU; and causing at least one server interface to access at least one second portion of the data stored at at least one second location of the one or more data locations when the second location is at a second level of the plurality of data levels.The method of claim 1, wherein the first level comprises at least one cache stored in a volatile memory.The method of claim 1 or 2, further comprising: calculating a third portion of the data if the third portion is not stored at the one or more data locations or the at least one PPU determines that it would take too long to access the third portion in the plurality of data planes.The method of any preceding claim, further comprising: waiting, by the at least one PPU, to allocate space in a cache for the second portion of the data until after the at least one server interface has accessed the second portion.The method of any preceding claim, further comprising: executing an application using first hardware comprising the at least one PPU; storing the accessed data obtained based at least in part on the at least one data access in at least one memory coupled to the at least one PPU; pause execution of the application by the first hardware; move the application and the accessed data to another second hardware; and resume execution of the application on the other second hardware.The method of any preceding claim, further comprising: executing an application using first hardware comprising the at least one PPU; storing the accessed data obtained based at least in part on the at least one data access to another second hardware; suspending execution of the application by the first hardware; moving the application to another third hardware; and resuming execution of the application on the another third hardware.The method of any preceding claim, further comprising: executing, by the at least one PPU, at least one process in response to at least one call, by an application, at least one function of an application programming interface, API, wherein the at least one process executes the at least one data access in response to the at least one data access request.The method of claim 7, wherein the at least one process is performed by a first compute node and the at least one server interface is performed by another second compute node.The method of any preceding claim, wherein the at least one server interface is configured to access the data within at least one particular level of the plurality of data levels other than the first level, and wherein the at least one particular level comprises at least one of a plurality of different storage locations operating with different storage methods.The method of any preceding claim, further comprising: performing, by the at least one PPU, at least one process that performs the at least one data access in response to the at least one data access request, wherein the at least one data access comprises a synchronous data access that waits for the synchronous data access to complete before the at least one process continues processing.The method of any preceding claim, further comprising: performing, by the at least one PPU, at least one process that performs the at least one data access in response to the at least one data access request, wherein the at least one data access comprises an asynchronous data access that provides at least one notification to at least one receiver indicating whether the asynchronous data access has been successfully completed, wherein the at least one process can continue processing before the asynchronous data access is completed.The method of claim 11, wherein the at least one notification comprises a different notification for each of a plurality of data items.The method of claim 11 or 12, wherein the at least one data access request comprises a plurality of data access requests originating from a plurality of threads, and wherein the at least one notification comprises a different notification for each of the plurality of threads.The method of any of claims 11 to 13, wherein the at least one data access request comprises a plurality of data access requests originating from a plurality of threads, and wherein the at least one notification comprises a single notification provided to the plurality of threads.The method of any preceding claim, wherein the at least one data access request originates from an application executing within a trusted execution environment, and wherein the method further comprises: using an application programming interface, API, to extend the trusted execution environment to include at least a portion of one of the plurality of data levels storing at least a portion of the data.The method of any preceding claim, further comprising: executing, by the at least one PPU, at least one process that executes the at least one data access in response to the at least one data access request, the at least one data access request originating from an application executing in a trusted execution environment; and expanding the trusted execution environment to include the at least one process.The method of claim 16, further comprising: extending the trusted execution environment to include the at least one server interface.The method of any preceding claim, wherein the at least one data access comprises at least 100 data accesses performed by the at least one PPU in parallel.The method of any preceding claim, further comprising: transforming, by the at least one PPU, at least a portion of the first portion of the data.The method of any preceding claim, wherein the at least one server interface transforms at least a portion of the second portion of the data.The method of any preceding claim, wherein the at least one PPU implements at least one node that implements a plurality of client interfaces that perform the at least one data access.The method of any preceding claim, wherein the first level comprises volatile memory, wherein the second level comprises nonvolatile memory, and wherein the at least one data access request requests information stored at the second level in a manner identical to that used by the at least one data access request to request information stored at the first level.A system comprising: at least one parallel processing unit, PPU; and a memory storing first instructions that, when executed by the at least one PPU, cause the system to perform at least one data access in response to at least one data access request by: accessing at least a first portion of data stored at at least a first location of one or more data locations when the first location is stored at a first level of a plurality of data levels accessible to the at least one PPU, and causing at least one server interface to access at least a second portion of the data stored at at least a second location of the one or more data locations when the second location is at a second level of the plurality of data levels.The system of claim 23, further comprising: one or more processors comprising the at least one PPU, wherein the memory stores second instructions that, when executed by the one or more processors, cause the system to execute an application using an application programming interface, API, to cause the at least one PPU to execute at least one process that performs the at least one data access in response to the at least one data access request.The system of claim 24, wherein the at least one data access request is from the application and / or the API.The system of any of claims 23 to 25, wherein the system uses at least one process to perform the at least one data access in response to the at least one data access request, and wherein the at least one data access comprises a synchronous data access that waits for completion of the synchronous data access before the at least one process continues processing.The system of any of claims 23 to 26, wherein the system uses at least one process to perform the at least one data access in response to the at least one data access request, and wherein the at least one data access comprises an asynchronous data access that provides at least one notification to at least one receiver indicating whether the asynchronous data access has been successfully completed, wherein the at least one process is capable of continuing processing before the asynchronous data access is completed.The system of claim 27, wherein the at least one notification comprises a different notification for each of a plurality of data items.The system of claim 27 or 28, wherein the at least one data access request comprises a plurality of data access requests originating from a plurality of threads, and wherein the at least one notification comprises a single notification for the plurality of threads or a different notification for each of the plurality of threads.The system of any of claims 23 to 29, wherein the at least one data access request originates from an application executing within a trusted execution environment, and wherein the first instructions, when executed by the at least one PPU, cause the system to expand the trusted execution environment to include at least a portion of a data store storing at least a portion of the data.The system of any of claims 23 to 30, wherein the system uses at least one process to perform the at least one data access in response to the at least one data access request, wherein the at least one data access request originates from an application executing in a trusted execution environment, and wherein the first instructions, when executed by the at least one PPU, cause the system to expand the trusted execution environment to include the at least one process.The system of claim 31, wherein the first instructions, when executed by the at least one PPU, cause the system to extend the trusted execution environment to include the at least one server interface.The system of any of claims 23 to 32, wherein the first instructions, when executed by the at least one PPU, cause the system to identify the one or more data locations.The system of any of claims 23 to 33, further comprising: calculating a third portion of the data if the third portion is not stored at the one or more data locations or the at least one PPU determines that it would take too long to access the third portion in the plurality of data planes.The system of any of claims 23 to 34, further comprising: at least one processor implementing at least one server node implementing the at least one server interface, wherein the at least one PPU implements at least one client node implementing at least one client interface performing the at least one data access.At least one parallel processing unit, PPU, comprising: one or more circuits for performing at least one data access in response to at least one data access request by: identifying one or more data locations comprising one or more first locations and one or more second locations, and accessing information at the one or more first locations and / or causing at least one server interface to access the information at the one or more second locations, wherein the one or more circuits are configured to access the information at the one or more first locations when the one or more first locations are stored at a first level of a plurality of data levels accessible to the one or more circuits, and wherein the one or more circuits are configured to cause the at least one server interface to, accessing the information at the one or more second locations when the one or more second locations are at a second level of the plurality of data levels.The at least one PPU of claim 36, wherein the one or more circuits are configured to execute an application that uses an application programming interface, API, to cause the one or more circuits to execute the at least one data access in response to the at least one data access request.The at least one PPU of claim 37, wherein the at least one data access request is from the applications and / or the API.The at least one PPU of any of claims 36 to 38, wherein the one or more circuits are configured to use at least one process to perform the at least one data access in response to the at least one data access request, and wherein the at least one data access comprises a synchronous data access that waits for completion of the synchronous data access before the at least one process continues processing.The at least one PPU of any of claims 36 to 39, wherein the one or more circuits are configured to use at least one process to perform the at least one data access in response to the at least one data access request, and wherein the at least one data access comprises an asynchronous data access that provides at least one notification to at least one receiver indicating whether the asynchronous data access has been successfully completed, the at least one process capable of continuing processing before the asynchronous data access is completed.The at least one PPU of claim 40, wherein the at least one notification comprises a different notification for each of a plurality of data items.The at least one PPU of claim 40 or 41, wherein the at least one data access request comprises a plurality of data access requests originating from a plurality of threads, and wherein the at least one notification comprises a single notification for the plurality of threads or a different notification for each of the plurality of threads.The at least one PPU of any of claims 36 to 42, wherein the at least one data access request is from an application executing within a trusted execution environment, and wherein the one or more circuits are configured to expand the trusted execution environment to include at least a portion of a data store that stores at least a portion of the data.The at least one PPU of any of claims 36 to 43, wherein the one or more circuits are configured to use at least one process to perform the at least one data access in response to the at least one data access request, wherein the at least one data access request originates from an application executing in a trusted execution environment, and wherein the one or more circuits are configured to extend the trusted execution environment to include the at least one process.The at least one PPU of claim 44, wherein the one or more circuits are configured to extend the trusted execution environment to include the at least one server interface.The at least one PPU of any of claims 36 to 45, wherein the at least one data access request requests that certain data comprising the information be accessed, and wherein the one or more circuits are configured to calculate a portion of the certain data if the portion is not stored at the one or more data locations or if the one or more circuits determine that it would take too long to access the portion in the plurality of data planes.The at least one PPU of any of claims 36 to 46, wherein the first level comprises volatile memory, wherein the second level comprises nonvolatile memory, and wherein the at least one data access request requests data stored at the second level in a manner identical to that used by the at least one data access request to request data stored at the first level.A processor comprising: one or more circuits to: receive a request having a reference used by an application to access a local volatile memory; use the reference to identify a data location within a plurality of data planes comprising a volatile memory directly accessible to the processor and a nonvolatile memory; access the data location if the data location is within the volatile memory directly accessible to the processor; and cause a service to access the data location if the data location is in the nonvolatile memory.The processor of claim 48, wherein the one or more circuits are configured to cause another processor to access the data location when the data location is in another volatile memory that is directly accessible to the other processor.The processor of claim 48 or 49, wherein the non-volatile memory is remote with respect to the processor.The processor of any of claims 48 to 50, wherein the one or more circuits are configured to cause the service to access the data location if the data location is in another volatile memory that is directly accessible to the service.

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