REDUCTION OF PROXIMITY EFFECTS FROM DEEP-TREATED VIAS

Abstract

Herein we disclose IC structures and devices designed to mitigate proximity effects of deep trench vias. An exemplary IC structure may include a device domain having a first surface and a second surface, the second surface being opposite the first surface, and further including a conductive via extending between the first surface and the second surface, wherein the conductive via contains an electrically conductive material and wherein the concentration of titanium on the sidewalls of the conductive via is less than about 10¹⁵ atoms per cubic centimeter.

Description

BackgroundIntegrated circuit (IC) fabrication typically involves two stages. The first stage is referred to as the "front-end-of-line (FEOL)", and the second stage is referred to as the "back-end-of-line (BEOL)". In the FEOL, individual semiconductor device components (e.g., transistors, capacitors, resistors, etc.) may be formed over a support structure (e.g., a wafer, substrate, die, or chip; also referred to herein simply as "support") occupying one or more layers referred to as "FEOL layers". In the BEOL, metal layers, vias, and isolation layers may be formed above the FEOL layers to interconnect the individual components of the FEOL layers. The BEOL typically begins with forming the first metal layer on the wafer. The first metal layer is often referred to as M 0. More metal layers may be formed on M 0 that are electrically isolated from each other by isolation layers, except for the conductive vias that may extend through the isolation layers to enable electrical connectivity between elements of different metal layers. These metal layers are often called M 1, M 2, and so forth, and are collectively referred to as BEOL layers.Conventionally, power has been provided from the front side of an IC device, i.e., the surface of an IC device that is above the BEOL layers, such that the BEOL layers are between the front side and the one or more FEOL layers. Recently, some IC devices have been implemented with back-side power delivery, i.e., power delivery from the surface of an IC device that is opposite the front side (such a surface is referred to as a "back side"). Such implementations are based on performing a backside exposure to remove some or all of the support over which the FEOL components were formed and then providing one or more layers of interconnects, such as conductive lines and conductive vias, for routing power on the exposed backside.Back side power delivery may provide advantages in terms of ease of manufacture, reduced complexity of power routing, and the ability to include various IC components (e.g., capacitors, inductors, resistors, etc.) for reducing parasitics of IC devices, e.g., for reducing parasitics associated with the interconnects used for power delivery. However, it also has challenges. Back side power delivery is based on the use of deep trench vias extending between the front side and the back side of the IC devices, and a challenge is undesirable shifts of threshold voltages of transistors when a deep trench via is placed in the vicinity of transistors, a phenomenon that may be referred to as a "deep trench via proximity effect.".Brief Description of the DrawingsEmbodiments will be readily understood from the following detailed description taken in conjunction with the accompanying drawings. For convenience in this description, like reference numerals designate like structural elements. Embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings. FIG. 1 provides a perspective view of an exemplary nanoband field effect transistor (FET) according to an embodiment of the present disclosure. FIG. 2 is a top view of an IC device fabricated using selective titanium deposition, according to an embodiment of the present disclosure. FIGS. 3A-3C are cross-sectional side views along different cross-sections of the IC device of FIG. 2, in accordance with some embodiments of the present disclosure. FIGS. 4A-4F are cross-sectional side views illustrating provision of back side interconnects for the IC device of FIG. 2, in accordance with some embodiments of the present disclosure. FIG. 5 is a top view of a wafer and dies that may include any of the IC devices disclosed herein, in accordance with any of the embodiments disclosed herein. FIG. 6 is a side cross-sectional view of an IC package that may include any of the IC devices disclosed herein, in accordance with various embodiments. FIG. 7 is a side cross-sectional view of an IC device assembly that may include any of the IC devices disclosed herein, in accordance with any of the embodiments disclosed herein. FIG. 8 is a block diagram of an example electrical device that may include any of the IC devices disclosed herein, in accordance with any of the embodiments disclosed herein.DETAILED DESCRIPTIONDisclosed herein are IC structures and devices that aim to mitigate (e.g., reduce or eliminate) proximity effects of deep trench vias. In some embodiments, deep trench vias may be used for back side power / signal / ground delivery. The systems, methods, and apparatuses of this disclosure each have some novel aspects, no single one of which is solely responsible for all the desirable attributes disclosed herein. Details of one or more implementations of the subject matter described in this specification are set forth in the description below and the accompanying drawings.For purposes of illustrating mitigation of proximity effects of deep trench vias proposed herein, it may be useful to first understand phenomena that may be useful when implementing deep trench vias. The following basic information can be regarded as a basis from which the present disclosure can be appropriately explained. Such information is provided for the purpose of explanation only and should accordingly not be construed in any way as limiting the broad scope of the present disclosure and its applications.In recent decades, the scaling of features in IC structures has been a driving force behind a constantly growing semiconductor industry. Scaling to smaller and smaller features enables increased densities of functional units on the limited useful area of semiconductor chips. For example, reducing the transistor size allows for the inclusion of a larger number of memory or logic devices on a chip, which lends itself to the fabrication of products with increased capacity. However, the development to the increasingly larger capacities also entails problems. The need to optimize each portion of IC structures is becoming more and more significant. Careful design of deep trench vias may aid in such optimization.Typically, metallization of deep trench vias is performed at substantially the same time as metallization of source / drain (S / D) contacts (i.e., contacts to source and drain regions of transistors). In this context, metallization is a process for filling the openings for deep trench vias and openings for S / D contacts with electrically conductive materials such as metals or metal alloys. To improve electrical contact between the electrically conductive materials of S / D contacts and S / D regions, a thin layer of interfacial material is sometimes deposited over the S / D regions before the remainder of the S / D contact openings are filled with the electrically conductive materials. Conventionally, titanium has been used as the material of choice for such an interfacial material deposited over the bottom and sidewalls of S / D contact openings by a conformal deposition process such as physical vapor deposition (PVD). Titanium on the bottom surfaces of S / D contact openings may then form titanium silicide with the silicon-based material of S / D regions (e.g., doped silicon), thereby improving electrical contact to S / D regions by reducing contact resistance. Since deep trench via metallization is performed simultaneously, titanium is also deposited on the bottom and sidewalls of the deep trench via openings.Embodiments of the present disclosure are based on the finding that although the presence of titanium on the bottom of S / D contact openings is advantageous for reduced contact resistance, it may not be the case for titanium deposited on the sidewalls of the openings for the deep trench vias. In particular, the presence of titanium on the sidewalls of deep trench vias may contribute to the undesirable shifts of threshold voltages of transistors described above. Embodiments of the present disclosure are further based on the finding that replacing the PVD process for depositing titanium with a selective deposition may help mitigate a proximity effect of a deep trench via. Selective deposition refers to a set of manufacturing processes that enable controlled and precise deposition of materials onto particular regions while avoiding deposition onto other regions. Using selective deposition techniques to deposit titanium on S / D regions may enable reducing or eliminating the presence of titanium on sidewalls of S / D contacts as well as on sidewalls of deep trench vias. This, in turn, may reduce or eliminate a proximity effect of a deep trench via.Implementing selective titanium deposition during metallization of deep trench vias and S / D contacts may result in some features characteristic of the use of such deposition in the final IC structures. For example, in one aspect, an example IC structure fabricated using selective titanium deposition may include a device region having a first surface and a second surface, the second surface opposing the first surface, and further including a conductive via extending between the first surface and the second surface, the conductive via including an electrically conductive material, and wherein a concentration of titanium on sidewalls of the conductive via is less than about 10 15 atoms per cubic centimeter.Although some descriptions are provided herein with respect to using deep trench vias for back side power delivery, embodiments of the present disclosure are equally applicable to using deep trench vias for back side signal or ground delivery, as well as deep trench vias used for the purpose of delivering power, signal, or ground to IC components from the front side. Further, although some descriptions are provided herein with respect to nanoribbon transistors, implementing selective titanium deposition to mitigate proximity effects of deep trench vias is equally applicable to non-planar transistors other than nanoribbon transistors (e.g., FinFETs) as well as planar transistors. Further, although descriptions are provided herein with respect to titanium being the interface material used to provide an interface between S / D regions and (a) conductive fill material(s) of S / D contacts, these descriptions are equally applicable to selective deposition of material other than titanium, where the material would be selected for a particular design.IC structures as described herein, particularly IC structures fabricated using selective titanium deposition during S / D contact metallization, may be implemented in one or more components associated with an IC or / and between various such components. In various embodiments, components associated with an IC include, for example, transistors, diodes, power sources, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. Components associated with an IC may include those mounted on the IC or those connected to an IC. The IC may be either analog or digital and may be used in a number of applications, such as microprocessors, optoelectronics, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. In some embodiments, IC structures as described herein may be included in a radio frequency integrated circuit (RFIC), which may be included in, for example, any component associated with an IC of a radio frequency (RF) receiver, an RF transmitter, or an RF transceiver, such as used in telecommunications within base stations (BS) or user equipment (UE). These components may include, but are not limited to, power amplifiers, low noise amplifiers, RF filters (including arrays of RF filters or RF filter banks), switches, boost converters, buck converters, and duplexers. In some embodiments, the IC structures as described herein may be included in memory devices or circuits. In some embodiments, the IC structures as described herein may be used as part of a chipset for performing one or more related functions in a computer.For purposes of explanation, specific numbers, materials, and configurations are set forth in order to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without the specific details, or / and that the present disclosure may be practiced with only some of the described aspects. In other instances, well-known features are omitted or simplified in order not to obscure the illustrative implementations. The terms "substantially," "narrow," "approximately," "near," and "about" generally refer to being within + / -10% of a target value, e.g., within + / -5% of a target value, based on the context of a particular value, as described herein or known in the art. Likewise, terms indicating an orientation of various elements, e.g., "coplanar," "perpendicular," "orthogonal," "parallel," or any other angle between the elements generally refer to being within + / - 10% of a target value, e.g., within + / - 5% of a target value, based on the context of a particular value as described herein or known in the art.In the following description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration embodiments which may be practiced. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Therefore, the following detailed description is not to be taken in a limiting sense. If a collection of drawings marked with different letters is present, e.g., FIGS. 3A-3C, this collection may be referred to herein without the letters, e.g., as "FIG. 3", for convenience.However, in the drawings, although some schematic illustrations of exemplary structures of various devices and assemblies described herein are shown with precise right angles and straight lines, this is for ease of illustration only, and embodiments of these assemblies may be curved, rounded, or otherwise irregularly shaped as dictated by and sometimes indispensable due to the manufacturing processes used to fabricate semiconductor device assemblies. Therefore, it should be appreciated that such schematic illustrations may not reflect real process constraints, which may cause the features to not look as "ideal" when any of the structures described herein are examined using, for example, scanning electron microscopy (SEM) images or transmission electron microscopy (TEM) images. In such real structure images, possible processing defects could also be visible, e.g., imperfect straight edges of materials, tapered vias or other openings, unintentional rounding of corners or variations in the thicknesses of different material layers, occasional threading, stepping or combinations of dislocations within the crystalline region, and / or occasional dislocation defects of individual atoms or clusters of atoms. There may be other defects not listed herein, but are common in the field of device fabrication. Inspection of layout and mask data and reverse engineering of portions of a device for reconstructing the circuit using, e.g., optical microscopy, TEM, or SEM, and / or inspection of a cross-section of a device for detecting the shape and location of various device elements described herein using, e.g., physical failure analysis (PFA) would allow determination of the presence of IC structures fabricated using selective titanium deposition during S / D contact metallization as described herein.Various aspects of the illustrative implementations are described using terms commonly employed by those skilled in the art to convey substance to others skilled in the art of their work. For example, the terms "oxide", "carbide", "nitride", "silicide", etc., refer to compounds each containing oxygen, carbon, nitrogen, silicon, etc.; the term "high-k dielectric" refers to a material having a higher dielectric constant than silicon oxide; the term "low-k dielectric" refers to a material having a lower dielectric constant than silicon oxide. Materials referred to herein by formulas or as compounds are intended to cover any materials that include elements of the formula or compound, e.g., TiSi or titanium silicide may refer to any material that includes titanium and silicon, WN or tungsten nitride may refer to any material that includes tungsten and nitrogen, etc. The term "insulating" means "electrically insulating," the term "conductive" means "electrically conductive," unless otherwise indicated. Furthermore, the term "connected" may be used to describe a direct electrical or magnetic connection between the things that are connected without any intervening devices, while the term "coupled" may be used to describe either a direct electrical or magnetic connection between the things that are connected or an indirect connection through one or more passive or active intervening devices. A first component described as being electrically coupled to a second component means that the first component is in conductive contact with the second component (i.e., a conductive path is provided to carry electrical signals / power between the first and second components).Various acts may be described as multiple discrete acts or acts in sequence in a manner that is most helpful in understanding the claimed subject matter. However, the order of description should not be construed to imply that these operations are necessarily order dependent. These operations may not be performed in the order of presentation. Described operations may be performed in a different order from the described embodiment. Various additional operations may be performed and / or described operations may be omitted in additional embodiments.For purposes of the present disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For purposes of the present disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term "between" when used with reference to measurement regions, including the ends of the measurement regions.The specification uses the phrases "in one embodiment" or "in embodiments," which may each refer to one or more of the same or different embodiments. The terms "comprising", "including", "having", and the like, as used with reference to embodiments of the present disclosure, are synonymous. The disclosure may use perspective-based descriptions such as "above", "below", "top", "bottom", and "side"; such descriptions are used to facilitate discussion and are not intended to limit the application of disclosed embodiments. The accompanying drawings are not necessarily to scale. Unless otherwise specified, the use of the ordering adjective "first / r / s", "second / r / s", and "third / r / s", etc. to describe a common object merely indicates that different instances of like objects are related, and it is not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking, or in any other manner. Although some materials may be described in the singular form, such materials may include multiple materials, e.g., one semiconductor material may include two or more different semiconductor materials.Fabrication of IC structures using selective titanium deposition during S / D contact metallization may be performed with transistors of any architecture, such as any non-planar or planar architecture. Non-planar transistors, such as dual gate transistors, tri-gate transistors, FinFETs, and nanowire / nanoribbon / nanosheet transistors, refer to transistors having a non-planar architecture. Compared to a planar architecture where the transistor channel has only one boundary surface, a non-planar architecture is any type of architecture where the transistor channel has more than one boundary surface. A boundary surface refers to a particular orientation of the channel surface that is bounded by the gate array. Non-planar transistors may improve performance relative to transistors having a planar architecture, such as single gate transistors.Nanoribbon transistors may be particularly advantageous for continuous scaling of complementary metal oxide semiconductor (CMOS) technology nodes due to the potential to form gates on all four sides of a channel material (therefore, such transistors are sometimes referred to as "gate all around" transistors). Thus, some IC structures illustrated herein show nanoribbon transistors as an example (e.g., IC structures shown in FIGS. 1, 3, and 4 ), although the fabrication described herein using selective titanium deposition during S / D contact metallization is not limited to such transistors.As used herein, the term "nanoribbon" refers to an elongated structure of a semiconductor material having a longitudinal axis parallel to a support structure (e.g., a substrate, die, chip, or wafer) over which such a structure is constructed. Typically, a length of such a structure (i.e., a dimension measured along the longitudinal axis shown in the present drawings as extending along the y-axis of an exemplary x-y-z coordinate system 105 shown in FIG. 1 ) is greater than each of a width (i.e., a dimension measured along the x-axis of the coordinate system 105) and a thickness / height (i.e., a dimension measured along the z-axis of the coordinate system 105). In some cases, the terms "nanoribbon" or "nanosheet" have been used to describe elongated semiconductor structures having a rectangular transverse cross-section (i.e., a cross-section in a plane perpendicular to the longitudinal axis of the structure), while the term "nanowire" has been used to describe similar elongated structures, but having a circular transverse cross-section. In the present disclosure, the term "nanoribbon" is used to refer to all such nanowires, nanoribbons, and nanosheets, as well as to elongate semiconductor structures having a longitudinal axis parallel to the support structures and having transverse cross-sections of any geometry (e.g., transverse cross-sections in the form of an oval or a polygon with rounded corners). A transistor may then be described as a "nanoribbon transistor" if the channel of the transistor is a part of a nanoribbon, i.e., a part around which a gate stack of a transistor may wrap. The semiconductor material in the part of the nanoribbon forming a channel of a transistor may be referred to as a "channel material", wherein source and drain regions of a transistor are provided on both sides of the channel material.FIG. 1 provides a perspective view of an example IC structure 100 including a nanoribbon transistor 110, in accordance with some embodiments of the present disclosure. As shown in FIG. 1, the IC structure 100 includes a semiconductor material formed as a nanoribbon 104 extending substantially parallel to a pillar 102. Transistor 110 may be formed based on nanoribbon 104 by having a gate stack 106 that wraps at least partially around a portion of the nanoribbon referred to as a "channel portion" and having source and drain regions shown in FIG. 1 as a first S / D region 114- 1 and a second S / D region 114- 2 on both sides of gate stack 106. One of the S / D regions 114 is a source region and the other is a drain region. However, as is common in the field of FETs, since source and drain designations are often interchangeable, they are referred to herein simply as a first S / D region 114- 1 and a second S / D region 114- 2.Implementations of the present disclosure may be formed or carried out on any suitable support 102, such as a substrate, die, wafer, or chip. The support 102 may be, for example, the wafer 1500 of FIG. 5 discussed below, and may be a die, for example, the singulated die 1502 of FIG. 5 discussed below, or included therein. The support 102 may be a semiconductor substrate made of semiconductor material systems including, for example, n-type or p-type material systems. In one implementation, the semiconductor substrate may be a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In other implementations, the semiconductor substrate may be formed using alternative materials that may or may not be combined with silicon, including but not limited to germanium, silicon germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, Aluminiumgalliumarsenid aluminum arsenide, indium aluminum arsenide, aluminum indium antimonide, Indiumgalliumarsenid gallium nitride, indium gallium nitride, aluminum indium nitride or gallium antimonide, or other combinations of Group III-V materials (i.e., materials from Groups III and V of the Periodic Table of Elements), Group II-VI (i.e., materials from Groups II and VI of the Periodic Table of the Elements) or Group IV materials (i.e., materials from Group IV of the Periodic Table of the Elements) may be included. In some embodiments, the substrate may be non-crystalline. In some embodiments, the support 102 may be a printed circuit board (PCB) substrate, a package substrate, an interposer, a wafer, or a die. Although a few examples of materials from which the support 102 may be formed are described herein, any material that may serve as a base on which an IC structure fabricated using selective titanium deposition during S / D contact metallization as described herein may be built falls within the spirit and scope of the present disclosure. Although only one nanoribbon 104 is shown in FIG. 1, the IC structure 100 may include a stack of such nanoribbons, wherein multiple nanoribbons 104 are stacked one above the other, as shown in FIGS. 3 and 4, for example, which show IC structures, which may be examples of the IC structure 100. In some embodiments, a portion of the support 102 directly below the lowermost nanoribbon 104 of the stack may be shaped as a sub-fin extending away from a base, as is known in the nanoribbon transistors art.The nanoribbon 104 may take the form of a nanowire or nanoribbon, for example. In some embodiments, a range of a transverse cross-section of the nanoribbon 104 (i.e., a range in the x-z plane of an x-y-z coordinate system 105 shown in FIG. 1 perpendicular to a longitudinal axis 120 of the nanoribbon 104) may be between about 25 and 10000 square nanometers, including all values and ranges therein (e.g., between about 25 and 1000 square nanometers, or between about 25 and 500 square nanometers). In some embodiments, a width of the nanoribbon 104 (i.e., a dimension measured in a plane parallel to the support 102 and in a direction perpendicular to the longitudinal axis 120 of the nanoribbon 104, e.g., along the x-axis of the coordinate system 105) may be at least about 3 times greater than a height of the nanoribbon 104 (i.e., a dimension measured in a plane perpendicular to the support 102, e.g., along the z-axis of the coordinate system 105) including all values and ranges therein, e.g., at least about 4 times greater or at least about 5 times greater. Although the nanoribbon 104 illustrated in FIG. 1 is shown as having a rectangular cross-section, the nanoribbon 104 may instead have a cross-section that is rounded or otherwise irregularly shaped at corners, and the gate stack 106 may correspond to the shape of the nanoribbon 104. The term "area" of a nanoribbon may refer to the side of the nanoribbon 104 that is larger than the side perpendicular thereto (measured in a plane substantially perpendicular to the longitudinal axis 120 of the nanoribbon 104), the latter side being referred to as a "sidewall" of a nanoribbon.In various embodiments, the semiconductor material of the nanoribbon 104 may be comprised of semiconductor material systems including, for example, n-type or p-type material systems. In some embodiments, the nanoribbon 104 may include a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. In some embodiments, the nanoribbon 104 may include a combination of semiconductor materials. In some embodiments, the nanoribbon 104 may include a monocrystalline semiconductor, such as silicon (Si) or germanium (Ge). In some embodiments, the nanoribbon 104 may include a compound semiconductor having a first sublattice of at least one element from group III of the periodic table (e.g., Al, Ga, In) and a second sublattice of at least one element from group V of the periodic table (e.g., P, As, Sb).In some example n-type transistor embodiments (i.e., for the embodiments where transistor 110 is an n-type metal oxide semiconductor (NMOS) transistor), the channel material of nanoribbon 104 may include a III-V material having a relatively high electron mobility, such as, but not limited to, InGaAs, InP, InSb, and InAs. For some such embodiments, the channel material of the nanoribbon 104 may be a ternary III-V alloy, such as InGaAs, GaAsSb, InAsP, or InPSb. For some In x Ga 1-x As fin embodiments, an In fraction (x) may be between 0.6 and 0.9, and may advantageously be at least 0.7 (e.g., In 0,7 Ga 0,3 As). For some example p-type transistor embodiments (i.e., for the embodiments where transistor 110 is a p-type metal oxide semiconductor (PMOS) transistor), the channel material of nanoribbon 104 may advantageously be a group IV material with a high hole mobility, such as, but not limited to, Ge or a Ge-rich SiGe alloy. For some embodiments, the channel material of the nanoribbon 104 may have a Ge content between 0.6 and 0.9 and may advantageously be at least 0.7.In some embodiments, the channel material of the nanoribbon 104 may be a thin film material, such as a high mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. Generally, if the transistor formed in the nanoribbon is a thin film transistor (TFT), the channel material of the nanoribbon 104 may be one or more of tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, n- or p-type amorphous silicon or n- or p-type polysilicon, germanium, Indiumgalliumarsenid silicon germanium, gallium nitride, gallium nitride, gallium nitride, gallium nitride, gallium nitride, gallium nitride, silicon nitride, silicon nitride, silicon nitride, silicon nitride, silicon nitride, silicon nitride, silicon nitride, silicon nitride, silicon nitride, silicon nitride, silicon nitride, silicon nitride, silicon nitride, silicon nitride, silicon nitride, silicon nitride, silicon nitride, silicon nitride, silicon nitride, silicon nitride, silicon nitride, and the like, silicon nitride, silicon nitride, silicon nitride, silicon nitride, silicon nitride, and the like, silicon nitride, and the, Examples of such materials include aluminum gallium nitride, indium phosphite, and black phosphorus, each of which may be possibly doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, and magnesium, etc. In some embodiments, the channel material of the nanoribbon 104 may have a thickness between about 5 and 75 nanometers, including all values and ranges therein. In some embodiments, a thin film channel material may be deposited at relatively low temperatures, allowing the channel material to be deposited within the thermal budgets imposed during back end fabrication to avoid damage to other components, e.g., front end components such as logic devices.A gate stack 106 including a gate electrode material 108 and optionally a gate insulator material 112 may wrap entirely or almost entirely around a portion of the nanoribbon 104 as shown in FIG. 1, wherein the active region (channel region) of the channel material of the transistor 110 corresponds to that of the nanoribbon 104 around which the gate stack 106 has wrapped. As shown in FIG. 1, the gate insulator material 112 may wrap around a transverse portion of the nanoribbon 104 and the gate electrode material 108 may wrap around the gate insulator material 112.The gate electrode material 108 may include one or more gate electrode materials, wherein the selection of the gate electrode materials may depend on whether the transistor 110 is a PMOS transistor or an NMOS transistor. For a PMOS transistor, gate electrode materials that may be used in various portions of the gate electrode material 108 may include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal oxides (e.g., ruthenium oxide). For an NMOS transistor, gate electrode materials that may be used in various portions of the gate electrode material 108 include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide). In some embodiments, the gate electrode material 108 may include a stack of multiple gate electrode materials, where zero or more materials of the stack are work function (WF) materials and at least one material of the stack is a fill metal layer. Other materials / layers may be included in addition to the gate electrode material 108 for other purposes, such as to function as a diffusion barrier layer or / and an adhesion layer.In some embodiments, gate insulator material 112 may include one or more high-k dielectrics including any of the materials discussed herein with reference to the insulator material, which may surround portions of transistor 110. In some embodiments, during a fabrication of the transistor 110, an anneal process may be performed on the gate insulator material 112 to improve the quality of the gate insulator material 112. The gate insulator material 112 may have a thickness that may be between about 0.5 nanometers and 3 nanometers in some embodiments, including all values and ranges therein (e.g., between about 1 and 3 nanometers, or between about 1 and 2 nanometers). In some embodiments, the gate stack 106 may be surrounded by a gate spacer, which is not shown in FIG. 1. Such a gate spacer would be configured to provide isolation between the gate stack 106 and the S / D contacts of the transistor 110, and could be made of a low-k dielectric material, some examples of which were previously provided.Turning to the S / D regions 114 of the transistor 110, in some embodiments, the S / D regions may be heavily doped, e.g., with dopant concentrations of about 10 21 cm -3, to advantageously form ohmic contacts to the respective S / D contacts (not shown in FIG. 1 ), although these regions may also have lower dopant concentrations and may form Schottky contacts in some implementations. Regardless of the exact dopant levels, the S / D regions of a transistor are the regions having a dopant concentration that is higher than in other regions, e.g., higher than a dopant concentration in the transistor channel (i.e., in a channel material extending between the first S / D region 114- 1 and the second S / D region 114- 2), and may therefore be referred to as "heavily doped" (HD) regions. Even if doped to realize threshold voltage tuning as described herein, the channel portions of transistors typically include semiconductor materials having doping concentrations significantly less than those of the S / D regions 114.The S / D regions 114 of the transistor 110 may generally be formed by either an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion implanted into the nanoribbon 104 to form the source and drain regions. An anneal process that activates the dopants and causes them to diffuse further into the nanoribbon 104 may follow the ion implantation process. In the latter process, portions of the nanoribbon 104 may be first etched to form recesses at the locations of the future S / D regions 114. An epitaxial deposition process may then be performed to fill the recesses with a material used to fabricate the S / D regions 114. In some implementations, the S / D regions 114 may be fabricated using a silicon alloy, such as silicon germanium or silicon carbide. In some implementations, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorus. In further embodiments, the S / D regions 114 may be formed using one or more alternative semiconductor materials, such as germanium or a / a group III-V material or alloy. And in further embodiments, one or more layers of metal and / or metal alloys may be used to form the S / D regions 114. In some embodiments, a distance between the first and second S / D regions 114 (i.e., a dimension measured along the longitudinal axis 120 of the nanoribbon 104) may be between about 5 and 40 nanometers, including all values and ranges therein (e.g., between about 22 and 35 nanometers, or between about 20 and 30 nanometers).The IC structure 100 shown in FIG. 1, as well as IC structures shown in other drawings of the present disclosure, are intended to show relative arrangements of some of the components therein, and the IC structure 100, or portions thereof, may include other components that are not illustrated (e.g., electrical contacts to the S / D regions 114 of the transistor 110, additional layers such as a spacer layer around the gate electrode of the transistor 110, etc.). For example, although not specifically illustrated in FIG. 1, a dielectric spacer may be provided between a first S / D contact (which may also be referred to as a "first S / D electrode") coupled to a first S / D region 114- 1 of transistor 110 and gate stack 106, and between a second S / D contact (which may also be referred to as a "second S / D electrode") coupled to a second S / D region 114- 2 of transistor 110 and gate stack 106 to provide electrical isolation between the source, gate, and drain electrodes. In another example, although not specifically illustrated in FIG. 1, at least portions of transistor 110 may be surrounded by an insulator material, such as any suitable interlayer dielectric (ILD) material. In some embodiments, such insulator material may be a high-k dielectric material including elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used for this purpose may include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, tantalum oxide, tantalum silicon oxide, lead scandium tantalum oxide, and lead zinc niobate. In other embodiments, the insulator material surrounding portions of transistor 110 may be a low-k dielectric material. Some examples of low-k dielectric materials include, but are not limited to, silicon dioxide, carbon doped oxide, silicon nitride, organic polymers such as perfluorocyclobutane or polytetrafluoroethylene, fused silica glass (FSG), and organosilicates such as silsesquioxane, siloxane, or organosilicate glass.FIG. 2 is a top view of an IC structure 200 fabricated using selective titanium deposition, according to an embodiment of the present disclosure. Some of the materials are not shown in plan view in order not to obscure the drawing.As shown in FIG. 2, if the transistors to be implemented in the IC structure 200 are nanoband transistors, such as that illustrated in FIG. 1, the IC structure 200 may include two nanoband stacks 204- 1 and 204- 2 (collectively referred to as "nanoband stack 204"). Alternatively, what is now shown as nanoband stacks 204- 1 and 204- 2 could be fins if the transistors to be implemented in the IC structure 200 are FinFETs. The nanoribbons 204 may include stacks of one or more nanoribbons 104 as described above, and may be provided over a support, such as support 102 (not specifically shown in FIG. 2 ). The nanoribbons 204 may extend substantially parallel to each other, e.g., along the y-axis of the coordinate system 105, in accordance with the illustration of FIG. 1. metal gate lines 205 (shown as lying within dashed contours in FIG. 2 ) and S / D contact lines 213 may extend substantially perpendicular to the nanoribbons 204 and substantially parallel to each other, e.g., along the x-axis of the coordinate system 105. FIG. 2 illustrates that the metal gate lines 205 and the S / D contact lines 213 may be provided in an alternating manner. Metal gate lines 205 may be cut and removed where the deep trench vias are placed, such that the gate contacts 206 effectively act as portions of the metal lines 205. In FIG. 2, portions of the metal gate lines 205 are shown with dashed contours, indicating that they are the portion in which the metal gate lines 205 have been removed. The gate contacts 206 are in conductive contact with the gate stacks 106 (which are below the gate contacts 206 and therefore not visible in the view of FIG. 2 ) provided via channel portions of the nanoribbons 204 that provide electrical connectivity to the gates of the nanoribbons. Accordingly, portions of the gate contacts 206 intersecting the gate stacks 106 are in conductive contact with the gate stacks 106 and serve as gate contacts for the transistors. Likewise, S / D contact lines 213 may be cut and removed where the deep trench vias are placed, such that S / D contacts 214 effectively act as portions of the S / D contact lines 213. In FIG. 2, portions of the S / D contact lines 213 are shown with dashed contours, indicating that they are the portion in which the S / D contact lines 213 have been removed. S / D contacts 214 are provided over S / D regions 114 (which are below S / D contacts 214 and therefore not visible in the view of FIG. 2 ) of nanoribbons 204, which provide electrical connectivity to S / D regions 114 of nanoribbons. Accordingly, portions of the S / D contacts 214 intersecting the S / D regions 114 are in conductive contact with the S / D regions 114 and serve as S / D contacts for the transistors.FIG. 2 further illustrates that deep trench vias 226 may be provided near the transistors formed based on the nanoribbon stacks 204. Two instances of the deep trench vias 226 are shown in FIG. 2, but in other embodiments, any other number of one or more deep trench vias 226 may be included in the IC structure 200. Similarly, although a particular arrangement of gate stacks 106, metal gate lines 205, gate contacts 206, S / D contact lines 213, and S / D contacts 214 is shown in FIG. 2, in other embodiments, these elements may be arranged differently within the IC structure 200. Characteristic of the use of selective titanium deposition, in a cross-section such as that shown in FIG. 2, there would be no titanium liner on the sidewalls of deep trench vias 226 as well as on the sidewalls of S / D contacts 214.To further illustrate details of the IC structure 200, FIG. 2 shows a portion 230 (illustrated with a dotted contour), a portion 240 (illustrated with a dash-dot contour), and a portion 250 (illustrated with a dash-dot contour). Portion 230 indicates an approximate outline of an example transistor, such as transistor 110, provided over nanoribbon stack 204- 1. Portion 240 illustrates a portion of IC structure 200 having a gate contact 206 provided over a gate stack 106 over a channel portion of nanoribbon stack 204- 1 and a deep trench via 226. Portion 250 illustrates a portion of IC structure 200 having S / D contacts 214 on both sides of deep trench via 226. FIGS. 3A-3C are cross-sectional side views along different cross-sections of the IC structure 200 of FIG. 2, in accordance with some embodiments of the present disclosure. In particular, FIG. 3A illustrates a cross-sectional side view of portion 230 along a plane AA shown in FIG. 2, FIG. 3B illustrates a cross-sectional side view of portion 240 along a plane BB shown in FIG. 2, and FIG. 3C illustrates a cross-sectional side view of portion 250 along a plane CC shown in FIG. 2. A number of elements referred to in the description of FIGS. 3A-3C as well as in FIGS. 4A-4F with reference numerals are illustrated in these drawings with different patterns, with a legend showing the correspondence between the reference numerals and patterns provided below in each drawing page including FIGS. 3A-3C and 4A-4F. For example, the legend illustrates that FIGS. 3A-3C use different patterns to show a gate electrode material 108, a semiconductor material 303, an electrically conductive material 306 of a gate contact 206, and so forth.As shown in FIG. 3A, portion 230 includes a transistor similar to transistor 110, but constructed based on a nanoribbon stack 204- 1 of multiple nanoribbons 104 instead of just one nanoribbon 104, as shown in FIG. 1. Although four nanoribbons 104 are shown as included in nanoribbon stack 204- 1, in other embodiments fewer nanoribbons 104 or more nanoribbons 104 may be included. FIG. 3A illustrates a semiconductor material 303 as the material of nanoribbons 104, wherein a sub-fin 305 of semiconductor material 303 is further illustrated below nanoribbon stack 204- 1, although in some embodiments nanoribbons 104 and at least a portion of sub-fin 305 may include semiconductor materials of different material compositions. As shown in FIG. 3A, a gate stack 106 including a gate insulator material 112 and a gate electrode material 108 may wrap around channel portions of the nanoribbons 104. FIG. 3A further illustrates a first S / D region 114- 1 and a second S / D region 114- 2 extending through the nanoribbon stack 204- 1 electrically isolated / separated from the gate electrode material 108 and from the semiconductor material 303 of the sub-fin 305 by an insulator material 307. In some embodiments, the insulator material 307 may form so-called "pits" 308 in regions where the insulator material 307 separates the S / D regions 114 from the gate electrode material 108. The insulator material 307 may include any of the insulator materials described herein, e.g., any of the ILD materials described above.Above the nanoribbon stack 204-1, FIG. 3A illustrates a gate contact 206 and S / D contacts 214 on both sides of the gate contact 206, which are individually referred to as a first S / D contact 214-1 for making electrical contact with the first S / D region 114-1 and a second S / D contact 214-2 for making electrical contact with the second S / D region 114-2. The gate contact 206 may include an electrically conductive material 306 in electrically conductive contact with the gate electrode material 108. In various embodiments, material compositions of the electrically conductive material 306 and the gate electrode material 108 may be substantially the same or different.S / D contacts 214 may be electrically isolated from gate electrode material 108 and electrically conductive material 306 of gate contact 206 by gate spacers 308. The gate spacers 308 may include one or more of spacer materials, diffusion barrier materials, adhesion materials, etc., as are known in the art for forming contacts with various components of IC structures. In some embodiments, the gate spacers 308 may include low-k dielectrics and / or any of the ILD materials described above. Optionally, sidewalls of the S / D contacts 214 may be lined with one or more liners 310, where the liners 310 may include, but are not limited to, materials comprising silicon and nitrogen (e.g., silicon nitride), materials comprising silicon and oxygen (e.g., silicon oxide), materials comprising silicon and carbon (e.g., silicon carbide), and / or mixtures thereof. Within the sidewalls, the S / D contacts 214 may be filled with an electrically conductive fill material 314. In various embodiments, material compositions of the electrically conductive fill material 314 and the electrically conductive material 306 may be substantially the same (e.g., both may be / include tungsten) or different. An interface material 316 is deposited on the bottom of the S / D contacts 214 to provide an interface between the S / D regions 114 and the electrically conductive fill material 314 of the S / D contacts 214. The interface material 316 may include / be a metal, such as titanium, that once deposited may mix with the material of the S / D regions 114, e.g., silicon, thereby forming a compound (e.g., titanium silicide) that may help reduce the contact resistance of the S / D contacts 214. During fabrication, the interface material 316 may be deposited within openings for future S / D contacts 214 using selective deposition in which the interface material 316 is deposited on the bottom of the openings for the S / D contacts 214, but not on the sidewalls of the openings for the S / D contacts 214. This is shown in FIG. 3A by illustrating that no interfacial material 316 is present on the sidewalls of the S / D contacts 214. Selective deposition may help ensure that a concentration of the interfacial material 316 on the sidewalls of the S / D contacts 214 may be below typical impurity concentrations, e.g., below about 10 15 atoms per cubic centimeter (cm -3) or below 10 13 cm -3.Because metallization of the S / D contacts 214 may be performed substantially simultaneously with metallization of deep trench vias, selective deposition may result in the interfacial material 316 also being selectively deposited on the bottom side, but not on the sidewalls of deep trench vias. This is illustrated in FIG. 3B, which shows a cross-sectional side view of the IC structure 200 along the plane BB shown in FIG. 2 and FIG. 3A (i.e., a gate section). FIG. 3C shows the plane AA along which the section from FIG. 3A is shown.FIG. 3B illustrates a deep trench via 226, an insulator material 318 surrounding the deep trench via 226, an electrically conductive via fill material 320 filling the deep trench via 226, and an insulator material 322 surrounding sidewalls of the sub-fin 305. For example, the insulator material 318 and the insulator material 322 may include any of the ILD materials described above and may have either substantially the same or different material compositions. The insulator material 322 may sometimes be referred to as a "shallow trench insulator" (STI). The insulator material 322 is provided to electrically isolate the deep trench via 226 from the adjacent electrically conductive structures and materials, e.g., to electrically isolate the deep trench via 226 from the electrically conductive material 306 of the gate contact 206, which may extend along any of the metal gate lines 205. The electrically conductive via fill material 320 filling the deep trench via 226 may include any suitable conductive material, e.g., tungsten, and may have substantially the same or different material composition as the electrically conductive material 306 of the gate contact 206 and / or as the electrically conductive fill material 314 of the S / D contacts 214.In some embodiments, sidewalls of the deep trench via 226 may be lined with a liner 324. The liner 324 may include, among other things, composite materials comprising an electrically conductive material such as tungsten and a material such as carbon or nitrogen (e.g., WCN). In some embodiments, the liner 324 may include a metal, such as tantalum. However, as shown in FIG. 3B, due to selective deposition of the interface material 316, no interface material 316 is present on the sidewalls of the deep trench via 226. Selective deposition may help ensure that the concentration of the interface material 316 on the sidewalls of the deep trench via 226 may be below typical impurity concentrations, similar to the concentration of the interface material 316 on the sidewalls of the S / D contacts 214.FIG. 3C provides another helpful illustration of the IC structure 200 along the plane shown in FIG. 2 and FIG. 3A CC (i.e., a cross-section across S / D regions 114 of two different nanoribbon stacks 204). FIG. 3C shows the plane AA along which the section from FIG. 3A is shown.FIG. 3C illustrates the deep trench via 226, wherein an insulator material 318 surrounds the deep trench via 226, as shown in FIG. 3B, and two S / D regions 114- 2, one on either side of the deep trench via 226 and electrically insulated from the deep trench via 226 by the insulator material 318. The two S / D regions 114- 2 are provided over different ones of the nanoribbon stacks 204- 1 and 204- 2, as shown in FIGS. 2 and 3C. FIG. 3C further illustrates an insulator material 326 that may surround the S / D regions 114 below the electrically conductive fill material 314 of the S / D contacts 214 and may also surround the sidewalls of the sub-fins 305 of the nanoribbon stacks 204- 1 and 204- 2. The insulator material 326 may include, for example, any of the ILD materials described above, and may have either substantially the same or different material compositions than any other insulator materials in the IC structure 200, e.g., as the insulator material 322.FIG. 3C illustrates portions 328 of the interfacial material 316 selectively deposited onto the S / D regions 114- 2. Portions 328 of FIG. 3C illustrate that, in a cross-section along an x-z plane of the coordinate system 105, the interfacial material 316, which is selectively deposited on the bottom surfaces of the openings for the S / D contacts 214, may wrap around the top portions of the S / D regions 114. FIG. 3C further illustrates a portion 330 of the interfacial material 316 selectively deposited on the bottom of the deep trench via 226. For example, in some embodiments, a thickness of the interfacial material 316, a dimension measured along the z-axis of the coordinate system 105, may be between about 1 nanometer and about 7 nanometers, including all values and ranges therein, e.g., between about 1 and 5 nanometers, or about 3 nanometers.FIGS. 4A-4F are cross-sectional side views illustrating provision of back side interconnects for the IC structure 200 of FIG. 2, in accordance with some embodiments of the present disclosure. Each of FIGS. 4A-4F illustrates the same cross-section of portion 240 as that shown in FIG. 3B.FIG. 4A illustrates an IC device 400A that includes a device region 404 with all portions of the IC structure 200 as shown in FIG. 3B, and that further includes a first interconnect layer 406 formed above the device region 404 and a second interconnect layer 408 formed above the first interconnect layer 406. Additional interconnect layers may be present above the second interconnect layer 408. A collection of interconnect layers, such as interconnect layers 406, 408, etc., may be referred to as a "metallization stack" 419 of the IC device 400A. Interchangeably, metallization stack 419 may be referred to as the "BEOL layer(s)" of IC device 400A, while device region 404 may be referred to as the "FEOL layer(s)" of IC device 400A.Electrical signals, such as power and / or input / output (I / O) signals, may be routed to and / or from the devices (e.g., transistors) of the device region 404 through one or more interconnect layers disposed on the device region 404 (illustrated as interconnect layers 406 and 408 in FIG. 4A ). For example, electrically conductive features of the device region 404 (e.g., the electrically conductive material 306 of the gate contact 206 and the electrically conductive via fill material 320 of the deep trench via 226) may be electrically coupled to the interconnect structures 428 of the interconnect layers 406 and 408. The interconnect structures 428 may be disposed within the interconnect layers of the metallization stack 419 to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures 428 shown in FIG. 4A ). Although a particular number of interconnect layers 406 and 408 are illustrated in FIG. 4A, embodiments of the present disclosure include IC structures with more or fewer interconnect layers than illustrated.In some embodiments, the interconnect structures 428 may include conductive lines 428 aand / or conductive vias 428 bbeing filled with an electrically conductive material, such as a metal. The lines 428 amay be arranged to route electrical signals in a direction of a plane substantially parallel to a surface of the support 102 on which the device region 404 is formed. For example, the lines 428a may route electrical signals in a direction into and out of the page as viewed from the perspective in Figure 4A. The vias 428 bmay be arranged to route electrical signals in a direction of a plane substantially perpendicular to the surface of the support 102 on which the device region 404 is formed. In some embodiments, the vias 428 bmay electrically couple lines 428 aof different interconnect layers of the metallization stack 419 to each other.The interconnect layers 406 and 408 may include a dielectric material 426 disposed between the interconnect structures 428, as shown in FIG. 4A. In some embodiments, the dielectric material 426 disposed between the interconnect structures 428 in different ones of the interconnect layers 406 and 408 may have different compositions; in other embodiments, the composition of the dielectric material 426 between different interconnect layers 406 and 408 may be the same.A first interconnect layer 406 may be formed above the device region 404. In some embodiments, the first interconnect layer 406 may include lines 428 aand / or vias 428 bas shown. The lines 428 aand / or the vias 428 bof the first interconnect layer 406 may be coupled to contacts (e.g., gate contacts 206 and / or S / D contacts 214 of the IC structure 200) of the device region 204.A second interconnect layer 408 may be formed above the first interconnect layer 406. In some embodiments, the second interconnect layer 408 may include vias 428 bto couple the lines 428 aof the second interconnect layer 408 to the lines 428 aof the first interconnect layer 406. Although the lines 428 aand the vias 428 bare structurally outlined with a line within each interconnect layer (e.g., within the second interconnect layer 408) for clarity, in some embodiments, the lines 428 aand the vias 428 bmay be structurally and / or materially contiguous (e.g., simultaneously filled during a dual damascene process).Additional interconnect layers may be formed as desired in sequence on the second interconnect layer 408 according to similar techniques and configurations described in connection with the second interconnect layer 408 or the first interconnect layer 406. In some embodiments, the interconnect layers located "higher up" in metallization stack 419 in IC device 400A (i.e., further away from device region 404) may be thicker. Although not specifically shown in FIG. 4A, in some embodiments, the IC device 400A may further include a solder resist material (e.g., polyimide or similar material) and one or more conductive contacts formed on the interconnect layers of the metallization stack 419.FIG. 4B illustrates that once metallization stack 419 has been formed, a carrier substrate 440 may be attached to the top of metallization stack 419 of IC device 400A, thereby providing an IC device 400B. The carrier substrate 440 may include any suitable structure that may provide adequate mechanical support for the subsequent processing steps, as shown in FIGS. 4C-4F.FIG. 4C illustrates an IC device 400C that is substantially the same as the IC device 400B, but is flipped over to continue processing on the back side of the IC device.FIG. 4D illustrates an IC device 400D after the start of backside processing, where the support 102 and a portion of the device region 404 closest to the support 102 are removed (e.g., by grinding). FIG. 4D shows that as a result, the interfacial material 316 that was selectively deposited on the bottom of the deep trench via 226 is removed, but the selective deposition characteristic (i.e., the lack of the interfacial material 316 on the sidewalls of the deep trench via 226) remains.FIG. 4E illustrates an IC device 400E substantially similar to the IC device 400D, but further including a metallization stack 449 on the back side of the device region 404. As shown in FIG. 4E, the metallization stack 439 may include a first interconnect layer 436 formed on the back side of the device region 404 and a second interconnect layer 438 formed above the first interconnect layer 436. Additional interconnect layers may be present above the second interconnect layer 438.Electrical signals, such as power and / or input / output (I / O) signals, may be routed to and / or from the devices (e.g., transistors) of the device region 404 through one or more interconnect layers disposed on the back side of the device region 404 (illustrated as interconnect layers 436 and 438 in FIG. 4E ). For example, electrically conductive features of the device region 404 (e.g., the electrically conductive via fill material 320 of the deep trench via 226) may be electrically coupled to the interconnect structures 458 of the interconnect layers 436 and 438. The interconnect structures 458 may be disposed within the interconnect layers of the metallization stack 449 to route electrical signals according to a wide variety of designs (in particular, the arrangement is not limited to the particular configuration of interconnect structures 458 shown in FIG. 4E ). Although a particular number of interconnect layers 436 and 438 are shown in FIG. 4E, embodiments of the present disclosure include IC structures with more or fewer interconnect layers than shown.In some embodiments, the interconnect structures 458 may include conductive lines 458 aand / or conductive vias 458 bbeing filled with an electrically conductive material, such as a metal. The interconnect layers 436 and 438 may include a dielectric material 456 disposed between the interconnect structures 458 as shown in FIG. 4E. Descriptions provided above with respect to the first interconnect layer 406, the second interconnect layer 408, the metallization stack 419, the dielectric material 426, the conductive lines 428a, and the conductive vias 428b apply to the first interconnect layer 436, the second interconnect layer 438, the metallization stack 449, the dielectric material 456, the conductive lines 458a, and the conductive vias 458b, respectively. Therefore, these descriptions will not be repeated in the interest of shortage.FIG. 4F illustrates an IC device 400F that is substantially the same as the IC device 400E, but after removal of the carrier substrate 440. Since metallization stack 419 is provided on the front side of device region 404 while metallization stack 449 is provided on the back side, there may be features indicating this in IC device 400F. In particular, for certain fabrication processes, cross-sectional shapes of interconnects in a plane, such as that of FIG. 4E (e.g., in a plane substantially perpendicular to the device region 404) may be trapezoidal, i.e., a cross-section of an interconnect may have two substantially parallel sides, one shorter than the other. Since the interconnects 428 are formed on a front side 462 of the device region 404, their trapezoidal shapes may be arranged such that their shorter sides are closer to a back side 464 of the device region 404 than their longer sides. Because the deep trench vias 226 have been formed from the same side, the trapezoidal shapes of the deep trench vias 226 may likewise be arranged such that their shorter sides are also closer to a back side 464 of the device region 404 than their longer sides. Since the interconnects 458 are formed on the back side 464 of the device region 404, their trapezoidal shapes may be arranged such that their shorter sides are closer to a back side 464 of the device region 404 than their longer sides.IC devices / structures fabricated using selective titanium deposition during S / D contact metallization as described herein (e.g., as described with reference to FIGS. 1-4 ) may be used to implement any suitable components. In various embodiments, the IC structures described herein may be part of, for example, one or more of: a central processing unit, a storage device (e.g., a high bandwidth storage device), a memory cell, a logic circuit, input / output circuitry, a field programmable gate array (FPGA) component, such as an FPGA transceiver or FPGA logic, power delivery circuitry, an amplifier (e.g., a III-V amplifier), a peripheral component interconnect express (PCIE) circuitry, a double data rate (DDR) transmission circuitry, a computing device (e.g., a wearable or handheld computing device), etc.The IC devices disclosed herein, e.g., IC devices 100, 200, or 400, or any variations thereof, may be included in any suitable electronic component. FIGS. 5-8 illustrate various examples of devices that may include any of the IC devices disclosed herein.FIG. 5 is a top view of a wafer 1500 and dies 1502, which may include one or more IC structures according to any of the embodiments disclosed herein. The wafer 1500 may be made of semiconductor material and may include one or more dies 1502 having IC structures formed on a surface of the wafer 1500. Each of the dies 1502 may be a repeating unit of a semiconductor product including any suitable IC. After the fabrication of the semiconductor product is completed, the wafer 1500 may undergo a dicing process in which the dies 1502 are separated from each other to provide discrete "chips" of the semiconductor product. Die 1502 may include one or more IC structures as described herein (e.g., any of IC devices 100, 200, 400) described herein, one or more transistors (e.g., nanoribbon transistors of IC devices 100, 200, 400), and / or supporting circuitry for routing electrical signals to the transistors, as well as any other IC components. In some embodiments, wafer 1500 or die 1502 may include a memory device (e.g., a random access memory (RAM) device, such as a static RAM (SRAM) device, a magnetic RAM (MRAM) device, a resistive RAM (RRAM) device, a conductive bridging RAM device (CBRAM), etc.), a logic device (e.g., an AND, OR, NAND, or NOR gate), or any other suitable circuit element. Multiple ones of these devices may be combined on a single die 1502. For example, a memory array formed by multiple memory devices may be formed on a same die 1502 as a processing device (e.g., processing device 1802 of FIG. 8 ) or other logic configured to store information in the memory devices or execute instructions stored in the memory array.FIG. 6 is a side cross-sectional view of an example IC package 1650 that may include one or more IC structures according to any of the embodiments disclosed herein (e.g., any of the IC devices 100, 200, 400) described herein. In some embodiments, the IC package 1650 may be a system-in-package (SIP).The package substrate 1652 may be formed of a dielectric material (e.g., a ceramic, a build-up film, an epoxy film with filler particles therein, glass, an organic material, an inorganic material, combinations of organic and inorganic materials, embedded portions formed of different materials, etc.), and may have conductive paths extending through the dielectric material between the surface 1672 and the surface 1674, or between different locations on the surface 1672, and / or between different locations on the surface 1674. These conductive paths may take the form of any of the interconnects 428 discussed above with reference to FIG. 4.The package substrate 1652 may include conductive contacts 1663 coupled to conductive paths (not shown) through the package substrate 1652, thereby allowing the circuitry within the dies 1656 and / or the interposer 1657 to be electrically coupled to various ones of the conductive contacts 1664 (or to devices not shown included in the package substrate 1652).The IC package 1650 may include an interposer 1657 coupled to the package substrate 1652 via conductive contacts 1661 of the interposer 1657, first level interconnects 1655, and the conductive contacts 1663 of the package substrate 1652. The first level interconnects 1665 illustrated in FIG. 6 are solder bumps, but any suitable first level interconnects 1665 may be used. In some embodiments, interposer 1657 may not be included in IC package 1650; instead, dies 1656 may be directly coupled to conductive contacts 1663 on side surface 1672 by first level interconnects 1665. More generally, one or more dies 1656 may be coupled to the package substrate 1652 via any suitable structure (e.g., a silicon bridge, an organic bridge, one or more waveguides, one or more interposers, wire bonds, etc.).The IC package 1650 may include one or more dies 1656 coupled to the interposer 1657 via conductive contacts 1654 of the dies 1656, first level interconnects 1658, and conductive contacts 1660 of the interposer 1657. The conductive contacts 1660 may be coupled to conductive paths (not shown) through the interposer 1657, thereby allowing circuitry within the dies 1656 to be electrically coupled to various ones of the conductive contacts 1661 (or to other devices not shown included in the interposer 1657). The first level interconnects 1658 illustrated in FIG. 6 are solder bumps, but any suitable first level interconnects 1658 may be used. As used herein, a "conductive contact" may refer to a portion of a conductive material (e.g., metal) that serves as an interface between different components; conductive contacts may be recessed in, flush with, or extend away from a surface of a component and may take any suitable shape (e.g., a conductive pad or socket).In some embodiments, an underfill material 1666 may be disposed between the package substrate 1652 and the interposer 1657 around the first level interconnects 1665, and a potting compound 1668 may be disposed around the dies 1656 and the interposer 1657 and in contact with the package substrate 1652. In some embodiments, the underfill material 1666 may be the same as the potting compound 1668. Example materials that may be used for the underfill material 1666 and the potting compound 1668 are suitable epoxy potting materials. Second level interconnects 1670 may be coupled to the conductive contacts 1664. The second level interconnects 1670 illustrated in FIG. 6 are solder balls (e.g., for a ball grid array assembly), but any suitable second level interconnects 1670 may be used (e.g., pins in a pin grid array assembly or pads in a pad grid array assembly). The second level interconnects 1670 may be used to couple the IC package 1650 to another component, such as a printed circuit board (e.g., a motherboard), interposer, or other IC package, as is known in the art and discussed below with reference to FIG. 7.The dies 1656 may take the form of any of the embodiments of the die 1502 discussed herein. In embodiments where the IC package 1650 includes multiple dies 1656, the IC package 1650 may be referred to as a multi-chip package (MCP). The dies 1656 may include circuitry for performing any desired functionality. For example, one or more of the dies 1656 may be logic dies (e.g., silicon-based dies) and one or more of the dies 1656 may be memory dies (e.g., high bandwidth memory).Although the IC package 1650 illustrated in FIG. 6 is a flip chip package, other package architectures may be used. For example, the IC package 1650 may be a ball grid array (BGA) package, such as an embedded wafer level ball grid array (eWLB) package. In another example, the IC package 1650 may be a wafer level chip scale package (WLCSP) or a panel fanout (FO) package. Although two dies 1656 are illustrated in the IC package 1650 of FIG. 6, an IC package 1650 may include any desired number of dies 1656. An IC package 1650 may include additional passive components, such as surface mounted resistors, capacitors, and inductors disposed on the first surface 1672 or the second surface 1674 of the package substrate 1652, or on both surfaces of the interposer 1657. More generally, an IC package 1650 may include any other active or passive components known in the art.FIG. 7 is a side cross-sectional view of an IC device assembly 1700, which may include one or more IC packages or other electronic components (e.g., a die) including one or more IC devices, in accordance with any of the embodiments disclosed herein. The IC device package 1700 includes a number of components disposed on a printed circuit board 1702 (which may be, e.g., a motherboard). The IC device assembly 1700 includes components disposed on a first surface 1740 of the circuit board 1702 and on an opposing second surface 1742 of the circuit board 1702; generally, components may be disposed on one or both surfaces 1740 and 1742. Any of the IC packages discussed below with reference to the IC device assembly 1700 may take the form of any of the embodiments of the IC package 1650 discussed above with reference to FIG. 6 (e.g., may include one or more IC devices 100, 200, 400).In some embodiments, the circuit board 1702 may be a PCB including a plurality of metal layers separated from each other by layers of dielectric material and interconnected by electrically conductive vias. Any one or more of the metal layers may be formed in a desired circuit structure to carry electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 1702. In some embodiments, the circuit board 1702 may be a non-PCB substrate.The IC device package 1700 illustrated in FIG. 7 includes a package-on-interposer structure 1736 coupled to the first surface 1740 of the circuit board 1702 by coupling components 1716. The coupling components 1716 may electrically and mechanically couple the package-on-interposer structure 1736 to the circuit board 1702 and may include solder balls (as shown in FIG. 7 ), male and female portions of a socket, an adhesive, an underfill material, and / or any other suitable electrical and / or mechanical coupling structure.The package-on-interposer structure 1736 may include an IC package 1720 coupled to a package interposer 1704 by coupling components 1718. The coupling components 1718 may take any form suitable for the application, such as the forms discussed above with respect to the coupling components 1716. Although a single IC package 1720 is shown in FIG. 7, multiple IC packages may be coupled to package interposer 1704; indeed, additional interposers may be coupled to package interposer 1704. The package interposer 1704 may provide an intervening substrate that bridges the circuit board 1702 and the IC package 1720. The IC package 1720 may be or include, for example, a die (die 1502 of FIG. 5 ), an IC device (e.g., any of the IC devices 100, 200, 400, or any combination of such IC devices described herein), or any other suitable component. Generally, the package interposer 1704 may spread a connection to a wider pitch or redirect a connection to another connection. For example, the package interposer 1704 may couple the IC package 1720 (e.g., a die) to a set of BGA conductive contacts of the coupling components 1716 for coupling to the circuit board 1702. In the embodiment illustrated in FIG. 7, the IC package 1720 and the circuit board 1702 are mounted on opposite sides of the package interposer 1704; in other embodiments, the IC package 1720 and the circuit board 1702 may be mounted on a same side of the package interposer 1704. In some embodiments, three or more components may be interconnected via the package interposer 1704.In some embodiments, the package interposer 1704 may be formed as a PCB including multiple metal layers separated from each other by layers of dielectric material and interconnected by electrically conductive vias. In some embodiments, the package interposer 1704 may be formed from an epoxy resin, a fiberglass reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymeric material such as polyimide. In some embodiments, the package interposer 1704 may be formed of alternative rigid or flexible materials, which may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other Group III-V and Group IV materials. The package interposer 1704 may include metal lines 1710 and vias 1708, including, but not limited to, through-silicon vias (TSVs) 1706. The package interposer 1704 may further include embedded devices 1714 that include both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices, such as RF devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical system (MEMS) devices, may also be formed on the package interposer 1704. The package-on-interposer structure 1736 may take the form of any of the package-on-interposer structures known in the art.The IC device assembly 1700 may include an IC package 1724 coupled to the first surface 1740 of the circuit board 1702 by coupling components 1722. The coupling components 1722 may take the form of any of the embodiments discussed above with respect to the coupling components 1716, and the IC package 1724 may take the form of any of the embodiments discussed above with respect to the IC package 1720.The IC device assembly 1700 illustrated in FIG. 7 includes a package-on-package structure 1734 coupled to the second surface 1742 of the circuit board 1702 by coupling components 1728. The package-on-package structure 1734 may include an IC package 1726 and an IC package 1732 coupled together by coupling components 1730 such that the IC package 1726 is disposed between the circuit board 1702 and the IC package 1732. The coupling components 1728 and 1730 may take the form of any embodiments of the coupling components 1716 discussed above, and the IC packages 1726 and 1732 may take the form of any embodiments of the IC package 1720 discussed above. The housing-on-housing structure 1734 may be configured according to any housing-on-housing structures known in the art.FIG. 8 is a block diagram of an example electrical device 1800 that may include one or more IC structures 100, in accordance with any of the embodiments disclosed herein. For example, any suitable one of the components of the electrical device 1800 may include one or more of the IC device assemblies 1700, IC packages 1650, or dies 1502 disclosed herein. A number of components are illustrated in FIG. 8 as included in the electrical device 1800, however, any one or more of these components may be omitted or duplicated as appropriate for the application. In some embodiments, some or all of the components included in the electrical device 1800 may be mounted on one or more motherboards. In some embodiments, some or all of these components may be fabricated on a single system-on-a-chip (SoC) die.Additionally, in various embodiments, the electrical device 1800 may not include one or more of the components illustrated in FIG. 8, but the electrical device 1800 may include interface circuitry for coupling to the one or more components. For example, the electrical device 1800 may not include a display device 1806, but may include display device interface circuitry (e.g., a connector and driver circuitry) to which a display device 1806 may be coupled. In another set of examples, the electrical device 1800 may not include an audio input device 1824 or audio output device 1808, but may include audio input or output device interface circuitry (e.g., connectors and support circuitry) to which an audio input device 1824 or audio output device 1808 may be coupled.The electrical device 1800 may include a processing device 1802 (e.g., one or more processing devices). As used herein, the term "processing device" or "processor" may refer to any device or portion of a device that processes electronic data from registers and / or memory to transform that electronic data into other electronic data that may be stored in registers and / or memory. The processing device 1802 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors executing cryptographic algorithms within hardware), server processors, or any other suitable processing devices. The electrical device 1800 may include memory 1804, which itself may include one or more storage devices, such as volatile memory (e.g., dynamic RAM (DRAM)), nonvolatile memory (e.g., read only memory (ROM)), flash memory, solid state memory, and / or a hard disk drive. In some embodiments, the memory 1804 may include memory sharing a die with the processing device 1802. This memory may be used as a cache memory and may include, for example, an embedded dynamic RAM (eDRAM) or a spin transfer torque magnetic RAM (STT-MRAM).In some embodiments, the electrical device 1800 may include a communication chip 1812 (e.g., one or more communication chips). For example, the communication chip 1812 may be configured to manage wireless communications for the transmission of data to and from the electrical device 1800. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they may not contain them.The communication chip 1812 may implement any of a number of wireless standards or protocols, including, but not limited to, Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long Term Evolution (LTE) project along with all changes, updates, and / or revisions (e.g., Advanced LTE project, Ultra-Mobile Broadband (UMB) project (also referred to as "3GPP2"), etc.). IEEE 802.16 compatible broadband wireless access (BWA) networks are commonly referred to as WiMAX networks, an acronym standing for worldwide interoperability for microwave access, which is a certification mark for products that pass compliance and interoperability tests for the IEEE 802.16 standards. The communication chip 1812 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication chip 1812 may operate in accordance with enhanced data for GSM evolution (EDGE), GSM EDGE radio access network (GERAN), universal terrestrial radio access network (UTRAN), or evolved UTRAN (E-UTRAN). The communication chip 1812 may operate in accordance with code division multiple access (CDMA), time division multiple access (TDMA), digital enhanced cordless telecommunications (DECT), evolution-data optimized (EV-DO), and variations thereof, as well as any other wireless protocols that are referred to as 3G, 4G, 5G, and beyond. The communication chip 1812 may operate according to other wireless protocols in other embodiments. The electrical device 1800 may include an antenna 1822 to facilitate wireless communications and / or to receive other wireless communications (such as AM or FM radio transmissions).In some embodiments, communication chip 1812 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As mentioned above, the communication chip 1812 may include multiple communication chips. For example, a first communication chip 1812 may be dedicated to shorter range wireless communications such as WiFi or Bluetooth and a second communication chip 1812 may be dedicated to longer range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 1812 may be dedicated to wireless communications and a second communication chip 1812 may be dedicated to wired communications.The electrical device 1800 may include battery / power circuitry 1814. The battery / power circuitry 1814 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of the electrical device 1800 to a separate energy source (e.g., the AC power supply) from the electrical device 1800.The electrical device 1800 may include a display device 1806 (or corresponding interface circuitry, as discussed above). The display device 1806 may include any visual indicators such as a heads-up display, a computer monitor, a projector, a touch screen display, a liquid crystal display (LCD), a light emitting diode display, or a flat panel display.The electrical device 1800 may include an audio output device 1808 (or corresponding interface circuitry, as discussed above). The audio output device 1808 may include any device that generates an acoustic indicator, such as speakers, earphones, or earphones.The electrical device 1800 may include an audio input device 1824 (or corresponding interface circuitry, as discussed above). Audio input device 1824 may include any device that generates a signal representing a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).The electrical device 1800 may include a GPS device 1818 (or corresponding interface circuitry, as discussed above). The GPS device 1818 may be in communication with a satellite-based system and receive a location of the electrical device 1800 as is known in the art.The electrical device 1800 may include another output device 1810 (or corresponding interface circuitry, as discussed above). Examples of the other output device 1810 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.The electrical device 1800 may include another input device 1820 (or corresponding interface circuitry, as discussed above). Examples of the other input device 1820 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a quick response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.The electrical device 1800 may have any desired form factor, such as a handheld or mobile electrical device (e.g., a mobile phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop electrical device, a server device, or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable electrical device. In some embodiments, the electrical device 1800 may be any other electronic device that processes data.The following paragraphs provide various examples of the embodiments disclosed herein.Example 1 provides an IC structure including: a transistor including a region of a doped semiconductor material, the region being one of a source region and a drain region of the transistor; and a contact structure coupled to the region, the contact structure including an interfacial material and a fill material, wherein within the contact structure, the interfacial material is confined to a region between (e.g., directly between) the region and the fill material.Example 2 provides the IC structure of example 1, wherein the interfacial material is limited to the region between the region and the fill material by being on a bottom side of the contact structure and substantially absent from sidewalls of the contact structure.Example 3 provides the IC structure of Examples 1 or 2, further including a device region, wherein: the transistor and the contact structure are located with the region within the device region, the device region has a first surface and a second surface, the second surface being opposite the first surface, the device region further includes a conductive via extending between the first surface and the second surface, and the interfacial material is absent from sidewalls of the conductive via or a concentration of the interfacial material at the sidewalls of the conductive via is less than about 10 15 atoms per cubic centimeter.Example 4 provides the IC structure of example 3, wherein the conductive via includes an electrically conductive fill material and wherein sidewalls of the conductive via are surrounded by an insulator material.Example 5 provides the IC structure of example 4, wherein the electrically conductive fill material is in contact with the insulator material at the sidewalls of the conductive via.Example 6 provides the IC structure of example 4, wherein the conductive via further includes a liner material, and wherein at the sidewalls of the conductive via, the electrically conductive fill material is in contact with the liner material and the liner material is in contact with the insulator material.Example 7 provides the IC structure of example 6, wherein the liner material includes carbon or nitrogen.Example 8 provides the IC structure of Examples 6 or 7, wherein the liner material either excludes the interfacial material or a concentration of the interfacial material within the liner material is less than about 10 15 atoms per cubic centimeter.Example 9 provides the IC structure of any of Examples 4-8, wherein the electrically conductive fill material includes tungsten.Example 10 provides the IC structure of any preceding example, wherein the interfacial material is titanium.Example 11 provides the IC structure of any preceding example, wherein the doped semiconductor material includes silicon and the interfacial material includes titanium and silicon (e.g., titanium silicide).Example 12 provides the IC structure of any preceding example, wherein a thickness of the interfacial material in the region between the region and the fill material is less than about 5 nanometers.Example 13 provides the IC structure of any of the preceding examples, wherein within the contact structure, one side of the interfacial material is in contact (e.g., in direct contact with) with the fill material and another side of the interfacial material is in contact (e.g., in direct contact with) with the doped semiconductor material.Example 14 provides an IC structure including: a device region having a first surface and a second surface, the second surface opposing the first surface; and a conductive via extending between the first surface and the second surface, the conductive via including an electrically conductive material, and wherein a concentration of titanium on sidewalls of the conductive via is less than about 10 15 atoms per cubic centimeter.Example 15 provides the IC structure of example 14, wherein the device region includes: a transistor; and a contact coupled to a source region of the transistor, wherein a portion of the contact closest to the source region includes an interfacial material, and the interfacial material includes titanium.Example 16 provides the IC structure of example 15, wherein titanium is substantially absent from sidewalls of the contact.Example 17 provides the IC structure of any of Examples 14-16, further including a plurality of first interconnects on the first surface of the device region and a plurality of second interconnects on the second surface of the device region, wherein: the conductive via is electrically connected to at least one of the first interconnects or at least one of the second interconnects, in a cross-section substantially perpendicular to the device region, each of the conductive via, the at least one of the first interconnects, and the at least one of the second interconnects has a trapezoidal shape having a first side and a second side, the first side being substantially parallel to the second side and shorter than the second side, for the trapezoidal shape of the at least one of the first interconnects, and the trapezoidal shape of the conductive via, the first side is closer to the second interconnects than the second side, and for the trapezoidal shape of the at least one of the second interconnects, the first side is closer to the device region than the second side.Example 18 provides a method of fabricating an IC structure, the method including: providing a channel material over a portion of a support; forming a source region of a transistor in the channel material; providing another material over the source region; forming an opening extending through the another material to expose a portion of the source region; performing selective deposition to deposit titanium on a bottom surface of the opening without substantially depositing titanium on sidewalls of the opening; and after performing selective deposition, filling the opening with an electrically conductive material.Example 19 provides the method of Example 18, wherein the portion of the support is a first portion, the opening is a first opening, the electrically conductive material is a first electrically conductive material, and the method further includes: providing an insulator material over a second portion of the support; forming a second opening extending into the insulator material; performing selective deposition to deposit titanium on a bottom surface of the second opening without substantially depositing titanium on sidewalls of the second opening; and after performing selective deposition to deposit titanium on the bottom surface of the second opening, filling the second opening with a second electrically conductive material.Example 20 provides the method of example 19, wherein a selective deposition to deposit titanium on the bottom of the first opening is performed substantially simultaneously with performing a selective deposition to deposit titanium on the bottom of the second opening.Example 21 provides the method of any of Examples 18-20, wherein the IC structure is an IC structure of any of the preceding Examples.Example 22 provides an IC package including: an IC die including an IC structure of any of Examples 1-17; and another IC component coupled to the IC die.Example 23 provides the IC package of example 22, wherein the further IC component is a package substrate.Example 24 provides the IC package of example 22, wherein the further IC component includes an interposer.Example 25 provides the IC package of example 22, wherein the further IC component includes a further IC die.Example 26 provides a computing device including a carrier substrate and an IC structure coupled to the carrier substrate, wherein the IC structure is an IC structure according to any of Examples 1-17, or the IC structure is included in the IC package according to any of Examples 22-25.Example 27 provides the computing device of example 26, wherein the computing device is a wearable or handheld computing device.Example 28 provides the computing device of Examples 26 or 27, wherein the computing device further includes one or more communication chips.Example 29 provides the computing device of any of Examples 26-28, wherein the computing device further includes an antenna.Example 30 provides the computing device of any of Examples 26-29, wherein the carrier substrate is a motherboard.Example 31 provides the IC structure of any of Examples 1-17, wherein the IC structure includes or is a part of a central processing unit.Example 32 provides the IC structure of any of Examples 1-31, wherein the IC structure includes or is a part of a memory device, e.g., a high bandwidth memory device.Example 33 provides the IC structure of any of Examples 1-32, wherein the IC structure includes or is a part of a logic circuit.Example 34 provides the IC structure of any of Examples 1-33, wherein the IC structure includes or is part of input / output circuitry.Example 35 provides the IC structure of any of Examples 1-34, wherein the IC structure includes or is a part of an FPGA transceiver.Example 36 provides the IC structure of any of Examples 1-35, wherein the IC structure includes or is a part of FPGA logic.Example 37 provides the IC structure of any of Examples 1-36, wherein the IC structure includes or is part of power delivery circuitry.Example 38 provides the IC structure of any of Examples 1-37, wherein the IC structure includes or is a part of a III-V amplifier.Example 39 provides the IC structure of any of Examples 1-38, wherein the IC structure includes or is part of PCIE circuitry or DDR transfer circuitry.The above description of illustrated implementations of the disclosure, including what is described in the Summary, is not intended to be exhaustive or to limit the disclosure to the precise forms disclosed. Although specific implementations of the disclosure and examples thereof are described herein for illustrative purposes, various equivalent modifications are possible within the scope of the disclosure, as will be apparent to one skilled in the art. These modifications may be made to the disclosure in light of the above detailed description.

Claims

An integrated circuit (IC) structure comprising: a transistor comprising a region of a doped semiconductor material, the region being one of a source region and a drain region of the transistor; and a contact structure coupled to the region, the contact structure comprising an interfacial material and a fill material, wherein within the contact structure, the interfacial material is confined to a region between the region and the fill material.The IC structure of claim 1, wherein the interfacial material is confined to the region between the region and the fill material by being on a bottom surface of the contact structure and substantially absent from sidewalls of the contact structure.The IC structure of claims 1 or 2, further comprising a device region, wherein: the transistor and the contact structure are located to the region within the device region, the device region has a first surface and a second surface, the second surface being opposite the first surface, the device region further includes a conductive via extending between the first surface and the second surface, and the interfacial material is absent from sidewalls of the conductive via or a concentration of the interfacial material at the sidewalls of the conductive via is less than about 10 15 atoms per cubic centimeter.The IC structure of claim 3, wherein the conductive via includes an electrically conductive fill material, and wherein sidewalls of the conductive via are surrounded by an insulator material.The IC structure of claim 4, wherein the electrically conductive fill material is in contact with the insulator material.The IC structure of claim 4, wherein the conductive via further includes a liner material, and wherein the electrically conductive fill material is in contact with the liner material and the liner material is in contact with the insulator material.The IC structure of claim 6, wherein the liner material includes carbon or nitrogen.The IC structure of claims 6 or 7, wherein the liner material either excludes the interface material or a concentration of the interface material within the liner material is less than about 10 15 atoms per cubic centimeter.The IC structure of any of claims 4-8, wherein the electrically conductive fill material includes tungsten.The IC structure of any of claims 1-9, wherein the interface material is titanium.The IC structure of any of claims 1-10, wherein the doped semiconductor material includes silicon and the interface material includes titanium and silicon.The IC structure of any of claims 1-11, wherein a thickness of the interfacial material in the region between the region and the fill material is less than about 5 nanometers.The IC structure of any of claims 1-12, wherein within the contact structure, one side of the interface material is in contact with the fill material and another side of the interface material is in contact with the doped semiconductor material.An integrated circuit (IC) structure comprising: a device region having a first surface and a second surface, the second surface opposing the first surface; and a conductive via extending between the first surface and the second surface, the conductive via including an electrically conductive material, and wherein a concentration of titanium on sidewalls of the conductive via is less than about 10 15 atoms per cubic centimeter.The IC structure of claim 14, wherein the device region includes: a transistor; and a contact coupled to a source region of the transistor, wherein a portion of the contact closest to the source region includes an interface material, and the interface material includes titanium.The IC structure of claim 15, wherein titanium is substantially absent from sidewalls of the contact.The IC structure of any of claims 14-16, further comprising a plurality of first interconnects on the first surface of the device region and a plurality of second interconnects on the second surface of the device region, wherein: the conductive via is electrically connected to at least one of the first interconnects or at least one of the second interconnects, in a cross-section substantially perpendicular to the device region, a single one of the conductive via, the at least one of the first interconnects, and the at least one of the second interconnects has a trapezoidal shape having a first side and a second side, the first side being substantially parallel to the second side and shorter than the second side, is closer to the second interconnects than the second side for the trapezoidal shape of the at least one of the first interconnects, and the trapezoidal shape of the conductive via the first side, and for the trapezoidal shape of the at least one of the second interconnects, the first side is closer to the device region than the second side.A method of fabricating an integrated circuit (IC) structure, the method comprising: providing a channel material over a portion of a support; forming a source region of a transistor in the channel material; providing another material over the source region; forming an opening extending through the another material to expose a portion of the source region; performing selective deposition to deposit titanium on a bottom surface of the opening without substantially depositing titanium on sidewalls of the opening; and after performing selective deposition, filling the opening with an electrically conductive material.The method of claim 18, wherein the portion of the support is a first portion, the opening is a first opening, the electrically conductive material is a first electrically conductive material, and the method further comprises: providing an insulator material over a second portion of the support; forming a second opening extending into the insulator material; performing selective deposition to deposit titanium on a bottom surface of the second opening without substantially depositing titanium on sidewalls of the second opening; and after performing selective deposition to deposit titanium on the bottom surface of the second opening, filling the second opening with a second electrically conductive material.The method of claim 19, wherein a selective deposition for depositing titanium on the bottom surface of the first opening is performed substantially simultaneously with performing a selective deposition for depositing titanium on the bottom surface of the second opening.

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