PHOTOELECTRIC CONVERSION DEVICE AND METHOD FOR CONTROLLING A PHOTOELECTRIC CONVERSION DEVICE

Abstract

A photoelectric conversion device comprises pixel circuits arranged to form a plurality of rows and a plurality of columns, and a control circuit for controlling the pixel circuits. Each pixel circuit includes a signal generation circuit with a photoelectric conversion section, a memory that holds a signal output by the signal generation circuit, and a sequential circuit with a first input node into which the signal from the memory is input, a second input node into which a control signal from the control circuit is input, a third input node, and an output node.The pixel circuits include first and second pixel circuits arranged in the same row or column, and the output node of the sequential circuit of the first pixel circuit is connected to the third input node of the sequential circuit of the second pixel circuit.

Description

TECHNICAL FIELD

[0001] The present invention relates to a photoelectric conversion device and a method for driving a photoelectric conversion device. BACKGROUND OF THE INVENTION

[0002] In recent years, performance improvements such as increasing the number of pixels and increasing the readout speed have been attempted in an image sensor, a distance measuring system, and the like. Some proposals have been made regarding a pixel information readout method corresponding to increasing the amount of information possessed by the entire pixel. JP 2012-070170 and JP 2018-186478 disclose an image sensing device in which image information from one light receiving unit is transmitted to an image processing unit via another light receiving unit, thereby reducing the length of the connections connected to a plurality of light receiving units.

[0003] However, in the technique described in JP 2012-070170, when there are a large number of pixel rows, the pixel signals outside the pixel circuits must be processed sequentially, and reading the signals from all pixels takes time. Furthermore, in the technique described in JP 2018-186478, an outside-pixel readout circuit provided for each pixel column is responsible for processing the signals of the corresponding pixel column, and essentially the same problem exists as in JP 2012-070170. SUMMARY OF THE INVENTION

[0004] The object of the present invention is to provide a photoelectric conversion device and a method for driving the same capable of reducing a time required for reading out pixel signals.

[0005] According to one aspect of the present invention, a photoelectric conversion device is provided including a plurality of pixel circuits arranged to form a plurality of rows and a plurality of columns, and a control circuit configured to drive the plurality of pixel circuits, wherein each of the plurality of pixel circuits includes a signal generating circuit having a photoelectric conversion unit, a memory configured to hold a signal output from the signal generating circuit, and a sequential circuit having a first input node to which a signal is input from the memory, a second input node to which a control signal is input from the control circuit, a third input node, and an output node, and wherein the plurality of pixel circuits includes a first pixel circuit and a second pixel circuit,which are arranged in the same row or column, and the output node of the sequential circuit of the first pixel circuit is connected to the third input node of the sequential circuit of the second pixel circuit.,

[0006] According to a further embodiment of the present invention, there is provided a photoelectric conversion device including a plurality of pixel circuits arranged to form a plurality of rows and a plurality of columns, and a control circuit configured to drive the plurality of pixel circuits, wherein each of the plurality of pixel circuits includes a signal generating circuit having a photoelectric conversion unit, a memory configured to hold a signal output from the signal generating circuit, and a sequential circuit to which the signal is transferred from the memory, wherein the plurality of pixel circuits includes a first group and a second group, each including two or more of the pixel circuits arranged in the same row, wherein the sequential circuits of the pixel circuits,which respectively form the first group and the second group, are connected in series along a row direction and are configured to sequentially transfer the signals held by the respective pixel circuits from one side to the other side along the row direction in accordance with a control signal from the control circuit, and wherein the control circuit is configured to perform a signal transfer operation in the pixel circuits of the first group and a signal transfer operation in the pixel circuits of the second group in parallel by supplying a common control signal to the pixel circuits of the first group and the pixel circuits of the second group.

[0007] According to a further embodiment of the present invention, a signal output device is provided which includes a plurality of signal holding circuits arranged to form a plurality of rows and a plurality of columns, and a control circuit configured to drive the plurality of signal holding circuits, wherein each of the plurality of signal holding circuits includes a memory configured to hold a predetermined signal and a sequential circuit to which the signal is transferred from the memory, wherein the plurality of signal holding circuits includes a first group and a second group, each including two or more of the signal holding circuits arranged in the same row, wherein the sequential circuits of the signal holding circuits each forming the first group and the second group,are connected in series along a row direction and are configured to sequentially transfer the signals held by the respective signal holding circuits from one side to the other side along the row direction in accordance with a control signal from the control circuit, and wherein the control circuit is configured to perform a signal transfer operation in the signal holding circuits of the first group and a signal transfer operation in the signal holding circuits of the second group in parallel by supplying a common control signal to the signal holding circuits of the first group and the signal holding circuits of the second group.

[0008] According to a further aspect of the present invention, there is provided a method for driving a photoelectric conversion device including a plurality of pixel circuits arranged to form a plurality of rows and a plurality of columns, each of the plurality of pixel circuits including a signal generating circuit having a photoelectric conversion device, a memory configured to hold a signal output from the signal generating circuit, and a sequential circuit to which the signal is transferred from the memory, the plurality of pixel circuits including a first group and a second group each including two or more of the pixel circuits arranged in the same row, and the sequential circuits of the pixel circuits each forming the first group and the second groupare connected in series along a row direction, the method comprising holding a signal based on a charge generated in the photoelectric conversion unit by incident light in the memory in each of the plurality of pixel circuits, transferring the signal held in the memory to the sequential circuit in each of the plurality of pixel circuits, and sequentially transferring the signals held by the sequential circuits of the pixel circuits each constituting the first group and the second group from one side to the other side along the row direction, wherein, in the sequential transfer, a signal transfer operation in the pixel circuits of the first group and a signal transfer operation in the pixel circuits of the second group are performed in parallel,by supplying a common control signal to the pixel circuits of the first group and the pixel circuits of the second group.,

[0009] Further features of the present invention will become apparent from the following description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWING Fig. 1 is a block diagram showing a schematic configuration of a signal output device according to a first embodiment of the present invention. Fig. 2 is a block diagram showing a configuration example of a signal holding circuit in the signal output device according to the first embodiment of the present invention. Fig. 3, Fig. 4, Fig. 5 and Fig. 6 are block diagrams showing a configuration example of a clock buffer circuit in the signal output device according to the first embodiment of the present invention. Fig. 7 is a timing chart illustrating a method of driving the signal output device according to the first embodiment of the present invention. Fig. 8 is a circuit diagram showing a schematic configuration of a signal output device according to a second embodiment of the present invention. Fig. 9 is a block diagram showing a schematic configuration of a signal output device according to a third embodiment of the present invention. Fig. 10 is a circuit diagram showing another configuration example of the signal output device according to the third embodiment of the present invention. Fig. 11 is a block diagram showing a schematic configuration of a photoelectric conversion device according to a fourth embodiment of the present invention. Fig. 12 is a block diagram showing a schematic configuration of a photodetection system according to a fifth embodiment of the present invention. Fig. 13 is a block diagram showing a schematic configuration of a distance image sensor according to a sixth embodiment of the present invention. Fig. 14 is a schematic diagram showing a configuration example of an endoscopic surgical system according to a seventh embodiment of the present invention. Fig. 15A, Fig. 15B and Fig. 15C are schematic diagrams showing an example of a configuration of a movable object according to an eighth embodiment of the present invention. Fig. 16 is a block diagram showing a schematic configuration of a photodetection system according to the eighth embodiment of the present invention. Fig. 17 is a flowchart showing the operation of the photodetection system according to the eighth embodiment of the present invention. Fig. 18A and Fig. 18B are schematic diagrams showing a schematic configuration of a photodetection system according to a ninth embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0010] Preferred embodiments of the present invention are described in detail below in accordance with the accompanying drawings. [First embodiment]

[0011] A signal output device and a method for driving the same according to a first embodiment of the present invention are described below with reference to Fig. 1 to Fig. 7 described. Fig. 1 is a block diagram showing a schematic configuration of a signal output device according to the present embodiment. Fig. 2 is a block diagram showing a configuration example of a signal holding circuit in the signal output device according to the present embodiment. Fig. 3 to Fig. 6 are circuit diagrams showing configuration examples of the clock buffer circuit in the signal output device according to the present embodiment. Fig. 7 is a timing chart showing a method of driving the signal output device according to the present embodiment. First, a schematic configuration of the

[0012] Signal output device according to the present embodiment with reference to Fig. 1. As described in Fig. 1, the signal output device 50 according to the present embodiment includes a signal holding section 10 and a clock buffer circuit 40.

[0013] The signal holding section 10 is equipped with a plurality of signal holding circuits 12 arranged in a matrix such that they form a plurality of rows and a plurality of columns. Fig. 1, the signal holding section 10 is assumed to consist of a plurality of signal holding circuits 12 arranged in a matrix of (M number of rows) × (N number of columns). Each of the plurality of signal holding circuits 12 is assigned coordinates corresponding to a row number and a column number. For example, the block of the signal holding circuit 12 arranged in the m-th row and the n-th column is designated by coordinates (m, n) in addition to the reference numeral 12. Where, m is an integer from 1 to M, and n is an integer from 1 to N.

[0014] The number of signal holding circuits 12 constituting the signal holding section 10 is not particularly limited as long as M is an integer of 1 or more and N is an integer of 2 or more. Note that a row and a column can be arbitrarily defined, and the row described in the present embodiment may be a column, and the column described in the present embodiment may be a row.

[0015] The N number of signal holding circuits 12 arranged in each row of the signal holding area 10 form a signal holding circuit group 14. Fig. 1, corresponding row numbers are appended to the reference numbers of the signal holding circuit groups 14 of the respective rows. For example, the signal holding circuit group 14 arranged in the m-th row is designated with the reference number 14 mThe N number of signal holding circuits 12 forming a signal holding circuit group 14 are connected in series. For example, if the signal holding circuit group 14 m As described by way of example, an input node of the signal holding circuit 12(m, 1) is connected to a ground voltage node, and an output node of the signal holding circuit 12(m, 1) is connected to an input node of the signal holding circuit 12(m, 2) (not shown). An input node of the signal holding circuit 12(m, n) is connected to an output node of the signal holding circuit 12(m, n-1), and an output node of the signal holding circuit 12(m, n) is connected to an input node of the signal holding circuit 12(m, n+1). An input node of the signal holding circuit 12(m, N) is connected to an output node of the signal holding circuit 12(m, N-1) (not shown), and an output node of the signal holding circuit 12(m, N) is connected to an output line 18. m tied together.

[0016] A signal line 16 is arranged in each column of the signal holding area 10. Fig. 1, the reference numbers of the signal lines 16 of the respective columns are provided with corresponding column numbers. For example, the signal line 16 arranged in the nth column is given the reference number 16 n Each of the signal lines 16 is connected to the signal holding circuits 12 arranged in the corresponding column. For example, the signal line 16 n connected to the signal latch circuits 12(1, n), ..., 12(m-1, n), 12(m, n), 12(m+1, n), ..., 12(M, n) arranged in the nth column. The signal lines 16 are connected to the clock buffer circuit 40.

[0017] The clock buffer circuit 40 serves as a control circuit for driving the signal holding circuits 12. The clock buffer circuit 40 has an input node to which a clock signal is input, and the number of output nodes TAP corresponds to each column of the signal holding area 10. Fig. 1, the reference numbers of the output nodes TAP of the respective columns are assigned corresponding column numbers. For example, the output node TAP located in the nth column is assigned the reference number TAP n From each of the output nodes TAP, a clock signal is output, which is input to the clock buffer circuit 40 and processed by its internal circuitry.

[0018] Although a clock buffer circuit 40 for the M number of signal holding circuit groups 141 to 14 M at Fig. 1, the clock buffer circuit 40 may be provided in units of arbitrary rows. For example, an M number of clock buffer circuits 40 may be provided corresponding to each of the plurality of signal holding circuit groups 141 to 14 M provided, or one clock buffer circuit 40 may be provided for any number of two or more signal latch circuit groups 14. Reducing the number of clock buffer circuits 40 has the advantage of improving the power efficiency of the entire device.

[0019] Next, a configuration example of the signal holding circuit 12 is described with reference to Fig. 2 described. Fig. 2 represents three signal holding circuits 12(m, n-1), 12(m, n) and 12(m, n+1) of the signal holding circuit group 14 marranged in adjacent columns of the plurality of signal holding circuits 12 forming the signal holding section 10. An internal circuit configuration and connection relationships of the other signal holding circuits 12 are similar to those shown in Fig. 2. Although the circuit constituting the signal holding circuit 12 is not particularly limited as long as it has the function of holding a signal, a pixel circuit of a photoelectric conversion device will be described here as an example.

[0020] Such as in Fig. 2, the signal holding circuit 12 may include a signal generating circuit 24, a memory 26, and a sequential circuit 28. The signal generating circuit 24 is connected to the memory 26. The memory 26 is connected to the sequential circuit 28. The signal generating circuit 24 includes a photoelectric conversion element, generates a signal according to the light incident on the photoelectric conversion element, and outputs the generated signal to the memory 26. The memory 26 holds the signal input from the signal generating circuit 24 and outputs the held signal to the sequential circuit 28 in accordance with an external control signal. The sequential circuit 28 is a circuit whose output state is determined by a combination of an external input signal and a held internal state, and may be implemented, for example, by a D flip-flop having a set terminal.Stell- or set connection can be configured.

[0021] The D-type flip-flop with the set terminal includes two input terminals (a D terminal and an S terminal), a clock input terminal (a CK terminal), and an output terminal (a Q terminal). When a signal is input to the S terminal, the data output from the Q terminal of the sequential circuit 28 is at the level of the signal input to the S terminal, regardless of the clock signal input to the CK terminal. When a signal is input to the D terminal, the data output from the Q terminal of the sequential circuit 28 assumes the level of the signal input to the D terminal, synchronously with the level transition of the clock signal input to the CK terminal. The clock signal input to the CK terminal can also be referred to as the control signal of the sequential circuit 28.

[0022] Note that a D flip-flop in which the level of the signal output from the Q terminal changes in accordance with the timing of the rising edge of the clock signal (positive edge) is called a positive-edge-triggered D flip-flop. A D flip-flop in which the level of the signal output from the Q terminal changes in accordance with the timing of the falling edge of the clock signal (negative edge) is called a negative-edge-triggered D flip-flop. Although the sequential circuit 28 can be configured by any D flip-flop, it is assumed here that the sequential circuit 28 is configured by a positive-edge-triggered D flip-flop.

[0023] The S terminal of the sequential circuit 28 is connected to the output node of the memory 26. The D terminal of the sequential circuit 28 is connected to the input node 20 of the signal holding circuit 12. The CK terminal of the sequential circuit 28 is connected to the input node 22 of the signal holding circuit 12. The Q terminal of the sequential circuit is connected to the output node 30 of the signal holding circuit 12.

[0024] The N number of signal holding circuits 12 arranged in the same row and forming a signal holding circuit group 14 are connected in series as described above. For example, the input node 20 of the signal holding circuit 12(m, n) is connected to the output node 30 of the signal holding circuit 12(m, n-1), and the output node 30 of the signal holding circuit 12(m, n) is connected to the input node 20 of the signal holding circuit 12(m, n+1). The signal line 16 arranged in the corresponding column is connected to the input node 22 of the signal holding circuit 12. For example, the input node 22 of the signal holding circuit 12(m, n) is connected to the signal line 16. n connected to the output node TAP nthe clock buffer circuit 40. Thus, the serial connection body of the sequential circuits 28 included in the signal holding circuits 12 of each column of the one signal holding circuit group 14 forms a shift register.

[0025] It can also be said that the signal holding circuit group 14 has an input node and an output node in each row as a whole. For example, the input node 20 of the signal holding circuit 12(m, 1) can be an input node of the signal holding circuit group 14. m and the output node 30 of the signal holding circuit 12(m, N) may be an output node of the signal holding circuit group 14 m Although the input node 20 of the signal holding circuit 12(m, 1) is connected to the ground voltage node in Fig. 1, any logic signal can be input from the input node 20 of the signal holding circuit 12(m, 1).

[0026] The following is a configuration example of the clock buffer circuit 40 with reference to Fig. 3 to Fig. 6 described.

[0027] As described above, the clock buffer circuit 40 includes an input node CIN and N (N number) of output nodes TAP1 to TAP N , which corresponds to the number of columns forming the signal holding area 10. A clock signal is input to the input node CIN and clock signals formed by an internal circuit are output from the output nodes TAP1 to TAP N issued. As in Fig. 3 to Fig. As shown in Figure 6, the clock buffer circuit 40 may include a plurality of buffer circuits 42 or a plurality of inverting buffer circuits 46. The clock buffer circuit 40 may be configured by a buffer structure such as a tree type, a repeater type, or the like, although it is assumed here that the clock buffer circuit has a tree type buffer structure.

[0028] At the Fig. 3, N buffer circuits 42 are connected in series, corresponding to the number of columns forming the signal holding area 10. The output nodes of the N buffer circuits 42 are connected to the output nodes TAPN, TAP N-1 , ..., TAP n+1 , TAP n , TAP n-1 , ..., TAP2 and TAP1 of the clock buffer circuit 40 in order from the side near the input node CIN.

[0029] The Fig. The clock buffer circuit 40 shown in Figure 4 is a configuration example in which a logic circuit 44 is connected between the output node TAP and the output node of the buffer circuit 42 of each column. Here, the logic circuit 44 is a circuit such as a buffer, an inverter, or the like for improving the bluntness of a voltage waveform. That is, by providing the logic circuit 44, the dependency relationship between the voltage waveforms of the output nodes TAP1 to TAP N and the output impedance of the buffer circuits 42 can be reduced and the degree of freedom in circuit design can be improved.

[0030] At the Fig. In the clock buffer circuit 40 shown in Figure 5, the buffer circuits 42 are replaced by inverting buffer circuits 46. The clock buffer circuit 40 does not necessarily have to be configured as a non-inverting buffer circuit, but can also be configured as an inverting buffer circuit. The inverting buffer circuit 46 can be based on the configuration example of Fig. 4 may be applied.

[0031] The Fig. The clock buffer circuit 40 shown in Figure 6 includes an (N / 2) number of buffer circuits 42 connected in series, where N is the number of columns forming the signal holding area 10. Two output nodes TAP of the clock buffer circuit 40 are connected to the output nodes of each of the (N / 2) number of buffer circuits 42. For example, an output node of the buffer circuit 42 located at a position closest to the input node CIN is connected to the output nodes TAP. Nand TAP N-1 The (N / 2)-th output node of the buffer circuit 42 from the input node CIN is connected to the output node TAP n and TAP1. Clock pulses are output from two output nodes TAP connected to the output node of the same buffer circuit 42 at the same time. Although an example is described here in which two output nodes TAP are connected to the output node of the same buffer circuit 42, three or more output nodes TAP may be connected to the output node of the same buffer circuit 42.

[0032] This configuration can also be applied to the configuration example of Fig. 4 or Fig. 5 can be applied.

[0033] Although the input node CIN of the clock buffer circuit 40 may be provided on the first column side of the signal holding circuit group 14, from the viewpoint of controllability of the timing design, it is more advantageous to provide it on the Nth column side of the signal holding circuit group 14, as shown in Fig. 3 to Fig. 6. In this case, for example, the number of buffer circuits 42 through which the clock signal supplied to the sequential circuit 28 of the signal holding circuit 12 of the (n-1)-th column passes is greater than the number of buffer circuits 42 through which the clock signal supplied to the sequential circuit 28 of the signal holding circuit 12 of the n-th column passes.

[0034] Next, the operation of the signal output device according to the present embodiment will be described with reference to Fig. 7 described. Fig. 7 schematically illustrates the operation of the signal output device in the J-th frame and the (J+1)-th frame. The period from time t0 to time t2 is the period of the J-th frame, and the period from time t2 to time t4 is the period of the (J+1)-th frame.

[0035] The period from time t1 to time t2 is the exposure period of the J-th frame. When light enters the signal holding area 10 during the exposure period, the signal generating circuit 24 of each signal holding circuit 12 generates a logic signal of logic H or logic L depending on the incident light and outputs the generated logic signal to the memory 26. The logic signal output from the signal generating circuit 24 is stored in the memory 26. The logic signal stored in the memory 26 during the exposure period of the J-th frame is read out during the next (J+1)-th frame period.

[0036] After the logic signal from the signal generation circuit 24 of each signal holding circuit 12 is determined at time t2, the latch 26 of each signal holding circuit 12 outputs the latched logic signal to the S terminal of the sequential circuit 28 in accordance with a control signal from a control circuit (not shown). As a result, the logic signal transmitted from the latch 26 is latched in the sequential circuit 28 as its output.

[0037] In a period from time t3 to time t4 after the transfer of the Likog signal from the memory 26 to the sequential circuit 28 in each signal latch circuit 12 is completed, the control circuit (not shown) inputs a predetermined number or more of clock pulses from the input node CIN of the clock buffer circuit 40. As a result, a clock pulse is output from each output node TAP of the clock buffer circuit 40 at a predetermined timing corresponding to the input timing of the clock pulse to the input node CIN and the number of buffer circuits 42 up to each output node TAP. The number of clock pulses input to the clock buffer circuit 40 (the predetermined number or more of clock pulses described above) may be equal to or greater than (N-1), where N is the number of signal latch circuits 12 (the number of columns) included in the signal latch circuit group 14.

[0038] The sequential circuit 28 of the signal latch circuit 12 of each column constituting the signal latch circuit group 14 is driven by a clock pulse output from the corresponding output node TAP of the clock buffer circuit 40. The sequential circuit 28 sends the adjusted logic signal to the subsequent sequential circuit 28 each time the clock pulse is received. For example, the logic signal adjusted in the sequential circuit 28 of the signal latch circuit 12(m, n) is adjusted in the sequential circuit 28 of the subsequent signal latch circuit 12(m, n+1) in response to an input of the clock pulse to the signal latch circuit 12(m, n).Furthermore, the logic signal set in the sequential circuit 28 of the signal latch circuit 12(m, n-1) is set in the sequential circuit 28 of the signal latch circuit 12(m, n) of the subsequent stage in response to the input of the clock pulse to the signal latch circuit 12(m, n-1). As a result, the logic signals held in the signal latch circuits 12 of the respective columns are sequentially transmitted to the output line 18, and the number of logic signals corresponding to the number of clock pulses input to the clock buffer circuit 40 is output as a bit stream to the output line 18 of the signal latch circuit group 14.

[0039] In this way, by inputting the number of clock pulses corresponding to the number of signal latch circuits 12 constituting each signal latch circuit group 14, the bit streams of the signal latch circuit groups 14 in all rows can be output. That is, the data of all the signal latch circuits 12 constituting the signal latch section 10 can be read out and output to a device in a subsequent stage (not shown). In a case where the signal latch section 10 is configured by the signal latch circuits 12 arranged in a matrix of (1000 rows) × (1000 columns), for example, 1M-bit information held in the signal latch section 10 can be read out by inputting the clock pulse 999 times, and the readout time can be shortened.

[0040] The phases of the clock pulses coming from the output nodes TAP1 to TAP Noutput from the output node TAP are different from each other, and the timing at which the sequential circuit 28 of the signal holding circuit 12 of each column sends the logic signal to the subsequent stage is also different. For example, the phase of the signal output from the output node TAP noutput clock pulse is delayed from the phase of the clock pulse output from the output node TAPN. As a result, the drive timing of the sequential circuit 28 of the signal hold circuit 12 in the nth column becomes later than the drive timing of the sequential circuit 28 of the signal hold circuit 12 in the Nth column. Therefore, the power surge generated by the readout operation of the logic signals from the signal hold section 10 is a superposition of small voltage spikes with different phases over the entire readout time. Since the intensity of the power surge is dispersed over time, it is possible to reduce an obstacle to accelerating the readout operation.

[0041] Furthermore, when the input node CIN of the clock buffer circuit 40 is located on the Nth column side of the signal latch section 10, it is easy to control the timing of the clock signal input from the control circuit (not shown) and the phase of the bit stream output from the signal latch circuit group 14. The ability to relax the timing constraints on the design is an advantage for accelerating the readout process.

[0042] The transfer period during which the transfer operation for outputting the logic signal captured during the exposure period of the Jth frame is performed can be performed in parallel with the exposure period of the next frame (the (J+1)th frame). This further increases the readout speed.

[0043] As described above, according to the present embodiment, it is possible to reduce the time required for reading out pixel signals in a photoelectric conversion device including a plurality of pixel circuits. [Second embodiment]

[0044] A signal output device and a method for driving the same according to a second embodiment of the present invention is described with reference to Fig. 8. The same components as those of the signal output device according to the first embodiment are denoted by the same reference numerals, and a description thereof is omitted or simplified. Fig. 8 is a circuit diagram showing a schematic configuration of a signal output device according to the present embodiment.

[0045] A schematic configuration of the signal output device according to the present embodiment is shown with reference to Fig. 8 described. Fig. Fig. 8 shows a corresponding section of the clock buffer circuit 40 and two signal holding circuits 12(m, n) and 12(m, n+1) arranged in adjacent columns of the signal holding circuit group 14 m are arranged under the signal holding circuits 12 which form the signal holding section 10.

[0046] In the signal output device according to the present embodiment, the configuration of the sequential circuit 28 is different in the signal latch circuits 12 arranged in adjacent columns of the same row. Specifically, one of the two adjacent signal latch circuits 12 is configured by using a positive-edge-triggered D flip-flop (sequence circuit 28P), and the other is configured by using a negative-edge-triggered D flip-flop (sequence circuit 28N). For example, in the case where the signal latch circuit 12(m, n) is configured by the positive-edge-triggered sequence circuit 28P, the signal latch circuit 12(m, n-1) and the signal latch circuit 12(m, n+1) are configured by the negative-edge-triggered sequence circuit 28N.The clock buffer circuit 40 is configured by the inverting buffer circuits 46 to adapt to the clock drive appropriate for the operations of the sequential circuits 28P and 28N.

[0047] Here, it is assumed that the signal generating circuit 24 is a SPAD (Single Photon Avalanche Diode) circuit and outputs a logic signal of logic H when incident light is detected. For example, as in Fig. As shown in Fig. 8, the signal generating circuit 24 may include an avalanche photodiode PD, a cancellation element Mq, a waveform shaping circuit INV, and a logic circuit AND1.

[0048] A voltage Vbias1 is applied to a cathode of the avalanche photodiode PD via the cancellation element Mq, and a voltage Vbias2 is applied to an anode of the avalanche photodiode PD. An input node of the waveform shaping circuit INV is connected to a connection node between the cathode of the avalanche photodiode PD and the cancellation element Mq. An output node of the waveform shaping circuit INV is connected to an input node of the logic circuit AND1, and a control signal sel is supplied to the other input node of the logic circuit AND1 from a control circuit (not shown). An output node of the logic circuit AND1 is the output node of the signal generating circuit 24.

[0049] When light is incident on the avalanche photodiode PD in a state where a reverse bias voltage corresponding to a potential difference between the voltage Vbias1 and the voltage Vbias2 is applied, an electron-hole pair is generated by photoelectric conversion, and an avalanche current flows using the charge as a nucleus. The waveform shaping circuit INV converts a voltage change due to the avalanche current flowing through the avalanche photodiode PD into a pulse signal and outputs a logic signal of logic H corresponding to the light incidence. The logic circuit AND1 outputs a logic signal of logic H when both the output signal of the waveform shaping circuit INV and the control signal sel are logic H.

[0050] Such as in Fig. As shown in Figure 8, the memory 26 may include an RS flip-flop circuit FF and a logic circuit AND2. The RS flip-flop circuit FF includes two input terminals (an S terminal and an R terminal) and one output terminal (a Q terminal). The S terminal of the RS flip-flop circuit FF is connected to the output node of the signal generating circuit 24, and the Q terminal of the RS flip-flop circuit FF is connected to an input node of the logic circuit AND2. The R terminal of the RS flip-flop circuit FF is supplied with a control signal clear from the control circuit (not shown), and the other input node of the logic circuit AND2 is supplied with a control signal WRT from the control circuit (not shown). An output node of the logic circuit AND2 is the output node of the memory 26.

[0051] The RS flip-flop circuit FF is bistable. When it receives a logic signal of logic H from the signal generation circuit 24, the RS flip-flop circuit FF latches the logic signal of logic H and outputs the logic signal from the Q terminal. When the RS flip-flop circuit FF receives a control signal clear of logic H from the control circuit (not shown), the RS flip-flop circuit FF resets the latched logic signal. The logic circuit AND1 outputs a logic signal of logic H when both the output signal of the RS flip-flop circuit FF and the control signal WRT are logic H.

[0052] The configuration and operation of the sequential circuits 28P and 28N are as described in the first embodiment. That is, the sequential circuit 28P can be configured by a positive-edge-triggered D flip-flop circuit, and the sequential circuit 28N can be configured by a negative-edge-triggered D flip-flop circuit. In the sequential circuits 28P and 28N, when the output of the latch 26 is logic H, the output of the Q terminal becomes logic H in response to a control signal at an appropriate timing from the control circuit (not shown).

[0053] Before this appropriate time, the Q terminals of the sequential circuits 28 of all the signal latches 12 constituting the signal latch group 14 must be logic L. This can be achieved by inputting clock pulses equal to or greater than the number of signal latches 12 constituting the signal latch group 14 to the input node CIN of the clock buffer circuit 40 while setting the input node of the signal latch group 14 to logic L.

[0054] In the signal output device according to the present embodiment, the design of the clock buffer circuit 40 and the sequential circuits 28P and 28N becomes simple, and the circuit area and power consumption can be reduced. Moreover, even if the output drive power of the inverting repetition buffer of the clock buffer circuit 40 is unbalanced at the rising and falling edges of the signal, the drive power unbalance is canceled during the repeated inverting propagation. This makes it possible to reduce the adverse effect that the reduction or widening of the duty cycle of the voltage waveform propagates to the taps on the upstream side of the signal holding circuit 12. The reduction in area and power consumption, as well as the improvement in the designability of the buffer circuit, are advantages for accelerating the readout operation.

[0055] As described above, according to the present embodiment, it is possible to reduce the time required for reading out pixel signals in a photoelectric conversion device including a plurality of pixel circuits. [Third embodiment]

[0056] A signal output device and a method for driving the same according to a third embodiment of the present invention is described with reference to Fig. 9 and Fig. 10. The same components as those of the signal output device according to the first or second embodiment are denoted by the same reference numerals, and the description thereof is omitted or simplified. Fig. 9 is a block diagram showing a schematic configuration of a signal output device according to the present embodiment. Fig. 10 is a circuit diagram showing a configuration example of the signal output device according to the present embodiment.

[0057] Fig. Fig. 9 illustrates a plurality of signal holding circuits 12 constituting one row among the components of the signal output device according to the present embodiment. In the present embodiment, the plurality of signal holding circuits 12 constituting one row (for example, the m-th row) are divided into two signal holding circuit groups 14A. m and 14B m The method for distributing the signal holding circuits 12 to the two signal holding circuit groups 14A m and 14B m is not particularly limited, but for example, the signal holding circuits 12 may be alternately applied to the signal holding circuit groups 14A m and 14B min units of a predetermined number of columns. When the signal holding circuits 12 are alternately distributed every two columns to the signal holding circuit groups 14A m and 14B m distributed, such as in Fig. 9, the signal holding circuits 12(m, 1), 12(m, 2), ..., 12(m, N-3) and 12(m, N-2) can be applied to the signal holding circuit group 14A m In addition, the signal holding circuits 12(m, 3), 12(m, 4), ..., 12(m, N-1) and 12(m, N) can be distributed to the signal holding circuit group 14B m The assignment of the signal holding circuits 12 to the signal holding circuit groups 14A m and 14B m can be performed for each column or for a predetermined number of columns of three or more columns. The plurality of signal latch circuits 12 forming a row can be divided into three or more signal latch circuit groups 14.

[0058] The output line 18 arranged in each row m is in output lines 18A m and 18B m divided into the signal holding circuit groups 14A m and 14B m The clock buffer circuit 40 is connected to the signal holding circuit groups 14A m and 14B m common and is configured to input the clock signal output from each output node TAP into the signal holding circuit 12 of the corresponding column, as in the first embodiment. Thus, the reading of the signals from the signal holding circuits 12 belonging to the signal holding circuit group 14A m belong to the output line 18A m and reading out the signals from the signal holding circuits 12 belonging to the signal holding circuit group 14B m belong to the output line 18B m take place in parallel.

[0059] Fig. Fig. 10 illustrates a part of the sequential circuits 28 of the plurality of signal holding circuits 12 constituting two rows (m-th row and (m+1)-th row) among the components of the signal output device according to the present embodiment. In the configuration example of Fig. 10, the signal latch circuit 12 including the sequential circuit 28P and the signal latch circuit 12 including the sequential circuit 28N are alternately arranged for every four columns, and a common clock signal is input to all four columns. The plurality of signal latch circuits 12 in each row are alternately distributed among the signal latch circuit groups 14A and 14B for each column. For example, the signal latch circuits 12 arranged in odd-numbered columns belong to the signal latch circuit group 14A, and the signal latch circuits 12 arranged in even-numbered columns belong to the signal latch circuit group 14B.

[0060] In the present embodiment, the number of signal latch circuits 12 included in each of the signal latch circuit groups 14A and 14B is half the number of signal latch circuits 12 included in the signal latch circuit group 14 of the first or second embodiment. Furthermore, the readout of the signals from the signal latch circuit group 14A and the readout of the signals from the signal latch circuit group 14B can be performed in parallel without the need to newly replace the clock buffer circuit 40. Therefore, according to the present embodiment, the readout time of the signal from the signal latch circuits 12 in each row can be reduced by half compared to the signal output device according to the first or second embodiment.Furthermore, in the present embodiment, the number of clock pulses required to read signals from the plurality of signal latch circuits 12 constituting one row is also halved. As a result, the circuit's power consumption during signal processing can be reduced.

[0061] As described above, according to the present embodiment, it is possible to reduce the time required for reading out pixel signals in a photoelectric conversion device including a plurality of pixel circuits. [Fourth embodiment]

[0062] A photoelectric conversion device according to a fourth embodiment of the present invention is described with reference to Fig. 11. The same components as those of the signal output devices according to the first to third embodiments are denoted by the same reference numerals, and their description is omitted or simplified. Fig. 11 is a block diagram showing a schematic configuration of the photoelectric conversion device according to the present embodiment.

[0063] In the present embodiment, an example is described in which the configuration of the signal output device according to the first embodiment is applied to a photoelectric conversion device. Although an example in which the signal output device according to the first embodiment is applied is described here, the signal output device according to the second or third embodiments can be similarly applied. The configuration of the signal output device according to the first to third embodiments is applicable not only to the photoelectric conversion device but also to various devices configured to output signals from a plurality of signal holding units.

[0064] The photoelectric conversion device 100 according to the present embodiment can be, for example, as shown in Fig. 11, a pixel region 110, a vertical drive circuit 120, a control circuit 130, a clock buffer circuit 140, a signal processing circuit 150, and an output circuit 160.

[0065] The pixel region 110 is provided with a plurality of pixels 112 arranged in an array to form a plurality of rows and a plurality of columns. Each pixel 112 is a functional block corresponding to the signal holding circuit 12 of the first to third embodiments and may include a photoelectric conversion unit including a photoelectric conversion element and a pixel signal processing unit that processes a signal output from the photoelectric conversion unit. The number of pixels 112 included in the pixel region 110 is not particularly limited. For example, the pixel region 110 may consist of a plurality of pixels 112 arranged in an array of several thousand rows × several thousand columns, as in a general digital camera. Alternatively, the pixel region 110 may also include a plurality of pixels 112 arranged in one row or one column.

[0066] In each row of the pixel array of the pixel area 110, a control line 114 is arranged, which extends in a first direction (lateral direction in Fig. 11). Each of the control lines 114 is connected to the pixels 112 arranged in the first direction in the corresponding row and forms a common signal line for these pixels 112. The first direction in which the control lines 114 extend may be referred to as the row direction or the horizontal direction. Each of the control lines 114 may include a plurality of signal lines for supplying a variety of types of control signals to the pixels 112. The control line 114 of each row is connected to the vertical drive circuit 120. The control signals supplied from the vertical drive circuit 120 to the pixels 112 may include, for example, the control signals sel, clear, and WRT described in the second embodiment.

[0067] The pixels 112 arranged in each row of the pixel array of pixel region 110 are connected in series in the first direction. An output line 118 is connected to an output node of pixel 112 located at the end of each row in the first direction. The output line 118 of each row is connected to the signal processing circuit 150.

[0068] In each column of the pixel array of the pixel area 110, a signal line 116 is arranged such that it extends in a second direction (vertical direction in Fig. 11) that intersects the first direction. Each of the signal lines 116 is connected to the pixels 112 arranged in the corresponding column in the second direction and forms a common signal line for these pixels 112.

[0069] The second direction in which the signal lines 116 extend may be referred to as the column direction or the vertical direction. The signal line 116 of each column is connected to the clock buffer circuit 140.

[0070] Similar to the clock buffer circuits in the first to third embodiments, the clock buffer circuit 140 has the function of supplying a clock pulse to the pixels 112 in each column at a predetermined timing.

[0071] The signal processing circuit 150 is a functional block that performs predetermined signal processing on the pixel signals output from the output line 118 of each row. The signal processing performed by the signal processing circuit 150 is not particularly limited and includes, for example, correction processing, binning processing, and summed average processing.

[0072] The output circuit 160 includes an external interface circuit and is a functional block for outputting the pixel signals processed by the signal processing device 150 to the outside of the photoelectric conversion device 100. The external interface circuit included in the output circuit 160 is not particularly limited. For example, a SerDes (SERializer / DESerializer) transmission circuit such as an LVDS (Low Voltage Differential Signaling) circuit or an SLVS (Scalable Low Voltage Signaling) circuit can be used as the external interface circuit.

[0073] The control circuit 130 is a control circuit for generating control signals for controlling the operations and timing of the vertical drive circuit 120, the clock buffer circuit 140, and the signal processing circuit 150 and supplying them to the respective functional blocks. At least some of the control signals for controlling the operations and timing of the vertical drive circuit 120, the clock buffer circuit 140, and the signal processing device 150 may be supplied from outside the photoelectric conversion device 100. The control signal supplied from the control circuit 130 to the clock buffer circuit 140 may include the clock signal described in the first to third embodiments.

[0074] As described above, according to the present embodiment, by applying the signal output devices according to the first to third embodiments, it is possible to realize a photoelectric conversion device capable of reading out pixel signals at high speed. [Fifth embodiment]

[0075] A photodetection system according to a fifth embodiment of the present invention is described with reference to Fig. 12 described. Fig. 12 is a block diagram illustrating a schematic configuration of a photodetection system according to the present embodiment. In the present embodiment, a photodetection sensor to which the photoelectric conversion device 100 according to the fourth embodiment is applied is described.

[0076] The photoelectric conversion device 100 described in the fourth embodiment is applicable to various photodetection systems. Examples of applicable photodetection systems include imaging systems such as digital still cameras, digital camcorders, surveillance cameras, copying machines, facsimiles, mobile phones, in-vehicle cameras, observation satellites, and the like. A camera module including an optical system such as a lens and an imaging device is also included in the photodetection system. Fig. 12 shows an example block diagram of a digital still camera as one of them.

[0077] The Fig. The photodetection system 200 shown in Figure 12 includes a photoelectric conversion device 201, a lens 202 that forms an optical image of an object on the photoelectric conversion device 201, a diaphragm 204 that changes the amount of light passing through the lens 202, and a barrier 206 that protects the lens 202. The lens 202 and the diaphragm 204 form an optical system that focuses light onto the photoelectric conversion device 201. The photoelectric conversion device 201 is the photoelectric conversion device 100 described in the fourth embodiment, which converts the optical image formed by the lens 202 into image data.

[0078] The photodetection system 200 further includes a signal processing unit 208 that processes an output signal output from the photoelectric conversion device 201. The signal processing unit 208 generates image data from the digital signal output from the photoelectric conversion device 201. Furthermore, the signal processing unit 208 performs various corrections and compressions as needed and outputs the processed image data. The photoelectric conversion device 201 may include an AD converter unit that generates a digital signal to be processed by the signal processing device 208.The AD conversion unit may be formed on a semiconductor layer (semiconductor substrate) on which the photoelectric conversion element of the photoelectric conversion device 201 is formed, or it may be formed on a semiconductor layer different from the semiconductor layer on which the photoelectric conversion element of the photoelectric conversion device 201 is formed. The signal processing unit 208 may be formed on the same semiconductor layer as the photoelectric conversion device 201.

[0079] The photodetection system 200 further includes a storage unit 210 for temporarily storing image data and an external interface unit (external I / F unit) 212 for communicating with an external computer or the like. Furthermore, the photodetection system 200 includes a storage medium 214, such as a semiconductor memory, for storing or reading image data, and a storage medium control interface unit (storage medium control I / F unit) 216 for storing to or reading from the storage medium 214. The storage medium 214 may be built into the photodetection system 200 or detachable. Communication between the storage medium control I / F unit 216 and the storage medium 214, and communication from the external I / F unit 212, may be wireless.

[0080] The photodetection system 200 further includes a general control / operation unit 218 that performs various calculations and controls the entire digital still camera, and a timing generation unit 220 that outputs various timing signals to the photoelectric conversion device 201 and the signal processing device 208. Here, the timing signal or the like can be input from the outside, and the photodetection system 200 can include at least the photoelectric conversion device 201 and the signal processing unit 208 that processes the output signal output from the photoelectric conversion device 201. The timing generation unit 220 can be attached to the photoelectric conversion device 201.Furthermore, the general control / operation unit 218 and the timing generation unit 220 may be configured to perform part or all of the control functions of the photoelectric conversion device 201.

[0081] The photoelectric conversion device 201 outputs an image signal to the signal processing unit 208. The signal processing unit 208 performs predetermined signal processing on the image signal output from the photoelectric conversion device 201 and outputs the processed image data. The signal processing unit 208 generates an image using the image signal. The signal processing unit 208 may be configured to perform a distance measurement calculation on a signal output from the photoelectric conversion device 201.

[0082] As described above, according to the present embodiment, by configuring the photodetection system using the photoelectric conversion device according to the fourth embodiment, a photodetection system capable of quickly capturing an image can be realized. [Sixth embodiment]

[0083] A distance image sensor according to a sixth embodiment of the present invention is described with reference to Fig. 13 described. Fig. 13 is a block diagram illustrating a schematic configuration of a distance image sensor according to the present embodiment. In the present embodiment, a distance image sensor is described as an example of a photodetection system to which the photoelectric conversion device 100 according to the fourth embodiment is applied.

[0084] As in Fig. As shown in Figure 13, the distance image sensor 300 according to the present embodiment may include an optical system 302, a photoelectric conversion device 304, an image processing circuit 306, a monitor 308, and a memory 310. The distance image sensor 300 receives light (modulated light or pulsed light) emitted from the light source device 320 toward an object 330 and reflected from the surface of the object 330, and acquires a distance image corresponding to the distance to the object 330.

[0085] The optical system 302 includes one or a plurality of lenses and has a function of forming an image of the image light (incident light) from the object 330 on a light receiving surface (sensor unit) of the photoelectric conversion device 304.

[0086] The photoelectric conversion device 304 is the photoelectric conversion device 100 described in the fourth embodiment, which has the function of generating a distance signal indicating the distance to the object 330 based on an image light from the object 330 and supplying the generated distance signal to the image processing circuit 306.

[0087] The image processing circuit 306 has the function of performing image processing to construct a distance image based on the distance signal supplied from the photoelectric conversion device 304.

[0088] The monitor 308 has the function of displaying a distance image (image data) obtained by the image processing in the image processing circuit 306. The memory 310 has the function of storing (recording) a distance image (image data) obtained by the image processing in the image processing circuit 306.

[0089] As described above, according to the present embodiment, by configuring the distance image sensor using the photoelectric conversion device according to the fourth embodiment, it is possible to realize a distance image sensor capable of quickly acquiring a distance image. [Seventh embodiment]

[0090] An endoscopic surgical system according to a seventh embodiment of the present invention is described with reference to Fig. 14 described.

[0091] Fig. 14 is a schematic diagram illustrating a configuration example of an endoscopic surgical system according to the present embodiment. In the present embodiment, an endoscopic surgical system is described as an example of a photodetection system to which the photoelectric conversion device 100 according to the fourth embodiment is applied.

[0092] Fig. 14 illustrates a state in which an operator (surgeon) 460 performs an operation on a patient 472 on a patient bed 470 using an endoscopic surgical system 400.

[0093] As in Fig. As shown in Figure 14, the endoscopic surgical system 400 according to the present embodiment may include an endoscope 410, a surgical tool 420, and a carriage 430 on which various devices for endoscopic surgery are mounted. A CCU (Camera Control Unit) 432, a light source device 434, an input device 436, a processing tool control device 438, a display device 440, and the like may be mounted on the carriage 430.

[0094] The endoscope 410 includes a lens tube 412, into which a portion having a predetermined length from the tip is inserted into the body cavity of the patient 472, and a camera head 414 connected to the lower end or base end of the lens tube 412. Although Fig. While Figure 14 illustrates an endoscope 410 configured as a so-called rigid mirror with a rigid lens tube 412, the endoscope 410 may be configured as a so-called flexible mirror with a flexible lens tube. The endoscope 410 is held in a movable state by an arm 416.

[0095] The tip of the lens tube 412 is provided with an opening into which the objective lens is inserted. A light source device 434 is connected to the endoscope 410, and the light generated by the light source device 434 is guided to the tip of the lens tube 412 through a light guide extending within the lens tube 412 and irradiated through an objective lens onto an observation target in the patient's body cavity 472. Note that the endoscope 410 may be a direct-view mirror, an oblique-view mirror, or a side-view mirror.

[0096] An optical system and a photoelectric conversion device (not shown) are provided inside the camera head 414, and the light reflected from the observation target (observation light) is focused onto the photoelectric conversion device by the optical system.

[0097] The photoelectric conversion device photoelectrically converts the observation light and generates an electrical signal corresponding to the observation light, that is, an image signal corresponding to the observation image. The photoelectric conversion device 100 described in the fourth embodiment can be used as the photoelectric conversion device. The image signal is transmitted to the CCU 432 as RAW data.

[0098] The CCU 432 may be configured by a CPU (central processing unit), a GPU (graphic processing unit), and the like, and integrally controls the operation of the endoscope 410 and the display device 440. Further, the CCU 432 receives an image signal from the camera head 414 and performs various types of image processing for displaying an image based on the image signal, such as development processing (demosaic processing) on ​​the image signal.

[0099] The display device 440 displays an image based on the image signal subjected to image processing by the CCU 432 under the control of the CCU 432.

[0100] The light source device 434 may be configured, for example, by a light source such as an LED (Light Emitting Diode) and supplies irradiation light to the endoscope 410 when photographing an image of a surgical part or the like.

[0101] The input device 436 is an input interface for the endoscopic surgical system 400.

[0102] The user can input various types of information and instructions into the endoscopic surgical system 400 via the input device 436.

[0103] The processing tool controller 438 controls the actuation of the energy processing tool 450 for tissue ablation, incision, blood vessel sealing, or the like.

[0104] The light source device 434 that supplies the irradiation light to the endoscope 410 when imaging the surgical part can be configured, for example, as a white light source in the form of an LED, a laser light source, or a combination thereof. When the white light source is configured by a combination of the RGB laser light sources, the white balance of an acquired image can be adjusted in the light source device 434 because the output intensity and output timing of each color (each wavelength) can be controlled with high precision. Furthermore, in this case, it is also possible to acquire an image corresponding to each of the RGB colors in a time-division manner by irradiating the observation target with laser light from each of the RGB laser light sources in a time-division manner and controlling the driving of the imaging element of the camera head 414 in synchronization with the irradiation time.This method allows a color image to be obtained without the need to provide a color filter in the image sensor.

[0105] Furthermore, the driving of the light source device 434 can be controlled such that the intensity of the light to be output changes every predetermined time. By controlling the driving of the image sensor of the camera head 414 synchronously with the timing of the change in the intensity of the light to capture an image in time-division multiplexing and synthesizing the image, it is possible to generate an image with a high dynamic range without so-called blackened shadows and blown highlights.

[0106] The light source device 434 may be configured to supply light in a predetermined wavelength band corresponding to the special light observation. For example, the special light observation utilizes the wavelength dependence of light absorption in body tissue. Specifically, a predetermined tissue, such as a blood vessel in the superficial layer of a mucous membrane, is photographed with high contrast by irradiating light in a narrow band compared to the irradiation light (i.e., white light) at the time of normal observation. Alternatively, the special light observation may also perform fluorescence observation, in which an image is obtained by fluorescence generated by irradiation with excitation light.In fluorescence observation, a body tissue is irradiated with excitation light to observe the fluorescence of the body tissue, or a body tissue is locally injected with a reagent such as indocyanine green (ICG), and the body tissue is irradiated with excitation light corresponding to a fluorescence wavelength of the reagent to obtain a fluorescence image. The light source device 434 can be configured to be able to provide narrowband light and / or excitation light corresponding to such a specific light observation.

[0107] As described above, according to the present embodiment, by configuring the endoscopic surgical system using the photoelectric conversion device according to the fourth embodiment, it is possible to realize an endoscopic surgical system capable of quickly acquiring an image. [Eighth embodiment]

[0108] A photodetection system and a moving object according to an eighth embodiment of the present invention are described with reference to Fig. 15A to Fig. 17 described. Fig. 15A to Fig. 15C are schematic diagrams showing configuration examples of a movable object according to the present embodiment. Fig. 16 is a block diagram showing a schematic configuration of a photodetection system according to the present embodiment. Fig. 17 is a flowchart illustrating the operation of the photodetection system according to the present embodiment. In the present embodiment, an application example of a vehicle-mounted camera as a photodetection system to which the photoelectric conversion device 100 according to the fourth embodiment is applied is described.

[0109] Fig. 15A to Fig. 15C are schematic diagrams showing a configuration example of a moving object (vehicle system) according to the present embodiment. Fig. 15A to Fig. 15C illustrates a configuration of a vehicle 500 (automobile) as an example of a vehicle system including a photoelectric detection system to which the photoelectric conversion device according to the fourth embodiment is applied. Fig. 15A shows a schematic front view of the vehicle 500, Fig. 15B shows a schematic plan view of the vehicle 500 and Fig. 15C shows a schematic rear view of the vehicle 500. The vehicle 500 includes a pair of photoelectric conversion devices 502 on its front surface. The photoelectric conversion device 502 is the photoelectric conversion device 100 described in the fourth embodiment. The vehicle 500 includes an integrated circuit 503, a warning device 512, and a main control unit 513.

[0110] Fig. 16 is a block diagram showing a configuration example of the photodetection system 501 mounted on the vehicle 500. The photodetection system 501 includes a photoelectric conversion device 502, an image pre-processing unit 515, an integrated circuit 503, and an optical system 514. The photoelectric conversion device 502 is the photoelectric conversion device 100 described in the fourth embodiment. The optical system 514 forms an optical image of an object on the photoelectric conversion device 502. The photoelectric conversion device 502 converts the optical image of the object generated by the optical system 514 into an electrical signal. The image pre-processing unit 515 performs predetermined signal processing on the signal output from the photoelectric conversion device 502.The function of the image pre-processing unit 515 can be integrated into the photoelectric conversion device 502. At least two sets of the optical system 514, the photoelectric conversion device 502, and the image pre-processing unit 515 are provided in the photodetection system 501, and an output from each set of the image pre-processing unit 515 is input to the integrated circuit 503.

[0111] The integrated circuit 503 is an integrated circuit for use in an imaging system application and includes an image processing unit 504, an optical distance measuring unit 506, a parallax calculation unit 507, an object detection unit 508, and an anomaly detection unit 509. The image processing unit 504 processes the image signal output from the image pre-processing unit 515. For example, the image processing unit 504 performs image processing such as development processing and error correction on the output signal of the image pre-processing unit 515. The image processing unit 504 includes a memory 505 that temporarily stores the image signal. The memory 505 can, for example, store the position of a known defective pixel in the photoelectric conversion device 502.

[0112] The optical distance measuring unit 506 focuses and measures the distance of the object. The parallax calculation unit 507 calculates distance measurement information (distance information) from a plurality of image data (parallax images) acquired by the plurality of photoelectric conversion devices 502. Each of the photoelectric conversion devices 502 can be configured to acquire various types of information, such as distance information. The object recognition unit 508 recognizes an object, such as a vehicle, a road, a sign, or a person.

[0113] After detecting an abnormality in the photoelectric conversion device 502, the abnormality detection unit 509 notifies the main control unit 513 of the abnormality.

[0114] The integrated circuit 503 can be implemented using custom hardware, a software module, or a combination thereof. Furthermore, it can be implemented using an FPGA (field programmable gate array), an ASIC (application specific integrated circuit), or the like, or a combination thereof.

[0115] The main control unit 513 integrally controls the operation of the photodetection system 501, the vehicle sensor 510, the control unit 520, and the like. The vehicle 500 need not include the main control unit 513.

[0116] In this case, the photoelectric conversion device 502, the vehicle sensor 510, and the control unit 520 transmit and receive control signals via a communication network. For example, the CAN (Controller Area Network) standard can be used for transmitting and receiving the control signals.

[0117] The integrated circuit 503 has the function of receiving a control signal from the main control unit 513 or transmitting a control signal and a setting value to the photoelectric conversion device 502 through its own control unit.

[0118] The photodetection system 501 is connected to the vehicle sensor 510 and can detect a driving state of the host vehicle, such as a vehicle speed, a yaw rate and a steering angle, an environment outside the host vehicle, and states of other vehicles and obstacles.

[0119] The vehicle sensor 510 is also a distance information acquisition unit that acquires distance information to the object. Furthermore, the photodetection system 501 is connected to a driving support control unit 511 that performs various types of driving support, such as automatic steering, automatic driving, a collision avoidance function, and the like. Specifically, regarding the collision determination function, the driving support control unit 511 estimates a collision with other vehicles or obstacles and determines whether or not there is a collision with other vehicles or obstacles based on the detection results of the photodetection system 501 and the vehicle sensor 510. Thus, evasive control at the time of an estimated collision and the activation of the safety device at the time of the collision are performed.

[0120] The photodetection system 501 is also connected to a warning device 512, which issues a warning to the driver based on the determination result of the collision determination unit. For example, if the determination result of the collision determination unit is that the probability of a collision is high, the main control unit 513 performs vehicle control to avoid a collision and reduce damage by applying a brake, releasing the accelerator pedal, suppressing engine power, or the like. The warning device 512 warns the user by emitting an alarm such as a sound, displaying warning information on a display screen of a vehicle navigation system, a scoreboard, or the like, or vibrating a seatbelt or steering wheel.

[0121] In the present embodiment, an image of the surroundings of the vehicle, e.g., the front or rear, is captured by the photodetection system 501. Fig. 15B illustrates an example of the arrangement of the photodetection system 501 in a case where the photodetection system 501 captures an image in front of the vehicle.

[0122] As described above, the photoelectric conversion devices 502 are arranged at the front of the vehicle 500. In particular, it is preferable that a center line with respect to a forward / backward traveling direction or an external shape (e.g., a vehicle width) of the vehicle 500 be regarded as an axis of symmetry, and two photoelectric conversion devices 502 are arranged line-symmetrically with respect to the axis of symmetry to acquire distance information between the vehicle 500 and an object to be imaged and determine a collision possibility. Furthermore, the photoelectric conversion device 502 is preferably arranged so that it does not obstruct the driver's field of vision when the driver visually recognizes a situation outside the vehicle 500 from the driver's seat. The warning device 512 is preferably arranged so that it easily enters the driver's field of vision.

[0123] Next, an error detection operation of the photoelectric conversion device 502 in the photodetection system 501 will be described with reference to Fig. 17. The error detection operation of the photoelectric device 502 can be carried out according to the Fig. 17, steps S110 to S180 are carried out.

[0124] At step S110, the settings for starting up the photoelectric conversion device 502 are made. That is, the setting for operating the photoelectric conversion device 502 is transmitted from outside the photodetection system 501 (e.g., the main control unit 513) or within the photodetection system 501, and the imaging operation and the defect detection operation of the photoelectric conversion device 502 are started.

[0125] Next, in step S120, pixel signals are acquired from the effective pixels. In step S130, an output value is acquired from the defect detection pixel provided for defect detection. The defect detection pixel includes a photoelectric conversion element in the same manner as the effective pixel. A predetermined voltage is written to the photoelectric conversion element. The defect detection pixel outputs a signal corresponding to the voltage written to the photoelectric conversion element. Note that steps S120 and S130 may be reversed.

[0126] Next, at step S140, classification is performed between the expected output value of the defect detection pixel and the actual output value of the defect detection pixel. As a result of the classification at step S140, if the expected output value matches the actual output value, the process proceeds to step S150, it is determined that the imaging operation is performed normally, and the process proceeds to step S160. At step S160, the pixel signals of the scanning line are transferred to the memory 505 and temporarily stored. Thereafter, the process returns to step S120 to continue the defect detection operation. On the other hand, if the expected output value does not match the actual output value as a result of the classification at step S140, the process proceeds to step S170.In step S170, it is determined that an abnormality in the imaging operation exists, and a warning is notified to the main control unit 513 or the warning device 512. The warning device 512 causes the display unit to indicate that an abnormality has been detected. Thereafter, in step S180, the photoelectric conversion device 502 is stopped, and the operation of the photodetection system 501 is terminated.

[0127] In the present embodiment, an example is described in which the flowchart is looped for each line, but the flowchart may be looped for any number of lines, or the error detection operation may be performed for each frame. The warning message of step S170 may be forwarded to the outside of the vehicle via a wireless network.

[0128] Furthermore, in the present embodiment, the control in which the own vehicle does not collide with other vehicles was described, but the present invention is also applicable to control in which the own vehicle follows another vehicle and performs automatic driving, control in which the vehicle performs automatic driving so as not to slip out of a lane, and the like. Furthermore, the photodetection system 501 is not limited to a vehicle such as the own vehicle, but can also be applied to other moving objects (mobile devices) such as a ship, an aircraft, an industrial robot, or the like. Furthermore, the present invention is not limited to a moving object and can be widely applied to devices that use object recognition, such as intelligent transportation systems (ITS).: “Intelligent Transport Systems”, ITS). [Ninth embodiment]

[0129] A photodetection system according to a ninth embodiment of the present invention is described with reference to Fig. 18A and Fig. 18B. Fig. 18A and Fig. 18B are schematic diagrams illustrating a configuration example of the photodetection system according to the present embodiment. In the present embodiment, an application example of eyeglasses (smart glasses) as the photodetection system to which the photoelectric conversion device 100 according to the fourth embodiment is applied is described.

[0130] Fig. 18A illustrates a pair of glasses 600 (smart glasses) according to an application example. The glasses 600 include lenses 601, a photoelectric conversion device 602, and a control device 603.

[0131] The photoelectric conversion device 602 is the photoelectric conversion device 100 described in the fourth embodiment, which is provided on the glass 601. One photoelectric conversion device 602 or a plurality of photoelectric conversion devices may be provided. When a plurality of photoelectric conversion devices 602 are used, a combination of a plurality of types of photoelectric conversion devices 602 may be used. The arrangement position of the photoelectric conversion device 602 is not limited to Fig. 18A. A display device (not shown) including a light-emitting device such as an OLED (Organic Light Emitting Diode) or an LED (Light Emitting Diode) may be provided on the backside of the glass 601.

[0132] The control device 603 functions as a power supply that supplies power to the photoelectric conversion device 602 and the display device. The control device 603 functions to control the operations of the photoelectric conversion device 602 and the display device. The glass 601 is equipped with an optical system for focusing light onto the photoelectric conversion device 602.

[0133] Fig. 18B illustrates a pair of glasses 610 (smart glasses) according to another application example. The glasses 610 include lenses 611 and a control device 612. A photoelectric conversion device (not shown) corresponding to the photoelectric conversion device 602 and a display device may be attached to the control device 612.

[0134] The glass 611 is equipped with a photoelectric conversion device in the control device 612 and an optical system for projecting light from the display device, and an image is projected onto it. The control device 612 acts as a power supply that supplies power to the photoelectric conversion device and the display device and has the function of controlling the operations of the photoelectric conversion device and the display device.

[0135] The control device 612 may further include a line-of-sight detection unit that detects the wearer's line of sight. In this case, an infrared light emitting unit is provided in the control device 612, and the infrared light emitted by the infrared light emitting unit can be used to detect a line of sight. Specifically, the infrared light emitting unit radiates infrared light toward the eyeball of the user viewing the display image. A captured image of the eyeball is obtained by detecting the reflected light of the infrared light emitted from the eyeball by an imaging unit including a light-receiving element. By providing a reduction unit that reduces the light from the infrared light emitting unit to the display unit in a plan view, it is possible to reduce deterioration in image quality.

[0136] The user's line of sight with respect to the display image can be detected from the captured image of the eyeball obtained by detecting infrared light. Any known technique using the captured image of the eyeball can be applied for line of sight detection. For example, a line of sight detection method based on a Purkinje image due to the reflection of the irradiation light from the cornea can be used. More specifically, a line of sight detection method based on the pupil-corneal reflection method is performed. The user's line of sight can be detected by calculating a line of sight vector representing the orientation (rotation angle) of the eyeball based on the image of the pupil included in the captured image of the eyeball and the Purkinje image using the pupil-corneal reflection method.

[0137] The display device according to the present embodiment may include a photoelectric conversion device having a light-receiving element and may be configured to control a display image based on the user's line-of-sight information from the photoelectric conversion device. Specifically, the display device determines a first visual range that the user is looking at and a second visual range different from the first visual range based on the line-of-sight information. The first visual range and the second visual range may be determined by a control device of the display device or by an external control device. When the determination is made by the external control device, the determination result is transmitted to the display device via communication.In the display area of ​​the display device, the display resolution of the first viewing area can be controlled to be higher than the display resolution of the second viewing area. That is, the resolution of the second viewing area can be lower than the resolution of the first viewing area.

[0138] The display area may include a first display area and a second display area different from the first display area, and a high-priority area may be determined from the first display area and the second display area based on the line-of-sight information. The first display area and the second display area may be determined by a control device of the display device or by an external control device. When the determination is made by the external control device, the determination result is transmitted to the display device via communication. The resolution of the high-priority area may be controlled to be higher than the resolution of the area not belonging to the high-priority area. That is, the resolution of the relatively low-priority area may be lowered.

[0139] It should be noted that AI (artificial intelligence) can be used to determine the first viewing area or the high-priority area. The AI ​​may be a model configured to estimate a line-of-sight angle and a distance to a target object in front of the line of sight from the eyeball image, using the eyeball image and the direction in which the eyeball of the image is actually viewed as teacher data. The AI ​​program may be included in the display device, the photoelectric conversion device, or the external device. If the external device has the information, the information is transmitted to the display device via communication.

[0140] When performing display control based on visual recognition detection, the present invention can be preferably applied to smart glasses that further include a photoelectric conversion device that captures an external image. The smart glasses can display the captured external information in real time. [Modified embodiments]

[0141] The present invention is not limited to the embodiments described above, and various modifications are possible.

[0142] An example in which a part of the configuration of one of the embodiments is added to other embodiments, or an example in which a part of the configuration of one of the embodiments is replaced by some of the configurations of the other embodiments is also an embodiment of the present invention.

[0143] Furthermore, in the first to third embodiments, for the convenience of description, the signal held by each of the plurality of signal holding circuits 12 constituting the signal holding section 10 is a 1-bit signal, but the signal is not necessarily a 1-bit signal and may be a multi-bit signal. For example, it is possible that the pulse signal output from the signal holding circuit 12 is counted, the count value is held in the memory 26, and a plurality of bits of the signal held in the memory 26 are transmitted to the sequential circuit 28.

[0144] Embodiments of the present invention may also be implemented by a computer of a system or apparatus that retrieves and executes computer-executable instructions (e.g., one or more programs) recorded on a storage medium (which may also be more fully referred to as a "non-transitory computer-readable storage medium") to perform the functions of one or more of the embodiments described above, and / or that includes one or more circuits (e.g., (e.g.,an application-specific integrated circuit (ASIC)) for performing the functions of one or more of the above-described embodiments, and be implemented by a method performed by the computer of the system or device, for example, by reading the computer-executable instructions from the storage medium and executing them to perform the functions of one or more of the above-described embodiments and / or by controlling the one or more circuits to perform the functions of one or more of the above-described embodiments. The computer may have one or more processors (e.g., a central processing unit (CPU), a microprocessor unit (MPU)) and may include a network of separate computers or separate processors to read and execute the computer-executable instructions.The computer-executable instructions may be provided to the computer, for example, via a network or a storage medium. The storage medium may include, for example, one or more hard disks, random access memory (RAM), read-only memory (ROM), distributed computing system memory, an optical disc (such as a compact disc (CD), a digital versatile disc (DVD), or a Blu-ray Disc (BD)™), a flash memory device, a memory card, and the like.

[0145] According to the present invention, in a photoelectric conversion device including a plurality of pixel circuits, the time required for reading out pixel signals can be reduced.

[0146] Although the present invention has been described with reference to exemplary embodiments, the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims should be broadly interpreted to include all such modifications and equivalent structures and functions. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 2012-070170 [0002, 0003] JP 2018-186478 [0002, 0003] JP 2012

[0003] JP 070170

[0003]

Claims

[1] Photoelectric conversion device comprising: a multitude of pixel circuits arranged to form a multitude of rows and a multitude of columns; and a control circuit designed to control the multitude of pixel circuits, where each of the multitude of pixel circuits includes the following a signal generation circuit with a photoelectric conversion unit, a memory configured to hold a signal output by the signal generation circuit, and a sequential circuit with a first input node into which a signal is input from the memory, a second input node into which a control signal is input from the control circuit, a third input node and an output node, and wherein the plurality of pixel circuits includes a first pixel circuit and a second pixel circuit arranged in the same row or column, and the output node of the sequential circuit of the first pixel circuit is connected to the third input node of the sequential circuit of the second pixel circuit. [2] Photoelectric conversion device according to claim 1, wherein the plurality of pixel circuits comprises a group of pixel circuits arranged in the same row or column, and the sequential circuits of the pixel circuits forming the group are connected in series to connect the output node and the third input node of the sequential circuits of the pixel circuits adjacent to each other. [3] Photoelectric conversion device according to claim 2, wherein the control circuit is configured to supply the control signal jointly to the pixel circuits of each column of two or more rows, each containing the group of pixel circuits, or to the pixel circuits of each row of two or more columns, each containing the group of pixel circuits. [4] Photoelectric conversion device according to any one of claims 1 to 3, wherein the control circuit is configured to supply the control signal to the pixel circuits arranged in the same row or column via at least a part of a plurality of buffer circuits connected in series, and where the number of buffer circuits through which the control signal supplied to the sequential circuit of the first pixel circuit passes is greater than the number of buffer circuits through which the control signal supplied to the sequential circuit of the second pixel circuit passes. [5] Photoelectric conversion device according to claim 4, wherein each of the plurality of buffer circuits is configured by a non-inverting buffer circuit. [6] Photoelectric conversion device according to claim 4, wherein each of the multitude of buffer circuits is configured by an inverting buffer circuit, and wherein the sequential circuitry of the first pixel circuit is configured to operate synchronously with a rising edge of the control signal, and the sequential circuitry of the second pixel circuit is configured to operate synchronously with a falling edge of the control signal. [7] Photoelectric conversion device according to one of claims 4 to 6, wherein the control circuit further includes a logic circuit which is arranged between an output of the buffer circuit and the second input node of the sequential circuit of the corresponding pixel circuit for each of the plurality of buffer circuits. [8] Photoelectric conversion device according to any one of claims 1 to 7, wherein the plurality of pixel circuits comprises a first group and a second group of pixel circuits arranged in the same row or column, and the sequential circuits of the pixel circuits forming the first group and the second group respectively are connected in series to connect the output node and the third input node of the sequential circuits of the pixel circuits adjacent to each other. [9] Photoelectric conversion device according to claim 8, wherein the pixel circuits forming the first group and the pixel circuits forming the second group are arranged alternately for a predetermined number of each. [10] Photoelectric conversion device according to claim 8 or 9, wherein the control circuit is configured to output each of the signals of the pixel circuits forming the first group and each of the signals of the pixel circuits forming the second group in parallel. [11] Photoelectric conversion device according to claim 8 or 9, where the first group includes the first pixel circuit and the second pixel circuit, and the second group includes a third pixel circuit. wherein the control circuit is configured to supply the control signal to the pixel circuits arranged in the same row or column via at least a part of a plurality of buffer circuits connected in series, wherein the number of buffer circuits through which the control signal supplied to the sequential circuit of the first pixel circuit passes is greater than the number of buffer circuits through which the control signal supplied to the sequential circuit of the second pixel circuit passes, and wherein the number of buffer circuits through which the control signal supplied to the sequential circuit of the second pixel circuit passes is equal to the number of buffer circuits through which the control signal supplied to the sequential circuit of the third pixel circuit passes. [12] Photoelectric conversion device according to one of claims 1 to 11, wherein the pixel circuit in which the output node of the sequential circuit is connected to the third input node of the other pixel circuit is configured to output a hold signal via the other pixel circuit. [13] Photoelectric conversion device according to any one of claims 1 to 12, wherein the sequential circuit is configured to hold the signal input from the memory into the first input node and to output the held signal from the output node. [14] Photoelectric conversion device according to any one of claims 1 to 13, wherein the sequential circuit is configured to hold a signal input from the third input node in response to the control signal input into the second input node and to output the held signal from the output node. [15] Photodetection system, comprising: the photoelectric conversion device according to any one of claims 1 to 14; and a signal processing device configured to process a signal output by the photoelectric conversion device.

Images