Integrated circuit and methods for performing tasks in an integrated circuit

Abstract

The invention relates to an integrated circuit and a method for executing tasks in an integrated circuit. The integrated circuit comprises a central processing unit (CPU) for executing instructions and a scheduling unit (SLA) implemented as a hardware component. The scheduling unit (SLA) is configured to retrieve information about pending tasks and associated timing information, including at least one execution duration (X) and one time limit (D) for each task. The scheduling unit (SLA) is further configured to select a task for the next execution based on the timing information. Finally, the scheduling unit (SLA) is configured to transmit information about the task selected for the next execution to the central processing unit (CPU).

Description

[0001] The invention relates to an integrated circuit and a method for performing tasks in an integrated circuit.

[0002] In integrated circuits used in real-time systems, for example, for real-time processing of sensor signals and / or for executing control functions, various tasks may be pending for execution by a central processing unit or may arrive at different times. It is generally known to use a task scheduling method to select the next task to be executed.

[0003] The presentation “Basic Scheduling Results for Event Driven Systems” by Hermann Härtig, Technische Universität Dresden, WS 2016 / 17 discusses principles of scheduling for real-time systems and examines various strategies.

[0004] However, especially in very simple, reduced hardware environments with only limited computing power and memory, the application of complex scheduling strategies by an operating system can tie up considerable resources.

[0005] Sáez, S. et al., “A Hardware Scheduler for Complex Real-Time Systems” in: ISIE '99. Proceedings of the IEEE International Symposium on Industrial Electronics (Cat. No. 99TH 8465), Bled, Slovenia, 1999, pp. 43–48, addresses the problem of scheduler overhead for scheduling both periodic tasks with hard deadlines and aperiodic tasks with soft deadlines. A hardware architecture is proposed that implements slack stealing in hardware using an optimal algorithm to operate efficiently. The proposed solution is a circuit that behaves like an interrupt controller, taking task utilization and interrupts as inputs and providing an output to inform the CPU which task has the highest priority. This involves selecting the highest-priority task at any given time and finding a set of slack gaps in a real-time computation.

[0006] It can therefore be seen as a task to propose an integrated circuit and a method for executing tasks in an integrated circuit, in which a meaningful sequence of task execution is achieved with the lowest possible computational load.

[0007] With regard to the problem, an integrated circuit according to claim 1 and a method for performing tasks in an integrated circuit according to claim 12 are proposed. Dependent claims relate to advantageous embodiments of the invention.

[0008] The integrated circuit according to the invention comprises at least one central unit and a scheduling unit designed as a hardware component of the integrated circuit.

[0009] It should be noted that terms such as "task" and "scheduling", as well as the technical terms for numerous components, properties and procedures of and in integrated circuits or microprocessor systems, are used as English technical terms that have also been adopted into German technical language.

[0010] An integrated circuit can be any type of circuit that has a central processing unit for executing instructions, i.e., it is programmable. For example, an integrated circuit can be a microprocessor, microprocessor system, signal processor, system-on-chip (SoC), ASIC, or—preferably—an FPGA.

[0011] The central processing unit (CPU) is designed to execute instructions. It can be a type of CPU suitable for the specific environment and application, for example, comprising at least one or more processor cores. A RISC CPU is preferred, and an ARM CPU is particularly preferred.

[0012] The integrated circuit can have one or more central processing units (CPUs), with a preferred application being hardware environments with very limited resources, especially with only one CPU with only one processor core.

[0013] Preferably, the integrated circuit includes further modules and units, for example volatile memory (RAM), permanent memory (flash, ROM), input / output units (interfaces) for external modules and devices and / or one or more buses for functionally connecting modules of the integrated circuit, for example a system bus, address bus, data bus, and / or control bus.

[0014] In the preferred implementation of the integrated circuit as an FPGA, a logic module consisting of programmable or programmed logic elements with a programmable or programmed interconnect structure is further preferably present. The central processing unit can be built from the logic elements (soft core) or provided as a separate hardware unit (hard core).

[0015] Preferably, one, several or all of the aforementioned assemblies of the integrated circuit can be arranged on a common die or chip and / or within a common housing or package.

[0016] According to the invention, one of the assemblies of the integrated circuit is a scheduling unit designed as a hardware component. The scheduling unit is configured to schedule the tasks pending execution, i.e., to select a task for the next execution at a given time and to transmit information about which task is to be executed next to the central processing unit.

[0017] According to the invention, the scheduling unit is configured to retrieve information about tasks pending execution and time information associated with these tasks, to select a task for the next execution based on the time information, and to transmit information about the task selected for the next execution to the central unit.

[0018] Information about pending tasks can be retrieved locally within the scheduling unit and / or from a separate integrated circuit module via a data connection, such as a bus. Preferably, the information is not retrieved from the central processing unit (CPU) to reduce its workload.

[0019] Preferably, at least one initial retrieval of information about pending tasks occurs during the first system startup, or at every system restart or reset. Subsequent retrievals can then occur during normal operation. However, it is also possible to forgo further retrievals and perform only a single retrieval at system (re)start.

[0020] Information about pending tasks can be retrieved once or repeatedly during the operation of the integrated circuit, for example, regularly or at irregular intervals, by the scheduling unit. A special case is recurring tasks, i.e., tasks that are scheduled for execution multiple times in succession, for example, periodically (i.e., with a constant frequency) or with a variable frequency, which is predetermined, for example, by a calculation rule or a table. An example of a recurring task would be querying a sensor, which should occur at least every 5 ms. For recurring tasks, the information preferably also includes the repetition frequency, e.g., the periodicity. In these cases, a single transmission of the information for one or more recurring tasks may be sufficient to provide the scheduling unit with all the data for these recurring tasks for subsequent operation.Accordingly, for individual, multiple, or all tasks, it is unnecessary to retrieve individual pieces of information about recurring tasks before each execution or at specific points during runtime. For example, it may be sufficient if information about recurring tasks is available once at system startup.

[0021] The data or information about tasks pending execution can preferably be stored in the scheduling unit itself, or alternatively in a separate storage module, which can be connected to the scheduling unit via a bus, for example. In both cases, the scheduling unit can retrieve the necessary information or data.

[0022] The time information assigned to each task includes at least the task's execution duration and a deadline. The task's execution duration can be the total time from start to finish, or, in the case of a partially executed task, the remaining execution time. The deadline specifies the time by which the task must be completed. The time information can be specified in any unit of time, such as microseconds, or in an equivalent unit like clock cycles. In addition to the aforementioned time information, further information or data can be retrieved for all or at least a majority of tasks, such as release time, priority, required resources, etc.

[0023] Based on the available information, the scheduling unit can schedule the tasks to be executed, ensuring compliance with the specified time constraints wherever possible. An example of a favorable scheduling strategy, preferably implemented by the scheduling unit, is discussed below.

[0024] In this way, the integrated circuit can execute the pending tasks in a favorable sequence, adhering to time constraints as far as possible, thus ensuring compliance with real-time operation requirements. Offloading the scheduling to a separate hardware component has the advantage of avoiding additional load on the central processing unit from calculations required for scheduling, and ideally also preventing any load on memory and / or bus modules.

[0025] According to the invention, the scheduling unit is designed to store lock variables for managing resources that are usable by different tasks (shared resources). Such shared resources can be, for example, registers, memory areas, bus segments, or hardware components such as interfaces. If, to ensure consistency, it is necessary to prevent a second task from accessing a shared resource while a first task is accessing it, a lock variable can be assigned to the shared resource. Before each access, especially a write access to such a shared resource by a task, it must first be checked whether the lock variable indicates a lock or whether the shared resource is signaled as free. A free shared resource can then be locked by the accessing task by setting the lock variable.

[0026] The state of the locking variable, as well as any additional information such as the specification of the locking task, etc., can be stored, for example, in the scheduling unit itself and / or in a separate memory (RAM) that the scheduling unit can access.

[0027] According to the invention, the scheduling unit is further designed to evaluate the locking variables when selecting a task for the next execution and to take into account whether a task needs access to a currently locked shared resource.

[0028] Preferably, the scheduling unit can be further configured to store at least one lock variable, one lock owner task, and one dynamic priority for each resource. As explained in more detail below, this information can be used to regulate access to potentially shared resources using the priority ceiling and / or priority inheritance protocols.

[0029] The inventive method according to claim 12 for executing tasks in an integrated circuit provides that a scheduling unit, designed as a hardware component of the integrated circuit, retrieves information about pending tasks and associated time information, including at least an execution duration and a time limit for each task. Based on the time information, the scheduling unit selects a task for the next execution and transmits information about this selected task to a central processing unit of the integrated circuit. The scheduling unit stores lock variables for managing shared resources that can be used by different tasks. When selecting a task for the next execution, the lock variables are evaluated, and it is taken into account whether a task requires access to a currently locked shared resource.

[0030] According to a preferred embodiment of the invention, the integrated circuit preferably comprises an interrupt controller for processing interrupts and controlling the central processing unit (CPU). Preferably, the interrupt controller can be an NVIC (Nested Vector Interrupt Controller), particularly preferably one conforming to the ARM specification. The interrupt controller can be configured to process interrupts of various types with different priorities. Preferably, the interrupt controller and the CPU are tightly coupled, particularly directly, i.e., not via a bus. The interrupt controller preferably includes memory capabilities such as registers and enables stacked / nested interrupts.

[0031] Preferably, communication between the scheduling unit and the central processing unit (CPU) occurs via the interrupt controller. To transmit information about the task selected for next execution, the scheduling unit preferably triggers an interrupt to inform the interrupt controller that a task has been selected for execution. Information about which task has been selected for execution can be passed, for example, via a register or in another manner.

[0032] Preferably, the interrupt controller is designed to process interrupts according to their respective priorities. Interrupts can originate from various sources within the integrated circuit, such as separate components like a controller, a timer, etc., or from an external component like a sensor. For example, at least one hardware component of the integrated circuit and / or an interface for an external hardware component can be connected to the interrupt controller to trigger hardware interrupts. Furthermore, it is preferred that the hardware interrupts have a higher priority than the interrupts triggered by the scheduling unit, which are also referred to here as software interrupts.

[0033] The scheduling strategy used to select the next task for execution preferably considers remaining availability time (slack time). Preferably, the scheduling unit is designed to select the next task for execution by determining the slack time for each task. The slack time is preferably calculated as the remaining time until the time limit (i.e., the time remaining from the current time) by subtracting the execution time (or remaining execution time) of the respective task. The slack time is an important indicator of whether a task is at risk of not completing before the specified time limit, thus necessitating its immediate execution.

[0034] The preferred scheduling strategy involves assigning a dynamic priority to each task based on its calculated slack time. The shorter the slack time, the higher the dynamic priority. The task with the highest priority, i.e., the shortest slack time, is then selected for execution.

[0035] The integrated circuit with the scheduling unit and the central processing unit can allow or perform various types of scheduling, including in particular preemptive scheduling, in which running tasks can be interrupted to execute another task on the same central processing unit. However, within the limited hardware environment focused on this invention, cooperative, non-preemptive scheduling is preferred, so that the additional overhead associated with storing the environment of interrupted (preempted) tasks can be avoided.

[0036] According to a preferred embodiment of the invention, the integrated circuit is an FPGA or comprises one. The scheduling unit is preferably formed as a programmed logic assembly of the FPGA.

[0037] Embodiments of the invention are described in more detail below with reference to the drawings. The drawings show: Fig. 1 a schematic representation of the system architecture of an integrated circuit with a central processing unit, an interrupt controller and a scheduling unit; Fig. 2 a schematic representation of the system architecture of the scheduling unit Fig. 1; Fig. 3 a schematic representation of an operating system architecture with the scheduling unit from Fig. 1, Fig. 2; Fig. 4 A schematic representation of the connection of components of the integrated circuit to a system bus.

[0038] The in Fig. A schematically represented integrated circuit 10 according to one embodiment is an FPGA with a configurable logic module and a hardware central processing unit, which is hereinafter referred to as the CPU by reference numeral. In the preferred embodiment, the CPU is an ARM M0 core.

[0039] The integrated circuit 10 is part of a system that provides real-time control of external hardware components. Specifically, as explained below, the integrated circuit units are designed to perform control functions in real time and process sensor input values ​​via an analog-to-digital converter in real time.

[0040] In this embodiment, the hardware environment implemented in the integrated circuit is equipped with particularly limited resources and has very little memory (in one example implementation, only 6 kB RAM and 32 kB flash memory). There is only a single CPU with a single core. Task execution is cooperative; that is, running tasks are not preempted, but switching to other tasks is only possible after a task has finished or when the CPU is actively released from it.

[0041] Directly coupled to the CPU is an interrupt controller, which will be referred to below as NVIC, consistent with its reference symbol. In the preferred embodiment, it is a Nested Vector Interrupt Controller according to the ARM specification. The NVIC processes interrupts 12 and 14 and controls the CPU accordingly. According to the ARM specification, the NVIC can process a multitude of interrupts, each with its own priority. The NVIC has an interrupt table 16 in which the interrupts and their priorities are stored.

[0042] In the illustrated embodiment, hardware interrupts 12 are triggered by integrated circuit units such as a pulse modulation controller (PWM) and an analog-to-digital converter (ADC). Software interrupts 14 are triggered by a scheduling unit or Schedule Logic Accelerator, which is hereinafter referred to as SLA, in accordance with its reference numeral.

[0043] The SLA is a hardware unit implemented in the programmable logic module of the FPGA 10 as a programmed structure of configurable logic blocks. The SLA processes 18 pieces of information about pending tasks as input data, as well as information from the CPU about the state of resources. This information can be transmitted, for example, by the real-time operating system.

[0044] In applications where one, several, or all tasks are recurring, information about these recurring tasks is transmitted at system startup. This includes the repetition frequency or a time limit (e.g., execute at least every 10ms) as well as the execution duration.

[0045] The SLA schedules the pending tasks, selects the next task to be executed, and generates software interrupts 14 as output, which transmit information about the task selected for next execution to the NVIC.

[0046] The SLA is, as in Fig. 4 schematically depicted, as are other components of the integrated circuit, here for example, besides the CPU, a clock generator CLK, a memory unit and a memory controller MC connected to a system bus SB, via which the SLA can, for example, directly access the memory unit.

[0047] As in Fig. As shown in Figure 2, the SLA comprises a scheduling logic 20 and a priority inheritance logic 22.

[0048] The scheduling logic 20 processes the information about pending tasks obtained from the input data 18. This includes, for example, a release time, at which the task is added to a list of pending tasks, an execution duration X, i.e., the time the task needs to run on the CPU, and a deadline D, by which the task must be completed. This can be written, for example, as T1: (0, 2, 4) for a task with a release time of 0, an execution duration of 2 ms, and a deadline of 4 ms.

[0049] Several scheduling strategies are generally known and described, for example, in the presentation "Basic Scheduling Results for Event Driven Systems" by Hermann Härtig, Technical University of Dresden, Winter Semester 2016 / 17. In the preferred embodiment, the SLA is designed to apply a Least Slack Time First strategy, in which, at the current time t, a slack time is determined for each pending task as the remaining time until the time limit is reached, subtracting the execution time X, i.e., slack time = D - x - t. The tasks are then prioritized in reverse order of their slack time; that is, the task with the shortest slack time is given the highest priority and selected for execution first.

[0050] The SLA stores information about pending tasks locally in a scheduling table and / or accesses this information in memory via the system bus SB and applies the Least Slack Time First strategy. After selecting a task for the next execution, a software interrupt 14 is triggered and transmitted to the NVIC.

[0051] In this system, various software interrupts are assigned to individual tasks. This means that, depending on the type of software interrupt (e.g., its number), the CPU receives information about which task to execute next. The memory unit stores the tasks themselves, as well as a table mapping the software interrupts to the tasks. Therefore, when a specific software interrupt is triggered, the CPU has all the necessary information to execute the assigned task. Each interrupt triggered by the SLA activates an interrupt handler routine within the CPU, which then executes the assigned task.

[0052] In alternative implementations, information about which task is to be executed next and where it is stored can also be passed, for example, via a register or in a separate, reserved memory area of ​​the storage unit. The SLA has access to the system bus and can thus store and / or retrieve information from the storage unit, particularly from a memory area reserved there. This is especially useful if the SLA does not have its own (or sufficient) internal memory or cannot manage it itself.

[0053] Additionally, the SLA manages lock variables (locks) in a lock variable table (24) via the Priority Inheritance logic. Each lock variable is assigned to a shared hardware resource, which should only be accessible to one task at a time. Before a task accesses such a shared resource, it requests the resource, and the corresponding lock variable is checked. If the variable is free (value = 0 in the lock variable table (24)), the lock is set, and the value 1 is set in the corresponding entry of the lock variable table. The requesting task is recorded as the owner of the lock variable in the lock variable table (24).

[0054] To avoid the problem of a possible priority inversion (i.e., a higher-priority task can be slowed down because a lower-priority task blocks a needed lock variable, especially if the lower-priority task does not execute because a medium-priority task is preferred), the SLA uses the Priority Ceiling Protocol, where the priority of the listed owner task is temporarily raised when a higher-priority task requests the blocked shared resource.

[0055] Fig.Figure 3 shows the architecture in a layered model, including the scheduling unit SLA. At the hardware level (HW) are the CPU (e.g., ARM M0, M4, M23, M33), the NVIC, and the SLA. The hardware abstraction layer (OS-HAL) contains standard interfaces (OsA). The real-time operating system (RTOS), located at the operating system layer (OS), communicates with the NVIC and the SLA, as well as with external application components (motor control application MOT-C, ultrasonic sensor application US-C, optical sensor application OP-C) at the application level.

[0056] It should be noted that the integrated circuit shown and described above represents only one embodiment and that different embodiments are possible. For example, the SLA may only include a scheduling logic 20 and omit a priority inheritance logic 22. While the SLA described above is used only in a significantly reduced hardware environment with little memory and only one CPU, such an SLA can also be advantageous for more extensive environments, e.g., for systems with multiple CPUs and / or in the context of preemptive scheduling. Reference symbol list 10 Integrated circuit, FPGA 12 Hardware interrupts 14 Software Interrupts 16 Interrupt Table 18 Input data to SLA 20 Scheduling Logic 22 Priority Inheritance Logic 24 Locking Variable Table 26 Tasks X Task execution time The time barrier SLA Scheduling Unit CPU Central Processing Unit NIVC Interrupt Controller PWM pulse modulation control ADC Analog-to-Digital Converter MOT-C application for engine control US-C application ultrasonic sensor OP-C application optical sensor OS operating system level OS-API Operating system API (program interface) RTOS Real-time operating system OS-HAL Hardware Abstraction Layer of the Operating System OSA standard interfaces HW Hardware CLK clock generator Memory MC Memory Controller SB Systembus

Claims

[1] Integrated circuit, with - a central processing unit (CPU) for executing instructions, - and a scheduling unit (SLA) designed as a hardware component, wherein the scheduling unit (SLA) is designed to - To retrieve information about pending tasks and associated time information, including at least an execution duration (X) and a time limit (D) for each task, - to select a task for the next execution based on the time information, - and to transmit information to the central processing unit (CPU) about the task selected for next execution, - where the scheduling unit (SLA) is further trained to store lock variables for managing shared resources that can be used by different tasks and, when selecting a task for the next execution, to evaluate the lock variables and consider whether a task needs access to a currently locked shared resource. [2] Integrated circuit according to claim 1, wherein - the information about tasks pending execution includes a repetition cycle for at least one task. [3] Integrated circuit according to claim 1 or 2, wherein - an interrupt controller (NVIC) is provided for processing interrupts (12, 14) and for controlling the central processing unit (CPU), - and the Scheduling Unit (SLA) is trained to trigger an interrupt (14) to inform the Interrupt Controller (NVIC) that a task has been selected for execution. [4] Integrated circuit according to claim 3, wherein - the interrupt controller (NVIC) is designed to process interrupts (12, 14) according to a respective priority, - and wherein at least one hardware component (Pwm, Adc) of the integrated circuit and / or a connection for an external hardware component for triggering hardware interrupts (12) is connected to the interrupt controller (NVIC), - where hardware interrupts (12) have a higher priority than interrupts (14) triggered by the scheduling unit (SLA). [5] Integrated circuit according to claim 4, wherein - a connection for an external sensor is provided for triggering a hardware interrupt (12). [6] Integrated circuit according to one of the preceding claims, wherein - the scheduling unit (SLA) is designed to select the task to be executed next by determining a slack time for each task, - where the slack time is determined as the period until the time limit (D) after subtracting an execution time (X). [7] Integrated circuit according to claim 6, wherein - A dynamic priority is set for each task based on the determined slack time, with the dynamic priority being higher the shorter the slack time. - and the task with the highest dynamic priority is selected for the next execution. [8] Integrated circuit according to one of the preceding claims, wherein - the scheduling unit (SLA) is designed to store at least one lock variable, one lock owner task, and one dynamic priority for each shared resource. [9] Integrated circuit according to one of the preceding claims, wherein - the Scheduling Unit (SLA) and the Central Processing Unit (CPU) are designed to perform cooperative, non-preemptive scheduling. [10] Integrated circuit according to one of the preceding claims, wherein - the integrated circuit has only a single central processing unit (CPU) for executing instructions. [11] Integrated circuit according to one of the preceding claims, wherein - the scheduling unit (SLA) is formed as a programmed logic structure of an FPGA. [12] Method for performing tasks in an integrated circuit, wherein - by a scheduling unit (SLA) designed as a hardware component of the integrated circuit, - Information about pending tasks and associated time information can be retrieved, including at least an execution duration (X) and a time limit (D) for each task, - and based on the time information, a task is selected for the next execution, - and information about the task selected for next execution is transmitted to a central processing unit (CPU) of the integrated circuit, - and lock variables are stored to manage shared resources that can be used by different tasks. - and when selecting a task for the next execution, the lock variables are evaluated and consideration is given to whether a task needs access to a currently locked shared resource.

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