METHOD FOR CREATING AN OPTICAL PACKAGE

Abstract

A method for forming an optical package is provided. The method includes forming a structured hard mask on the surface of a semiconductor wafer. The structured hard mask comprises a plurality of wells that define the positions of cavities to be formed in the semiconductor wafer. Additionally, the method includes forming a photoresist structure on the surface of the semiconductor wafer within the plurality of wells. The size of the surface area covered by the photoresist structure in each well depends on the position of the well on the semiconductor wafer. The method further includes performing a first etching process. In the first etching process, the semiconductor wafer is etched in the wells at positions not covered by the photoresist structure.Additionally, the process includes removing the photoresist structures after the first etching process and performing a second etching process after the removal of the photoresist structures. In the second etching process, the semiconductor wafer is etched in the depressions to form the cavities by deposition of structures formed in the first etching process.

Description

Area

[0001] This disclosure relates to the formation of optical packages. In particular, examples in this disclosure relate to methods for forming an optical package. background

[0002] Wafer-plane glass blowing is a cost-effective method for fabricating optical wafer-plane packages for microelectromechanical systems (MEMS), such as laser beam scanners. A silicon wafer is patterned using deep reactive ion etching (DRIE) to create cavities that are typically elliptical or circular in shape with diameters of a few millimeters and depths of a few hundred micrometers. The patterned silicon wafer is irreversibly bonded to a glass wafer under controlled conditions. The bonded wafer stack is heated in a furnace process to temperatures near the glass's softening point. At these elevated temperatures, the glass viscosity decreases, and the pressure of the gas encapsulated in the cavities increases. Dome-shaped glass structures are formed over the cavities.By either opening the cavities in the silicon wafer or completely removing the silicon wafer from the glass wafer and performing another wafer bonding process, the dome structures act as an optical wafer-plane package for MEMS structures.

[0003] The depths of the DRIE cavities vary considerably across the wafer. This variation in uniformity is typically tool / equipment-related (e.g., chamber geometry, showerhead configuration, fixture configuration with respect to biasing). An increase in cavity depth at the wafer edge compared to the wafer center is typically observed. With the increased cavity volume associated with the increased depth, the final height of the blown dome structures also increases by a similar relative amount from the wafer center to the edge. The dome height distribution causes collisions within manufacturing tools during subsequent processing steps. Furthermore, the dome height affects the optical properties of the package. To minimize optical aberrations, the dome's center of curvature at the vertex should be equal to the distance of the dome vertex to the MEMS mirror surface.Distributing the dome heights across a wafer essentially violates this condition for a large number of devices. This violation leads to a significant yield loss.

[0004] Therefore, there may be a need for improved imaging of optical packages. Summary

[0005] This need is met by the subject matter of the independent claims. Advantageous embodiments are addressed by the dependent claims.

[0006] According to a first aspect, the present disclosure provides a method for forming an optical package. The method comprises forming a structured hard mask on the surface of a semiconductor wafer. The structured hard mask includes a plurality of wells that define the positions of cavities to be formed in the semiconductor wafer. Additionally, the method comprises forming a photoresist structure on the surface of the semiconductor wafer within the plurality of wells. The size of the surface area covered by the photoresist structure in each well depends on the position of the well on the semiconductor wafer. The method further comprises performing a first etching process. In the first etching process, the semiconductor wafer is etched in the wells at positions not covered by the photoresist structure.Additionally, the process includes removing the photoresist structures after the first etching process and performing a second etching process after the removal of the photoresist structures. In the second etching process, the semiconductor wafer is etched in the depressions to form the cavities by deposition of structures formed in the first etching process.

[0007] According to a second aspect, the present disclosure provides a further method for forming an optical package. The method comprises forming a structured masking layer on the surface of a semiconductor wafer. The structured masking layer comprises a plurality of depressions that define the positions of cavities to be formed in the semiconductor wafer. Additionally, the method comprises performing a first etching process. In the first etching process, the semiconductor wafer is etched in the plurality of depressions to form cavities in the surface of the semiconductor wafer. The method includes removing the structured masking layer. Furthermore, the method comprises forming a photoresist structure after removing the structured masking layer. The photoresist structure partially covers the surface of the semiconductor wafer in the cavities.The size of the surface area covered by the photoresist structure in each cavity depends on the cavity's position on the semiconductor wafer. The process also includes a second etching process. In this second process, the semiconductor wafer is etched in areas not covered by the photoresist structure within the cavities to create the cavities.

[0008] By varying the size of the photoresist structures in the process according to the first aspect, and by varying the size of the surface area covered by the photoresist structure in the respective cavity in the process according to the second aspect, the methods compensate for potential etch depth variations across the semiconductor wafer, particularly from the center to the edge of the wafer, resulting in more uniform cavity depths. The methods enable the achievement of more uniform cavity depths across the wafer, which is advantageous for the consistent performance of the optical components packaged in these cavities. Consequently, the yield can be increased. Overall, the methods enable the creation of well-defined cavities in semiconductor wafers, which is beneficial for high-precision optical packages used in various technological applications. Brief description of the characters

[0009] The following are some examples of devices and / or methods, described solely by way of example and with reference to the accompanying figures, in which the following applies: Fig. Figure 1 illustrates a flowchart of an example of a first procedure for forming an optical package; Fig. Figure 2 illustrates a semiconductor wafer during various stages of a first implementation variant of the first method for forming an optical package; Fig. Figure 3 illustrates a semiconductor wafer during various stages of a second implementation variant of the first method for forming an optical package; Fig. Figure 4 illustrates an example of a semiconductor wafer with formed cavities; Fig. Figure 5 illustrates the formation of dome-shaped structures; Fig. Figure 6 illustrates a comparison of the variation in the relative volumes of the cavities across the semiconductor wafer between the first method and a conventional method; Fig. Figure 7 illustrates a flowchart of an example of a second method for forming an optical package; and Fig. Figure 8 illustrates a semiconductor wafer during various stages of the second process for forming an optical package. Detailed description

[0010] Some examples are now described in more detail with reference to the accompanying figures. However, other possible examples are not limited to the features of these detailed embodiments. Other examples may exhibit modifications of the features, as well as equivalents and alternatives to the features. Furthermore, the terminology used herein to describe certain examples should not be considered restrictive for other possible examples.

[0011] The same or similar reference symbols throughout the description of the figures refer to identical or similar elements and / or features, which may be identical or implemented in a modified form, while providing the same or a similar function. Furthermore, the thickness of lines, layers, and / or areas in the figures may be exaggerated for clarity.

[0012] When two elements A and B are combined using "or," this is to be understood as revealing all possible combinations, i.e., only A, only B, and A and B, unless explicitly defined otherwise in a specific case. As an alternative formulation for the same combinations, "at least one of A and B" or "A and / or B" can be used. This applies accordingly to combinations of more than two elements.

[0013] When a singular form, e.g., "ein, eine" and "der, die, das", is used, and the use of only a single element is neither explicitly nor implicitly defined as mandatory, subsequent examples may also use multiple elements to implement the same function. If a function is subsequently described as being implemented using multiple elements, further examples may implement the same function using a single element or a single processing entity.It is further understood that the terms "include", "comprehensive", "exhibit" and / or "exhibit" when used describe the presence of the specified features, integers, steps, operations, processes, elements, components and / or a group thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, processes, elements, components and / or a group thereof.

[0014] Fig. Figure 1 illustrates a flowchart of a procedure 100 for forming an optical package.

[0015] Method 100 comprises forming 102 a structured hard mask on the surface of a semiconductor wafer. The structured hard mask includes a plurality of depressions that define the positions of cavities to be formed in the semiconductor wafer.

[0016] The semiconductor wafer is a thin, typically circular piece of semiconductor material that serves as a basic platform. The semiconductor material can be, for example, silicon. The diameter of the semiconductor wafer can be, for example, between approximately 100 mm and approximately 300 mm, in particular 200 mm. The thickness of the semiconductor wafer can be, for example, between 400 µm and 1000 µm, in particular 600 µm. It should be noted that the present disclosure is not limited to the exemplary material and dimensions of the semiconductor wafer mentioned above. Other suitable semiconductor materials and dimensions can also be used.

[0017] The structured hard mask is a material layer used to pattern the cavities on the substrate. The cavities are recessed areas (depressions, voids) that are to be formed in the semiconductor wafer. The multiple depressions indicate where the cavities are to be formed (or will be formed) in the wafer. For example, the structured hard mask can be made of a durable material such as dielectric materials like silicon nitride (Si3N4) or silicon dioxide (SiO2), or metals like titanium or tungsten, such that the structured hard mask is not photosensitive like a photoresist. Forming the structured hard mask can, for example,The process involves depositing hard mask material onto the semiconductor wafer, applying a photoresist layer to the hard mask material, structuring the photoresist using a photomask that incorporates the desired pattern defining where the cavities are to be formed, developing the photoresist to remove the exposed or unexposed areas (depending on the type of photoresist) and reveal the underlying hard mask material pattern, etching away the exposed hard mask material to transfer the pattern from the photoresist to the hard mask material, and stripping away the remaining photoresist, leaving the structured hard mask on the semiconductor wafer. The thickness of the structured hard mask can be, for example, between 0.5 µm and 10 µm, particularly 2.5 µm.

[0018] Additionally, the process involves forming 100 photoresist structures on the surface of the semiconductor wafer within the majority of wells. The size of the surface area covered by each photoresist structure in a given well depends on the position of that well on the semiconductor wafer. In other words, photoresist structures are formed on the surface of the semiconductor wafer within the wells of the hard mask. The size of each photoresist structure varies based on its position on the wafer. The photoresist structures are made of a photosensitive material that undergoes chemical changes when exposed to light. For example, positive or negative photoresist can be used. The formation of each photoresist structure can, for example,The process includes applying photoresist material, soft-firing the applied photoresist material, structuring the photoresist material using a photomask that includes the desired pattern defining where the photoresist structures are to be formed, and developing the photoresist to remove the exposed or unexposed areas of the photoresist (depending on the type of photoresist) and expose the areas of the semiconductor wafer to be etched.

[0019] Method 100 further comprises performing a first etching process (first etching process). In the first etching process, the semiconductor wafer is etched in the wells at positions not covered by the photoresist structure. The photoresist structures define the areas of the semiconductor wafer that are exposed through the wells in the structured hard mask and are protected during the first etching process. Areas of the semiconductor wafer surface not covered by the structured hard mask and the photoresist structures are etched to a specified depth in the first etching process. For example, DRIE can be used to etch the semiconductor wafer in the first etching process.

[0020] Additionally, the process includes removing 108 of the photoresist structures after the first etching process. The photoresist structures can be removed using various techniques, such as chemical peeling, plasma ashing, or wet chemical etching. After removing 108 of the photoresist structures, the areas of the semiconductor wafer that were protected during the first etching process are exposed.

[0021] Procedure 100 comprises performing a second etching process (second etching process) after removing the photoresist structures. In the second etching process, the semiconductor wafer is etched in the depressions to form the cavities by deposition of structures formed in the first etching process. In other words, the cavities in the semiconductor wafer are further etched during the second etching process based on the initial structures formed during the first etching. For example, DRIE can be used in the second etching process to etch the semiconductor wafer.

[0022] By varying the size of the photoresist structures, Method 100 compensates for potential etch depth variations across the semiconductor wafer, particularly from the center (central region) to the edge (perimeter or outermost part) of the wafer, resulting in more uniform cavity depths. Cavity depth refers to the vertical distance from the surface of the wafer to the bottom of the etched cavities. Method 100 enables the achievement of more uniform cavity depths across the wafer, which is beneficial for the consistent performance of optical devices packaged in these cavities. For example, the cavity depths can differ by less than 15% or less than 10% across the wafer.In particular, the depths of the cavities can vary by less than 15% or less than 10%, especially from the center to the edge of the semiconductor wafer. The cavity depths can be at least 20%, 25%, or 30% and at most 75%, 80%, or 85% of the thickness of the semiconductor wafer. For example, if the thickness of the semiconductor wafer is between 400 µm and 1000 µm, the cavity depths can be between 100 and 600 µm, particularly 400 µm, with a depth variation of less than 15% or less than 10% across the semiconductor wafer (especially from the center to the edge). Overall, Method 100 enables the creation of well-defined cavities in semiconductor wafers, which is advantageous for high-precision optical packages used in various technological applications.

[0023] The majority of the cavities in the structured hard mask can have the same dimensions. In other words, all the cavities can have uniform dimensions with respect to shape, size, and depth. Accordingly, the cavities can be designed with uniform dimensions in terms of shape and size. For example, the majority of the cavities can have a circular or elliptical shape. The present disclosure is not limited to this, however. The cavities can generally have any shape. The lateral extent (i.e., the horizontal dimension or width) of each cavity in the semiconductor wafer can be between 3 mm and 10 mm, in particular 5 mm.

[0024] According to examples in the present disclosure, the size of the surface area covered by the respective photoresist structure in the respective well can vary from the center to the edge of the semiconductor wafer. In other words, the size of the photoresist-covered area is not uniform across the semiconductor wafer. Instead, it changes progressively across the semiconductor wafer (e.g., from the center of the semiconductor wafer to its edge). In particular, the size of the surface area covered by the respective photoresist structure in the respective well can vary from the center to the edge of the semiconductor wafer to compensate for the etch depth variation from the center to the edge of the semiconductor wafer in the first and second etching processes. By varying the photoresist coverage, the method compensates for 100 variations in etch depth that naturally occur from the center to the edge of the semiconductor wafer.This ensures more uniform cavity depths across the entire semiconductor wafer. The size of the surface area covered by the respective photoresist structure in each cavity can increase, for example, from the center to the edge of the semiconductor wafer. In other words, the surface area covered by the photoresist structures in the cavities increases as one moves from the center of the semiconductor wafer to its edge. This variation typically compensates for faster etch rates at the semiconductor wafer edge, thus ensuring uniform cavity depths.

[0025] Further details of procedure 100 are given below with reference to Fig. 2 and Fig. Figure 3 describes a semiconductor wafer during different stages of two implementation variants of Method 100.

[0026] Fig. Figure 2 illustrates a semiconductor wafer 200 during various stages of a first implementation variant of the process 100. Fig. Figure 2 illustrates a cross-sectional view through one half of the semiconductor wafer 200. The dashed line 201 indicates the center of the semiconductor wafer 200 (with a radial distance R = 0). The other half of the semiconductor wafer 200 is symmetrical and therefore not shown.

[0027] As shown in partial figure (a), the structured hard mask 210 is initially formed on the surface 205 of the semiconductor wafer 200. For the sake of simplicity, the structured hard mask 210 comprises only two depressions 211 and 212. However, it should be noted that the present disclosure is not limited to this. Any number N ≥ 2 of depressions can be formed in the structured hard mask 210. Depression 211 is closer to the center of the semiconductor wafer 200 than depression 212. Depression 212 is closer to the edge 202 of the semiconductor wafer 200 than depression 211. Depressions 211 and 212 have a circular shape and the same dimensions in the example shown. Fig. 2. In particular, the radius r c of both depressions 211 and 212 constant (the same).

[0028] Then, as shown in partial figure (b), a photoresist structure 221, 222 is formed on the surface 201 of the semiconductor wafer 200 in the wells 211 and 212. The photoresist structures 221 and 222 are formed at the boundaries of the wells 211 and 212. The photoresist structures 221 and 222 contact the structured hard mask 210 along their entire respective boundaries. The photoresist structures 221 and 222 do not cover the semiconductor wafer 200 in the centers of the wells 211 and 212. The inner contours of the photoresist structures 221 and 222 have the same shape as the boundaries of the wells 211 and 212. Since the wells 211 and 212 have a circular shape, the photoresist structures 221 and 222 are annular rings in the example shown. Fig. 2.

[0029] As can be seen from partial figure (b), the size of the surface area covered by the respective photoresist structure 221, 222 in the respective well 211, 212 depends on the position of the respective well 211, 212 on the semiconductor wafer 200. In particular, the size of the surface area covered by the respective photoresist structure 221, 222 in the respective well 211, 212 increases from the center to the edge of the semiconductor wafer 200. The photoresist structure 222 covers more of the surface area in well 212 than the photoresist structure 221 covers in well 211.

[0030] The surface area in the respective well 211, 212 that is not covered by the respective photoresist structure 221, 222 decreases from the center to the edge of the semiconductor wafer 200. The surface area A sin the respective depression 211, 212, which is not covered by the respective photoresist structure 221, 222, depends on the radial distance R to the center of the semiconductor wafer 200 and is defined as follows: As(R)=π⋅rs2(R) where r s the radius of the respective surface area A s in the respective depression 211, 212, which is not covered by the respective photoresist structure 221, 222.

[0031] Then, as further shown in subfigure (b), the first etching process is carried out to etch the semiconductor wafer 200 in the cavities 211 and 212 at the central positions not covered by the photoresist structures 221 and 222. For example, DRIE can be used to etch the semiconductor wafer 200 in the first etching process. A first part of each cavity is formed in the first etching process by removing a portion of the semiconductor wafer 200 at the central positions not covered by the photoresist structures 221 and 222. The portions of the semiconductor wafer 200 that are etched away in the first etching process are designated by reference numerals 231 and 232. A cylindrical first partial cavity is formed in each of the cavities 211 and 212 in the first etching process.

[0032] As shown in subfigure (b), the depths of the structures formed in the first etching process are not uniform across the semiconductor wafer 200. The depths of the structures formed in the first etching process depend on the radial distance R from the center of the semiconductor wafer 200. In particular, the depth increases with increasing radial distance R from the center of the semiconductor wafer 200. The structure formed in the center of the depression 212, which is not covered by the photoresist structure 222, is deeper than the structure formed in the center of the depression 211, which is not covered by the photoresist structure 221. This can be expressed as follows: d1(R)=d1,0⋅detch(R) where d1(R) denotes the depth of the structure formed in the first etching process at a specific radial distance R to the center of the semiconductor wafer 200, d 1,0a constant reference depth in the center of the semiconductor wafer (i.e., d 1,0 = d1(R = 0)) denotes and d etch (R) denotes a scaling function that depends on the radial distance R to the center of the semiconductor wafer 200. The value of the scaling function increases with increasing radial distance R to the center of the semiconductor wafer 200.

[0033] Then, after the first etching process, the photoresist structures 221 and 222 are removed. After the removal of the photoresist structures 221 and 222, the second etching process is performed. This is illustrated in subfigure (c). For example, DRIE can be used to etch the semiconductor wafer 200 in the second etching process. In the second etching process, the semiconductor wafer 200 is etched in the wells 211 and 212 to form the cavities by deposition of the structures formed in the first etching process. Accordingly, a second part of each cavity is formed in the second etching process by removing a portion of the semiconductor wafer 200 in the wells 211 and 212. The portions of the semiconductor wafer 200 that are etched away in the second etching process are designated by reference numerals 241 and 242. A cylindrical second partial cavity is formed in each of the recesses 211 and 212 in the second etching process.

[0034] As shown in subfigure (c), the depths of the structures formed in the second etching process are not uniform across the semiconductor wafer 200. The depths of the structures formed in the second etching process depend on the radial distance R to the center of the semiconductor wafer 200. In particular, the depth increases with increasing radial distance R to the center of the semiconductor wafer 200. The structure formed in well 212 is deeper than the structure formed in well 211. This can be expressed as follows: d2(R)=d2,0⋅detch(R) where d2(R) denotes the depth of the structure formed in the second etching process at a specific radial distance R to the center of the semiconductor wafer 200, and d 2,0 a constant reference depth in the center of the semiconductor wafer (i.e., d 2,0 = d2(R = 0)).

[0035] The resulting cavities 251 and 252 are shown in subfigure (d). Cavity 252 is deeper than cavity 251. The volume V of each cavity can be expressed as follows: V=π⋅rs2(R)⋅d1(R)+π⋅rc2⋅d2(R)

[0036] This can be rewritten based on mathematical expressions (3) and (4) as follows: V=π⋅rs2(R)⋅d1.0⋅detch(R)+π⋅rc2⋅d2.0⋅detch(R) V=π⋅detch(R)⋅(rs2(R)⋅d1.0+rc2⋅d2.0) Vπ⋅detch(R)=rs2(R)⋅d1.0+rc2⋅d2.0 Vπ⋅detch(R)−rc2⋅d2,0=rs2(R)⋅d1,0 rs2(R)=1d1.0⋅(Vπ⋅detch(R)−rc2⋅d2.0) rs(R)=1d1.0⋅(Vπ⋅detch(R)−rc2⋅d2.0)

[0037] The parameters V and r c are predefined target parameters. The parameters d 1,0 , d 2,0 and d etch (R) can be measured. Thus, the mathematical expression (10) allows the radius of the respective surface area A to be determined. sto determine in the respective well 211, 212 which is not covered by the respective photoresist structure 221, 222.

[0038] In the example of Fig. 2. The etch depth variation is compensated for by structuring cavities with smaller diameters. The cavity structures formed in the first etching step are radius-dependent. The step-like structure, which in the example of Fig. Etching process 2 creates cavities with varying diameters after the cavities are opened from the back of the wafer. The fact that no structures are released during the opening process can reduce the defect density.

[0039] Fig. Figure 3 illustrates a semiconductor wafer 300 during various stages of an alternative second implementation variant of the process 100. Fig. Figure 3 illustrates a cross-sectional view through one half of the semiconductor wafer 300. The dashed line 301 indicates the center of the semiconductor wafer 300 (with a radial distance R = 0). The other half of the semiconductor wafer 300 is symmetrical and therefore not shown.

[0040] As shown in partial figure (a), the structured hard mask 310 is initially formed on the surface 305 of the semiconductor wafer 300. For the sake of simplicity, the structured hard mask 310 comprises only two depressions 311 and 312. However, it should be noted that the present disclosure is not limited to this. Any number N ≥ 2 of depressions can be formed in the structured hard mask 310. Depression 311 is closer to the center of the semiconductor wafer 300 than depression 312. Depression 312 is closer to the edge 302 of the semiconductor wafer 300 than depression 311. Depressions 311 and 312 have a circular shape and the same dimensions in the example shown. Fig. 3. In particular, the radius r c of both depressions 311 and 312 constant (the same).

[0041] As can be seen from partial figure (b), the size of the surface area covered by the respective photoresist structure 321, 322 in the respective well 311, 312 depends on the position of the respective well 311, 312 on the semiconductor wafer 300. In particular, the size of the surface area covered by the respective photoresist structure 321, 322 in the respective well 311, 312 increases from the center to the edge of the semiconductor wafer 300. The photoresist structure 322 covers more of the surface area in well 312 than the photoresist structure 321 covers in well 311.

[0042] The surface area in the respective well 311, 3212, which is not covered by the respective photoresist structure 321, 322, decreases from the center to the edge of the semiconductor wafer 200. The surface area A pin the respective depression 311, 312, which is not covered by the respective photoresist structure 321, 322, depends on the radial distance R to the center of the semiconductor wafer 200 and is defined as follows: Ap(R)=π⋅(rc2−rp2(R)) where r p denotes the radius of the respective surface area in the respective depression 211, 212, which is covered by the respective photoresist structure 221, 222.

[0043] Then, as further shown in subfigure (b), the first etching process is carried out to etch the semiconductor wafer 300 in the cavities 311 and 312 at the positions in the boundary that are not covered by the photoresist structures 321 and 322. For example, DRIE can be used to etch the semiconductor wafer 300 in the first etching process. A first part of each cavity is formed in the first etching process by removing a portion of the semiconductor wafer 300 at the positions in the boundary that are not covered by the photoresist structures 321 and 322. The portions of the semiconductor wafer 300 that are etched away in the first etching process are designated by reference numerals 331 and 332. An annular first partial cavity is formed in each of the cavities 311 and 312 in the first etching process. The annular first partial cavity encloses a respective column in the middle of each of the depressions 311 and 312.

[0044] As shown in subfigure (b), the depths of the structures formed in the first etching process are not uniform across the semiconductor wafer. The depths of the structures formed in the first etching process depend on the radial distance R to the center of the semiconductor wafer 300. In particular, the depth increases with increasing radial distance R to the center of the semiconductor wafer 300. The ring-shaped structure formed at the boundary of the depression 312, which is not covered by the photoresist structure 322, is deeper than the ring-shaped structure formed at the boundary of the depression 311, which is not covered by the photoresist structure 321. The depths can be expressed analogously to the mathematical expression (2) above.

[0045] Then, after the first etching process, the photoresist structures 321 and 322 are removed. After the removal of the photoresist structures 321 and 322, the second etching process is performed. This is illustrated in subfigure (c). For example, DRIE can be used to etch the semiconductor wafer 300 in the second etching process. In the second etching process, the semiconductor wafer 300 is etched in the wells 311 and 312 to form the cavities by deposition of the structures formed in the first etching process. Accordingly, a second part of each cavity is formed in the second etching process by removing a portion of the semiconductor wafer 300 in the wells 311 and 312. The portions of the semiconductor wafer 200 that are etched away in the second etching process are designated by reference numerals 341 and 342. A cylindrical second partial cavity is formed in each of the recesses 311 and 312 in the second etching process.

[0046] As shown in subfigure (c), the depths of the structures formed in the second etching process are not uniform across the semiconductor wafer 300. The depths of the structures formed in the second etching process depend on the radial distance R to the center of the semiconductor wafer 300. In particular, the depth increases with increasing radial distance R to the center of the semiconductor wafer 300. The structure formed in well 312 is deeper than the structure formed in well 311. The depths can be expressed analogously to the mathematical expression (2) above.

[0047] The resulting cavities 351 and 352 are shown in subfigure (d). Cavity 352 is deeper than cavity 351. The volume V of each cavity can be expressed as follows: V=π⋅(rc2−rp2(R))⋅d1(R)+π⋅rc2⋅d2(R)

[0048] This can be rewritten based on the analogues of mathematical expressions (3) and (4) as follows: V=π⋅(rc2−rp2(R))⋅d1.0⋅detch(R)+π⋅rc2⋅d2.0⋅detch(R) V=π⋅detch(R)⋅((rc2−rp2(R))⋅d1.0+rc2⋅d2.0) Vπ⋅detch(R)=(rc2−rp2(R))⋅d1.0+rc2⋅d2.0 Vπ⋅detch(R)=−rp2(R)⋅d1.0+rc2(d1.0+d2.0) rc2(d1,0+d2,0)−Vπ⋅detch(R)=rp2(R)⋅d1,0 rp2(R)=1d1,0⋅(rc2(d1,0+d2,0)−Vπ⋅detch(R)) rp(R)=1d1,0⋅(rc2(d1,0+d2,0)−Vπ⋅detch(R))

[0049] Like the mathematical expression (10), the mathematical expression (19) makes it possible to determine the radius of the respective surface area in the respective depression 311, 312 that is covered by the respective photoresist structure 321, 322.

[0050] In the example of Fig. 3. A hard mask is used in both etching steps to define the shape of the cavities on the wafer surface. In the first etching step, circular resist points define cylindrical structures at the centers of the circles that are not covered by the hard mask. The radii of these cylinders depend on their position on the wafer according to the spatial dependence of the etch depth d. etch(R) to create cavities that are uniform in volume. After resist removal, the second etching stage lowers the structure created in the first stage. The second stage ensures that the shape of the cavity at the silicon interface, which later defines the shape of the dome structure, is independent of the structure that compensates for spatial etch depth variation. One advantage of using a cylindrical structure at the cavity bottom is that all cavities on the wafer have the same diameter after the cavities are opened from the back of the wafer by wet or dry etching. Furthermore, the orientation of the mask that defines the resist points relative to the circular cavities in the hard mask is not critical.

[0051] A perspective view of a 400 wafer with a plurality of 410 cavities, arranged as above in relation to Fig. 3 described are formed, is in Fig. 4 illustrates.

[0052] With renewed reference to Fig. 2 and Fig. 3 lifts subfigure (d) of each of Fig. 2 and Fig. 3 further states that the process 100 may optionally include the removal 112 of the structured hard mask 210 / 310 after performing the second etching process. The structured hard mask can be removed using various techniques, such as wet chemical etching, dry etching (plasma etching), or a peel-off technique. Removing 112 the hard mask leaves a clean semiconductor wafer surface for subsequent manufacturing steps.

[0053] Exemplary subsequent manufacturing steps of process 100 are described below with regard to Fig. 1 and Fig. 5 described. The process 100 can further comprise forming 114 a bonded wafer stack after removal of the structured hard mask by bonding the semiconductor wafer to a glass wafer. This is exemplified in the left part of Fig. Figure 5 illustrates this. The semiconductor wafer 510 is bonded to a glass wafer 520 to form the bonded wafer stack 500. For simplicity, only a single cavity 515 in the semiconductor wafer 510 is shown. The glass wafer 520 is a thin, typically circular piece of glass material.

[0054] Bonding the semiconductor wafer 510 to the glass wafer 520 can involve, for example, aligning and bonding the semiconductor wafer 510 to the glass wafer 520. Bonding can be achieved using various techniques, such as anodic bonding, adhesive bonding, or thermocompression bonding. This creates a composite wafer stack with the semiconductor wafer 510 on one side and the glass wafer 520 on the other. The glass material can be any type of glass with a coefficient of thermal expansion (CTE) similar to that of the semiconductor wafer 510. For example, the glass material can be sodium-containing glass such as borosilicate glass. The diameter of the glass wafer 520 can be identical to the diameter of the semiconductor wafer 510 (e.g., between approximately 100 mm and approximately 300 mm), but it need not be. The thickness of the glass wafer 520 can be identical to or different from the thickness of the semiconductor wafer 510.It should be noted that the present disclosure is not limited to the exemplary material and dimensions of the glass wafer 520 given above. Other suitable glass materials and dimensions may also be used. The pressure used to bond the semiconductor wafer 510 to the glass wafer 520 may, for example, be between 0 bar and 3 bar, in particular 2 bar. The semiconductor wafer 510 may, for example, be bonded to the glass wafer 520 at a temperature between 300 °C and 500 °C, in particular 330 °C.

[0055] Method 100 can further comprise forming 116 dome-shaped structures in the glass wafer at the cavity locations by subjecting the bonded wafer stack to a furnace process. The dome-shaped structures are convex, meaning they curve outwards, forming a dome shape that protrudes from the surface of the glass wafer and thus the bonded wafer stack. The dome-shaped structures are positioned directly above the cavities in the semiconductor wafer. The size and curvature of each dome-shaped structure correspond to the dimensions of the underlying cavity. This is exemplified in the right part of Fig. Figure 5 illustrates this. In the furnace process, controlled heating causes the glass wafer 510 to soften, increasing the pressure of the gas encapsulated in the cavities, such as cavity 515. The encapsulated gas deforms the softened glass wafer at the positions corresponding to the cavities, such as cavity 515 in the semiconductor wafer 510, to form the dome-shaped structures. An exemplary dome-shaped structure 525 at the position of cavity 515 is shown in Figure 5. Fig. Figure 5 illustrates this. The furnace process can use a temperature between 700 °C and 900 °C, particularly 750 °C.

[0056] Uniform cavity depths across the semiconductor wafer result in more consistent heights of the dome-shaped structures. With more consistent dome heights, the physical dimensions of the optical package fall within tighter specifications. Additionally, optical aberrations introduced by the optical package are reduced and remain within a smaller range. This can increase the yield.

[0057] These dome-shaped structures can act as lenses or protective covers for underlying features, such as MEMS devices or other photonic or optical devices. Two exemplary approaches for further processing of the bonded wafer stack are described below, with reference to... Fig. 1 described.

[0058] According to the first approach, the process can further involve removing the semiconductor wafer from the glass wafer after the formation of the dome-shaped structures. In other words, the two wafers are carefully separated without damaging the dome-shaped structures in the glass wafer. For example, techniques such as chemical etching, mechanical separation, or other processes designed to release the bond without damaging the glass wafer or the dome-shaped structures can be used.

[0059] Method 100 can further include, in the first step, bonding 120 optical MEMS devices to the glass wafer after the semiconductor wafer has been removed from the glass wafer. The dome-shaped structures cover the optical MEMS devices. For example, the optical MEMS devices can be aligned and bonded to the glass wafer. The bonding process ensures precise placement and secure attachment of the optical MEMS devices beneath the dome-shaped structures. The dome-shaped structures provide a robust physical barrier that protects the sensitive optical MEMS devices from mechanical damage and environmental contaminants such as dust or moisture. Furthermore, the dome-shaped structures can act as lenses, focusing light onto or away from the optical MEMS devices, thereby improving their optical performance.

[0060] Forming the dome-shaped structures and bonding the optical MEMS devices in successive steps can standardize the manufacturing process so that it can be easily controlled.

[0061] In the alternative second approach, the process can further include forming 122 openings in the semiconductor wafer at the positions of the cavities after forming the dome-shaped structures. The openings in the semiconductor wafer extend from a second surface of the semiconductor wafer to the cavities. The second surface is opposite the surface of the semiconductor wafer. The openings can be formed, for example, in another etching process (e.g., using DRIE) or by laser drilling such that precise openings are formed in the semiconductor wafer, extending from the second surface (the back side) of the wafer to the preformed cavities.

[0062] Method 100 can further include, in the second approach, bonding 124 optical MEMS devices to the second surface of the semiconductor wafer after the openings in the semiconductor wafer have been formed. The dome-shaped structures cover the optical MEMS devices. For example, the optical MEMS devices can be aligned and bonded to the semiconductor wafer. According to the second approach as well, the dome-shaped structures provide a robust physical barrier that protects the sensitive optical MEMS devices from mechanical damage and environmental contaminants such as dust or moisture. Furthermore, the dome-shaped structures can act as lenses that focus light onto or away from the optical MEMS devices, thereby improving their optical performance.

[0063] The main difference between the first and second approaches lies in the placement and integration of the optical MEMS devices. In the first approach, the optical MEMS devices are bonded to the glass wafer after the semiconductor wafer has been removed, while in the second approach, the optical MEMS devices are bonded to the second surface of the semiconductor wafer through openings extending to the cavities, with the dome-shaped structures in the glass wafer covering these devices.

[0064] Optical MEMS devices can be any type of miniaturized system that combines optical components with microelectromechanical elements. These optical MEMS devices integrate photonic and mechanical functionalities on a microscopic scale to manipulate light and perform various optical functions. For example, optical MEMS devices can be MEMS laser beam scanners. These are miniature devices that use microfabricated mechanical structures to guide and manipulate laser beams (e.g., with high precision). These MEMS laser beam scanners integrate optical components with MEMS technology to achieve precise control over the position, direction, and movement of laser beams for various applications (e.g., light detection and distance measurement, LiDAR (Light Detection and Ranging), or medical imaging).

[0065] As described above, Method 100 enables more uniform cavity depths to be achieved across the semiconductor wafer. This is further demonstrated in the Fig. Figure 600 is highlighted in Figure 6. Figure 600 illustrates a comparison of the variation in the relative volumes of the cavities across the semiconductor wafer between Method 100 and a conventional method. The abscissa represents the distance of each cavity from the center of the semiconductor wafer in arbitrary units. The ordinate represents the relative volume of each cavity.

[0066] Data points 610 represent the relative volumes of cavities formed in a semiconductor wafer according to the method 100 described above. For reference, data points 620 represent the relative volumes of cavities formed in a semiconductor wafer according to a conventional method. The semiconductor wafers are identical for both methods.

[0067] As from Fig. As can be seen in Figure 6, the relative volumes of the cavities vary (differ) less across the semiconductor wafer when formed using Method 100. This is due to the more uniform cavity depths across the semiconductor wafer achieved with Method 100.

[0068] An alternative method 700 for forming a semiconductor package is described below with reference to Fig. 7 described.

[0069] Method 700 comprises forming 702 a structured masking layer on the surface of a semiconductor wafer. The structured masking layer includes a plurality of depressions that define the positions of cavities to be formed in the semiconductor wafer.

[0070] The structured masking layer is a structured material layer applied to the surface of the semiconductor wafer. It is used to structure the cavities to be formed in the semiconductor wafer. For example, the structured masking layer can be a structured hard mask, as used in the procedure described above. Alternatively, the structured masking layer can be a structured photoresist. The structured photoresist is made of a light-sensitive material that undergoes chemical changes when exposed to light. For example, positive or negative photoresist can be used. The structured photoresist can be formed, for example, by spin coating. Forming the structured photoresist by spin coating can, for example,The process includes dispensing (a predefined amount) of liquid photoresist material onto the center of the semiconductor wafer, spinning the semiconductor wafer (e.g., at a rotational speed between 1000 and 6000 revolutions per minute) to distribute the photoresist material evenly over the semiconductor wafer, soft-firing the distributed photoresist material, structuring the photoresist material using a photomask that includes the desired pattern defining where the structured photoresist is to be formed, and developing the photoresist to remove the exposed or unexposed areas of the photoresist (depending on the type of photoresist) and expose the areas of the semiconductor wafer to be etched.

[0071] Method 700 further comprises performing 704 a first etching process (first etching process) after forming the structured masking layer. In the first etching process, the semiconductor wafer is etched in a plurality of pits to form cavities (deepenings, spaces, depressions) in the surface of the semiconductor wafer. The structured masking layer covers the areas of the semiconductor wafer that are protected during the first etching process. Areas of the surface of the semiconductor wafer that are not covered by the structured masking layer are etched in the first etching process to a certain depth such that the cavities in the surface of the semiconductor wafer are formed. For example, DRIE can be used to etch the semiconductor wafer in the first etching process.

[0072] Additionally, the procedure includes removing the structured masking layer after the first etching process. The structured masking layer can be removed using various techniques, such as chemical peeling, plasma ashing, (wet) chemical etching, dry etching (plasma etching), or a peeling technique. After removing the structured masking layer, the areas of the semiconductor wafer that were protected during the first etching process are exposed.

[0073] Method 700 comprises forming a photoresist structure after removing the structured masking layer. The photoresist structure partially covers the surface of the semiconductor wafer within the cavities. The size of the surface area covered by the photoresist structure in each cavity depends on the cavity's position within the semiconductor wafer. In other words, the photoresist structure is applied such that it partially covers the wafer surface within the previously etched cavities. The photoresist structure extends to the boundaries of the cavities. The photoresist structure does not cover the semiconductor wafer in the centers of the cavities. That is, the edges of the cavities are covered (protected) by the photoresist structure, but the central areas remain exposed.For example, the internal contours of the photoresist structure within the cavities can have the same shape as the cavity boundaries. This means that the photoresist pattern within the cavity can closely match the shape of the cavity itself, ensuring precise and consistent coverage. The size of the area covered by the photoresist in each cavity is controlled and varies depending on the cavity size on the wafer. Different cavities can exhibit varying degrees of photoresist coverage.

[0074] The photoresist structure is made from a light-sensitive material that undergoes chemical changes when exposed to light. For example, positive or negative photoresist can be used. The photoresist structure can be formed by spray coating. Forming the photoresist structure by spray coating can involve, for example, spraying liquid photoresist material through a nozzle at controlled pressure onto the surface of the semiconductor wafer, soft-firing the sprayed photoresist material, structuring the photoresist material using a photomask that includes the desired pattern defining where the photoresist structure is to be formed, and developing the photoresist to remove the exposed or unexposed areas (depending on the type of photoresist) and expose the areas of the semiconductor wafer to be etched.

[0075] Procedure 700 comprises performing a second etching process (second etching process) after forming the photoresist structure. In the second etching process, the semiconductor wafer is etched in the cavities at locations not covered by the photoresist structure to form the cavities. In other words, the semiconductor wafer is further etched within the cavities, but only in the areas exposed by the photoresist structure. This additional etching deepens the cavities to form the final cavities. The photoresist acts as a protective mask during this second etching process, preventing certain areas within the cavities from being further etched. For example, DRIE can be used to etch the semiconductor wafer in the second etching process.

[0076] By varying the size of the surface area covered by the photoresist structure in each cavity, Method 700 compensates for potential etch depth variations across the semiconductor wafer, particularly from the center to the edge, resulting in more uniform cavity depths. Like Method 100, Method 700 enables the achievement of more uniform cavity depths across the semiconductor wafer, which is advantageous for the consistent performance of optical devices packaged in these cavities. For example, the cavity depths across the semiconductor wafer can differ by less than 15% or less than 10%. Specifically, the cavity depths from the center to the edge of the semiconductor wafer can differ by less than 15% or less than 10%.The cavity depths can be at least 20%, 25%, or 30% and at most 75%, 80%, or 85% of the semiconductor wafer thickness. For example, if the semiconductor wafer thickness is between 400 µm and 1000 µm, the cavity depths can be between 100 and 600 µm, particularly 400 µm, with a depth variation of less than 15% or less than 10% across the semiconductor wafer (especially from the center to the edge). Overall, Method 700 enables the creation of well-defined cavities in semiconductor wafers, which is advantageous for high-precision optical packages used in various technological applications.

[0077] The photoresist structure can cover other parts of the semiconductor wafer. For example, the photoresist structure can be formed to cover the sidewalls of cavities. The sidewalls are the vertical or inclined surfaces of the cavities that were etched into the semiconductor wafer in the first etching process. When the sidewalls of the cavities are covered with photoresist (i.e., by the photoresist structure), the surfaces are protected during the second etching process. Accordingly, only the bottom of the cavities is etched further, not the sides. This helps to maintain the shape and integrity of the cavity sidewalls.

[0078] Alternatively or additionally, the photoresist structure can be formed to cover the surface of the semiconductor wafer in areas that are covered by the structured masking layer in the first etching process. Essentially, this means that the photoresist structure is applied to areas of the semiconductor wafer that were not etched in the first step. This helps to protect these regions from unwanted etching.

[0079] Analogous to what is described above for Method 100, the plurality of depressions in the structured masking layer can have the same dimensions. In other words, all depressions can have uniform dimensions with respect to shape, size, and depth. Accordingly, the cavities can be formed with uniform dimensions with respect to shape and size. For example, the plurality of depressions can have a circular or elliptical shape. The present disclosure is not limited to this, however. The depressions can generally have any shape. The lateral extent (i.e., the horizontal dimension or width) of each cavity in the semiconductor wafer can be between 3 mm and 10 mm, in particular 5 mm.

[0080] According to examples in the present disclosure, the size of the surface area covered by the photoresist structure in the respective cavity can vary from the center to the edge of the semiconductor wafer. In other words, the size of the photoresist-covered area is not uniform across the semiconductor wafer. Instead, it changes progressively across the semiconductor wafer (e.g., from the center of the semiconductor wafer to its edge). In particular, the size of the surface area covered by the photoresist structure in the respective cavity can vary from the center to the edge of the semiconductor wafer to compensate for the etch depth variation from the center to the edge of the semiconductor wafer in the first and second etching processes. By varying the photoresist coverage, Method 700 compensates, analogously to Method 100, for variations in etch depth that naturally occur from the center to the edge of the semiconductor wafer.This ensures more uniform cavity depths across the entire semiconductor wafer. The size of the surface area covered by the photoresist structure in each cavity can increase, for example, from the center to the edge of the semiconductor wafer. In other words, the size of the surface area covered by the photoresist structure in each cavity increases as one moves from the center of the semiconductor wafer to its edge. This variation typically compensates for faster etch rates at the semiconductor wafer edge, thus ensuring uniform cavity depths.

[0081] Further details of procedure 700 are given below with reference to Fig. Figure 8 describes a semiconductor wafer 800 during various stages of the process 700. Fig. Figure 8 illustrates a cross-sectional view through the semiconductor wafer 800. The dashed line 801 indicates the center of the semiconductor wafer 800 (with a radial distance R = 0).

[0082] As shown in partial figure (a), the structured masking layer 810 is initially formed on the surface 805 of the semiconductor wafer 800. For the sake of simplicity, the structured masking layer 810 comprises only four depressions 811, ..., 814. However, it should be noted that the present disclosure is not limited to this. Any number K ≥ 2 of depressions can be formed in the structured masking layer 810. The wells 811 and 813 are located in the center of the semiconductor wafer 800. Well 811 is closer to the center of the semiconductor wafer 800 than well 812. Well 812 is closer to the edge 802 of the semiconductor wafer 800 than well 811. Similarly, well 813 is closer to the center of the semiconductor wafer 800 than well 814. Wells 811, ..., 814 have a circular shape and the same dimensions in the example of Fig. 8. In particular, the radius of the depressions 811, ..., 814 is constant (the same).

[0083] Then, as shown in sub-figure (b), the first etching process is carried out to etch the semiconductor wafer 800 in the wells 811, ..., 814, i.e., at the positions not covered by the structured masking layer 810. For example, DRIE can be used to etch the semiconductor wafer 800 in the first etching process. A cavity is formed in the first etching process as the first part of the respective cavity by removing a portion of the semiconductor wafer 800 in the wells 811, ..., 814. The portions of the semiconductor wafer 800 that are etched away in the first etching process are designated by reference numerals 821, ..., 824. A cylindrical first partial cavity is formed in each of the wells 811, ..., 814 in the first etching process.

[0084] As shown in subfigure (b), the depths of the cavities 821, ..., 824 formed in the first etching process are not uniform across the semiconductor wafer 800. The depths of the cavities 821, ..., 824 formed in the first etching process depend on the radial distance R to the center of the semiconductor wafer 800. In particular, the depth increases with increasing radial distance R to the center of the semiconductor wafer 800. The cavity 822 formed in the depression 812 is deeper than the cavity 821 formed in the depression 811. Similarly, the cavity 824 formed in the depression 814 is deeper than the cavity 823 formed in the depression 813. Since the depressions 811 and 813 are positioned at the same radial distance to the center of the semiconductor wafer 800, the depths of the cavities 821 and 823 are essentially identical.Similarly, since the depressions 812 and 814 are positioned at the same radial distance to the center of the semiconductor wafer 800, the depths of the cavities 822 and 824 are essentially identical.

[0085] Then, after the first etching process, the structured masking layer 810 is removed. This is illustrated in subfigure (c).

[0086] After removal of the structured masking layer 810, a photoresist structure 830 is formed. This is illustrated in subfigure (d). The photoresist structure 830 covers the surface 805 of the semiconductor wafer 805 at positions that were covered by the structured masking layer 810 in the first etching process. In other words, the photoresist structure 830 covers the parts of the surface 805 of the semiconductor wafer 805 where the cavities 821, ..., 824 are not formed.

[0087] The photoresist structure 830 partially covers the surface 805 of the semiconductor wafer 800 in the cavities 821, ..., 824. The photoresist structure 830 covers the boundaries of the cavities 821, ..., 824. In other words, the photoresist structure 830 extends to the boundaries of the cavities 821, ..., 824. The photoresist structure 830 also covers the side walls of the cavities 821, ..., 824. The photoresist structure 830 does not cover the semiconductor wafer 800 in the centers of the cavities 821, ..., 824. The inner contours of the photoresist structure 830 in the cavities 821, ..., 824 have the same shape as the boundaries of the cavities 821, ..., 824. Since the depressions 811, ..., 814 and thus the cavities 821, ..., 824 have a circular shape in the example of Fig. 8 exhibits the photoresist structure 830 forming ring-shaped rings in the cavities 821, ..., 824.

[0088] As can be seen from partial figure (d), the size of the surface area covered by the photoresist structure 830 in the respective cavity 821, ..., 824 depends on the position of the respective cavity 821, ..., 824 in the semiconductor wafer 800. In particular, the size of the surface area covered by the respective photoresist structure 830 in the respective cavity 821, ..., 824 increases from the center to the edge of the semiconductor wafer 800. The photoresist structure 830 covers more of the surface area in cavity 822 than in cavity 821. Similarly, the photoresist structure 830 covers more of the surface area in cavity 824 than in cavity 823.Since the depressions 811 and 813, and thus the cavities 821 and 823, are positioned at the same radial distance from the center of the semiconductor wafer 800, the surface areas covered by the photoresist structure 830 in cavities 821 and 823 are essentially identical. Similarly, since the depressions 812 and 814, and thus the cavities 822 and 824, are positioned at the same radial distance from the center of the semiconductor wafer 800, the surface areas covered by the photoresist structure 830 in cavities 822 and 824 are essentially identical.

[0089] As illustrated in subfigure (e), the second etching process is carried out after the formation of the photoresist structure 830. For example, DRIE can be used to etch the semiconductor wafer 800 in the second etching process. In the second etching process, the semiconductor wafer 800 is etched in cavities 821, ..., 824 at positions not covered by the photoresist structure 830. Accordingly, a second part of each cavity is formed in the second etching process by removing a portion of the semiconductor wafer 800 from the cavities 821, ..., 824. The portions of the semiconductor wafer 800 that are etched away in the second etching process are designated by reference numerals 841, ..., 844. A cylindrical second partial cavity is formed in each of the cavities 811, ..., 814 in the second etching process.

[0090] As shown in subfigure (e), the depths of the structures (second subcavities) formed in the second etching process are not uniform across the semiconductor wafer 800. The depths of the structures formed in the second etching process depend on the radial distance R to the center of the semiconductor wafer 800. In particular, the depth increases with increasing radial distance R to the center of the semiconductor wafer 800.

[0091] The resulting cavities 851, ..., 854 are shown in subfigure (f). Cavity 852 is deeper than cavity 851. Similarly, cavity 854 is deeper than cavity 853. Since depressions 811 and 813, and thus cavities 821 and 823, are positioned at the same radial distance from the center of the semiconductor wafer 800, the depths of cavities 851 and 853 are essentially identical. Likewise, since depressions 812 and 814, and thus cavities 822 and 824, are positioned at the same radial distance from the center of the semiconductor wafer 800, the depths of cavities 852 and 854 are essentially identical.

[0092] In the example of Fig. 8. The etch depth variation is compensated for by structuring cavities with smaller diameters. The cavity structures formed in the second etching step are radius-dependent. The step-like structure, which in the example of Fig. Etching process 8 creates cavities with varying diameters after the cavities are opened from the back of the wafer. The fact that no structures are released during the opening process can reduce the defect density.

[0093] Analogous to the removal of the structured hard masks 210 / 310 in the examples of Fig. 2 and Fig. 3 lifts subfigure (f) of Fig. Figure 8 states that the process 700 may optionally further include the removal 712 of the photoresist structure 830 after performing the second etching process. The photoresist structure 830 can be removed using various techniques, such as chemical peeling, plasma ashing, or wet chemical etching. The removal 712 of the photoresist structure 830 leaves a clean semiconductor wafer surface for subsequent manufacturing steps.

[0094] For example, the method 700 can further form 714 a bonded wafer stack after removal of the photoresist structure by bonding the semiconductor wafer to a glass wafer and Forming 716 dome-shaped structures in the glass wafer at the cavity positions by subjecting the bonded wafer stack to a furnace process. This can be done analogously to what is described above for process 100.

[0095] Method 700 may include further features of Method 100 described above. For example, Method 700 may further include removing 718 the semiconductor wafer from the glass wafer after forming the dome-shaped structures and bonding 720 optical MEMS devices to the glass wafer after removing the semiconductor wafer from the glass wafer. The dome-shaped structures cover the optical MEMS devices. Alternatively, Method 700 may further include forming 722 openings in the semiconductor wafer at the positions of the cavities after forming the dome-shaped structures. The openings in the semiconductor wafer extend from a second surface of the semiconductor wafer to the cavities. The second surface is opposite the surface of the semiconductor wafer. Method 700 may then additionally include bonding 724 optical MEMS devices to the second surface of the semiconductor wafer after forming the openings in the semiconductor wafer.The dome-shaped structures cover the optical MEMS devices. Details of these optional additional features of Method 700 are given above with reference to Method 100.

[0096] The aspects and features described in connection with one of the previous examples can also be combined with one or more of the further examples to replace an identical or similar feature of that further example or to additionally introduce the features into the further example.

[0097] It is further understood that the disclosure of several steps, processes, operations, or functions disclosed in the description or claims should not be interpreted as necessarily occurring in the described sequence, unless explicitly stated in a specific case or required for technical reasons. Therefore, the preceding description does not restrict the execution of several steps or functions to a specific sequence. Furthermore, in other examples, a single step, function, process, or operation may comprise and / or be broken down into several sub-steps, functions, processes, or operations.

[0098] If certain aspects related to a device or system have been described, these aspects should also be understood as a description of the corresponding procedure. For example, a block, device, or functional aspect of the device or system may correspond to a feature, such as a process step, of the corresponding procedure. Similarly, aspects described in connection with a procedure should also be understood as a description of a corresponding block, element, property, or functional feature of a corresponding device or system.

[0099] The following claims are hereby included in the detailed description, each claim being a separate example. It should also be noted that, although a dependent claim may refer to a specific combination with one or more other claims, other examples may include a combination of the dependent claim with the subject matter of any other dependent or independent claim. Such combinations are hereby explicitly proposed unless it is stated in a specific case that a particular combination is not intended. Furthermore, features of a claim for any other independent claim are also intended to be included, even if that claim is not directly defined as dependent on that other independent claim.

Claims

[1] A method (100) for forming an optical package, wherein the method (100) comprises: Forming (102) a structured hard mask on a surface of a semiconductor wafer, wherein the structured hard mask comprises a plurality of depressions that define positions of cavities to be formed in the semiconductor wafer; Forming (104) a respective photoresist structure on the surface of the semiconductor wafer in the plurality of wells, wherein the size of the surface area covered by the respective photoresist structure in the respective well depends on the position of the respective well on the semiconductor wafer; Performing (106) a first etching process, wherein in the first etching process the semiconductor wafer is etched in the depressions at positions not covered by the photoresist structure; Removal (108) of the photoresist structures after performing the first etching process; and Performing (110) a second etching process after removing the photoresist structures, wherein in the second etching process the semiconductor wafer is etched in the depressions to form the cavities by sinking structures formed in the first etching process. [2] The method (100) according to claim 1, wherein the size of the surface area covered by the respective photoresist structure in the respective depression varies from a center to an edge of the semiconductor wafer. [3] The method (100) according to claim 1 or claim 2, wherein the size of the surface area covered by the respective photoresist structure in the respective depression varies from a center to an edge of the semiconductor wafer to compensate for etch depth variation from the center to the edge of the semiconductor wafer in the first and second etching processes. [4] The method (100) according to any one of claims 1 to 3, wherein the size of the surface area covered by the respective photoresist structure in the respective depression increases from a center to an edge of the semiconductor wafer. [5] The method (100) according to any one of claims 1 to 4, wherein the photoresist structures have the same shape as the depressions. [6] The method (100) according to any one of claims 1 to 5, wherein the photoresist structures are formed in the centers of the depressions. [7] The method (100) according to any one of claims 1 to 6, wherein the photoresist structures are spaced apart from the boundaries of the depressions formed by the structured hard mask. [8] The method (100) according to any one of claims 1 to 4, wherein the photoresist structures are formed at the boundaries of the wells and contact the structured hard mask along the entire respective boundary, and wherein the photoresist structures do not cover the semiconductor wafer in the centers of the wells. [9] The method (100) according to claim 8, wherein the inner contours of the photoresist structures have the same shape as the boundaries of the depressions. [10] The method (100) according to any one of claims 1 to 9, further comprising: Removal (112) of the structured hard mask after performing the second etching process. [11] The method (100) according to claim 10, further comprising: Forming (114) a bonded wafer stack after removal of the structured hard mask by bonding the semiconductor wafer to a glass wafer; and Forming (116) dome-shaped structures in the glass wafer at the positions of the cavities by subjecting the bonded wafer stack to a furnace process. [12] A method (700) for forming an optical package, wherein the method (700) comprises: Forming (702) a structured masking layer on a surface of a semiconductor wafer, wherein the structured masking layer comprises a plurality of recesses, define the positions of cavities to be formed in the semiconductor wafer; Performing (704) a first etching process, wherein in the first etching process the semiconductor wafer is etched in the plurality of depressions to form cavities in the surface of the semiconductor wafer; Removal (706) of the structured masking layer; Forming (708) a photoresist structure after removal of the structured masking layer, wherein the photoresist structure partially covers the surface of the semiconductor wafer in the cavities, wherein the size of the surface area covered by the photoresist structure in the respective cavity depends on the position of the respective cavity in the semiconductor wafer; and Performing (710) a second etching process, wherein in the second etching process the semiconductor wafer is etched in the cavities at positions not covered by the photoresist structure to form the cavities. [13] The method (700) according to claim 12, wherein the structured masking layer is a structured hard mask. [14] The method (700) according to claim 12, wherein the structured masking layer is a structured photoresist. [15] The method (700) according to claim 14, wherein the structured photoresist is formed by spin coating. [16] The method (700) according to any one of claims 12 to 15, wherein the photoresist structure is formed to cover side walls of the cavities. [17] The method (700) according to any one of claims 12 to 15, wherein the photoresist structure is formed to cover the surface of the semiconductor wafer at positions covered by the structured masking layer in the first etching process. [18] The method (700) according to any one of claims 12 to 17, wherein the photoresist structure is formed by spray coating. [19] The method (700) according to any one of claims 12 to 18, wherein the size of the surface area covered by the photoresist structure in the respective cavity varies from a center to an edge of the semiconductor wafer. [20] The method (700) according to any one of claims 12 to 19, wherein the size of the surface area covered by the photoresist structure in the respective cavity varies from a center to an edge of the semiconductor wafer to compensate for etch depth variation from the center to the edge of the semiconductor wafer in the first and second etching processes. [21] The method (700) according to any one of claims 12 to 20, wherein the size of the surface area covered by the photoresist structure in the respective cavity increases from a center to an edge of the semiconductor wafer. [22] The method (700) according to any one of claims 12 to 21, wherein the photoresist structure extends to the boundaries of the cavities, and wherein the photoresist structure does not cover the semiconductor wafer in the centers of the cavities. [23] The method (700) according to claim 22, wherein the inner contours of the photoresist structure in the cavities have the same shape as the boundaries of the cavities. [24] The method (700) according to any one of claims 12 to 23, further comprising: Removal (712) of the photoresist structure after performing the second etching process. [25] The method (700) according to claim 24, further comprising: Forming (714) a bonded wafer stack after removal of the photoresist structure by bonding the semiconductor wafer to a glass wafer; and Forming (716) dome-shaped structures in the glass wafer at the positions of the cavities by subjecting the bonded wafer stack to a furnace process. [26] The method (100, 700) according to claim 11 or claim 25, further comprising: Removal (118, 718) of the semiconductor wafer from the glass wafer after forming the dome-shaped structures; and Bonding (120, 720) of optical MEMS devices to the glass wafer after removal of the semiconductor wafer from the glass wafer, wherein the dome-shaped structures cover the optical MEMS devices. [27] The method (100, 700) according to claim 11 or claim 25, further comprising: Forming (122, 722) openings in the semiconductor wafer at the positions of the cavities after forming the dome-shaped structures, wherein the openings in the semiconductor wafer extend from a second surface of the semiconductor wafer to the cavities, and wherein the second surface is opposite the surface of the semiconductor wafer; and Bonding (124, 724) of optical MEMS devices to the second surface of the semiconductor wafer after forming the openings in the semiconductor wafer, wherein the dome-shaped structures cover the optical MEMS devices. [28] The method (100, 700) according to claim 26 or claim 27, wherein the optical MEMS devices are MEMS laser beam scanning devices. [29] The method (100, 700) according to any one of claims 1 to 28, wherein deep reactive ion etching is used in the first and second etching process to etch the semiconductor wafer. [30] The method (100, 700) according to any one of claims 1 to 29, wherein the plurality of depressions have the same dimensions. [31] The method (100, 700) according to any one of claims 1 to 30, wherein the majority of depressions have a circular or elliptical shape. [32] The method (100, 700) according to any one of claims 1 to 31, wherein the depths of the cavities are at least 25% and at most 80% of the thickness of the semiconductor wafer. [33] The method (100, 700) according to any one of claims 1 to 32, wherein the depths of the cavities differ from each other by less than 15% across the semiconductor wafer. [34] The method (100, 700) according to any one of claims 1 to 33, wherein the lateral extent of the respective cavity in the semiconductor wafer is at most 10 mm.

Images