Semiconductor chip and semiconductor device

Abstract

A semiconductor chip comprises a semiconductor substrate, which has a first surface and a semiconductor element formed on the semiconductor substrate, and a plurality of pads that are electrically connected to the semiconductor element and arranged on the first surface with a space between them. The plurality of pads includes a first control pad and a second control pad. In a top view, the second control pad has a sub-region with a different shape, the outer form of which differs from that of the first control pad.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This non-provisional application is based on Japanese Patent Application No. 2023-162904 filed with the Japan Patent Office on September 26, 2023, the entire contents of which are hereby incorporated by reference. BACKGROUND OF THE INVENTIONField of the invention

[0002] The present disclosure relates to a semiconductor chip and a semiconductor device. Description of the background technology

[0003] A semiconductor device is known that comprises a singulated semiconductor chip and a mounting substrate on which the semiconductor chip is mounted. An alignment mark for positioning the semiconductor chip in the semiconductor device is arranged on the semiconductor chip.

[0004] In general, alignment marks on a semiconductor chip are formed as two or more patterns in a region different from a wiring region such as a pad electrically connected to an external component (see, for example, WO 02 / 082540). SUMMARY OF THE INVENTION

[0005] In order to properly position a semiconductor chip in a semiconductor device, it is necessary to form a relatively large alignment mark having high detectability on the semiconductor chip.

[0006] Consequently, it has been difficult to achieve downsizing of a semiconductor chip in the case where an alignment mark having high visibility is formed in a region other than a wiring region such as a pad as mentioned above.

[0007] In particular, the miniaturization of a power semiconductor chip made of silicon carbide (SiC) or the like has been advanced in recent years, and it has been difficult to form an alignment mark having high detectability in such a power semiconductor chip.

[0008] A primary object of the present disclosure is to provide a semiconductor chip and a semiconductor device that enable downsizing while incorporating an alignment mark having high detectability.

[0009] A semiconductor chip according to the present disclosure includes a semiconductor substrate having a first surface and a semiconductor element formed on the semiconductor substrate, and a plurality of pads electrically connected to the semiconductor element and arranged on the first surface with a gap established therebetween. The plurality of pads includes a first pad and a second pad. In plan view, the second pad has a portion with a different shape, the outer shape of which is different from that of the first pad.

[0010] The above-described and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a plan view for explaining a semiconductor chip according to Embodiment 1. Fig. 2 is a partially enlarged plan view for explaining the semiconductor chip according to Embodiment 1. Fig. 3 is a plan view for explaining a semiconductor device according to Embodiment 1. Fig. 4 is a plan view for explaining a first variant of the semiconductor device according to Embodiment 1. Fig. 5 is a partially enlarged plan view for explaining a second variant of the semiconductor chip according to Embodiment 1. Fig. 6 is a partially enlarged plan view for explaining a third variation of the semiconductor chip according to Embodiment 1. Fig. 7 is a partially enlarged plan view for explaining a fourth variation of the semiconductor chip according to Embodiment 1. Fig. 8 is a plan view for explaining a semiconductor chip according to Embodiment 2. Fig. 9 is a plan view for explaining a semiconductor chip according to Embodiment 3. Fig. 10 is a plan view for explaining a semiconductor chip according to Embodiment 4. Fig. 11 is a along arrows XI-XI in Fig. 10 partially enlarged cross-sectional view. DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0011] Embodiments of the present disclosure will be described below with reference to the drawings. The same or corresponding portions are denoted by the same reference numerals hereinafter, and overlapping descriptions will not be repeated. Embodiment 1<Konfiguration eines Halbleiter-Chips>

[0012] As in Fig. 1 and Fig. 2, a semiconductor chip 1 according to an embodiment 1 comprises a semiconductor substrate 2 and a plurality of contact points or pads 3.

[0013] The semiconductor substrate 2 has a first surface 2A and a second surface 2B opposite the first surface 2A. A plan view as provided herein is based on a view from a direction orthogonal to the first surface 2A. The semiconductor substrate 2 has a given element configuration formed on the semiconductor substrate having the first surface 2A and the second surface 2B. In plan view, the outer shape of the semiconductor substrate 2 is, for example, a rectangular shape. The semiconductor substrate 2 contains, for example, silicon carbide (SiC) as a base material.

[0014] A semiconductor element is, for example, a vertical semiconductor element. The semiconductor element is, for example, a power semiconductor element. The semiconductor element is, for example, a switching element such as an insulated-gate bipolar transistor (IGBT), a gate-commutated turn-off thyristor (GCT), or a metal-oxide-semiconductor field-effect transistor (MOSFET). The semiconductor element is arranged, for example, to control a main current flowing to a main pad 4 according to a signal input to a first control pad 6 and a second control pad 7, which are described below.

[0015] In plan view, the outer shape of the semiconductor substrate 2 is not limited to a rectangular shape. The semiconductor substrate 2 is not limited to a vertical semiconductor element. The semiconductor substrate 2 may contain a compound semiconductor material other than silicon (Si) or SiC as the base material. The semiconductor substrate 2 is not limited to a switching element but may be a rectifying element such as a diode.

[0016] The plurality of pads 3 are arranged with a gap between them on the first surface 2A of the semiconductor substrate 2. Each of the plurality of pads 3 is electrically connected to the semiconductor element. For example, the plurality of pads 3 includes the main pad 4, the first control pad 6, and the second control pad 7. The main current of the semiconductor element flows to the main pad 4. A signal for controlling the main current is input to and output from the first control pad 6 and the second control pad 7.

[0017] In plan view, the first control pad 6 and the second control pad 7 are adjacent to the main pad 4 and arranged with a gap established between the main pad 4 and the first control pad 6 and with a gap established between the main pad 4 and the second control pad 7 in a first direction X along the first surface 2A, respectively. In plan view, the first control pad 6 and the second control pad 7 are adjacent to each other and arranged with a gap established between them in a second direction Y along the first surface 2A, which is perpendicular to the first direction X. In plan view, the first control pad 6 and the second control pad 7 are each arranged in a rectangular area corresponding to a field of view FV, which will be described below.The gap between the first control pad 6 and the second control pad 7 is, for example, greater than or equal to the width of the first control pad 6 in the Y direction.

[0018] In plan view, the second control pad 7 has a sub-area 7A with a different shape, the outer shape of which is different from that of the first control pad 6. Viewed from a different angle, in plan view, the first control pad 6 has a sub-area 6A with a different shape, the outer shape of which is different from that of the second control pad 7.

[0019] The different-shape portion 7A is, for example, a portion of an outer edge portion of the second control pad 7. From a different perspective, in plan view, the first control pad 6 and the second control pad 7 further include congruent portions 6B and 7B, respectively, located at respective corresponding positions in the first control pad 6 and the second control pad 7 and having respective outer shapes that are congruent with each other. The entire outer edge portion of the second control pad 7 can be formed as the different-shape portion 7A.

[0020] In plan view, the partial regions 6A and 7A are formed with different shapes at respective corresponding positions in the first control pad 6 and the second control pad 7.

[0021] Herein, the description means that two subregions with different shapes are formed at respective corresponding positions in two pads in plan view, and that, in plan view, directions from the respective centers toward the respective subregions with different shapes in the two pads are equal to each other. In plan view, the relative positions of the congruent subregions and subregions with different shapes in the two pads are equal to each other. In plan view, imaginary straight lines connecting the respective centers and subregions with different shapes of the two pads are, for example, parallel to each other.

[0022] In plan view, the direction from the center toward the different-shape partial area 6A in the first control pad 6 is the same as the direction from the center toward the different-shape partial area 7A in the second control pad 7. In plan view, the relative positions of the congruent partial area 6B and the different-shape partial area 6A in the first control pad 6 are the same as the relative positions of the congruent partial area 7B and the different-shape partial area 7A in the second control pad 7. In plan view, an imaginary straight line A connecting the center and the different-shape partial area 6A in the first control pad 6 is, for example, parallel to an imaginary line B connecting the center and the different-shape partial area 7A in the second control pad 7.

[0023] The subregion 7A with a different shape can indicate the position and alignment or orientation of the semiconductor chip 1 in plan view if it is detected at least together with the subregion 6A with a different shape. For example, the subregion 7A with a different shape can be detected together with the subregion 6A with a different shape and the congruent subregions 6B and 7B in the Fig. 1, indicate that the direction in which the imaginary straight lines A and B are adjacent to each other is the Y direction, and the direction perpendicular to the Y direction and oriented toward the side on which the portion 7A having a different shape with respect to the center of the second control pad 7 in plan view is formed is the X direction.

[0024] In plan view, the outer shape of the first control pad 6 is, for example, a rectangular shape with rounded corners, with four corners being rounded. The first control pad 6 has a plurality of corner portions 61, 62, 63, and 64 and a plurality of side portions, each of which connects two of the adjacent corner portions. In plan view, for example, the first control pad 6 has rotational symmetry about the center of the first control pad 6.

[0025] In plan view, the second control pad 7 has a plurality of corner portions 71, 72, 73, and 74 and a plurality of side portions, each connecting two of the adjacent corner portions. The corner portion 71 consists, for example, of a plurality of corner portions 75, 76, and 77 and a plurality of side portions connecting these corner portions. In plan view, the plurality of corner portions 71, 72, 73, and 74 are located at positions corresponding to the plurality of corner portions 61, 62, 63, and 64, respectively. In plan view, the second control pad 7 has no rotational symmetry about the center of the second control pad 7.

[0026] The second control pad 7, for example, has a subregion 7A with a different shape. The subregion 7A with a different shape is formed, for example, in the corner region 71 of the second control pad 7. Viewed from a different angle, for example, the subregion 6A with a different shape is formed in the corner region 61 of the first control pad 6. In a plan view, for example, the corner region 71 is closest to a corner region of the semiconductor substrate 2 among the plurality of corner regions of the second control pad 7.

[0027] The different-shape portion 7A includes, for example, a recessed portion whose outer shape is a recessed shape compared with the first control pad 6. The different-shape portion 7A includes the plurality of corner portions 75, 76, and 77. The number of corner portions of the second control pad 7 is greater than the number of corner portions of the first control pad 6. The shape of the recessed portion is not particularly limited. The size of the recessed portion is not particularly limited as long as a mounting device used in a step of mounting the semiconductor chip 1 on a mounting substrate in a method of manufacturing a semiconductor device 100 described below can recognize it as an alignment mark.

[0028] The congruent portions 6B and 7B are formed by the respective remnants of the outer edge portions of the first control pad 6 and the second control pad 7, except for the portions 6A and 7A having different shapes. The congruent portion 7B includes the corner portions 72, 73, and 74 different from the corner portion 71, and the plurality of side portions included in the outer edge portion of the second control pad 7. The congruent portion 6B includes the corner portions 62, 63, and 64 different from the corner portion 61, and the plurality of side portions included in the outer edge portion of the first control pad 6.

[0029] For example, in a top view, the outer shape of the main pad 4 is rectangular with rounded corners, with four corners rounded. For example, in a top view, the outer shapes of the first control pad 6 and the main pad 4 are each rectangular with rounded corners, with four corners rounded.

[0030] In plan view, the base area of ​​the main pad 4 is larger than each of the respective base areas of the first control pad 6 and the second control pad 7. In plan view, for example, the base area of ​​the main pad 4 is larger than the sum of the respective base areas of the first control pad 6 and the second control pad 7.

[0031] The plurality of pads 3 may further include a third control pad 8. For example, the third control pad 8 is arranged so that it is adjacent to the main pad 4 with a gap established between the main pad 4 and the third control pad 8 in the first direction X and arranged with a gap established between the first control pad 6 and the third control pad 8 in the second direction Y.

[0032] On the first surface 2A, the semiconductor chip 1 does not have an alignment mark without electrical connection to the semiconductor element, that is, a pattern that functions only as an alignment mark.

[0033] For example, the semiconductor chip 1 further includes a protective film (not illustrated) formed to surround the plurality of pads 3 on the first surface 2A. <Verfahren zum Herstellen eines Halbleiter-Chips>

[0034] The semiconductor chip 1 can be manufactured in a manner similar to the way a conventional semiconductor chip is manufactured. The second control pad 7 having the differently shaped portion 7A can be formed by a predetermined method and can be formed, for example, by patterning a conductive film formed on the first surface 2A using a mask suitable for the differently shaped portion 7A. <Konfiguration der Halbleitervorrichtung>

[0035] As in Fig. 3, a semiconductor device 100 according to Embodiment 1 includes a semiconductor chip 1, a mounting substrate 110, a first connecting member 111, a second connecting member 112, a third connecting member 113, a fourth connecting member 114, and a sealing member (not illustrated).

[0036] The semiconductor chip 1 is mounted on the mounting substrate 110. A region where the semiconductor chip 1 is to be mounted is pre-designated on the mounting substrate 110, and the semiconductor chip 1 is bonded to the region using a bonding material. The mounting substrate 110 may be a substrate formed of a metal such as copper or aluminum. Alternatively, the mounting substrate 110 may be a substrate whose base material is a ceramic, resin, or the like.

[0037] The first connection component 111 is electrically connected to the first control pad 6. The second connection component 112 is electrically connected to the second control pad 7. The third connection component 113 is electrically connected to the main pad 4. The fourth connection component 114 is electrically connected to the third control pad 8. The first connection component 111, the second connection component 112, the third connection component 113, and the fourth connection component 114 are each electrically connected to, for example, another component (not illustrated) included in the semiconductor device 100. The first connection component 111, the second connection component 112, and the fourth connection component 114 are, for example, wires or ribbons. The third connection component 113 is, for example, a lead terminal.

[0038] In the semiconductor device 100, the semiconductor chip 1 is sealed with the sealing member. <Verfahren zum Herstellen einer Halbleitervorrichtung>

[0039] The semiconductor device 100 can be manufactured in a manner similar to how a conventional semiconductor device is manufactured. The method for manufacturing the semiconductor device 100 includes a first step of preparing a semiconductor chip 1 and a second step of mounting a semiconductor chip 1 prepared in the first step on the mounting substrate 110.

[0040] In the second step, the first control pad 6 and the second control pad 7 are simultaneously detected by the assembly device and used as alignment marks. The assembly device can detect the position and orientation of the semiconductor chip 1 in plan view by detecting the partial areas 6A and 7A with different shapes in their field of view FV (see Fig. 3) be recognized simultaneously.

[0041] The method for manufacturing the semiconductor device 100 further includes a third step following the second step. In the third step, the first connection component 111, the second connection component 112, the third connection component 113, and the fourth connection component 114 are electrically connected to the first control pad 6, the second control pad 7, the main pad 4, and the third control pad 8, respectively. < Effects>

[0042] In the semiconductor chip 1, the second control pad 7 (a second pad) has a different-shape portion 7A whose external shape is different from that of the first control pad 6 (a first pad). Thus, in the semiconductor device 100, the first control pad 6 and the second control pad 7 serve as wiring components for electrically connecting the semiconductor element in the semiconductor chip 1 to an external component and can also function as alignment marks. Consequently, the footprints of the first control pad 6 and the second control pad 7 are smaller than the sum of the footprints of a pad having a footprint equivalent to these and the footprint of an alignment mark formed in a region different from the pad.As a result, the semiconductor chip 1 enables downsizing while incorporating an alignment mark having higher visibility greater than or equal to that in a conventional semiconductor chip having a pad electrically connected to an external component and an alignment mark formed in a region different from the pad.

[0043] Furthermore, the first control pad 6 and the second control pad 7, which can function as alignment marks, are wiring components as described above, and accordingly, can be made larger than an alignment mark formed separately from a pad in a conventional semiconductor chip. Thus, the semiconductor chip 1 enables downsizing while incorporating an alignment mark having higher visibility than that in the above-mentioned conventional semiconductor chip. This semiconductor chip 1 is suitable for a power semiconductor chip for which downsizing is being promoted, such as a power semiconductor chip whose base material is silicon carbide (SiC).

[0044] In the semiconductor chip 1, the first control pad 6 and the second control pad 7 further include congruent portions 6B and 7B, respectively. In this case, the orientation of the semiconductor chip 1 can be recognized based on information about the position of the different-shape portion 7A with respect to both the different-shape portion 6A and the congruent portion 7B. Furthermore, in this case, the second control pad 7, which includes the different-shape portion 7A and the congruent portion 7B, can be easily formed because it has at least one recessed portion compared with the control pad 6.

[0045] In the semiconductor chip 1, among the plurality of pads 3, the first control pad 6 and the second control pad 7 are adjacent to each other. Accordingly, the field of view FV required to simultaneously observe the first control pad 6 and the second control pad 7 of the semiconductor chip 1 can be made smaller than in a case where the first control pad 6 and the second control pad 7 are not adjacent to each other. Thus, the first control pad 6 and the second control pad 7 can be observed at a higher magnification, and as a result, the observability of the portion 7A with a different shape is increased, and the above-mentioned mounting of the semiconductor chip 1 can be performed with higher efficiency.Generally, the above-mentioned conventional semiconductor chip includes an alignment mark located at one end portion of a chip in plan view, and another alignment mark located at another end portion of the chip in plan view. Therefore, in general, in the step of mounting the conventional semiconductor chip on the mounting substrate, the alignment of the semiconductor chip is performed by the mounting device that detects the two alignment marks individually and sequentially. In contrast, in the semiconductor chip 1, the alignment can be performed by detecting the first control pad 6 and the second control pad 7 simultaneously. Accordingly, the above-described mounting can be performed with higher efficiency compared with the above-mentioned conventional semiconductor chip.

[0046] The semiconductor device 100 includes the semiconductor chip 1 and can thus be downsized compared to a semiconductor device including the conventional semiconductor chip. Furthermore, the method for manufacturing the semiconductor device 100 mounts the semiconductor chip 1 on the mounting substrate 110, with the first control pad 6 and the second control pad 7 serving as alignment marks. Accordingly, the manufacturing efficiency of the semiconductor device 100 is higher than that of the conventional semiconductor device. <varianten>

[0047] As in Fig. As illustrated in Fig. 4, a third control pad 8 may be disposed between the first control pad 6 and the second control pad 7. It is not essential that the first control pad 6 and the second control pad 7 be adjacent to each other. The second control pad 7 may be disposed adjacent to the third control pad 8. Also in this case, the first control pad 6 and the second control pad 7 may be formed as alignment marks that are larger and have higher visibility than the alignment marks of the above-mentioned conventional semiconductor chip.

[0048] It is only necessary that in the semiconductor chip 1, the different-shape portion 7A is formed to have a given shape at a given position in the outer peripheral portion of the second control pad 7. As shown in Fig. 5, the sub-region 7A may be formed with a different shape in the corner sub-region 72. In this case, the corner sub-region 71 may be included in the congruence sub-region 7B. As shown in Fig. As illustrated in Figure 6, the differently shaped portion 7A may be formed in one of the side portions. In this case, the plurality of corner portions may be included in the congruent portion 7B.

[0049] As in Fig. 7, for example, the different-shape portion 7A may include a protruding portion whose outer shape is a protruding shape compared with the first control pad 6. In plan view, the second control pad 7 has an outer shape obtained when, for example, one of the corner portions of a relatively small rectangular shape with rounded corners is superimposed on one of the corner portions of a relatively large rectangular shape with rounded corners. The corner portion 71 is composed of, for example, a plurality of corner portions 75, 76, 77, 78, and 79 and a plurality of side portions connecting these corner portions.

[0050] The portion 7A with a different shape may include both the above-described recessed portion and the above-described protruding portion. For example, at least one of the corner portions 77, 78, and 79 shown in Fig. 7, have the recessed part.

[0051] The different-shape portion 7A is preferably formed in at least one of the plurality of corner portions 71, 72, 73, and 74 of the second control pad 7. Accordingly, even if the area that the different-shape portion 7A can occupy is limited, the degree of flexibility in the shape and arrangement of the different-shape portion 7A can be increased compared with a case where the different-shape portion 7A is formed in one of the plurality of side portions. Embodiment 2

[0052] Unless expressly described otherwise, a semiconductor chip 12 and a semiconductor device according to Embodiment 2 have the same configuration and the same functions and effects as those according to Embodiment 1 described above. Thus, the same constituent elements as those of Embodiment 1 described above are denoted by the same reference numerals and will not be explained repeatedly.

[0053] As in Fig. 8, in the semiconductor chip 12 according to Embodiment 2, the gap between a second control pad 7 and a first control pad 6 in a second direction Y is smaller than the width of the second control pad 7 in the second direction Y. The gap between the second control pad 7 and the first control pad 6 in the second direction Y is, for example, smaller than any other gap between two pads of a plurality of pads 3 adjacent to each other in a first direction X or the second direction Y.

[0054] In the semiconductor chip 12, the gap between the second control pad 7 and the first control pad 6 in the second direction Y can be shorter than that in the semiconductor chip 1. Thus, a field of view FV required to simultaneously detect the first control pad 6 and the second control pad 7 of the semiconductor chip 12 can be smaller than the field of view FV required to simultaneously detect the first control pad 6 and the second control pad 7 of the semiconductor chip 1. Accordingly, in the semiconductor chip 12, the detectability of a portion 7A having a different shape is further increased, and the above-described mounting of the semiconductor chip 12 can be performed with higher efficiency compared with the semiconductor chip 1.

[0055] The semiconductor chip 12 according to Embodiment 2 can be varied similarly to the semiconductor chip 1 according to Embodiment 1. Embodiment 3

[0056] Unless expressly described otherwise, a semiconductor chip 13 and a semiconductor device according to Embodiment 3 have the same configuration and the same functions and effects as those according to Embodiment 1 described above. Thus, the same constituent elements as those in Embodiment 1 described above are denoted by the same reference numerals and will not be explained repeatedly.

[0057] As in Fig. 9, in the semiconductor chip 13 according to Embodiment 3, a plurality of pads 3 includes a first main pad 4 (a first pad), a second main pad 5 (a second pad), and a plurality of control pads 8. The second main pad 5 is arranged with a gap established between the first main pad 4 and the second main pad 5 in a second direction Y. The first main pad 4 and the second main pad 5 are arranged with a gap established between the plurality of control pads 8 and the first main pad 4 and with a gap established between the plurality of control pads 8 and the second main pad 5 in a first direction X, respectively. The footprint of each of the first main pad 4 and the second main pad 5 is larger than the footprint of each of the plurality of control pads 8.

[0058] In plan view, the second main pad 5 has a sub-region 5A with a different shape, the outer shape of which is different from that of the first main pad 4. Viewed from a different angle, in plan view, the first main pad 4 has a sub-region 4A with a different shape, the outer shape of which is different from that of the second main pad 5.

[0059] For example, the different-shape portion 5A is formed in a corner portion of the second main pad 5. In plan view, for example, the different-shape portion 5A is formed in a corner portion included in a plurality of corner portions of the second main pad 5 and located on the side of the plurality of control pads 8.

[0060] The different-shape portion 5A has a recessed portion whose outer shape is a recessed shape compared with, for example, the first main pad 4.

[0061] The different-shape portion 5A is, for example, a part of an outer edge portion of the second main pad 5. Viewed from a different angle, in plan view, the first main pad 4 and the second main pad 5 further comprise congruence portions 4B and 5B, respectively, which are located at respective corresponding positions in the first main pad 4 and the second main pad 5 and have respective congruent outer shapes.

[0062] It is only necessary that the subregions 4A and 5A with different shapes have similar configurations to those of the subregions 6A and 7A with different shapes of the semiconductor chip 1. It is only necessary that the congruent subregions 4B and 5B have similar configurations to those of the congruent subregions 6B and 7B of the semiconductor chip 1. The entire outer edge subregion of the second main pad 5 can be formed as a subregion 5A with a different shape.

[0063] In the semiconductor chip 13, the first main pad 4 and the second main pad 5 are simultaneously recognized by a mounting device and used as alignment marks. The first main pad 4 and the second main pad 5 are larger than the first control pad 6 and the second control pad 7 and can thus be formed as alignment marks that have a higher recognizability than the first control pad 6 and the second control pad 7.

[0064] The semiconductor chip 13 according to Embodiment 3 can also be varied similarly to the semiconductor chip 1 according to Embodiment 1. Embodiment 4

[0065] Unless expressly described otherwise, a semiconductor chip 14 and a semiconductor device according to Embodiment 4 have the same configuration and the same functions and effects as those according to Embodiment 1 described above. Thus, the same constituent elements as those in Embodiment 1 described above are denoted by the same reference numerals and will not be explained repeatedly.

[0066] As in Fig. 10 and Fig. As illustrated in FIG. 11, the semiconductor chip 14 according to Embodiment 4 further includes an outer peripheral portion 9 arranged to surround a second control pad 7 (a second pad) on a first surface 2A of a semiconductor substrate 2. In plan view, the outer peripheral portion 9 can be visually recognized simultaneously with the second control pad 7 and its portion 7A having different shapes. The outer peripheral portion 9 is arranged at least in a field of view FV.

[0067] The visible light reflectance of a material from which the outer edge portion 9 is formed is lower than the visible light reflectance of a material from which the second control pad 7 is formed. The material from which the second control pad 7 is formed is a conductive material and includes at least one selected from a group consisting of, for example, gold (Au), copper (Cu), nickel (Ni), and aluminum (Al). The material from which the outer edge portion 9 is formed can be a specific material only if the material has a lower visible light reflectance than the material from which the second control pad 7 is formed, but is preferably a material with electrical insulation properties. The material from which the outer edge portion 9 is formed is, for example, polyimide or a nitride film.In this case, for example, the outer peripheral portion 9 may be formed to surround each of a plurality of pads 3 as part of a protective film.

[0068] The semiconductor chip 14 may further include a protective film arranged to surround each of the plurality of pads 3 and the outer peripheral portion 9.

[0069] In the semiconductor chip 14, a portion 7A having a different shape of the second control pad 7 and the outer peripheral portion 9 differ greatly in color tone, and thus a first control pad 6, the second control pad 7, and the outer peripheral portion 9 can function as alignment marks having excellent recognizability.

[0070] Although embodiments of the present disclosure have been described, it should be understood that the embodiments disclosed herein are presented in all respects for illustrative and exemplary purposes and are not to be taken as limiting. The scope of the present disclosure is defined by the claims and is intended to include all changes within the spirit and scope equivalent to the claims. QUOTES CONTAINED IN THE DESCRIPTION

[0000] This list of documents submitted by the applicant was generated automatically and is included solely for the convenience of the reader. This list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions. Cited patent literature

[0000] JP 2023-162904

[0001] WO 02 / 082540

[0004] < / varianten>

Claims

[1] Semiconductor chip (1, 12, 13, 14), comprising: a semiconductor substrate (2) having a first surface (2A) and having a semiconductor element formed on the semiconductor substrate (2); and a plurality of pads (3) electrically connected to the semiconductor element and arranged on the first surface (2A) with a gap therebetween, wherein the plurality of pads (3) comprises a first pad (4, 6) and a second pad (5, 7) and in plan view, the second pad (5, 7) has a partial area (5A, 7A) with a different shape, the outer shape of which is different compared to the first pad (4, 6). [2] The semiconductor chip (1, 12, 13, 14) according to claim 1, wherein, in plan view, the first pad (4, 6) and the second pad (5, 7) further comprise respective congruence portions located at respective corresponding positions in the first pad (4, 6) and the second pad (5, 7) and having respective mutually congruent outer shapes. [3] Semiconductor chip (1, 12, 13, 14) according to claim 1, wherein in plan view, the first pad (4, 6) and the second pad (5, 7) further comprise respective corner portions located at respective corresponding positions in the first pad (4, 6) and the second pad (5, 7), and the partial region (5A, 7A) with a different shape is arranged in the corner partial region (71, 72) of the second pad (5, 7). [4] The semiconductor chip (1, 12, 13, 14) according to claim 1, wherein the portion (5A, 7A) having a different shape of the second pad (5, 7) compared with the first pad (4, 6) has a recessed portion whose outer shape is a recessed shape or a projecting portion whose outer shape is a projecting shape. [5] The semiconductor chip (1, 12, 14) according to claim 1, wherein the first pad (4, 6) and the second pad (5, 7) among the plurality of pads are adjacent to each other. [6] Semiconductor chip (1, 12, 14) according to claim 1, wherein the plurality of pads (3) further comprises a third pad (4) to which a main current of the semiconductor element flows, and a signal to control the main current is fed into and output from the first pad (6) and the second pad (7). [7] Semiconductor chip (13, 14) according to claim 1, wherein a main current of the semiconductor element flows to the first pad (4) and the second pad (5) and the plurality of pads (3) further comprises a third pad (6) and a fourth pad (7), and a signal to control the main current is input to and output from the third pad (6) and the fourth pad (7). [8] Semiconductor chip (14) according to claim 1, further comprising an outer edge portion (9) arranged in plan view to surround the second pad (7) on the first surface (2A) and visually recognizable, wherein a visible light reflectivity of a material from which the outer edge portion (9) is formed is lower than a visible light reflectivity of a material from which the second pad (7) is formed. [9] Semiconductor chip (1, 12, 13, 14) according to claim 1, wherein the semiconductor element contains silicon carbide. [10] A semiconductor device (100), comprising: the semiconductor chip (1, 12, 13, 14) according to one of claims 1 to 9; a mounting substrate (110) on which the semiconductor chip is mounted; a first connecting component (111) electrically connected to the first pad (4, 6); and a second connecting component (112) electrically connected to the second pad (5, 7).

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